LC78626E Compact Disk Players Overview LC78626E monolit
|
|
|
Top Searches for this datasheet
Ordering number EN5692
LC78626E
Compact Disk Players
Overview
LC78626E monolithic compact disk player signal processing servo control CMOS equipped with internal anti-shock control function. Designed total functionality including support EFM-PLL, one-bit converter, containing analog low-pass filter, LC78626E provides optimal cost-performance low-end players that provide anti-shock systems. basic functions provided this include modulation signal from optical pick-up, deinterleaving, detection correction signal errors, prevention maximum approximately seconds skipping, signal processing such digital filtering (which useful reducing cost player), processing variety servo-related commands from microprocessor.
After subcode signal passes check, output microprocessor through serial transmission (LSB first). demodulated signal buffered internal RAM, which able absorb frame's worth jitter resulting from variations disk rotation speed. demodulated signal unscrambled specific sequence, deinterleaving performed. Error detection correction performed, flag process. (C1: error/C2: error correction method.) flag after referencing flag results check, where signal from flag interpolated held previous level. interpolation circuit uses double interpolation. When there more flags row, previous value held.
Continued next page.
Functions
When signal input, sliced precise levels converted signal. phase compared with internal clock reproduced average frequency 4.3218 MHz. Precise timing variety required internal timing needs (including generation reference clock) produced attachment external 16.9344 crystal oscillator. speed revolution disk motor controlled frame phase difference signal generated playback clock reference clock. frame synchronizing signal detected, stored, interpolated insure stable data read back. signal demodulated converted 8-bit symbolic data. demodulated signal divided into subcodes output external microprocessor. (Three general ports shared [exclusively] this purpose.)
Package Dimensions
unit: 3151-QFP100E (FLP100)
[LC78626E]
SANYO: QIP100E (FLP100)
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN
13098HA(OT) 5692-1/32
LC78626E
Continued from preceding page.
Command (such track jump, start focus, disk motor start/stop, muting on/off, track count, etc.) executed after they entered from microprocessor. 8-bit serial input used.) digital output equipped internally. High speed access supported through discretionary track counting. Using oversampling digital filter, converter signals with improved continuity output data produced. -type converter using 3-order noise shaper equipped internally. analog low-pass filter equipped internally.) Internal digital attenuator (8-bit-[ALPHA]; steps.) Internal digital deemphasis. Uses cross mute. Bilingual compatibility. General ports: (Three these shared, exclusively, with subcode output function.) seconds skip prevention (when using DRAM) through ADPCM compression/decompression processing. 1M/4M DRAM selected. Memory overflow detection output. Free memory output.
Features
100-pin single power supply
5692-2/32
Slice level control Digital Interpolation mute
Equivalent Circuit Block Diagram
clock production clock control 8-bit
address generator
Sync detect demodulation
digital servo ADPCM encoder
error detection correction flag process
Digital attenuator
Contact detector
Shock detector
Subcode partition QCRC oversampling digital filter Data width changer
LC78626E
Microprocessor interface One-bit
ADPCM decoder
Overflow process initiation control
Servo commands
Disable
General ports
Crystal oscillator-system timing generator
Low-pass filter
DRAM control
5692-3/32
LC78626E Assignment
view
5692-4/32
LC78626E
Specifications
Absolute Maximum Ratings 25°C,
Parameter Maximum power supply voltage Input voltage Output voltage Allowable power dissipation Operating temperature range Storage temperature range Symbol VOUT Topr Tstg Conditions Ratings VSS-0.3 VSS+7.0 VSS-0.3 VDD+0.3 VSS-0.3 VDD+0.3 +125 Unit
Allowable Operating Range 25°C,
Parameter Symbol VDD1 Power supply voltage VDD2 VIH1 Input high level voltage VIH2 VIH3 VIL1 Input level voltage VIL2 VIL2 Data setup time Data hold time High level clock pulse width level clock pulse width Data read access time Command transfer time Subcode read enable time Subcode ready cycle time Subcode read enable time Port input data setup time Port input data hold time Port input clock setup time Port output data delay time Input level Range operating frequencies Crystal oscillator frequency tRAC tRWC tSQE tCSU tCHD tRCQ tCDD VIN1 VIN2 Conditions VDD, XVDD, LVDD, RVDD, VVDD: ATT/DF/DAC normal speed VDD, XVDD, LVDD, RVDD, VVDD: functions guaranteed speed input pins with exception EFMI DRAM0 DRAM3 EFMI DRAM0 DRAM3 input pins with exception EFMI DRAM0 DRAM3 EFMI DRAM0 DRAM3 COIN, RWC: Figure COIN, RWC: Figure SBCK, CQCK: Figures SBCK, CQCK: Figures SQOUT, Figures RWC: Figure WRQ: Figure signal SFSY: Figure SFSY: Figure CONT2 CONT5, RWC: Figure CONT2 CONT5, RWC: Figure RWC, CQCK: Figure CONT2 CONT5, RWC: Figure EFMI: slice level control, XIN: coupling input EFMI XIN, XOUT 16.9344 1200 Ratings 0.7VDD 0.6VDD 0.45VDD 1000 11.2 0.3VDD 0.4VDD 0.2VDD Unit Vp-p Vp-p
Electrical Characteristics 25°C,
Parameter Consumption current Symbol Conditions VDD, XVDD, LVDD, RVDD, VVDD: with normal playback DEFI, EFMI, HFL, TES, RWC, COIN, CQCK, FMT, MR1, RES, TESD, WOK, PAUSE SHOCK, TESCLK, TESA, TESB, TESC, TESGB, TEST1: TAI, TEST2 TEST5, TESE: Ratings Unit
IIH1 Input high level current. IIH2
Continued next page.
5692-5/32
LC78626E
Continued from preceding page.
Parameter Symbol Conditions DEFI, EFMI, HFL, TES, RWC, COIN, CQCK, FMT, MR1, RES, TESE, TESD, WOK, PAUSE SHOCK, TESCLK, TESA, TESB, TESC, TESGB, TAI, TEST1 TEST5, EFMO, CLV+, CLV-, V/P, TOFF, TGL, JP+, JP-, PCK, FSEQ, EFLG, FSX, EMPH CONT2 CONT5, SBSY, MUTEL, MUTER, C2F, WRQ, SQOUT, 16M, 4.2M, EMPP, OVF, CNTOK, -0.5 DOUT CAS, RAS, AD0, DRAM3 DRAM0 -0.5 MMC0 MMC3 EFMO, CLV+, CLV-, V/P, TOFF, JP+, JP-, PCK, FSEQ, EFLG, FSX, EMPH CONT2 CONT5, SBSY, MUTEL, MUTER, C2F, WRQ, SQOUT, 16M, 4.2M, EMPP, OVF, CNTOK, DOUT CAS, RAS, AD0, DRAM3 DRAM0 MMC0 MMC3 PDO, CLV+, CLV-, JP+, JP-, CONT2 CONT5, DRAM0 DRAM3, ASRES VOUT PDO, CLV+, CLV-, JP+, JP-, CONT2 CONT5, DRAM0 DRAM3, ASRES VOUT RISET RISET Ratings Unit
Input level current
VOH1
2.56
Output high level current
VOH2 VOH3 VOH4 VOH5 VOL1 VOL2
2.56 2.72 2.24 0.64
0.32 0.48 0.44 0.96
Output level current VOL3 VOL4 VOL5 IOFF1 Output leakage current IOFF2 IPDOH IPDOL
Charge pump output current
One-bit Converter Analog Characteristics 25°C, LVDD RVDD L/RVSS
Parameter Total harmonic distortion rate Symbol TRD+N Conditions LCHO, RCHO; kHz: Uses data input kHz-LPF AD725D). LCHO, RCHO; kHz: Uses data input, kHz-LPF AD725D), filter. LCHO, RCHO; kHz: Uses data input, kHz-LPF AD725D), filter. LCHO, RCHO; kHz: Uses data input kHz-LPF AD725D). Ratings 0.015 0.018 Unit
Dynamic range
Signal noise ratio
Cross talk
Note: Measured with normal-speed playback mode Sanyo one-bit converter block reference digital attenuator circuit.
Analog output
5692-6/32
LC78626E
Figure Command Input
Figure Subcode Output
Figure Subcode Output
5692-7/32
LC78626E
Figure General Port Input Timing
Figure General Port Output Timing
5692-8/32
LC78626E Description Pins
Name DEFI VVSS ISET VVDD TESCLK TESA TESB TESC TESGB TEST5 TEST1 EFMO EFMI TEST2 CLV+ CLV- TOFF FSEQ Track jump control output. 3-state output depending command. data playback clock monitor. 4.3218 during phase lock. Sync signal detect output. high level when sync signal detected from signal matches internally generated sync signal. Digital system power supply. Disk motor control output. have 3-state output depending command. Rough servo/phase control automatic switching monitor output. high level then rough servo mode. level then phase control mode. Track detect signal input. Schmidt input. Tracking error signal input. Schmidt input. Tracking output. Tracking gain switch output. Gain increased with level. Function Defect detection signal (DEF) input. When used, must connected Test input. Equipped with internal pull-down resistor. Must connected External control phase comparator output. Internal ground. Must connected output current adjustment resistor connection. Internal power supply. frequency range adjustment Digital system ground. Must connected Test clock input. Must connected VDD. Test operation mode control input. Must connected VDD. Test operation mode control input. Must connected VDD. Test operation mode control input. Must connected VDD. Test operation mode control input. Must connected VDD. Test input. Equipped with internal pull-down resistor. Must connected Chip select input. Equipped with internal pull-down resistor. When controlled, must connected Test input. Must connected slice level control. signal output. signal input.
Test input. Equipped with internal pull-down resistor. Must connected
ASRES
Reset signal input initializing only anti-shock control part (i.e. excluding part). Resets when this level, release reset when this high level. this level (i.e., connected when using software control anti-shock part alone through anti-shock part only reset disable/release I(I/O) command ($F4) anti-shock only reset enable/inrush command ($F5). Note: This assigned least significant general port however, general disabled. When port command ($DB) executed, least significant always "0," output driver turned General This controls commands from microcontroller. When used, either this input port connect this output port leave open.
CONT2
Continued next page.
5692-9/32
LC78626E
Continued from preceding page.
Name CONT3/SBCK Description General This controls commands from microcontroller. This shared exclusively with subcode read clock input (SBCK). When used, either this input port connect this output port leave open. General This controls commands from microcontroller. This shared exclusively with subcode frame sync signal output (SFSY). When used, either this input port connect this output port leave open. General This controls commands from microcontroller. This shared, exclusively, with subcode output (PW). When used, either this input port connect this output port leave open. Subcode block sync signal output. Test input. Equipped with internal pull-down resistor. Must connected Digital output. EIAJ format. Test input. Equipped with internal pull-down resistor. Must connected 16.9344 output. 4.2336 output. error, error error correction monitor output 7.35 sync signal output (frequency divided from crystal oscillator). Deemphasis monitor output. When high level, deemphasis disk being played back. flag output. Test output. Under normal operation, this should left open. DRAM switch: high Test input. Must connected Test input. Must connected channel mute output. channel power supply. channel output. one-bit converter channel ground. Must connected channel output. channel power supply. channel mute output. Crystal oscillator power supply. 16.9344 crystal oscillator connection. Crystal oscillator ground. Must connected Read/write control input. Schmidt input. Microcontroller command input. Input command input latch clock subcode readout clock. Schmitt input. Subcode output. Subcode output standby output. Operating mode switch: high: shock proof, low: through. DRAM empty pulse output when DRAM empty). External reset input: reset (all internal blocks reinitialized).
CONT4/SFSY
CONT5/PW SBSY TEST3 DOUT TEST4 4.2M EFLG EMPH TOUT TESE TESD MUTESL LVDD LCHO L/RVSS RCHO RVDD MUTER XVDD XOUT XVSS COIN CQCK SQOUT EMPP
Continued next page.
5692-10/32
LC78626E
Continued from preceding page.
Name MMC0 MMC1 MMC2 MMC3 CNTOK PAUSE EMPN SHOCK DRAM3 DRAM2 DRAM1 DRAM0 Remaining DRAM output. Remaining DRAM output. Remaining DRAM output. Remaining DRAM output. DRAM write terminated. pulse output when there overflow shock.) Data contact point detection complete signal: high: detection complete. (DRAM write start). DRAM write enable signal input: high: write enable. Pause signal input: high: pause. data contact point detection start signal: high: detection start. Remaining DRAM alarm output: low: memory low. shock detect pause signal input: low: pause shock detection. DRAM data DRAM data DRAM data DRAM data DRAM control signal. DRAM control signal. DRAM control signal. DRAM control signal. DRAM address DRAM address DRAM address DRAM address DRAM address Digital system ground. Must connected DRAM address DRAM address DRAM address DRAM address DRAM address Digital system power supply. Description
5692-11/32
LC78626E Applications Signal Input Circuit EFMI, EFMO, DEFI, CLV+ When signal input EFMI, signal (NRZ), sliced optimal levels, obtained. countermeasure against defects, when DEFI (Pin high, slice level control output EFMO (Pin goes high impedance state, slice level held. However, this only enabled when phase-control mode, other words, when (Pin low. This structured from combination with LA9230/40 series ICs. When EFMI CLV+ signal lines close each other then error rate unnecessary radiation increase. recommended that these lines separated ground line line shield line.
Signal
Clock Playback Circuit
PDO, ISET circuit equipped internally, circuit structured using external resistors external capacitors. ISET reference current charge pump. loop filter circuit, resistor that determines frequency range VCO. Reference Values (standard speed) 0.047 speed) recommended that carbon coated resistor with tolerance 5.0% used
Frequency phase comparator
Charge pump
Monitor This monitor with average frequency 4.3218 MHz, which frequency division from VCO.
Sync Detect Monitor FSEQ signal goes high when frame sync signal (the true sync signal) from matches timing (the interpolated sync signal) generated counter. This serves sync detect monitor (holding high level over single frame).
5692-12/32
LC78626E Servo Command Functions RWC, COIN, CQCK Various commands executed setting high inputting command from COIN synchronized with CQCK clock. commands executed beginning with falling edge RWC. Focus start Track jump Mute control Disk motor control Other control Track check Digital attenuator General port settings Single-byte Commands
Single-byte commands
Two-byte command (two sets RWC). Two-byte commands (once RWC).
Two-byte commands (RWC set: track count)
least Command ($F0, $F8) Data ($08 $FE), command ($FF)
Two-byte commands (RWC set: digital attenuation setting general port)
Data
Commands ($81 $87, $DB, $DC)
Eliminating Command Noise
Code COMMAND Command input noise reduction mode Resets command input noise reduction mode.
This command makes possible reduce noise that mixed into CQCK clock. This effective noise less than however, CQCK timing must have more tWL, tWH, tSU.
5692-13/32
LC78626E Servo Circuit CLV+, CLV-,
Code COMMAND DISC MOTOR START (Accelerate) DISC MOTOR (CLV) DISC MOTOR BRAKE (Decelerate) DISC MOTOR STOP (Stop)
CLV+ signal accelerating disk forward direction, while CLV- signal decelerating disk. Depending commands from microcontroller, following four modes selected: Accelerate, decelerate, CLV, stop. CLV+ CLV- outputs each mode shown table below.
MODE Accelerate Decelerate Stop CLV+ high Pulse output CLV- high Pulse output
servo control command such that TOFF only when mode effect, high otherwise. TOFF control command only active when mode effect. Mode mode rotation disk detected from signal, precise linear speed rotation derived exerting respective forms control when internal modes change. frequency 7.35 kHz. high output when internal mode rough servo, output when internal mode phase control.
Internal mode Rough servo (when rotational speed determined low) Rough servo (when rotational speed determined high) Phase control (when clock running) CLV+ high CLV- high high high
Switching Rough Servo Gain
Code COMMAND DISC DISC
When internal mode rough servo, control gain disk reduced from level disk.
5692-14/32
LC78626E Switching Phase Control Gain
Code COMMAND phase comparator frequency division. phase comparator frequency division. phase comparator frequency division. phase comparator, frequency division.
changing frequency division value first-stage frequency divider phase comparator possible change phase control gain.
Phase comparator
3-state Output
Code COMMAND 3-state output 2-state output (traditional method)
3-state output command makes possible control with single pin. However, because this will cause spindle gain fall will necessary increase gain servo side.
2-state output
3-state output
High impedance output
Acceleration
Deceleration
5692-15/32
LC78626E Internal Brake Mode
Code COMMAND Internal Break Internal Break Internal brake control Internal brake continuous mode Internal brake continuous mode reset Internal brake mode Internal brake mode reset
internal brake mode turned inputting internal brake command ($C5). When this mode, when brake command ($06) executed becomes possible monitor state deceleration disk using pin. this mode, status deceleration disk determined counting density signals single frame, CLV- number signals less. same time, signal high break complete monitor. microcontroller issues STOP command senses that signal high, thus brings disk complete stop. internal break continuous mode CLV- high brake operation continues even when break complete monitor goes high. When noise signal causes deceleration status judged incorrectly, advisable internal break control command ($A3) change signal count from TOFF output inhibited mode ($CD), TOFF while internal break operation. recommended because effective preventing incorrect detection mirrored surface disk.
signal
command
When there loss focus during execution internal break command will necessary reissue internal brake command after focus been reestablished. Because there risk that signal will discerned incorrectly depending playback status (scratched disks, access processes, etc.), conjunction with microcontroller recommended. When internal brake mode effect, then possible monitor disk deceleration status executing DISC BRAKE command ($06) this DSP. However, another command executed while this command process, then command will aborted. When wish prevent function from being aborted, then, after issuing DISC BRAKE command ($06), issue other commands until high signal detected DISC STOP command ($07) issued. Track Jump Circuit HFL, TES, TOFF, TGL, JP+, Types Track Counters following track count modes have been provided.
Code COMMAND track count combination HFL). conventional track count (direct count signal).
conventional track counter uses signal itself internal track counter clock. track count method, however, signal combined with signal reduce amount noise, producing more accurate track count through reducing number miscounts noise rising edge falling edge signal. However, when signal absent because dust, scratches, etc., there danger that there will track count pulse, thus caution required when using this method.
5692-16/32
LC78626E Command
Code COMMAND conventional track jump track jump. TRACK JUMP TRACK JUMP TRACk JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK CHECK TOFF TRACK JUMP BRAKE pulse period TOFF output mode. pulse period TOFF output mode reset.
(Brake period)
pulse period)
When track jump command input servo command acceleration pulse generated (period following which deceleration pulse generated (period after which specific jump completed after brake period (period elapses. this break period beam slip direction detected through inputs, segment signal that propagates internal slip TOFF. Moreover, increasing servo gain using TGL, possible lock onto track that jump destination. pulse interval TOFF output mode, TOFF high during interval when pulse generated. TOFF only when mode active when related disk control mode, this terminal high during start, stop, break control. Moreover, TOFF turned independently using commands. However, disk motor control only enabled when mode active.
5692-17/32
LC78626E Mode relationships between acceleration pulse, deceleration pulse, brake interval shown table below.
When conventional track jump mode Command TRACK JUMP (OUT) TRACK JUMP (OUT) TRACK JUMP (OUT) TRACK JUMP (OUT) TRACK JUMP (OUT) TRACK JUMP (OUT) TRACK JUMP (OUT) TRACK JUMP (OUT) TRACK JUMP (OUT) TRACK JUMP (OUT) TRACK JUMP period TRACK JUMP period TRACK JUMP period TRACK JUMP period TRACK JUMP period TRACK JUMP period TRACK JUMP period TRACK JUMP period None TRACK JUMP period TRACK JUMP period TRACK JUMP period TRACK JUMP period This period does exist TOFF ="L" during period When track jump mode. Same conventional mode. TRACK JUMP period TRACK JUMP period TRACK JUMP period TRACK JUMP period TRACK JUMP period TRACK JUMP period same same same same same same This period does exist TOFF ="L" during period
Same conventional mode. Same conventional mode. Same conventional mode.
TRACK JUMP (OUT) TRACK JUMP BRAKE
TOFF high during period over which tracks elapse pulses produced. There period.
Same conventional mode. Same conventional mode.
TRACK CHECK does produce actuator drive signal shown table above, rather because mode such that signal counted when tracking loop off, necessary provide feed feed motor. When track jump sequence completed, servo command register reset automatically. When command been input when track jump process, that command executed that instant. TRACK JUMP command there brake period (period rather caution warranted because necessary generate brake mode using external circuit. Although 2TRACK JUMP (OUT) track jump mode brake period (period exist LC78620E/21E/25E ICs, this period been changed
Slip detector High during brake interval
5692-18/32
LC78626E THLD Signal generated LA9230M, 9240M Series side, causes tracking error signal held during pulse period. Tracking Brake relationship between TES, HFL, TOFF signals during track jump period shown below. TOFF signal generated from signal with changing edge signal. high signal mirrored area, while pitted area. beam sweeps from mirrored surface pitted area, TOFF becomes high, beam sweeps from pitted area mirrored surface, TOFF made gain-enhanced state (TGL low), brake applied.
(when moving towards outside) (when moving towards inside) TOFF output
3-state Output
Code COMMAND 3-state output 2-state output (conventional method)
Using 3-state command, track jump controlled with single pin, however, gain must increased servo side because kick gain will decrease
2-state output
3-state output
High impedance output
Track Check Mode
Code COMMAND Track check Track check byte command reset
After track check track check command been entered, then when discretionary number between entered binary data, track count specified number will performed.
number desired track checks number track checks input
Command Binary input desired Track check number tracks In/Out command Track check Double byte command reset Brake command
Rising edge number tracks/2
Goes when track check complete.
5692-19/32
LC78626E When desired number tracks entered binary number, track check operation begins with falling edge RWC. During track check TOFF becomes high tracking loop turns off, thus there need provide feed feed motor. When track check In/Out commands entered, signal changes from subcode standby monitor that during normal times become track check monitor. This signal becomes high when half number tracks have been checked, becomes when check complete. microcontroller sees that signal become determines that check been completed. two-byte reset command entered, track check operation begins again. other words, wished advance 20,000 tracks, then single track check code would sent then when cycles have been counted, then there have been 20,000 track checks. When track check performed, brake command used lock pickup track.
Error Flag Output EFLG,
correction correction Correction function errors
7.35 frame sync signal that created frequency dividing crystal clock. each frame, error correction status output EFLG. easy tell quality playback number high pulses that appear EFLG signal. Subcode Output Circuits SBCK, SFSY/CONT4, PW/CONT5, SBSY subcode signal output pin. (Note: are, respectively, general exclusively shared pin, selection depends commands from micro controller. Item page 24.) applying clocks SBCK within falling edge SFSY, possible read codes until signal that appears changes with rising edge SBCK. When clock applied SBCK, code output SFSY signal that output each subcode frame, falling edge this signal indicates that subcode symbol output standby. subcode data output falling edge this signal.
SBSY signal output each subcode block. This signal becomes high during sync signals falling edge indicates subcode sync signal beginning data subcode block EIAJ format).
5692-20/32
LC78626E Subcode Output Circuit WRQ, RWC, SQOUT, CQCK,
Code COMMAND ADDRESS FREE ADDRESS
possible read subcode from SQOUT inputting clock into CQCK pin. 8-bit subcodes, signal useful accessing musical selections, displays, etc. only high when been passed address subcode format "1." (See Note When microcontroller detects this high level, transmit CQCK signal read data from SQOUT order shown below. When CQCK transmission begins, data changes internal registers inhibited. Once microcontroller completed read, temporarily goes high, enabling data updating. this time, goes low. Because goes after being high 11.2 CQCK input starts during interval when high. data read beginning with least significant bit. Note This conditions ignored address-free command sent (corresponding CDV).
CONT INDEX (POINT) FRAME ZERO AMIN (PMIN) ASEC (PSEC) AFRAME (PFRAME)
items within parentheses read-in area.
data
normally indicates subcode standby; however, when track counter mode when there internal bake, becomes different monitor. (See track count internal brake items.) This becomes active when low, subcode data output from SQOUT pin. When high, SQOUT enters high impedance state.
5692-21/32
LC78626E Bilingual Function
Code COMMAND CONT CONT CONT
reset when stereo command ($28) been entered, output, respectively, Rch. When command ($29) entered, data output both Rch. When command ($2A) entered, data output both Rch. Deemphasis EMPH subcode control data, pre-emphasis On/Off output from EMPH pin. When this high, deemphasis circuit within this activated, converter output de-emphasized. Digital Attenuator possible apply digital attenuation audio data setting high inputting from COIN byte command synchronized with CQCK clock.
Code COMMAND DATA 4STEP 4STEP 8STEP 8STEP 16STEP 16STEP DOWN DOWN DOWN DATA (MUTE -dB)
After reset, attenuation level "MUTE" (the attenuation coefficient 00H, where MUTE thus necessary directly attenuation coefficient using direct (ATT DATA SET) command order produce sound. attenuation level range from (239 different levels) microcontroller commands. This byte command different from byte commands used track counting that only needs once, necessary reset byte command either. (See byte command RWC1 page 13.)
Command
Attenuation data
Attenuate command
After inputting target attenuation level terms EEH, then attenuate step-up/step-down commands transmitted, system steps closer target with corresponding step size synchronized with rising edge LRSY. However, when DATA command been used, then target value directly. When data entered during transition, then target value approached from whatever value effect that time. Caution required when using step-up/step-down commands this time.
5692-22/32
LC78626E
44.1 (normal speed), 88.2 (double speed)
Start Stop
DATA audio output level [dB] 100H Because, example, time that would take increase attenuation level from "00H" "EEH" using step-up command would calculated below, this amount time must left before entering next attenuation level command: level Step-up 21.6 (approx.) 44.1 (LRSY) order prevent noise arithmetic overflow one-bit converter, settings greater than prohibited. Mute Output MUTEL, MUTER When Mute control (MUTE $03) exerted, once data each channel been continuously specified amount time, then this output goes high. Afterwards, when data again entered, this output immediately goes low. Flag Output 8-bit unit flag that indicates data error status. Digital Output Circuit DOUT This digital audio interface output pin. output EIAJ format. This signal interpolated, signal output through MUTE circuit. Because this output equipped with internal driver, drive transformer directly.
Code COMMAND DOUT DOUT UBIT UBIT CDROM-XA ROMXA-RST
digital fixed inputting DOUT command. DOUT data, UBIT data fixed entering UBIT command. entering CDROM-XA command, DOUT switched CD-ROM data that subjected interpolation mute control. (When this done, audio output into mute mode.) ROMXA-RST command returns DOUT audio data output mode which subject interpolation mute control. (When this done, audio output mute released.) Mute Control Circuit
Code COMMAND MUTE MUTE
sound level muted (MUTE entry commands above. Because zero cross mute used, there little noise during this operation. zero cross determination made range where most significant bits "0." Because MUTE-12 command ($02) that found LC78620E 78621E been deleted, digital attenuator used DATA ($3C) set.
5692-23/32
LC78626E Interpolation Circuit when error correction circuit cannot correct error, erroneous audio data output without correction, result would excessive noise. order reduce this noise, erroneous data replaced with linear approximation based correct data either side incorrect data. When there more flags, previous data level held. However, when data output after more continuous flags, then linear approximation made based correct data held value that points earlier middle point replaced with this linear approximation.
Correct data Flagged data Interpolated data Held previous value.
When there error place
When there continuous errors (three errors this example).
General Ports CONT2, CONT3, CONT4/SFSY, CONT5/PW four signal lines, CONT2 CONT5, have ports. These lines input terminals time reset. Unused ports must either connected ground output ports. Moreover, pins pins that shared (exclusively) respectively, subcode frame sync signal output (SFSY) subcode output (PW). selection function these pins done commands from microcontroller.
Code COMMAND PORT READ PORT PORT OUTPUT PORT
Code
COMMAND SFSY, output enabled SFSY, output disabled
port data read sequentially from CONT2, CONT3, CONT4, CONT5 with falling edge CQCK from SQOUT when there port read command. command uses single-byte command format. When command applied this during track check, track jump, internal brake operation, then will terminate those operations. wish terminate these operations, apply unnecessary commands (including general port operation commands) during track check, track jump, internal brake operations.
These ports each individual control output ports port command. ports selected lower four bits single byte. Starting with least significant bit, these four bits this single byte data correspond CONT2, CONT3, CONT4, CONT5. command uses two-byte command format (RWC1 set).
5692-24/32
LC78626E
Single-byte data PORT
CONTn output CONTn input pin. Where ports that output pins then they independently output either high levels. lower four bits single byte data correspond respective ports. Starting with least significant this single byte data, bits correspond CONT2, CONT3, CONT4, CONT5. command uses two-byte command format (RWC1 set).
Single-byte data PORT OUTPUT
Outputs high level from CONTn that being output Outputs level from CONTn that being output
Clock Oscillator XIN, XOUT
Code COMMAND XTAL Normal speed playback Double speed playback
connecting 16.9344 oscillator these pins clock generated that serves time base. command command stop oscillation oscillator oscillation. Moreover, depending command, double speed playback also possible.
Oscillator
(C1)
(C2)
When structuring double speed playback system, connect 16.9344 oscillator between (Pin XOUT (Pin 59), playback speed using double speed playback command. Recommended crystal/ceramic oscillator constants.
Manufacturer Product Load Capacitance C1/C2 (±10%) (±10%) (Internal type) Dumping Resistance (±10%) (±10%)
CITIZEN WATCH CO., LTD. CSA-309 (16.9344 MHz) (Crystal Oscillator) TDK, Ltd. (Ceramic oscillator) 16.93M2G (16.93 MHz) 16.93MCG (16.93 MHz)
load capacitance Cout will have different requirements depending actual print circuit board used, thus necessary perform verification testing print circuit board. Consult oscillator manufacturer. 4.2M Pins 16M, 4.2M When using double speed/normal speed playback mode, 16.9344 signal will output from after external crystal oscillator 16.9344 MHz. 4.2336 will output constantly from 4.2M pin, forming LA9230/40 Series system clock. When OFF, both terminals constantly either high low.
5692-25/32
LC78626E Reset Circuit When power supply turned first this then high. muting disk motor stop.
servo relationship Muting control Subcode address parameter Track jump mode Track count mode Digital attenuator Playback speed Digital filter normal speed START Address1 Conventional Conventional DATA0 Normal speed STOP Address Free DATA Double speed BRAKE
When low, then statuses found boxes above directly.
Other Pins TAI, TEST1, TEST2, TEST3, TEST4, TEST5 These pins testing circuits within While TEST1 TEST5 equipped with internal pulldown resistors, safety reasons, they should connected Explanation Block Functions Address Control This contains bits words on-board RAM, and, depending address control, modulation data jitter absorption capability have frames buffer memory capacity. Moreover, normally this buffer margin checked, precisely controlling servo circuit PCK-side frequency ratio possible control data write address that will centered size buffer. Also, when frame buffer capacity exceeded, write address forced because resulting errors cannot subjected flag processing, mute applied frame period.
Position lower greater Frequency Divider Ratio Process Forces transition Forces transition Backwards frequency division Standard frequency division Forward frequency division
5692-26/32
LC78626E Corrections Data that been modulated written internal RAM, jitters absorbed, then, following processes performed with uniform timing through crystal oscillator clock. First, there error checking correction block, flag determined written flag register. Next, error checking corrections performed block, flag determined written internal RAM.
Check error error errors more errors Correction Flag Process Correction required/flag reset Correction performed/flag reset Correction performed flag Correction possible flag
Check error error errors more errors
Correction Flag Process Correction required/flag reset Correction performed/flag reset flag. (Note flag. (Note
Note: error position determined check matches flag, then error correction performed flag reset. However, when there seven more flags, then there would risk erroneous correction, thus correction performed flags become flags. When error positions match, another error position does match, then correction performed. Moreover, when there five less flags, then check thought somewhat dubious, thus flag set. When there more, error correction possible they handled together, flags become flags they are. When none error positions match, naturally error correction cannot performed, when number flags less, then there errors even data that deemed check, thus flag set. other cases, flags used flags they are. When determined that error correction possible because there three more errors, then naturally error correction cannot performed when number flags less, even data that deemed check contain errors, thus flags set. other cases, flags used flags directly.
Anti-shock Function FMT, MR1, WOK, CNTOK, OVF, C2F, WRQ, SQOUT anti-shock function this reads data from disk double speed stores external DRAM. replaying that data that stored when external shock caused data acquisition defective, possible avoid defective playback external shocks. anti-shock mode placing high. When data stored external DRAM, 16-bit data compressed bits using ADPCM. Depending DRAM capacity (256K bits bits) time that stored will approximately seconds (1M) approximately seconds (4M). Depending type DRAM, might have set. (See table.) When anti-shock mode, double speed data written external DRAM then read normal speed speed) playback, thus external DRAM will eventually become full. When this happens, this stops writing DRAM places high. microcontroller monitors when microcontroller senses that signal gone high, places order find point which writing terminated (called point below) system must perform track jump. microcontroller already determined through monitoring frame number subcode location point. frame number point when becomes high track jumps location, point sought placing high that many frames earlier. When this finds point, CNTOK high, DRAM data write process begins again. Furthermore, sometimes point cannot found, such when there external shock during point search. CNTOK become high even point frame number been passed three more frames), then determined that point found. When this happens, track jump performed again, point search begins again. When search performed again, track jump performed with High. This determines whether there been external shock through flag. When flag becomes high then becomes high just DRAM full, writing DRAM terminated. this case, microcontroller should perform same process DRAM become full. Setting pins
High Anti-shock mode: (256K bit) DRAM Anti-shock mode: bit) DRAM
5692-27/32
LC78626E Schematic timing various signals during anti-shock operations shown figure below.
Beginning point search
point because shock
Track jump
point because DRAM full Track jump
point found. Beginning writing DRAM
Anti-shock Independent Reset possible initialize only anti-shock controller part (excluding part) setting ASRES low. reset released setting this high. Furthermore, when controlling independent reset using commands, ASRES must tied (connected
Code COMMAND Independent reset disable (release) Independent reset enable/inrush
5692-28/32
LC78626E Table Commands Commands with blank columns: Commands that used. Commands with asterisk marks: Commands that latched (i.e. mode commands). Commands marked with signs: Commands that shared with (LA9240M, etc.). Commands parentheses: Commands that exclusive (reference). Commands marked with signs: Commands changed added from LC78622E.
(ADJ. RESET) MUTE MUTE DISC START DISC DISC BRAKE DISC STOP FOCUS START ADDRESS FREE TRACKING TJ-time TOFF TJ-time TOFF Track Count Track Count CONT CONT CONT UBIT UBIT DOUT DOUT normal speed "OFF" normal speed "ON"
16TJ 64TJ 256TC 128TJ 16TJ 64TJ 128TJ
32TJ 32TJ
DISC BRAKE command ($06) function, when internal brake mode function that puts high latched. details, internal brake mode section 6-(5) page
5692-29/32
LC78626E Commands with blank columns: Commands that used.Commands with asterisk marks: Commands that latched (i.e. mode commands). Commands marked with signs: Commands that shared with (LA9240M, etc.). Commands parentheses: Commands that exclusive (reference). Commands marked with signs: Commands changed added from LC78622E.
DATA 4STP 4STP DOWN 8STP 16STP DOWN ATT16STP 16STP DOWN CDROMXA ADDRESS ROMXA TRACK BRAKE TRACKING Track Jump Track Jump FOCUS START Internal Brake CONT DISC DISC 12cm Double speed playback Normal speed playback Internal BRAKE Internal BRAKE Internal BRK-DMC Internal BRK-DMC Internal BRK-time TOFF Internal BRK-time X'tal Command noise Command noise
F.OFF.ADJ.START) F.OFF.ADJ.OFF) T.OFF.ADJ.START) T.OFF.ADJ.OFF) LASER LSR.OFF/F.SV.ON) OFF/F.SV.OFF) SP.8cm) SP.12cm) SP.OFF) SLED SLED OFF) EF.BAL.START) T.SERVO OFF) T.SERVO
frequency divider mode frequency divider mode frequency divider mode frequency divider mode 3-state output 3-state output 3-state output 3-state output PORT OP.ED PORT DATA PORT READ
TRACK CHECK (2BYTE DETECT) Anti-shock part independent reset disable/release Anti-shock part independent reset enable/inrush
output enable output disable TRACK CHECK (2BYTE DETECT) NOTHING 2BYTE RESET
After (the frequency divider part) reset, then this turns OFF. (the opposite LC78622E). However, functions commands ($AC, $AD) same LC78622E.
5692-30/32
LC78626E Sample Application Circuit
5692-31/32
LC78626E Comparison CD-DSP Functions
Model Function EFM-PLL Replay speed Digital Interpolation Zero cross mute Level meter peak search Bilingual Digital attenuator Digital filter Digital Deemphasis Output General Ports compatible Anti-shock Anti-shock controller text CD-ROM One-bit converter L.P.F Power supply voltage Package LC7861NE LC7861KE Paired with LA9210M -12dB, QFP64E LC78621E Internal 1.2k -12dB, QFP80E LC78622E Internal 1.2k QFP64E LC78624E Internal 1.2k QFP64E LC78625E Internal 1.2k -12dB, QFP80E LC78626E Internal 5.1k necessary QFP100E LC78630E Internal 1.2k QFP80E
products described contained herein intended surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment like, failure which directly indirectly cause injury, death property loss. Anyone purchasing products described contained herein above-mentioned shall: Accept full responsibility indemnify defend SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees, jointly severally, against claims litigation damages, cost expenses associated with such use: impose responsibility fault negligence which cited such claim litigation SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees jointly severally. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties. This catalog provides information January, 1998. Specifications information herein subject change without notice. 5692-32/32
Other recent searches
S1T2425A - S1T2425A S1T2425A Datasheet
NA1731 - NA1731 NA1731 Datasheet
LTC3672BEDC-1 - LTC3672BEDC-1 LTC3672BEDC-1 Datasheet
LP38842 - LP38842 LP38842 Datasheet
DS1865 - DS1865 DS1865 Datasheet
AN550 - AN550 AN550 Datasheet
AN556 - AN556 AN556 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
