LC7234 Single-chip Microcontroller with Driver Overview

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LC7234 Single-chip Microcontroller with Driver Overview

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Ordering number:ENN3620C
LC7234
Single-chip Microcontroller with Driver
Overview
LC7234 single-chip microcontroller that incorporates 150MHz phase-locked loop (PLL) liquid-crystal display (LCD) driver, making ideal digital tuners. large number input/output ports frequency measurement circuit. LC7234 freatures on-chip ROM, programmable high-speed divider, 6-bit analog-to-digital converter low-voltage detection reset circuit. LC7234 operates from supply available 64-pin QIPs.
Package Dimensions
unit:mm 3159-QIP64E
[LC7234]
17.2 14.0 0.35 0.15
17.2
14.0
Features
phase-locked loop. driver. 6-bit analog-to-digital converter. 4-bit input ports. 4-bit input/output ports. 6-bit keypad matrix scan output port. 2-bit open-drain high-voltage output port. mask-selectable output drivers. 20-bit universal counter. 2048 16-bit program (001H 7FFH user-addressable memory). 4-bit data RAM. Low-voltage detection reset circuit. Programmable high-speed divider. Single-word instructions. Four-level stack. PLL-unlocked flip-flop. Timer flip-flop. Programmable watchdog interrupt address. Standby mode. operates down 3.5V retains data retention down 1.3V. supply. 64-pin QIP.
3.0max
15.6
SANYO QIP64E
Assignment
view
SANYO products described contained herein have specifications that handle applications that require extremely high levels reliability, such life-support systems, aircraft's control systems, other applications whose failure reasonably expected result serious physical and/or material damage. Consult with your SANYO representative nearest before using SANYO products described contained herein such applications. SANYO assumes responsibility equipment failures that result from using products values that exceed, even momentarily, rated values (such maximum ratings, operating condition ranges,or other parameters) listed products specifications SANYO products described contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
80101TN No.3620-1/12
LC7234
Block Diagram
No.3620-2/12
LC7234
Function
Number Name Crystal oscillator connections XOUT TEST2 TEST1 Equivalent circuit Description
Test pins
Input port
PH1,
Output port
Input/output port
Input/output port
PC1,
Output port
Output port
Input port
segment outputs
Continued next page.
No.3620-3/12
LC7234
Continued from preceding page.
Number Name Equivalent circuit Description
COM2, COM1
common driver outputs
HOLD
Hold-mode control input
Power-fail detect
converter input
HCTR
Univarsal counter input
supply
FMIN
input
AMIN
input
Ground
Phase comparator output
Analog input
AOUT
Analog output
No.3620-4/12
LC7234 Specifications
Absolute Maximum Ratings 25°C,
Parameter Maximum supply voltage Port HOLD, input voltage Input voltage (other inputs) Port AOUT output voltage Output voltage (all other outputs) Port output current Ports output current Ports output current AOUT output current Allowable power dissipation Operating temperature Storage temperature Symbol Topr Tstg Ta=-40 +85°C Conditions Ratings +6.5 +13.0
VDD+0.3 +15.0 VDD+0.3
Unit
+125
Reommended Operating Conditions +85°C, 5.5V
Parameter Supply voltage (PLL CPU) Supply voltage (CPU) Supply voltage data retention Port input high-level voltage Ports input high-level voltage Port input high-level voltage HOLD input high-level voltage input high-level voltage Port input low-level voltage Ports input low-level voltage Port input low-level voltage HOLD input low-level voltage input low-level voltage input frequency FMIN input frequency AMIN input frequency (low range) AMIN input frequency (high range) HCTR input frequency input amplitude FMIN input amplitude AMIN input amplitude HCTR input amplitude input voltage Port input voltage Symbol VDD1 VDD2 VDD3 VIH1 VIH2 VIH3 VIH4 VIH5 VIL1 VIL2 VIL3 VIL4 VIL5 Port high impedance. VI=0.5 1.5V VI=0.1 1.5V, VDD=4.5 5.5V VI=0.15 1.5V, VDD=4.5 5.5V VI=0.1 1.5V, VDD=4.5 5.5V VI=0.1 1.5V, VDD=4.5 5.5V VI=0.1 1.5V, VDD=4.5 5.5V Conditions Ratings 0.6VDD 0.7VDD 0.7VDD 0.8VDD 0.2VDD 0.3VDD 0.3VDD 0.4VDD 10.0 12.0
0.05VDD
Unit Vrms Vrms Vrms Vrms Vrms
Electrical Characteristics +85°C, 5.5V, unless otherwise noted
Parameter reject pulsewidth Standby threshold voltage Ports high-level input current Port high-level input current high-level input current FMIN, AMIN HCTR high-level input current HOLD, ADI, port high-level input current high-level input current Ports low-level input current low-level input current FMIN, AMIN HCTR low-level input current Symbol Prej VDET IIH1 IIH2 IIH3 IIH4 IIH5 IIH6 IIL1 IIL2 IIL3 Ports high impedance. Port RPD. VI=VDD VI=VDD=5.0V. Port RPD. VI=VDD VI=VDD=5.0V VI=5.5V VI=VDD=5.0V Ports high impedance. Port RPD. VI=VSS VI=VSS VI=VSS 0.01
10.0
Conditions
Ratings
Unit
0.01
10.0
Continued next page. No.3620-5/12
LC7234
Continued from preceding page.
Parameter HOLD, ADI, port low-level input current low-level input current Port pull-down resistance Ports low-level output leakage current low-level output leakage current Ports high-level output leakage current Port high-level output leakage current AOUT high-level output leakage current high-level output leakage current Ports high-level output voltage Ports high-level output voltage COM1 COM2 high-level output voltage high-level output voltage high-level output voltage XOUT high-level output voltage Ports low-level output voltage Ports low-level output voltage Port low-level output voltage AOUT low-level output voltage COM1 COM2 low-level output voltage low-level output voltage low-level output voltage XOUT low-level output voltage COM1 COM2 mid-level output voltage converter error Supply current Hold-mode supply current Symbol IIL4 IIL5 IOFFL1 IOFFL2 IOFFH1 IOFFH2 IOFFH3 IOFFH4 VOH1 VOH2 VOH3 VOH4 VOH5 VOH6 VOL1 VOL2 VOL3 VOL4 VOL5 VOL6 VOL7 VOL8 IDD1 IDD2 VI=VSS VI=VSS VDD=5V VO=VSS VO=VSS VO=VDD VO=13V VO=13V VO=VDD IO=1 IO=1 IO=25µA IO=500µA IO=- 0.1mA IO=200µA IO=50µA IO=1mA IO=5mA IO=5mA, VAIN=1.3V IO=25µA IO=500µA IO=0.1mA IO=200µA VDD=5V, IO=20µA VDD=4.5 5.5V fI=130MHz, VDD=4.5 5.5V halted, tcyc=2.67µs halted, tcyc=13.33µs halted, tcyc=40.00µs Standby-mode supply current IDD3 VDD=5.5V, oscillator halted, Ta=25°C VDD=2.5V, oscillator halted, Ta=25°C
VDD-
VDD- 0.75 VDD- 0.75
Conditions
Ratings
Unit
0.01
10.0
0.01 10.0
VDD- VDD- VDD- VDD-
VDD- VDD- VDD-
0.75 (150)
(400)
0.75
+1/2
Test Circuits
Hold Mode
Notes Ports selected output ports. Ports S23, COM1 COM2 open.
No.3620-6/12
LC7234
Standby Mode
Note Ports S23, COM1 COM2 open.
Functional Description
Driver LC7234 drive segments. instructions transfer data outputs. instruction transfers data directly outputs. instruction converts data 7-segment format before transfer outputs. driver outputs. frame rate 100Hz with duty cycle. After reset power-up, blank signal present outputs. standby mode, outputs LOW. They used general-purpose outputs appropriate mask option selected. COM1 COM2 common driver outputs. Output drive duty with bias. Upon reset after power-up, normal drive signals present these outputs. standby mode, outputs LOW. Frequency Counter Frequency measurement performed HCTR input 20-bit universal counter. input frequency range 12MHz, which used measuring frequencies. Capacitive coupling should used. Phase-Locked Loop FMIN AMIN input signal divided down programmable divider, then compared with crystal frequency, which also divided down using selectable ratios. phase difference between signals measured using phase detector output FMIN input input signal. input frequency range 130MHz. Capacitive coupling should used. AMIN input. bandwidth adjustable ranges using instruction-HIGH 40MHz) band, (0.5 10MHz), bands. Capacitive coupling should used. Input/Output Ports Port This input port switching threshold, which used keypad matrix inputs. Pull-down resistors pins available mask option. Note that either none pins should have pull-down resistors. standby mode, inputs ignored. Ports These output ports have unbalanced CMOS outputs which used keypad matrix scan outputs. Upon reset, outputs LOW, standby mode, outputs high impedance. outputs short-circuited. Port transfer direction this input/output port selected automatically under software control. When input instruction (IN, TPT, TPF) executed, port configured input operation, output instruction (OUT, RPB), output operation. Upon reset, pins become inputs. standby mode, output drivers high impedance input signals ignored. bits should either inputs outputs.
No.3620-7/12
LC7234
Port transfer direction this input/output port selected instruction. Each this port independently input output. Upon reset, pins become inputs. standby mode, output drivers high impedance input signals ignored. Port This input port only. standby mode, inputs ignored. Port These output ports high-voltage, n-channel open-drain drivers, which used switching power supplies. Upon reset standby mode, outputs high impedance. Converter converter 6-bit successive approximation type. conversion cycle time 1.28 Full-scale output data input (63/96) VDD. Power-Fail Detection When connected supply, used power-fail detector. also used standard input port. Crystal Oscillator master crystal oscillator, which feedback resistor on-chip, requires only connection 4.5MHz crystal. Low-Power Modes Hold Mode When hold-mode control pin, HOLD, driven HOLDEN (hold enable) flip-flop previously been instruction, LC7234 enters hold mode. HOLD high-voltage input (VIH(max) 8.0V) which connected directly power supply. Standby Mode When LC7234 hold mode HOLD LOW, standby mode CKSTP instruction. Test Pins device test pins provided-TEST1 TEST2. These should either tied left open.
Instruction
ADDR Program memory address bits] Borrow Bank number bits] Carry Data memory address high-order bits (row address) bits] Data memory address low-order bits (column address) bits] Immediate data bits] Data memory address position bits] Port number bits] General register (Bank addresses 0FH) Register number bits] Contents register memory Contents register memory
No.3620-8/12
Mnemonic
Operand Notation Description Skip condition Subtract Compare (M), skip zero (M), skip skip zero skip
Compares contents skips they equal. Compares contents skips greater than equal Compares immediate data contents skips they equal. Compares contents with immediate data skips greater than equal
Operation
Instruction format
skip carry skip carry skip carry
Adds contents contents stores result Adds contents contents stores result Skips carry generated. Adds immediate data contents stores result Adds immediate data contents stores result Skips carry generated. Adds immediate data contents stores result Adds immediate data contents stores result Skips carry generated.
(M), skip carry
Adds contents contents stores result Skips carry generated.
Adds contents contents stores result
skip carry.
Carry
with carry.
with carry skip carry.
Carry
skip carry.
Carry
with carry.
AICS
with carry skip carry.
Carry
skip borrow skip borrow skip borrow (M), skip borrow
Subtract from
skip carry
Subtracts contents from contents stores result Subtracts contents from contents stores result Skips borrow generated. Subtracts contents from contents with borrow stores result Subtracts contents from contents with borrow stores result Skips borrow generated. Subtracts immediate data from contents stores result Subtracts immediate data from contents stores result Skips borrow generated. Subtracts immediate data from contents with borrow stores result Subtracts immediate data from contents with borrow stores result Skips borrow generated.
Subtract from skip borrow.
Borrow
LC7234
Subtract from with borrow.
Subtract from with borrow skip borrow.
Borrow
Subtract from
Subtract from skip borrow.
Borrow
Subtract from with borrow.
SIBS
Subtract from with borrow skip borrow.
Borrow
Skip equals
Skip greater than equal
SEQI
Skip equals
SGEI
Skip greater than equal
No.3620-9/12
Continued next page.
Continued from preceding page.
Instruction format
Mnemonic
Operand Notation Description Skip condition Logic arithmetic Load store
Moves contents Moves contents Moves contents address referenced Moves contents memory location referenced Moves contents memory location memory location Moves immediate data Moves contents registers.
Operation
Calculates logic-XOR contents stores result
Calculates logic-OR immediate data contents stores result
with
Calculates logic-AND immediate data contents stores result
with
Exclusive-OR with
test Jump subroutine Flag test Status register test Bank select
BANK
PLLr
[DH. DL1] [DH. DL2]
[DH, [DH,
Load into
Store
MVRD
Move addressed
MVRS
Move addressed
MVSR
Move
Move
Load registers.
skip M(N)
Test bits skip ture
skip M(N)
Tests bits memory location specified Skips bits logic Tests bits memory location specified Skips bits logic
bits specified bits specified
LC7234
Test bits skip false
ADDR bits)
ADDR
Jump address
ADDR bits)
ADDR Stack (PC) ADDR stack Skip timer Skip
Jumps address specified ADDR. Jumps subroutine specified ADDR. Returns from subroutine.
ADDR
Call subroutine
Return from subroutine
T
Test timer flip-flop
Tests timer flip-flop skips zero. Tests PLL-unlocked flip-flop skips zero.
Timer
Test flip-flop
status register bits
(Status register Sets bits status register specified (Status register Resets bits status register specified Skip (Status register Skip (Status register
Reset status register bits
Test status register bits skip true
Tests bits status register specified Skips bits Tests bits status register specified Skips bits
bits specified bits specified
Test status register bits skip false
BANK
Select bank
Selects four memory banks.
No.3620-10/12
Continued next page.
Continued from preceding page.
Instruction format
Mnemonic
Operand Notation Description Skip condition Input/output
Loads immediate data directly driver. Converts immediate data 7-segment format using then transfers driver. Moves data from input port Moves contents memory location port Sets bits port specified logic Sets bits port specified logic Tests bits port specified Skips bits logic Tests bits port specified Skips bits logic bits specified bits specified
Operation
Skip (port (Pn)) Skip (port (Pn))
Universal counter Miscellaneous
Stop clock HOLD
(port (Pn))
Move data segments.
(port (Pn))
(port (Pn))
(port (Pn))
DIGIT
(DIGIT)
DIGIT
(DIGIT)
Move 7-segment data LCD.
Move port data
Move data port.
port bits.
Reset port bits.
Test bits port skip true.
Test bits port skip false.
UCCW2
UCCW1.
UCCW1
Sets universal counter flag Sets universal counter flag
UCCW2.
Port direction control.
latch
Defines direction individual pins port port direction register FPC, corresponding port becomes output. Stops processor clock HOLD operation
CKSTP
Stop clock.
LC7234
operation
No.3620-11/12
LC7234
Mask Option
Parameter Watchdog timer (WDT) Pull-down resistors port (the keypad matrix input port) Instruction cycle time 2.67 Options
Parameter Instruction cycle time configuration 13.33 40.00 driver output port General-purpose otuput port Options
Development System LC7234 development environment shown following figure. uses LC72EV32 evaluation chip mounted TB-72EV32 target board multifunc-
tional emulator (RE32), which controlled personal computer, provide full debugging facilities.
Specifications SANYO products described contained herein stipulate performance, characteristics, functions described products independent state, guarantees performance, characteristics, functions described products mounted customer's products equipment. verify symptoms states that cannot evaluated independent device, customer should always evaluate test devices mounted customer's products equipment. SANYO Electric Co., Ltd. strives supply high-quality high-reliability products. However, semiconductor products fail with some probability. possible that these probabilistic failures could give rise accidents events that could endanger human lives, that could give rise smoke fire, that could cause damage other property. When designing equipment, adopt safety measures that these kinds accidents events cannot occur. Such measures include limited protective circuits error prevention circuits safe design, redundant design, structural design. event that SANYO products(including technical data,services) described contained herein controlled under applicable local export control laws regulations, such products must expor without obtaining expor license from authorities concerned accordance with above law. part this publication reproduced transmitted form means, electronic mechanical, including photocopying recording, information storage retrieval system, otherwise, without prior written permission SANYO Electric Co., Ltd. information described contained herein subject change without notice product/technology improvement, etc. When designing equipment, refer "Delivery Specification" SANYO product that intend use. Information (including circuit diagrams circuit parameters) herein example only guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties.
This catalog provides information August, 2001. Specifications information herein subject change without notice.
No.3620-12/12

LC7234 Single-chip Microcontroller with Driver Overview

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