LC72336, 72338 Single-Chip Microcontrollers with Built-In Driver
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Ordering number EN5157C
LC72336, 72338
Single-Chip Microcontrollers with Built-In Driver Circuits
Overview
LC72336 LC72338 single-chip microcontrollers electronic tuners. These products include chip circuit that operate duty drivers. They feature highly efficient instruction powerful hardware.
Package Dimensions
unit: 3174-QFP80E
[LC72336, 72338]
Functions
High-speed programmable divider Program memory (ROM) LC72336: 6143 bits LC72338: 8191 bits Data memory (RAM): bits instructions one-word instructions Cycle time: 1.33 Stack: levels drivers: segments (1/3 duty, bias) Serial I/O: channels (8-bit 3-wire type) External interrupts: interrupts (INT0, INT1) Interrupt rising falling edge (selectable) Internal interrupts: interrupt built-in timer interrupts serial interrupt Nested interrupt levels: levels converter: channels (8-bit output) converter: channels (6-bit successive approximation) General-purpose ports: Input ports: Output ports: maximum) ports: maximum, switched between input output units.) block: Supports types dead zone control, includes built-in unlock detection circuit. Supports different reference frequencies. Universal counter: bits (Can used either frequency period measurement.) Timers: Eight types time measurement Beep function: beep tones Reset: Built-in voltage detection type reset circuit Halt mode: Stops controller operating clock. Operating supply voltage: (3.5 only controller block operates.)
SANYO: QIP80E
This easily that SANYO's original format.
trademark SANYO ELECTRIC CO., LTD. SANYO's original format addresses controlled SANYO.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, JAPAN
O3097HA (OT)/13095HA (OT) 5157-1/16
LC72336, 72338 Assignment
Vdd1 Vdd2
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LC72336, 72338 Block Diagram
Vdd1 Vdd2
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Specifications
Absolute Maximum Ratings 25°C,
Parameter Maximum supply voltage Input voltage Output voltage Symbol VOUT VOUT IOUT IOUT Output current IOUT IOUT IOUT Allowable power dissipation Operating temperature Storage temperature Note: Reference value Topr Tstg input pins Port output ports other than VOUT Port EO1, Ports COM1 COM3 85°C Conditions Ratings -0.3 +6.5 -0.3 -0.3 -0.3 +125 Unit
Allowable Operating Ranges +85°C,
Parameter Symbol Supply voltage Input high-level voltage Input low-level voltage Input frequency Input amplitude Input voltage range Conditions operating operating Memory retention Ports HCTR LCTR (when selected input) Ports LCTR (frequency measurement mode), HOLD Port Port HCTR LCTR (when selected input) Port LCTR (frequency measurement mode) HOLD FMIN: (2), FMIN: (3), AMIN (H): (3), AMIN (L): (3), HCTR: (3), LCTR: (3), LCTR (frequency measurement mode): (2), (2), FMIN FMIN, AMIN, HCTR, LCTR ADI0 ADI3 0.10 0.07 +1.3 Unit Vrms Vrms Vrms
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LC72336, 72338 Electrical Characteristics Allowable Operating Ranges
Parameter Symbol Input high-level current Conditions XIN: FMIN, AMIN, HCTR, LCTR: Ports SNS, HOLD, HCTR, LCTR: pull-down resistors port with input mode selected ports With pull-down resistors port XIN: FMIN, AMIN, HCTR, LCTR: Ports SNS, HOLD, HCTR, LCTR: pull-down resistors port VSS, with input mode selected ports With pull-down resistors port With pull-down resistors port Ports LCTR frequency measurement mode) Ports Ports EO1, EO2: -500 XOUT: -200 S32: COM1, COM2, COM3: -100 Ports Ports EO1, EO2: XOUT: S32: COM1, COM2, COM3: Port S32: S32: COM1, COM2, COM3: ±100 COM1, COM2, COM3: ±100 Ports Port ADI0 ADI3: TEST1, TEST2 (1): MHz, 25°C (2): halt mode*, 25°C (Fig. oscillator stopped, 25°C (Fig. oscillator stopped, 25°C (Fig. 0.45 0.75 -3.0 -100 -5.0 -1/2 +3.0 +100 +5.0 +1/2 Unit
Input low-level current Input floating voltage Pull-down resistance Hysteresis Output high-level voltage Output low-level voltage VMID VMID Output mid-level voltage VMID VMID IOFF Output leakage current IOFF IOFF conversion error Reject pulse width Power-down detection voltage Pull-down resistance PREJ VDET Current drain
0.05
Note: case instruction execution steps intervals with PLL, counter functions other functions stopped.
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Note: Except divider resistors used bias voltage generation circuit incorporated Vdd1 Vdd2 systems.
Vdd1 common segment drivers Vdd2 loss these resistor excluded
Test Circuits
Note: With ports other than those indicated figure open. With segment port function selected ports With output function selected ports
Note: With ports other than those indicated figure open. With segment port function selected ports With output function selected ports
Figure IDD2, IDD3, IDD4 Hold Mode
Figure IDD5 Backup Mode
Functions
Symbol type Function These special-purpose ports return signal inputs. Their threshold voltage lower than that other inputs. When matrix formed conjunction with ports three simultaneous presses detected. pull-down resistors four pins instruction b1). This cannot specified individual basis. Input disabled clock stop mode. Unbalanced CMOS push-pull circuits These special-purpose ports return signal outputs. diodes preventing short-circuits multiple simultaneous presses required since output transistor circuits unbalanced CMOS circuits. These pins become high-impedance outputs clock stop mode. These pins function high-impedance outputs after power-on reset retain that state until output instruction executed.
Inputs with pull-down resistors
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Symbol type Function
Shared-function general-purpose output serial port Inputs Schmitt input. instruction used switch between general-purpose port function serial function, well between input output general-purpose port function. When used general-purpose port: Input output specified units (bit I/O). These ports general-purpose ports with instruction with SI/O0 General-purpose ports SI/O ports instruction used specify input output units. Input Output When used serial port: These ports serial ports with instruction with contents serial data buffers saved loaded with OUTR instructions. Note: setup states when used serial ports: General-purpose SCK0 output internal clock mode SCK0 input external clock mode output input These ports input disabled high-impedance state clock stop mode. These ports function general-purpose input ports after power-on reset.
PG1/SCK0 PG2/SO0 PG3/SI0 CMOS push-pull
XOUT
crystal oscillator connections
Charge pump outputs CMOS tristate These pins high-impedance state when HOLD hold enable state. These pins high-impedance state clock stop mode, after power-on reset, stopped state.
Power supply connections
(local oscillator) input This selected band using instruction field. AMIN CMOS amplifier input (SW) (MW, Band
input signal must capacitor coupled. Input disabled HOLD HOLD enabled state. Input disabled clock stop mode, after power-on reset, stopped state.
(local oscillator) input This selected using instruction field don't care). FMIN CMOS amplifier input input signal must capacitor coupled. Input disabled HOLD HOLD enabled state. Input disabled clock stop mode, after power-on reset, stopped state.
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Symbol type Function
Shared-function voltage sensing input general-purpose input port input threshold voltage lower than that other inputs. When used voltage sensing pin: This used recognize power failures recovery from backup (clock stop) mode. internal sensing flip-flop used this determination. instruction (b2) used test sense flip-flop. When used general-purpose input port: instruction (b3) test this when used general-purpose input port. Unlike other input ports, input disabled during clock stop mode power-on reset. Thus applications must take through currents into consideration this used general-purpose input port.
CMOS input
Shared-function universal counter (frequency period measurement) generalpurpose input port instruction used switch this between universal counter general-purpose input port functions. When used frequency measurement: Select universal counter function with instruction LCTR frequency measurement mode with instruction After selecting measurement time, start counter with instruction. CNTEND flag will when count completes. Since this circuit operates amplifier this mode, input must capacitor coupled. LCTR CMOS amplifier input When used period measurement: With universal counter function selected, period measurement mode with instruction After selecting measurement time, start counter with instruction. CNTEND flag will when count completes. Since bias feedback resistor switched this mode, input must coupled. When used general-purpose input port: Specify general-purpose input port function with instruction (b1) internal register (address 0EH) input instruction read input data. Input disabled clock stop mode. (The input pulled down.) universal counter function selected after power-on reset. (HCTR frequency measurement mode.)
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Symbol type Function
Shared-function universal counter input general-purpose input port instruction used switch this between universal counter general-purpose input port functions. When used frequency measurement: Select universal counter function with instruction HCTR frequency measurement mode with instruction After selecting measurement time, start counter with instruction. CNTEND flag will when count completes. Since this circuit operates amplifier this mode, input must capacitor coupled. When used general-purpose input port: general-purpose input port function with instruction (b1) internal register (address 0EH) input instruction read input data. Input disabled clock stop mode. (The input pulled down.) universal counter function selected after power-on reset.
HCTR
CMOS amplifier input
Controls circuit clock stop mode. When this hold enabled state, FMIN AMIN input disabled goes high-impedance state. switch clock stop mode, HOLDEN flag, this low, execute CKSTP instruction. this high clear clock stop mode.
HOLD
CMOS input
Shared-function general-purpose input converter input port instruction used switch these pins between general-purpose converter input port functions. When used general-purpose input port: general-purpose input port function units) with instruction PH0/ADI0 PH1/ADI1 PH2/ADI2 PH3/ADI3 CMOS input Analog input When used converter input: converter input port function with instruction Specify convert with instruction Start conversion with instruction (b2). ADCE flag when conversion completed. Note: Since input disabled, will always returned input instruction (the instruction) executed port specified converter input. other words, port must general-purpose input function before input instruction executed.) Input disabled clock stop mode. general-purpose input function selected after power-on reset.
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Symbol type Function Shared-function general-purpose converter output port instruction used switch these pins between general-purpose converter output port functions. Since these pins open drain circuits, pull-up resistors required external circuits accepting these outputs. PJ0/DAC0 PJ1/DAC1 PJ2/DAC2 PJ3/DAC3 N-channel open drain When used general-purpose port: general-purpose input port function with instruction When used converter output: instruction switch port units. converter data loaded into DAC0 DAC3 specified with instruction. Although waveform output soon port switched, after data loaded, data prior that load output (1/8.79 kHz). clock stop mode, these outputs transistor (high output) state. general-purpose output port function selected after power-on reset, outputs transistor (high output) state.
Shared-function general-purpose external interrupt port There instruction that switches between general-purpose port external interrupt functions. Rather, corresponding becomes input-only (output disabled) point where external interrupt enable flag that set. When used general-purpose port: Input output specified units (bit I/O). instruction used specify input output units. CMOS push-pull When used external interrupt pins: These pins enabled setting external interrupt enable flags (INT0EN INT1EN) status register that point automatically input port. status register interrupt enable flag (INTEN) must also enable interrupt operation. instruction INT1, INT0) select rising falling edge detection. Input disabled with pins high-impedance state clock stop mode. general-purpose input port function selected after power-on reset.
PK0/INT0 PK1/INT1
Vdd1 Vdd2 TEST1 TEST2 COM1 COM2 COM3
Apply drive bias voltage this pin. Apply drive bias voltage this pin. test This must left open connected ground. driver common output pins
CMOS 3-value output
This drive circuit implements 1/3-duty, 1/3-bias drive scheme. These pins fixed level clock stop mode. These pins fixed level after power-on reset. driver segment output pins This drive circuit implements 1/3-duty, 1/3-bias drive scheme.
CMOS 3-value output
frame frequency These pins fixed level clock stop mode. These pins fixed level after power-on reset.
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Symbol type Function
Shared-function driver segment output, general-purpose I/O, serial port instruction used switch between driver segment output, generalpurpose I/O, serial functions, switch between input output general-purpose input port function. When used segment output: function specified units. Segment output specified with instruction 0DH). S17/PE0 Segment output S18/PE1 output S19/PE2 S20/PE3 When used general-purpose port: Input output specified units (1-bit I/O). general-purpose port function specified with instruction SI/O2 General-purpose port SI/O port Input output specified with instruction units. Input Output When used serial port: serial port function specified with instruction contents serial data buffer saved loaded with OUTR instructions. Note: setup states when used serial port: General-purpose SCK2 output internal clock mode SCK2 input external clock mode output input clock stop mode, this port used general-purpose port serial port, pins input disabled high-impedance state. used segment output, pins fixed level. segment output port function selected after power-on reset.
S17/PE0 S18/PE1/SCK2 S19/PE2/SO2 S20/PE3/SI2
CMOS 3-value output push-pull
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Symbol type Function
Shared-function driver segment output, general-purpose I/O, serial port inputs Schmitt inputs. instruction used switch between driver segment output, generalpurpose I/O, serial functions, switch between input output general-purpose input port function. When used segment output: function specified 4-bit units. Segment output specified with instruction 0EH). S24/PF0 Segment output output When used general-purpose port: Input output specified units (1-bit I/O). general-purpose port function specified with instruction SI/O1 General-purpose port SI/O port Input output specified with instruction units. Input Output When used serial port: serial port function specified with instruction contents serial data buffer saved loaded with OUTR instructions. Note: setup states when used serial port: General-purpose SCK1 output internal clock mode SCK1 input external clock mode output input clock stop mode, this port used general-purpose port serial port, pins input disabled high-impedance state. used segment output, pins fixed level. segment output port function selected after power-on reset.
S21/PF0 S22/PF1/SCK1 S23/PF2/SO1 S24/PF3/SI1 CMOS 3-value output push-pull
Shared-function driver segment output general-purpose port instruction used switch between driver segment output general-purpose functions, switch between input output generalpurpose input port function. When used segment output: function specified 4-bit units. Segment output specified with instruction 0EH). S28/PM0 Segment output output When used general-purpose port: Input output specified units (1-bit I/O). Input output specified with instruction units. Input Output clock stop mode, this port used general-purpose port, pins input disabled high-impedance state. used segment output, pins fixed level. segment output port function selected after power-on reset.
S25/PM0 S26/PM1 S27/PM2 S28/PM3 CMOS 3-value output push-pull
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Symbol type Function
Shared-function segment output, general-purpose output, beep tone output port instruction used switch between segment output port functions. BEEP instruction used switch between general-purpose output port beep tone output functions. When used segment output: function specified 3-bit units. Segment output specified with instruction 0EH). S32/PN0 Segment output output CMOS 3-value output push-pull When used general-purpose output port: general-purpose output port function selected with BEEP instruction dedicated general-purpose output function pins. When used BEEP output pin: Beep tone output specified with BEEP instruction frequency specified with BEEP instruction (b0, b2). When beep tone function specified, executing output instruction will only overwrite contents internal latch. will have effect output whatsoever. clock stop mode, this port used general-purpose output port, pins input disabled high-impedance state. used segment output, pins fixed level. segment output port function selected after power-on reset.
S29/PN0/BEEP S30/PN1 S31/PN2 S32/PN3
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LC72336, 72338 LC723336 LC72338 Instruction Table Abbreviations: ADDR: Program memory address Borrow Carry Data memory address high (row address) bits] Data memory address (column address) bits] Immediate data bits] Data memory address position bits] Port number bits] General register (one locations bank) Register number bits] Contents register memory Contents register memory
Instruction group Operand Mnemonic Addition instructions AICS then skip carry with carry with carry, then skip carry then skip carry with carry with carry, then skip carry Subtract from Subtract from then skip borrow Subtract from with borrow Subtract from with borrow, then skip borrow Subtract from Subtract from then skip borrow Subtract from with borrow Subtract from with borrow, then skip borrow Skip equal Skip equal Skip equal Skip greater than equal Skip greater than equal Skip less than skip carry skip carry skip carry skip carry skip borrow skip borrow skip borrow skip borrow skip zero skip zero skip zero skip borrow skip borrow skip borrow Function Operation Machine code
Subtraction instructions
SIBS
Comparison instructions SEQI SNEI SGEI SLEI
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Instruction group Operand Mnemonic Logical operation instructions ANDI EXLI Transfer instructions MVRD with with with with Exclusive with Exclusive with Load Store Move destination referring same Move source referring same Move same Move Test bits, then skip bits specified true Test bits, then skip bits specified false Jump address Call subroutine Return from subroutine Return from subroutine skip Return from subroutine with bank data Return from subroutine with bank data skip Return from interrupt [DH, Function Operation Machine code
MVRS
[DH, [DH, DL1] [DH, DL2] "1", then skip "0", then skip ADDR Stack (PC) Stack Stack Stack BANK Stack Stack BANK Stack Stack BANK Stack CARRY Stack (Status (Status (Status "1", then skip (Status "0", then skip
MVSR test instructions
RTBS
Jump subroutine call instructions
ADDR ADDR
ADDR bits) ADDR bits)
Status register instructions test instruction
status register Reset status register Test status register true Test status register false
Test unlock then skip been
Unlock "0", then skip
Internal register transfer instructions
OUTR
Load registers
data data
Input register/port data Output contents register/port
reg)
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Instruction group Operand Mnemonic Hardware control instructions BEEP Bank switching instruction Serial control UCCW1 UCCW2 Beep control Dead zone control port control word UCCW1 UCCW2 BEEP Timmer Function Operation Machine code
BANK
Select bank
BANK
LCDA control instructions LCDB LCPA LCPB instructions
Output segment pattern digit direct Output segment pattern digit through Logic Array Input port data Output contents port port bits Reset port bits Test port bits, then skip bits specified true Test port bits, then skip bits specified false Halt mode control Clock stop
(DIGIT) (DIGIT) Logic Array (Pn) (Pn) (Pn) (Pn) "1", then skip (Pn) "0", then skip HALT then clock stop Stop X'tal HOLD Shift right with carry
DIGIT DIGIT DIGIT DIGIT
Other instructions
HALT CKSTP
operation
operation
products described contained herein intended surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment like, failure which directly indirectly cause injury, death property loss. Anyone purchasing products described contained herein above-mentioned shall: Accept full responsibility indemnify defend SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees, jointly severally, against claims litigation damages, cost expenses associated with such use: impose responsibility fault negligence which cited such claim litigation SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees jointly severally. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties. This catalog provides information November, 1997. Specifications information herein subject change without notice. 5157-16/16
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