LC72322R, 72323R Single-Chip Microcontroller with Driver Ove

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LC72322R, 72323R Single-Chip Microcontroller with Driver Ove

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Ordering number EN5378
LC72322R, 72323R
Single-Chip Microcontroller with Driver
Overview
LC72322R LC72323R single-chip microcontrollers electronic tuning applications. These include chip both drivers circuit that operate MHz. LC72322R LC72323R feature that these reversed pinassignment versions LC72322 LC72323 respectively have equal functions specifications theirs respectively.
Functions
Stack: Eight levels Fast programmable divider General-purpose counters: HCTR frequency measurement LCTR frequency period measurement driver displays with segments (1/2 duty, bias) Program memory (ROM): 4095 16-bit digits: LC72322R 3071 16-bit digits: LC72323R Data memory (RAM): 4-bit digits instructions single-word instructions Cycle time: 2.67 13.33 40.00 (option) Unlock 0.55 detection, detection Timer 5ms, 25ms, 125ms Input ports*: dedicated input port high-breakdown voltage port Output ports*: dedicated output ports, high-breakdown voltage open-drain port
CMOS output ports which switched used driver outputs) Seven CMOS output ports (mask option switchable ports) ports*: switchable between input output four-bit units switchable between input output units Note: Each port consists four bits. Program runaway detected special address (Programmable watchdog timer). Voltage detection type reset circuit 6-bit converter 8-bit converters (PWM): LC72322R only external interrupt Hold mode backup Sense hot/cold startup determination PLL: CPU: RAM: LC72P321R used Package: QIP80DR
Package Dimensions
unit: 3223-QFP80DR
[LC72322R, LC72323R]
This easily that SANYO's original format.
trademark SANYO ELECTRIC CO., LTD. SANYO's original format addresses controlled SANYO. SANYO: QIP80DR
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, JAPAN
93096HA (OT) 5378-1/13
LC72322R, 72323R Assignment
5378-2/13
LC72322R, 72323R Block Diagram
5378-3/13
LC72322R, 72323R
Specifications
Absolute Maximum Ratings 25°C,
Parameter Maximum supply voltage Input voltage Symbol VIN1 VIN2 VOUT1 VOUT2 IOUT1 Output current IOUT2 IOUT3 IOUT4 Allowable power dissipation Operating temperature Storage temperature Topr Tstg HOLD, INT, RES, ADI, SNS, port Inputs other than VIN1 port Outputs other than VOUT1 port pins port pins port pins port pins +85°C Conditions Ratings -0.3 +6.5 -0.3 -0.3 -0.3 -0.3 +125 Unit
Output voltage
Allowable Operating Ranges +85°C,
Ratings Parameter Symbol VDD1 Supply voltage VDD2 VDD3 VIH1 VIH2 VIH3 Input high level voltage VIH4 VIH5 VIH6 VIL1 VIL2 VIL3 Input level voltage VIL4 VIL5 VIL6 VIL7 fIN1 fIN2 fIN3 Input frequency fIN4 fIN5 fIN6 fIN7 fIN8 VIN1 VIN2 Input amplitude VIN3 VIN4, VIN6, Input voltage range VIN8 Conditions operating operating Memory retention voltage port RES, INT, HOLD port PE0, ports LCTR (period measurement), VDD1, port RES, INT, PE1, port PE0, ports LCTR (period measurement), VDD1 HOLD FMIN, VIN2, VDD1 FMIN, VIN3, VDD1 AMIN (L), VIN4, VDD1 AMIN (H), VIN5, VDD1 HCTR, VIN6, VDD1 LCTR (frequency), VIN7, VDD1 LCTR (period), VIH6, VIL6, VDD1 FMIN FMIN AMIN LCTR, HCTR 0.50 0.10 0.15 0.10 0.10 Unit Vrms Vrms Vrms Vrms Vrms
5378-4/13
LC72322R, 72323R Electrical Characteristics Allowable Operating Ranges
Ratings Parameter Hysteresis Rejected pulse width Power-down detection voltage Symbol PREJ VDET IIH1 IIH2 Input high level current IIH3 IIH4 IIH5 IIL1 Input level current IIL2 IIL3 IIL4 Input floating voltage Pull-down resistance IOFFH1 Output high level leakage current IOFFH2 IOFFH3 Output level leakage current IOFFL1 IOFFL2 VOH1 VOH2 VOH3 Output high level voltage VOH4 VOH5 VOH6 VOH7 VOL1 VOL2 VOL3 Output level voltage VOL4 VOL5 VOL6 VOL7 VOL8 Output middle level voltage conversion error IDD1 IDD2 IDD3 Current drain IDD4 INT, HOLD, RES, ADI, SNS, port: ports: ports with outputs off, port with RPD, XIN: FMIN, AMIN, HCTR, LCTR: port: With RPD, INT, HOLD, RES, ADI, SNS, port: ports: ports with outputs off, port with RPD, XIN: FMIN, AMIN, HCTR, LCTR: port: With port: With RPD, EO1, EO2: ports: port: EO1, EO2: ports: ports: ports: EO1, EO2: XOUT: port: -0.1 port: COM1, COM2: ports: ports: EO1, EO2: XOUT: port: port: COM1, COM2: port: VDD1 COM1, COM2: ADI: VDD1 VDD1, fIN2 VDD2, stopped, 2.67 (HOLD mode, Figure VDD2, stopped, 13.33 (HOLD mode, Figure VDD2, stopped, 40.00 (HOLD mode, Figure oscillator stopped, 25°C (BACK mode, Figure oscillator stopped, 25°C (BACK mode, Figure (150 0.75 -1/2 0.75 0.75 (400 +1/2 0.01 0.01 0.05 Conditions LCTR (period), RES, INT, PE1, Unit
IDD5
5378-5/13
LC72322R, 72323R Test Circuits
Note: open. However, specified output.
Figure IDD2 IDD4 HOLD Mode
Note: COM1, COM2 open.
Figure IDD5 BACK Mode
5378-6/13
LC72322R, 72323R Functions
Functions circuit type
Low-threshold type dedicated input ports These pins used, example, data acquisition. Built-in pull-down resistors specified option. This option 4-pin units, cannot specified individual pins. Input through these pins disabled BACKUP mode. Input
Dedicated output ports Since output transistor impedances unbalanced CMOS, these pins effectively used functions such scan timing. These pins output highimpedance state BACKUP mode. These pins level during reset, i.e., when low. Output
Dedicated output ports These normal CMOS outputs. These pins output high-impedance state BACKUP mode. These pins level during reset, i.e., when low.
ports These pins switched between input output follows: Once input instruction (IN, TPT, TPF) executed, these pins latch input mode. Once output instruction (OUT, SPB, RPB) executed, they latch output mode. These pins input mode during reset, i.e., when low. BACKUP mode these pins input mode with input disabled.
ports These pins switched between input output instruction. states this port specified individual pins. These pins input mode during reset, i.e., when low. BACKUP mode these pins input mode with input disabled.
Dedicated input ports Input through these pins disabled BACKUP mode. Input
Continued next page. 5378-7/13
LC72322R, 72323R
Continued from preceding page.
Dedicated output ports Since these pins high-breakdown voltage n-channel transistor open-drain outputs, they effectively used functions such band power supply switching. And, also used DAC1 DAC2 output ports respectively. contained LC72322R only.) These ports high impedance state during reset, i.e., when low, BACKUP mode. Output Functions circuit type
PH2/DAC*1 PH3/DAC*2
Dedicated output ports While these pins have CMOS output circuit structure, they switched function drivers. Their function switched instructions. These pins cannot switched individually. driver function selected segment-off signal output when power first applied when low. These pins held level BACKUP mode. Note that when general-purpose port option specified, these pins output contents IPORT when contents general-purpose output port LATCH when Output
PI0/S25 PI1/S26 PI2/S27 PI3/S28
driver segment outputs frame frequency duty, bias drive type used. segment-off signal output when power first applied when low. These pins held level BACKUP mode. these pins general-purpose output ports specified option. Output
driver common outputs COM1 COM2 duty, bias drive type used. output when power first applied when identical normal operating mode output. These pins held level BACKUP mode. Output
FMIN
(local oscillator) input input must capacitor coupled. input frequency range from MHz. (Max. MHz) (local oscillator) input input must capacitor coupled Input
AMIN
band supported this selected using instruction. High MHz) (0.5 MHz)
Continued next page. 5378-8/13
LC72322R, 72323R
Continued from preceding page.
Universal counter input HCTR input must capacitor coupled. input frequency range from MHz. This input effectively used counting. Universal counter input input must capacitor coupled input frequencies range kHz. LCTR Capacitor coupling required input frequencies from kHz. This input effectively used counting. Input Functions circuit type
converter input 1.28 period required 6-bit sequential comparison conversion. full scale input ((63/96) VDD) data value 3FH. Input
External interrupt request input interrupt generated when INTEN flag instruction) falling edge input. Input
Reference frequency programmable divider phase comparison error outputs Charge pump circuits built same. Output
Input used determine power outage occurred BACKUP mode This also used normal input port.
Input
Input used force HOLD mode HOLD goes HOLD mode when HOLDEN flag instruction) HOLD input goes low. high-breakdown voltage circuit used that this input used conjunction with normal power switch. System reset input This signal should held after power first applied effect power-up reset. reset starts when level been input least reference clock cycles. Input Input
XOUT
Crystal oscillator connections (4.5 MHz) feedback resistor built
Input Output
TEST1 TEST2
test pins. These pins must connected VSS.
Power supply
5378-9/13
LC72322R, 72323R Mask Options
Description (watchdog timer) inclusion selection Selections included Pull-down resistors included pull-down resistors 2.67 Cycle time selection 13.33 40.00 port/general-purpose port selection ports General-purpose output ports
Port pull-down resistor inclusion selection
Development Environment LC72P321R used OTP. LC72EV321 used evaluation chip. total debugging system available which TB-72EV32 evaluation chip board RE32 multifunction emulator controlled personal computer.
5378-10/13
LC72322R, 72323R LC72322R, 72323R Instruction Table Abbreviations: ADDR: Program memory address bits] Borrow Bank number bits] Carry Data memory address high (row address) bits] Data memory address (column address) bits] Immediate data bits] Data memory address position bits] Port number bits] General register (one locations bank Register number bits] Contents register memory Contents register memory
Instruction Group Operand Mnemonic Addition instructions AICS then skip carry with carry with carry, then skip carry then skip carry with carry with carry, then skip carry Subtract from Subtract from then skip borrow Subtract from with borrow Subtract from with borrow, then skip borrow Subtract from Subtract from then skip borrow Subtract from with borrow Subtract from with borrow, then skip borrow Skip equals Skip greater than equal Skip equal Skip greater than equal skip carry skip carry skip carry skip carry skip borrow skip borrow skip borrow skip borrow skip zero skip borrow skip zero skip borrow Function Operation Machine code
Subtraction instructions
SIBS
Comparison instructions
SEQI
SGEI
Continued next page. 5378-11/13
LC72322R, 72323R
Continued from preceding page.
Instruction Group Operand Mnemonic Transfer instructions MVRD with with Exclusive with Load Store Move destination referring same Move source referring same Move same Move Load registers Test bits, then skip bits specified true Test bits, then skip bits specified false Jump address Call subroutine Return from subroutine Return from interrupt Test timer then skip been Test unlock then skip been status register Reset status register Test status register true Test status register false [DH, Function Operation Machine code
Logical operation instructions
MVRS
[DH, [DH, DL1] [DH, DL2] DATA then skip then skip ADDR Stack (PC) Stack BANK Stack Stack CARRY Stack timer then skip then skip (Status register (Status register (Status register then skip (Status register then skip
MVSR
test instructions
ADDR bits) ADDR bits)
ADDR ADDR
Jump subroutine call
test instructions
T
Status register instructions
Bank switching instructions
BANK
Select bank
BANK
Continued next page. 5378-12/13
LC72322R, 72323R
Continued from preceding page.
Instruction Group Operand Mnemonic instructions Output segment pattern digit direct Output segment pattern digit through Input port data Output contents port port bits Reset port bits Test port bits, then skip bits specified true Test port bits, then skip bits specified false UCCW1 (DIGIT) (DIGIT) (Port (P)) (Port (P)) (Port (P)) (Port (P)) (Port (P)) then skip (Port (P)) then skip Function Operation DIGIT DIGIT Machine code
Universal counter instructions
UCCW1
UCCW2 port control Clock stop
UCCW2 latch Stop clock HOLD DATA
Other instructions
CKSTP DAC*
Load registers operation
Note: contained LC72322R only.
products described contained herein intended surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment like, failure which directly indirectly cause injury, death property loss. Anyone purchasing products described contained herein above-mentioned shall: Accept full responsibility indemnify defend SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees, jointly severally, against claims litigation damages, cost expenses associated with such use: impose responsibility fault negligence which cited such claim litigation SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees jointly severally. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties. This catalog provides information November, 1997. Specifications information herein subject change without notice. 5378-13/13

LC72322R, 72323R Single-Chip Microcontroller with Driver Ove

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