LC72144M Frequency Synthesizer Overview LC72144M electr

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LC72144M Frequency Synthesizer Overview LC72144M electr

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Ordering number EN5377B
LC72144M
Frequency Synthesizer
Overview
LC72144M electronic tuning frequency synthesizer home products, allows high-performance multifunction tuners implemented easily, since includes converter, high-speed lockup circuit, crystal oscillator circuit that support up-conversion.
Package Dimensions
unit: 3112-MFP24S
[LC72144M]
Features
High-speed programmable dividers FMIN using pulse swallower 40.0 AMIN using pulse swallower direct division General-purpose counters HCTR 25.0 frequency measurement LCTR frequency measurement period measurement 4.5, 7.2, 10.25 10.35 crystal Twelve selectable reference frequencies 3*2, 9*2, 3.125, 6.25, 12.5, 30*2, 100*1 kHz) Note: supported when 10.35 10.25 crystal oscillator used. supported when 10.25 crystal oscillator used. Phase comparator Insensitive band control Unlock detection Sub-charge pump high-speed locking Deadlock clear circuit converter: bits, inputs Serial data input output Supports control communication format Power-on reset circuit On-chip crystal oscillator output buffer Inputs/outputs (using general-purpose input/output ports) Operating ranges Power-supply voltage: Operating temperature: 85°C Package: MFP24S
trademark SANYO ELECTRIC CO., LTD. SANYO's original format addresses controlled SANYO.
SANYO: MFP24S
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, JAPAN
82097HA (OT)/N3096HA (OT)/73096HA (OT) 5377-1/22
LC72144M Assignment
Block Diagram
5377-2/22
LC72144M
Specifications
Absolute Maximum Ratings 25°C,
Parameter Supply voltage Symbol VIN1 Maximum input voltage VIN2 VIN3 Maximum output voltage Maximum output current Allowable power dissipation Operating temperature Topr XIN, FMIN, AMIN, HCTR/I-6, LCTR/I-7, I/O-0, I/O-4, I/O-5, ADC0, ADC1 I/O-1 I/O-3 XOUT, I/O-0, I/O-4, I/O-5, PD0, PD1, PDS, XBUF I/O-1 I/O-3 I/O-0, I/O-4, I/O-5, XBUF I/O-1 I/O-3 85°C Conditions Ratings -0.3 +7.0 -0.3 +7.0 -0.3 -0.3 -0.3 +7.0 -0.3 -0.3 +125 Unit
Storage temperature Tstg Note: capacitor least 2000 must inserted between power supply, VDD, VSS.
Allowable Operating Ranges 85°C,
Parameter Supply voltage Symbol VDD1 VDD2 VIH1 Input high-level voltage VIH2 VIH3 Input low-level voltage VIL1 VIL2 fIN1 fIN2 Input frequency fIN3 fIN4 fIN5 fIN6 Guaranteed crystal oscillator ranges Xtal1 Xtal2 VIN1 VIN2-1 VIN2-2 VIN3-1 VIN3-2 Input amplitudes VIN3-3 VIN3-4 VIN4-1 VIN4-2 VIN5-1 VIN5-2 VIN5-3 Input voltage range Note: VIN6 VDD: Serial data hold voltage I/O-1 I/O-3 I/O-0, I/O-4, I/O-5, HCTR/I-6, LCTR/I-7 LCTR/I-7: Pulse waveform, I/O-0 I/O-5, HCTR/I-6, LCTR/I-7 LCTR/I-7: Pulse waveform, I/O-1 I/O-3 XIN: Sine wave, capacitor coupled FMIN: Sine wave, capacitor coupled AMIN: Sine wave, capacitor coupled HCTR/I-6: Sine wave, capacitor coupled LCTR/I-7: Sine wave, capacitor coupled LCTR/I-7: Pulse waveform, coupled, XIN, XOUT: XIN, XOUT: FMIN: MHz, FMIN: MHz, AMIN: MHz, AMIN: MHz, AMIN: MHz, AMIN: MHz, HCTR/I-6: MHz, HCTR/I-6: MHz, LCTR/I-7: kHz, LCTR/I-7: kHz, LCTR/I-7: kHz, ADC0, ADC1 Conditions 10.5 1500 1500 1500 1500 1500 1500 1500 1500 1500 1500 1500 1500 Unit mVrms mVrms mVrms mVrms mVrms mVrms mVrms mVrms mVrms mVrms mVrms mVrms
Output voltage
Period measurement Refer item structure programmable divider. Serial data: Serial data:
Continued next page. 5377-3/22
LC72144M
Continued from preceding page.
Parameter Data setup time Data hold time Clock low-level time Clock high-level time wait time setup time hold time Data latch change time Data output time Note: Refer serial data timing. Symbol Differs depending values pull-up resistor printed circuit board capacitances. Conditions 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 Unit
Electrical Characteristics Allowable Operating Ranges
Parameter Symbol Built-in feedback resistors Hysteresis VHIS VOH1 VOH2 VOL1 VOL2 Low-level output voltage VOL3 I/O-1 I/O-3 FMIN AMIN HCTR/I-6 LCTR/I-7 LCTR/I-7 -0.5 High-level output voltage PD0, PD1, PDS, I/O-0, I/O-4, I/O-5 XBUF -0.5 PD0, PD1, PDS, I/O-0, I/O-4, I/O-5 XBUF VOL4 IIH1 IIH2 High-level input current IIH3 IIH4 IIH5 IIH6 IIL1 IIL2 Low-level input current IIL3 IIL4 IIL5 IIL6 Output leakage current IOFF1 IOFF2 I/O-1 I/O-3: I/O-0, I/O-4, I/O-5, ADC0, ADC1, HCTR/I-6, LCTR/I-7: XIN: FMIN, AMIN: HCTR/I-6, LCTR/I-7: I/O-0, I/O-3: I/O-0, I/O-4, I/O-5, ADC0, ADC1, HCTR/I-6, LCTR/I-7: XIN: FMIN, AMIN: HCTR/I-6, LCTR/I-7: I/O-1 I/O-3: Conditions Unit
Continued next page.
5377-4/22
LC72144M
Continued from preceding page.
Parameter High-level 3-state leakage current Low-level 3-state leakage current Input capacitance converter linearity error Pull-down transistor resistance Symbol IOFFH IOFFL Rpd1 Rpd2 IDD1 Current drain IDD2 IDD3 Conditions PD0, PD1, PDS: PD0, PD1, PDS: FMIN ADC0, ADC1 FMIN AMIN VDD: Xtal 10.35 MHz, fIN2 MHz, VIN2 mVrms, fIN4 MHz, VIN4 mVrms VDD: block stopped (PLL INHIBIT), Xtal oscillator operating (Xtal 10.35 MHz) VDD: block stopped, Xtal oscillator stopped -0.5 0.01 0.01 +0.5 Unit
Serial Data Timing
Internal data latching
When stopped level
Internal data latching
When stopped high level
5377-5/22
LC72144M Functions
Symbol Type Function circuit
XOUT
Xtal oscillator
Crystal oscillator connection (4.5, 7.2, 10.25, 10.35 MHz)
FMIN selected when serial data input FMIN Local oscillator signal input input frequency range MHz. signal transmitted swallow counter. divisor value range 65,535.
AMIN selected when serial data input When serial data input input frequency range MHz. signal transmitted swallow counter. divisor value range 65,535. When serial data input input frequency range MHz. signal transmitted 12-bit programmable divider. divisor value range 4,095.
AMIN
Local oscillator signal input
Chip enable
This must high during serial data input (DI) LC72144M, during serial data output (DO).
Clock
Used data synchronization during serial data input (DI) LC72144M, during serial data output (DO).
Input data
Used input serial data transferred LC72144M from controller.
Output data
Used output serial data transferred controller from LC72144M.
Power supply
LC72144M power supply connection. Provide voltage between when circuit operation. power reset circuit operates when power first applied.
Ground
LC72144M ground connection.
General-purpose ports I/O-1 I/O-2 I/O-3 General-purpose ports output circuits open-drain circuits. I/O-1 I/O-2 input ports after power reset. I/O-3 becomes output port fixed level. These pins switched between input output I/O-1 I/O-3 bits serial data transferred from controller.
General-purpose ports I/O-0 I/O-4 I/O-5 General-purpose ports output circuits complementary circuits. These ports input ports after power reset. These pins switched between input output I/O-0, I/O-4, I/O-5 bits serial data transferred from controller.
Continued next page. 5377-6/22
LC72144M
Continued from preceding page.
Symbol Type Function circuit
ADC0 ADC1
converter input
converter inputs 6-bit successive-approximation converter item structure converter details.
Main charge pump output
charge pump output high level output from when frequency created dividing local oscillator frequency higher than reference frequency. level output when frequency lower. goes high-impedance state when frequencies agree. operates same manner.
Sub-charge pump output
high-speed lockup circuit formed using this combination with main charge pump. item structure charge pump details.
HCTR/I-6
General-purpose counter
HCTR selected when CTS1 serial data input frequency range MHz. signal passes through divide-by-2 circuit then input general-purpose counter. integrating count also performed. result count output from generalpurpose counter through output pin. item structure general-purpose counter details. When serial data H/I-6 This functions input port, state output from output pin. LCTR selected when CTS1 serial data When CTS0 serial data circuit switches frequency measurement mode. input frequency range kHz. signal input directly general-purpose counter without passing through divide-by-2 counter. result count output from generalpurpose counter through output pin.
LCTR/I-7
General-purpose counter
When CTS0 serial data circuit switches period measurement mode. input frequency range kHz. measurement period periods. result count output from generalpurpose counter through output pin. item structure general-purpose counter details. When L/I-7 serial data This functions input port, state output from output pin. Output buffer crystal oscillator circuit.
XBUF
Xtal oscillator buffer
serial data output buffer operates crystal oscillator signal pulse waveform) output. this outputs level. (Since after power reset, output will fixed level.)
5377-7/22
LC72144M Serial Data Input Output Methods Data input output using (computer control bus) format, which Sanyo's audio serial format.
mode Address Function Control data input mode (serial data input) bits data input. Control data input mode (serial data input) bits data input. Data output mode (serial data output) number bits equal number clock cycles output. mode determined.
Serial data input (IN1/IN2)
Internal data
Serial data output (OUT)
Note: Since n-channel open drain output, data value transition time will differ depending value pull-up resistor printed circuit board capacitance values. Note: normally open.
5377-8/22
LC72144M Structure Control Data
Address
Address
5377-9/22
LC72144M Control Data Functions
Control section/ data Function Data that sets programmable divider's divisor. binary value MSB. differs depending bits. don't care) Programmable divider data P15, DVS, Divisor setting 65535 65535 4095 Related data
Note: When LSB, ignored. These bits select signal input (FMIN AMIN) programmable divider switch input frequency range. Input port FMIN AMIN AMIN Input frequency range (MHz)
Note: "Programmable Divider Structure" item details. Data that controls sub-change pump PDC1 Sub-charge pump control data PDC0, PDC1 PDC0 High impedance Charge pump operates (when unlocked) Charge pump operates (normal operation) UL0, UL1, Sub-charge pump state
Note: sub-charge pump form high-speed lockup circuit when combined with pins (the main charge pump). item structure charge pump details. Data that selects reference frequency (fref) Reference frequency (kHz) 100*1 12.5 6.25 3.125 3.125 30*2 inhibited crystal oscillator stopped inhibited
Reference divider data
Note: Cannot used when crystal oscillator frequency 10.25 10.35 MHz. Note: Cannot used when crystal oscillator frequency 10.25 MHz. Note: inhibit (backup mode) programmable divider block stopped FMIN AMIN both pulled down ground. charge pump output goes floating state.
Continued next page. 5377-10/22
LC72144M
Continued from preceding page.
Control section/ data Function Data that determines I/O-5 outputs when unlocked end-AD end-UC IN*1 Open end-AD end-UC IN*1 when unlocked*2 OUT5 flag*2 I/O-5 Related data
Note: end-AD: converter conversion completion end-UC: General-purpose counter conversion completion Control data I/O-5 pins ULD, DT0, DT1, IL0, Start Finish High (I-1 charge)
OUT5 I/O-1, I/O-2, I/O-5
Note: Open (pin state) (pin state) goes when changes. state
Note: However, this becomes open I/O-1 I/O-2 pins specified output ports. Note: Invalid I/O-5 specified input port. Note: Cannot used when crystal oscillator stopped. (The will change state.) (Reference divider: When converter conversion start data Resets starts converter Resets converter ADI1 converter control data ADS, ADI0, ADI1 ADI0 Stopped ADC0 ADC1 ADC0, ADC1 input
ADC0 ADC1 specified input same time, conversions performed order ADC0 first, then ADC1. item structure converter details.
Continued next page. 5377-11/22
LC72144M
Continued from preceding page.
Control section/ data Function Data that selects input (HCTR LCTR) general-purpose counter CTS1 CTS0 Input HCTR LCTR LCTR Measurement mode Frequency Frequency Period Related data
Data that specifies start general-purpose counter measurement operation Count start Count reset Generalpurpose counter control data CTS0, CTS1, CTE, GT0, CTP, Data that determines general-purpose counter measurement time frequency mode) number periods period mode) Frequency measurement mode Measurement time (ms) Wait time (ms) period period periods periods Period measurement mode H/I-6, L/I-7
general-purpose counter input pulled down count reset time (when wait time shortened pulling down general-purpose counter input count reset time (when However, immediately after system must wait until general-purpose counter input biased before starting count. input sensitivity lowered setting (Sensitivity: mVrms) port control data I/O-0 I/O-5 Data that specifies input output state ports Data value Input port Output port Note: I/O-0, I/O-1, I/O-2, I/O-4, I/O-5 function input ports after power reset. I/O-3 function output port after power reset. Data that determines output values output ports Data value Open high Note: This data invalid when corresponding port specified function input port unlock state output. Data that sets general-purpose counter pins function input ports H/I-6 (input port) HCTR (general-purpose counter) L/I-7 (input port) LCTR (general-purpose counter) Data that selects phase error detection width used lock state discrimination phase error excess detection width listed table below detected, system considers phase error have occurred unlocked state. detection I/O-5) unlocked state. (10) Unlock detection data UL0, detection width Stopped ±0.5 ±1.0 Open output with expansion with expansion ULD, DT0, Detection output
OUT0 OUT5,
Output port data OUT0 OUT5 Generalpurpose counter input control data H/I-6, L/I-7
I/O-0 I/O-5,
CTS0, CTS1
Expansion
I/O-5
Unlock state output
Continued next page. 5377-12/22
LC72144M
Continued from preceding page.
Control section/ data Data that selects crystal oscillator element (11) Crystal oscillator circuit XS0, XS1, Xtal 10.25 10.35 Function Related data
Note: 10.25 setting selected after power reset. Data that controls crystal oscillator element buffer output Buffer output (This mode selected after power reset.) Buffer output Note: Turn XBUF output reception mode (PD0 used). Data that controls phase comparator dead band Insensitive band (dead zone) mode
(12)
Phase comparator control data DZ0,
Note: selected after power-on reset. Data that forces charge pump output level (VSS level). level Normal operation Note: deadlock occurs oscillator being stopped control voltage (Vtune) becoming deadlock resolved setting charge pump output level then setting Vtune VCC. This data normal operating mode state after power reset. Data that controls testing This data must i.e.: TEST0 TEST1 TEST2 Note: test data after power reset.
(13)
Charge pump control data
test data (14) TEST0, TEST1, TEST2
5377-13/22
LC72144M Structure Output Data (Serial Data Output)
Address
Data with value
Control section/ data port data Generalpurpose counter binary data converter ADC0 data AD00 AD05 converter data ADC1 data AD10 AD15
Function port data: pins reflect latched I/O-0 I/O-7 port states. Data latched when data output mode entered. states latched regardless input output mode specification. state high: low: Counter contents Bits latched contents 20-bit binary counter. LSB. C19: result conversion signal input ADC0 latched output from AD00 AD05 pins AD05: AD00: result conversion signal input ADC1 latched output from AD10 AD15 pins AD15: AD10:
Related data
I/O-0 I/O-5, H/I-6, L/I-7
CTS0, CTS1,
ADI0, ADI1,
ADI0, ADI1,
5377-14/22
LC72144M Programmable Divider
Divisor setting 65535 65535 4095
Input frequency range
Input port FMIN AMIN AMIN
Note: don't care
Minimum input sensitivity [MHz]) FMIN mVrms mVrms mVrms mVrms mVrms mVrms
AMIN
AMIN
General-Purpose Counter LC72144M includes general-purpose 20-bit binary counter whose value read from pin, first.
Input signal switching gate
General-purpose counter (20-bit binary counter)
period/two periods extraction
Check signal:
(1/T) check signal (900 kHz)
When using this counter frequency measurement, four measurement times selected GT1. frequency input either HCTR LCTR measured determining number pulses input counter during measurement period. This counter used measure period signal input LCTR determining many cycles reference signal (900 kHz) input counter during periods LCTR signal.
5377-15/22
LC72144M Check Signal Frequency
10.35 Xtal Check signal 10.25 1025 fref 1030 fref: frequency other than 1150
CTS1
CTS0
Input HCTR LCTR LCTR
Measurement mode Frequency Frequency Period
Frequency range 25.0
Input sensitivity mVrms* mVrms* (pulse)
Note: mVrms mVrms However, frequency ranges will follows when HCTR: MHz, LCTR:
data input sensitivity switching data, input sensitivity degraded when
HCTR: Minimum input sensitivity rating (MHz)] (normal mode) (degraded mode) mVrms mVrms mVrms) mVrms mVrms) mVrms LCTR: Minimum input sensitivity rating (kHz)] mVrms mVrms (0.1 mVrms) mVrms mVrms)
stipulated (not included device guarantee) Actual performance estimates (reference values)
data determines state general-purpose counter input (HCTR/LCTR) when general-purpose counter reset (CTE general-purpose counter input pulled down. wait time shortened pulling down general-purpose counter input pin. must least before count start (CTE issued. must left counter used.
Frequency measurement mode Measurement time (ms) Wait time (ms) period period periods periods Period measurement mode
Counter Operation Before starting count operation with general-purpose counter, reset that counter setting general-purpose counter count operation started setting serial data Although serial data loaded into LC72144M internal registers changing level input from high low, input HCTR LCTR must provided within wait period that follows point when goes latest. Next, count result general-purpose counter after measurement completes must read period when since general-purpose counter reset when Also note that although signal input LCTR transmitted directly general-purpose counter, signal input HCTR only transmitted general-purpose counter after first being divided internally. Thus value result general-purpose counter actual frequency signal input HCTR pin.
5377-16/22
LC72144M
data Wait time Frequency measurement time Measurement time
Signal input
least mVrms* (during frequency measurement) Note: mVrms mVrms (min) (max) period (during period measurement)
Period measurement time Check signal
Integrating Count
Internal data latch (CTE)
Generalpurpose counter
(Integration)
Count complete
Count complete
Note: CTE:
General-purpose counter reset General-purpose counter start Restarts setting integrated count mode, count value accumulated general-purpose counter. Care required handle counter overflow. Counter values: FFFFFH (1,048,575) implement integrating count operation leave When serial data (IN1) transmitted again, general-purpose counter will start measure input again result will added count.
5377-17/22
LC72144M Structure Converter converter 6-bit successive-approximation converter with conversion time 0.56 full-scale input level (for data value 3FH) (63/96) VDD.
Multiplexer
Discrimination circuit
Comparator
Decoder
Register
Data with value
ADI1
ADI0
Input Illegal value ADC0 ADC1 ADC0/ADC1
TWA1 0.08 0.11 TWA1 0.08 0.09
Completion conversion
Conversion
0.56 0.62
Start conversion
5377-18/22
LC72144M Charge Pump
Pins I/O-5
PDC1
PDC0
(sub-charge pump state) High impedance Charge pump operates (when unlocked) Charge pump operates (normal operation)
PD1, PD0, Normal operation Forced
When unlock detected following channel change, (the sub-charge pump) operates. value changes (R1S shown following figure, decreasing low-pass filter time-constant accelerating locking.
unlock detection data must unlock detection range will ±0.5 phase difference excess these values detected circuit will unlock state sub-charge pump will operate. When circuit approaches lock state phase difference falls under unlock detection range, sub-charge pump operation will stop, i.e., sub-charge pump will high impedance state.
5377-19/22
LC72144M Others Notes phase comparator dead zone
Dead zone mode Charge pump ON/ON ON/ON OFF/OFF OFF/OFF Dead zone
Cases where charge pump ON/ON state require special care during system design since charge pump outputs correction pulses even when locked easy loop become unstable. following problems occur ON/ON state. Sidebands generated reference frequency leakage. Sidebands generated frequency leakage correction pulse envelope. settings that have dead zone (the OFF/OFF settings) provide good loop stability, hard achieve good ratio with these settings. Inversely, settings with dead zone (the ON/ON settings) allow high ratio achieved hard achieve good loop stability with these settings. Therefore, effective select either setting, i.e., setting which dead zone, when ratio between higher required mode, when stereo pilot margin needs increased. However, cases where such high ratio required where adequate stereo pilot margin achieved stereo used, either setting, i.e., setting which dead zone, should selected. Dead Zone Definition phase comparator compares with reference frequency (fr) shown Figure Figure shows characteristics ideal phase comparator, which outputs output voltage that proportional phase difference However, actual region (dead zone) which minute phase differences cannot detected occurs internal circuit delays other factors (B). implement product with high ratio, dead zone should small possible. However, there cases where larger dead zone make popularly-priced model easier use. This because possible leakage from mixer modulate popularly-priced models when strong input applied. When dead zone small output that compensates this problem generated, this output itself modulate generate beating with frequency.
Leakage
Figure
Figure
5377-20/22
LC72144M Notes FMIN, AMIN, HCTR/I-6, LCTR/I-7 Pins coupling capacitors must placed close possible. capacitance about desirable. particular, only capacitances under 1000 with HCTR/I-6, LCTR/I-7 pins. Large capacitances will increase time required reach bias level and, depending relationship with wait time, cause counting errors. Notes counting must used together with counting When using general-purpose counter counting, always IF-IC (station detect) signal. microcontroller should first check presence signal, then turn count buffer only that signal present perform count. Techniques that only count implement autosearch function dangerous because they stop frequencies that have station leakage from count buffer. Using modes other than data output mode, also used counter completion, unlock detection, checking changes input pin. state input (I/O-1, I/O-2) input controller directly through pin. Notes using XBUF When XBUF output turned (when up-conversion used), since XBUF signal leaks into adjacent pins, pins I/O-3, which adjacent XBUF, must used reception control. reception charge pump. Turn XBUF output setting data when using I/O-3 reception control. Power supply pins exclude noise, capacitor least 2000 must inserted between power supply lines. Locate this capacitor close chip's pins possible.
States Power Reset
State Power Reset Power Reset State
Floating
5377-21/22
LC72144M Application System Example
10.8 Mixer input: 10.35
products described contained herein intended surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment like, failure which directly indirectly cause injury, death property loss. Anyone purchasing products described contained herein above-mentioned shall: Accept full responsibility indemnify defend SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees, jointly severally, against claims litigation damages, cost expenses associated with such use: impose responsibility fault negligence which cited such claim litigation SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees jointly severally. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties. This catalog provides information August, 1997. Specifications information herein subject change without notice. 5377-22/22

LC72144M Frequency Synthesizer Overview LC72144M electr

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