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µPD784044(A), 784046(A) 16-BIT SINGLE-CHIP MICROCONTROLLER D


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INTEGRATED CIRCUIT
µPD784044(A), 784046(A)
16-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
µPD784046(A) model µPD784046 subseries within 78K/IV series. stricter quality assurance program applies µPD784046(A) compared µPD784046 (standard model). terms NEC's quality grading, this "special" grade product.) µPD784046(A) provided with many peripheral hardware functions such ROM, RAM, port, 10-bit resolution converter, timer, serial interface, interrupt functions, addition high-speed, high-performance CPU. µPD784046(A) under development. Moreover, flash memory model, µPD78F4046Note, that operate same supply voltage mask model, many development tools under development. Note functional evaluation only. functions described detail following User's Manuals. sure read these manuals when designing your system. µPD784046 Subseries User's Manual Hardware U11515E 78K/IV Series User's Manual Instruction U10905E
FEATURES
Higher reliability compared µPD784044 784046 Minimum instruction execution time (with 12.5-MHz internal clock) µPD784044(A), 784046(A) (with 10-MHz internal clock) µPD784044(A1), (A2), 784046(A1), (A2) port lines Timer 16-bit timer/counter units 16-bit timer units converter 10-bit resolution channels Serial interface UART/IOE (3-wire serial I/O) channels Watchdog timer channel Standby function HALT/STOP/IDLE mode Supply voltage
APPLICATION FIELDS
Automotive appliances, etc. this document, addition µPD784044(A) µPD784046(A), µPD784044(A1), 784044(A2) 784046(A1), 784046(A2) also explained. However, unless otherwise specified, µPD784046(A) treated representative model throughout this document.
information this document subject change without notice. Document U13121EJ1V1DS00 (1st edition) Date Published March 2001 CP(K) Printed Japan
1998
µPD784044(A), 784046(A)
ORDERING INFORMATION
Part Number Package plastic plastic plastic plastic plastic plastic Internal (bytes) Internal (bytes) 1024 1024 1024 2048 2048 2048
80-pin 80-pin 80-pin Note 80-pin Note 80-pin Note 80-pin
Note Under development
Remark indicates code suffix.
QUALITY GRADE Special
Please refer "Quality Grades Semiconductor Devices" (Document C11531E) published Corporation know specification quality grade devices recommended applications.
Differences between µPD784046 µPD784046(A)
Part Number Item Quality grade Operating ambient temperature Operating frequency Minimum instruction execution time characteristics characteristics converter characteristics
PD784044, 784046, 78F4046
Standard (with 16-MHz internal clock) supply current differs. timing serial operation differ. Conversion time sampling time differ.
PD784044(A), 784046(A)
Special (with 12.5-MHz internal clock)
Differences between µPD784046(A), 784046(A1) 784046(A2)
Part Number Item Operating ambient temperature Operating frequency Minimum instruction execution time characteristics characteristics converter characteristics
PD784046(A)
(with 12.5-MHz internal clock)
PD784046(A1)
+110 (with 10-MHz internal clock)
PD784046(A2)
+125
Analog input leakage current, supply current data retention current differ. timing serial operation differ. current converter data retention current differ.
Remark differences between PD784044(A), 784044(A1) 784044(A2) same above table.
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Product Development 78K/IV Series
Under mass production Under development
Standard models
multimaster
PD784038Y µPD784038
Improved internal memory capacity, compatible with µPD784026 multimaster
PD784225Y µPD784225
pins, correction added multimaster
µPD784026
A/D, 16-bit timer, improved power management
µPD784216Y µPD784216
pins, I/O, improved internal memory capacity
µPD784218Y µPD784218
Improved internal memory capacity, correction added
µPD784054
µPD784046
Internal 10-bit ASSP models
µPD784955
converter control
µPD784908
Internal IEBuscontroller multimaster
µPD78F4943
CD-ROM Flash memory:
µPD784928Y µPD784928
Improved functions µPD784915
µPD784915
Software servo control, internal analog circuit VCR, improved timer
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
FUNCTION LIST
Item Product bits registers banks, bits registers banks (memory mapping) (with internal 12.5-MHz clock): PD784044(A), 784046(A) (with internal 10-MHz clock) PD784044(A1), (A2), 784046(A1), (A2) bytes 1024 bytes bytes with program/data combined Total Input pins pins pins bytes 2048 bytes
PD784044(A)
PD784046(A)
Number basic instructions (mnemonics) General-purpose register Minimum instruction execution time Internal memory Memory space port
Pins with Pins with pins ancillary pull-up functions Note resistors Real-time output port Timer/counter bits Timer bits) Timer bits) Timer/counter bits) Timer/counter bits) Timer bits) converter Serial interface Watchdog timer Interrupt Hardware source Software source Non-maskable Maskable Timer register capture/compare register Timer register compare register Timer register compare register Timer register compare register Timer register compare register Pulse output possible Toggle output Set/reset output Pulse output possible Toggle output Set/reset output Pulse output possible Toggle output PWM/PPG output Pulse output possible Toggle output PWM/PPG output Pulse output possible Read-time output bits
10-bit resolution channels UART/IOE (3-wire serial I/O): channels (with baud rate generator) channel (internal: external: (internal/external: instruction, BRKCS instruction, operand error Internal: external: Internal: external: (internal/external: levels programmable priorities processing formats: vectored interrupt/macro service/context switching
sizing Standby Supply voltage Package
8-bit/16-bit external data width selectable HALT/STOP/IDLE mode 80-pin plastic
Note
pins with ancillary functions included pins.
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
CONTENTS
DIFFERENCES BETWEEN µPD784044(A) 784046(A) CONFIGURATION (Top View) SYSTEM CONFIGURATION EXAMPLE BLOCK DIAGRAM FUNCTIONS
Port Pins Pins Other Than Port Pins Circuits Pins Processing Unused Pins
ARCHITECTURE
Memory Space Registers 6.2.1 6.2.2 6.2.3 General-purpose registers Control registers Special function registers (SFRs)
PERIPHERAL HARDWARE FUNCTIONS
Ports Clock Generation Circuit Real-Time Output Port Timer/Counter Converter Serial Interface 7.6.1 Asynchronous serial interface/3-wire serial (UART/IOE) Edge Detection Circuit Watchdog Timer
INTERRUPT FUNCTION.40
Interrupt Source Vectored Interrupt Context Switching Macro Service
LOCAL INTERFACE
Memory Expansion Memory Space Programmable Wait Sizing Function
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
STANDBY FUNCTION RESET FUNCTION INSTRUCTION ELECTRICAL SPECIFICATIONS PACKAGE DRAWING RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTS
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
DIFFERENCES BETWEEN µPD784044(A) 784046(A)
only difference between PD784044(A) PD784046(A) internal memory capacity. differences shown Table 1-1. Table 1-1. Differences between µPD784044(A) 784046(A)
Part Number Item Internal Internal
PD784044(A)
bytes (mask ROM) 1024 bytes
PD784046(A)
bytes (mask ROM) 2048 bytes
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
CONFIGURATION (Top View)
80-pin plastic
Note Under development
P24/INTP3/TO03
P70/ANI0 P71/ANI1 P72/ANI2 P73/ANI3 P74/ANI4 P75/ANI5 P76/ANI6 P77/ANI7 AVREF AVDD P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1 P40/AD0 P22/INTP1/TO01 P21/INTP0/TO00 MODE P20/NMI P13/TO31 P12/TO30 P11/TO21 P10/TO20 P03/RTP3 P02/RTP2 P01/RTP1 P00/RTP0 P37/ASCK2/SCK2 P36/TxD2/SO2 P35/RxD2/SI2 P34/ASCK/SCK1 P33/TxD/SO1
P30/TO10
P31/TO11
Caution
Directly connect MODE VSS.
Data Sheet U13121EJ1V1DS
P32/RxD/SI1
P52/AD10
P53/AD11
P54/AD12
P55/AD13
P56/AD14
P57/AD15
P60/A16
P61/A17
P62/A18
P63/A19
P93/ASTB
P92/HWR
P50/AD8
P51/AD9
P90/RD
P91/LWR
P94/WAIT
P23/INTP2/TO02
P27/INTP6/TI3
P26/INTP5/TI2
P25/INTP4
P87/ANI15
P86/ANI14
P85/ANI13
P84/ANI12
P83/ANI11
P82/ANI10
P81/ANI9
P80/ANI8
CLKOUT
RESET
AVSS
µPD784044(A), 784046(A)
A16-A19 AD0-AD15 ANI0-ANI15 ASCK, ASCK2 ASTB CLKOUT INTP0-INTP6 MODE P00-P03 P10-P13 P20-P27 P30-P37 P40-P47 Address Address/Data Analog Input Asynchronous Serial Clock Address Strobe Analog Power Supply Analog Reference Voltage Analog Ground Width Definition Clock High Address Write Strobe Interrupt from Peripherals Address Write Strobe Mode Non-maskable Interrupt Port0 Port1 Port2 Port3 Port4 P50-P57 P60-P63 P70-P77 P80-P87 P90-P94 RESET RTP0-RTP3 RxD, RxD2 SCK1,SCK2 SI1, SO1, TI2, TO20,TO21,TO30,TO31 TxD, TxD2 WAIT Port5 Port6 Port7 Port8 Port9 Read Strobe Reset Real-Time Port Receive Data Serial Clock Serial Input Serial Output Timer Input Timer Output Transmit Data Power Supply Ground Wait Crystal
TO00-TO03, TO10, TO11,
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
SYSTEM CONFIGURATION EXAMPLE SERVO MOTOR CONTROL)
Display lamp control unit
PD784046(A)
Output interface
Subthrottle control
Pulse Right front wheel speed Left front wheel speed Right rear wheel speed Left rear wheel speed Digital quantity Brake Parking Neutral etc.
Generalpurpose
Solenoid drive circuit Monitor circuit Input interface External interface
Input interface
Generalpurpose
ROM: 10-bit converter
Solenoid Right front wheel Left front wheel Right rear wheel Left rear wheel
Timer unit Interrupt controller
Analog quantity sensor (front, rear) sensor (left, right) Throttle divergence Rupture detection, etc. External tester display system
Serial
UART
Microcomputer monitor Battery voltage Power unit
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
BLOCK DIAGRAM
RxD/SI1 TxD/SO1 ASCK/SCK1 RxD2/SI2 TxD2/SO2 ASCK2/SCK2 AD0-AD15 A16-A19 LWR, ASTB WAIT P00-P03 P10-P12 P21-P27 P30-P37 P40-P47 P50-P57 P60-P63 P70-P77 P80-P87 P90-P94 CLKOUT RESET MODE
INTP0-INTP6
Programmable interrupt controller
UART/IOE1 Baud-rate generator UART/IOE2 Baud-rate generator
INTP0-INTP3 TO00-TO03
Timer bits)
TO10, TO11
Timer bits)
INTP5/TI2 TO20, TO21
Timer/counter2 BITS)
78K/IV core
Port
INTP6/TI3 TO30, TO31
Timer/counter3 BITS)
Port Port
Timer bits) RTP0-RTP3 Real-time output port
Port Port Port Port
ANI0-ANI15 AVDD AVSS AVREF INTP4 converter
Port Port Port
Watchdog timer
System control
Remark internal capacity differs depending products.
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
FUNCTIONS Port Pins (1/2)
Name P00-P03 Shared RTP0-RTP3 Function Port (P0): 4-bit port input/output mode bit-wise. Pins input mode connected pull-up resistors once software. Port (P1): 4-bit port input/output mode bit-wise.
P40-P47
TO20 TO21 TO30 TO31
Input
INTP0/TO00 INTP1/TO01 INTP2/TO02 INTP3/TO03 INTP4 INTP5/TI2 INTP6/TI3
Port (P2): 8-bit port
Input only input/output mode bit-wise.
TO10 TO11 RxD/SI1 TxD/SO1 ASCK/SCK1 RxD2/SI2 TxD2/SO2 ASCK2/SCK2
Port (P3): 8-bit port input/output mode bit-wise.
AD0-AD7
Port (P4): 8-bit port input/output mode bit-wise. Pins input mode connected pull-up resistors once software. Port (P5): 8-bit port input/output mode bit-wise. Pins input mode connected pull-up resistors once software. Port (P6): 4-bit port input/output mode bit-wise. Pins input mode connected pull-up resistors once software.
P50-P57
AD8-AD15
P60-P63
A16-A19
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Port Pins (2/2)
Name P70-P77 P80-P87 Input Input Shared ANI0-ANI7 ANI8-ANI15 ASTB WAIT Port (P7): 8-bit input port Port (P8): 8-bit input port Port (P9): 5-bit port input/output mode bit-wise. Pins input mode connected pull-up resistors once software. Function
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Pins Other Than Port Pins (1/2)
Name RTP0-RTP3 INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 TO00 TO01 TO02 TO03 TO10 TO11 TO20 TO21 TO30 TO31 RxD2 TxD2 ASCK ASCK2 SCK1 SCK2 AD0-AD7 AD8-AD15 Note Output Input Input Output Input Input Output Output Input Shared P00-P03 P21/TO00 P22/TO01 P23/TO02 P24/TO03 P26/TI2 P27/TI3 P21/INTP0 P22/INTP1 P23/INTP2 P24/INTP3 P26/INTP5 P27/INTP6 P32/SI1 P35/SI2 P33/SO1 P36/SO2 P34/SCK1 P37/SCK2 P32/RxD P35/RxD2 P33/TxD P36/TxD2 P34/ASCK P37/ASCK2 P40-P47 P50-P57 External count clock input timer/counter External count clock input timer/counter Serial data input (UART0) Serial data input (UART2) Serial data output (UART0) Serial data output (UART2) Baud rate clock input (UART0) Baud rate clock input (UART2) Serial data input (3-wire serial I/O1) Serial data input (3-wire serial I/O2) Serial data output (3-wire serial I/O1) Serial data output (3-wire serial I/O2) Serial clock input/output (3-wire serial I/O1) Serial clock input/output (3-wire serial I/O2) Lower multiplexed address/data when external memory connected When 8-bit specified Higher address when external memory connected When external 16-bit specified Higher multiplexed address/data when external memory connected Higher address when external memory connected Read strobe external memory Timer output from timer/counter Real-time output Non-maskable interrupt request input External interrupt request input Capture trigger signal CC00 Capture trigger signal CC01 Capture trigger signal CC02 Capture trigger signal CC03 Conversion start trigger input converter Function
A16-A19 Note
Output Output
P60-P63
Note
number pins used address pins differs depending external address space (refer LOCAL INTERFACE).
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Pins Other Than Port Pins (2/2)
Name Output Shared Function When external 8-bit specified Write strobe external memory When external 16-bit specified Write strobe external memory located lower position Write strobe external memory located higher position when external 16-bit specified Timing signal output externally latch address information output from through AD15 pins access external memory WAIT MODE CLKOUT RESET ANI0-ANI7 ANI8-ANI15 Input Input Input Output Input Input Input P70-P77 P80-P87 Reference voltage converter Positive power supply converter converter Positive power supply Chip reset Analog voltage input converter Inserts wait. Sets width. Directly connect this (this specifies test mode IC). Clock output. Outputs level during IDLE mode STOP mode. Otherwise, always outputs (oscillation frequency). Connect crystal system clock oscillation (clock also input X1).
ASTB Output
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Circuits Pins Processing Unused Pins
Table shows circuit type each recommended processing unused pins. circuit type, refer Figure 5-1. Table 5-1. Circuit Type Each Recommended Processing Unused Pins
Name P00/RTP0-P03/RTP3 P10-P12 P11/TO21 P12/TO30 P13/TO31 P20/NMI P21/INTP0/TO00 P22/INTP1/TO01 P23/INTP2/TO02 P24/INTP3/TO03 P25/INTP4 P26/INTP5/TI2 P27/INTP6/TI3 P30/TO10 P31/TO11 P32/RxD/SI1 P33/TxD/SO1 P34/ASCK/SCK1 P35/RxD2/SI2 P36/TxD2/SO2 P37/ASCK2/SCK2 P40/AD0-P47/AD7 P50/AD8-P57/AD15 P60/A16-P63/A19 P70/ANI0-P77/ANI7 P80/ANI8-P87/ANI15 P90/RD P91/LWR P92/HWR P93/ASTB P94/WAIT MODE RESET CLKOUT Connect Output Leave unconnected. Connect Input Directly connect Input: Individually connect resistor. Output: Leave unconnected. Input Connect Input Connect Input: Individually connect resistor. Output: Leave unconnected. Circuit Type Recommended Connection Unused Pins Input: Individually connect resistor. Output: Leave unconnected.
Remark circuit type numbers serial series always with some models (because some models provided with particular circuits).
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Figure 5-1. Circuits Pins
Type Type
P-ch
Pullup Enable Data
P-ch P-ch IN/OUT
N-ch
Output disable Input enable
N-ch
Type
Type
Data Output disable N-ch P-ch IN/OUT
Schmitt trigger input with hysteresis characteristics Type Type
P-ch N-ch
P-ch N-ch
Comparator
VREF (Threshold voltage)
Input enable
Type Data P-ch IN/OUT Output disable N-ch
Input enable
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
ARCHITECTURE Memory Space
1M-byte memory space accessed. mapping internal data area (special function registers internal RAM) selected using LOCATION instruction. LOCATION instruction must always executed after reset signal been deasserted, must used more than once. When LOCATION instruction executed Internal memory internal data area internal area follows:
Product Name Internal Data Area 0FB00H-0FFFFH 0F700H-0FFFFH Internal Area 00000H-07FFFH 00000H-0F5FFH
PD784044(A) PD784046(A)
Caution
0F600H 0FFFFH on-chip (00000H 0FFFFH) µPD784046(A) cannot used execution LOCATION instruction (refer Figure 6-2).
External memory external memory accessed external memory expansion mode. When LOCATION instruction executed Internal memory internal data area internal area follows:
Product Name Internal Data Area FFB00H-FFFFFH FF700H-FFFFFH Internal Area 00000H-07FFFH 00000H-0FFFFH
PD784044(A) PD784046(A)
External memory external memory accessed external memory expansion mode.
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Figure 6-1. µPD784044(A) Memory
When LOCATION instruction executed
External memory Note (960K bytes) Main Peripheral Program/data area (512 bytes)
Note
When LOCATION instruction executed
Special function registers (SFRS) Note (256 bytes)
General-purpose registers (128 bytes)
Internal bytes) Cannot used (1280 bytes)
Special function registers (SFRs) Note (256 bytes) Internal memory bytes) Cannot used (1280 bytes)
Macro service control word area bytes) Data area (512 bytes)
External memoryNote (1013248 bytes)
Program/data area (32K bytes) CALLF entry area bytes)
Note
External memory Note (30208 bytes)
Internal (32K bytes)
CALLT table area bytes) Vector table area bytes)
Internal (32K bytes)
Notes Accessed external memory expansion mode. Base area entry area reset interrupt. internal reset.
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Figure 6-2. µPD784046(A) Memory
When LOCATION instruction executed Special function registers (SFRs) Note (256 bytes) Internal bytes) FFE8
When LOCATION instruction executed External memoryNote (960K bytes) General-purpose registers (128 bytes)
FDFH
Cannot used (256 bytes)
Special function registers (SFRs) Note (256 bytes) Internal bytes)
Macro service control word area bytes) Main Peripheral Data area (512 bytes)
FFE3 FFE0
Program/data area (1536 bytes) Note Program/data areaNote CALLF entry area bytes) External memoryNote (980480 bytes)
Cannot used (256 bytes)
Note
Internal (62976 bytes)
CALLT table area bytes) Vector table area bytes)
Internal (64K bytes)
Note
Notes Accessed external memory expansion mode. 2560 bytes this area used inernal only when LOCATION instruction executed. When LOCATION instruction executed: 62976 bytes When LOCATION instruction executed: 65536 bytes Base area entry area reset interrupt. internal reset.
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Registers
6.2.1 General-purpose registers Sixteen 8-bit general-purpose registers provided. 8-bit general-purpose registers used pairs 16-bit general-purpose register. 16-bit registers, four used with 8-bit register address expansion 24-bit address specification registers. Eight banks register sets available which selected software context switching function. general-purpose registers except registers address expansion mapped internal RAM. Figure 6-3. General-Purpose Register Format
A(R1) AX(RP0) B(R3) BC(RP1) VVP(RG4) UUP(RG5) D(R13) TDE(RG6) H(R15) WHL(RG7) HL(RP7) DE(RP6) UP(RP5) VP(RP4)
X(R0) C(R2)
E(R12)
L(R14)
banks
absolute name
Caution
RP2, used registers, respectively, setting However, this function only when using 78K/III series program.
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
6.2.2 Control registers Program counter (PC) This 20-bit program counter. contents automatically updated program executed. Figure 6-4. Program Counter (PC) Format
Program status word (PSW) This register retains status contents automatically updated program executed. Figure 6-5. Program Status Word (PSW) Format
PSWH PSWL
RBS2
RBS1
RBS0
Note
Note
This flag provided that µPD784046(A) maintains compatibility with 78K/III series. sure clear this flag when using 78K/III series software.
Stack pointer (SP) This 24-bit pointer that holds first address stack. sure write high-order bits this pointer. Figure 6-6. Stack Pointer (SP) Format
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
6.2.3 Special function registers (SFRs) special function registers registers which special functions assigned, include mode registers control registers internal peripheral hardware. These registers mapped 256-byte space addresses 0FF00H through 0FFFFH Note. Note When LOCATION instruction executed. FFF00H through FFFFFH when LOCATION instruction executed. Caution access address this area which allocated. address which allocated accessed mistake, µPD784046(A) deadlocked. deadlock status cleared only inputting reset signal. Table lists special function registers. meanings symbols this table follows: Symbol Symbol indicating SFR. These symbols reserved NEC's assembler (RA78K4). With compiler (CC78K4), they used variables using #pragma directive. Indicates whether corresponding read/written. Read/write Read only Write only
units manipulation Indicates units which corresponding manipulated. SFRs that manipulated 16-bit units written operand sfrp. Specify even addresses these SFRs when specifying address. SFRs that manipulated bit-wise written manipulation instructions. reset Indicates status each register when RESET signal input.
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Table 6-1. Special Function Register List (1/5)
Address Note
Special Function Register (SFR) Name
Symbol
units manipulation bits bits
reset
0FF00H 0FF01H 0FF02H 0FF03H 0FF04H 0FF05H 0FF06H 0FF07H 0FF08H 0FF09H 0FF0EH 0FF10H 0FF11H 0FF12H 0FF13H 0FF14H 0FF15H 0FF16H 0FF17H 0FF18H 0FF19H 0FF1AH 0FF1BH 0FF1CH 0FF1DH 0FF1EH 0FF1FH 0FF20H 0FF21H 0FF22H 0FF23H 0FF24H 0FF25H 0FF26H 0FF29H 0FF2EH 0FF2FH
Port Port Port Port Port Port Port Port Port Port Port buffer register Timer register
Undefined
Note
0000H
Capture/compare register
CC00
Undefined
Capture/compare register
CC01
Capture/compare register
CC02
Capture/compare register
CC03
Timer register
0000H
Compare register
CM10
Undefined
Compare register
CM11
Port mode register Port mode register Port mode register Port mode register Port mode register Port mode register Port mode register Port mode register Real-time output port control register Port read control register
Note RTPC PRDC
Notes When LOCATION instruction executed. "F0000H" this value when LOCATION instruction executed. only read. read/written. fixed hardware.
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Table 6-1. Special Function Register List (2/5)
Address Note
Special Function Register (SFR) Name
Symbol
units manipulation bits bits
reset
0FF30H 0FF31H 0FF32H 0FF33H 0FF34H 0FF35H 0FF36H 0FF37H 0FF38H 0FF39H 0FF3AH 0FF3BH 0FF3CH 0FF3DH 0FF3EH 0FF3FH 0FF41H 0FF42H 0FF43H 0FF49H 0FF4EH 0FF4FH 0FF50H 0FF51H 0FF52H 0FF53H 0FF54H 0FF55H 0FF56H 0FF57H 0FF58H 0FF59H 0FF5AH 0FF5BH 0FF60H 0FF61H
Timer unit mode register Timer mode control register Timer output control register Timer output control register Timer unit mode register Timer mode control register Timer output control register Timer mode control register Prescaler mode register Prescaler mode register Prescaler mode register Noise protection control register External interrupt mode register External interrupt mode register Interrupt valid edge flag register Interrupt valid edge flag register Port mode control register Port mode control register Port mode control register Port mode control register Pull-up resistor option register Pull-up resistor option register Timer register
TUM0 TOC0 TOC1 TUM2 TMC2 TOC2 TMC4 PRM2 PRM4 INTM0 INTM1 IEF1 IEF2 PMC1 PMC2 Note PMC3 PMC9 PUOL PUOH
Undefined
0000H
Compare register
CM20
Undefined
Compare register
CM21
Timer register
0000H
Compare register
CM30
Undefined
Compare register
CM31
Timer register
0000H
Notes When LOCATION instruction executed. "F0000H" this value when LOCATION instruction executed. Bits through PMC2 fixed hardware.
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Table 6-1. Special Function Register List (3/5)
Address Note Special Function Register (SFR) Name Symbol units manipulation 0FF62H 0FF63H 0FF64H 0FF65H 0FF6EH 0FF70H 0FF71H 0FF71H 0FF72H 0FF73H 0FF73H 0FF74H 0FF75H 0FF75H 0FF76H 0FF77H 0FF77H 0FF78H 0FF79H 0FF79H 0FF7AH 0FF7BH 0FF7BH 0FF7CH 0FF7DH 0FF7DH 0FF7EH 0FF7FH 0FF7FH 0FF84H 0FF85H 0FF88H 0FF89H 0FF8AH 0FF8BH conversion result register Clocked serial interface mode register Clocked serial interface mode register Asynchronous serial interface mode register Asynchronous serial interface mode register ADCR7H CSIM1 CSIM2 ASIM ASIM2 conversion result register conversion result register ADCR6H ADCR7 conversion result register conversion result register ADCR5H ADCR6 conversion result register conversion result register ADCR4H ADCR5 Undefined conversion result register conversion result register ADCR3H ADCR4 conversion result register conversion result register ADCR2H ADCR3 conversion result register conversion result register ADCR1H ADCR2 conversion result register conversion result register ADCR0H ADCR1 converter mode register conversion result register ADCR0 Undefined Compare register CM41 Compare register CM40 bits bits Undefined reset
Asynchronous serial interface status register ASIS Asynchronous serial interface status register ASIS2
Note
When LOCATION instruction executed. "F0000H" this value when LOCATION instruction executed.
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Table 6-1. Special Function Register List (4/5)
Address Note
Special Function Register (SFR) Name
Symbol
units manipulation bits bits
reset
0FF8CH
Serial receive buffer: UART0 Serial transmit shift register: UART0 Serial shift register: IOE1
SIO1 RXB2 TXS2 SIO2 BRGC BRGC2 ISPR MK0L
Undefined
0FF8DH
Serial receive buffer: UART2 Serial transmit shift register: UART2 Serial shift register: IOE2
0FF90H 0FF91H 0FFA8H 0FFAAH 0FFACH 0FFACH 0FFADH 0FFADH 0FFAEH 0FFAEH 0FFAFH 0FFAFH 0FFC0H 0FFC2H 0FFC4H 0FFC7H 0FFC8H 0FFC9H 0FFCAH 0FFCBH 0FFCFH 0FFD0H0FFDFH 0FFE0H 0FFE1H 0FFE2H 0FFE3H 0FFE4H 0FFE5H
Baud rate generator control register Baud rate generator control register In-service priority register Interrupt mode control register Interrupt mask register Interrupt mask register
FFFFH
Interrupt mask register Interrupt mask register Interrupt mask register
MK0H MK1L
FFFFH
Interrupt mask register Standby control register Note register Note
MK1H STBC PWC1 PWC2
AAAAH
Watchdog timer mode
Memory expansion mode register Programmable wait control register Programmable wait control register
width specification register
Note
Oscillation stabilization time specification register OSTS External area Interrupt control register (INTOV0) Interrupt control register (INTOV1) Interrupt control register (INTOV4) Interrupt control register (INTP0) Interrupt control register (INTP1) Interrupt control register (INTP2) OVIC0 OVIC1 OVIC4 PIC0 PIC1 PIC2
Undefined
Notes When LOCATION instruction executed. "F0000H" this value when LOCATION instruction executed. These registers written only using dedicated instructions STBC, #byte WDM, #byte, cannot written other instructions. value this register reset differs depending setting pin. 0000H 00FFH
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Table 6-1. Special Function Register List (5/5)
Address Note Special Function Register (SFR) Name Symbol units manipulation 0FFE6H 0FFE7H 0FFE8H 0FFE9H 0FFEAH 0FFEBH 0FFECH 0FFEDH 0FFEEH 0FFEFH 0FFF0H 0FFF1H 0FFF2H 0FFF3H Interrupt control register (INTP3) Interrupt control register (INTP4) Interrupt control register (INTP5) Interrupt control register (INTP6) Interrupt control register (INTCM10) Interrupt control register (INTCM11) Interrupt control register (INTCM20) Interrupt control register (INTCM21) Interrupt control register (INTCM30) Interrupt control register (INTCM31) Interrupt control register (INTCM40) Interrupt control register (INTCM41) Interrupt control register (INTSER) Interrupt control register (INTSR) Interrupt control register (INTCSI1) 0FFF4H 0FFF5H 0FFF6H Interrupt control register (INTST) Interrupt control register (INTSER2) Interrupt control register (INTSR2) Interrupt control register (INTCSI2) 0FFF7H 0FFF8H Interrupt control register (INTST2) Interrupt control register (INTAD) PIC3 PIC4 PIC5 PIC6 CMIC10 CMIC11 CMIC20 CMIC21 CMIC30 CMIC31 CMIC40 CMIC41 SERIC SRIC CSIIC1 STIC SERIC2 SRIC2 CSIIC2 STIC2 ADIC bits bits reset
Note
When LOCATION instruction executed. "F0000H" this value when LOCATION instruction executed.
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
PERIPHERAL HARDWARE FUNCTIONS Ports
PD784046(A) ports shown Figure 7-1. These ports used various control operations. function each port shown Table 7-1. Ports through connected internal pull-up resistor software when they input mode. Figure 7-1. Port Configuration
Port Port
Port
Port
Port
P70-P77
Port
Port
P80-P87
Port
Port
Port
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Table 7-1. Port Function
Port Name Port Port Port Name P00-P03 P10-P13 P20-P27 input output mode bit-wise (however, input-only). Port Port Port Port Port Port Port P30-P37 P40-P47 P50-P57 P60-P63 P70-P77 P80-P87 P90-P94 input output mode bit-wise. pins input mode Input port input output mode bit-wise. pins input mode Function input output mode bit-wise. Specification Pull-Up Resistor Software pins input mode
Clock Generation Circuit
clock generation circuit generates controls internal system clock (CLK) supplied CPU. Figure shows configuration this circuit. Figure 7-2. Block Diagram Clock Generation Circuit
Divider Clock generation circuit fCLK Internal system clock (CLK)
Remark crystal/ceramic oscillation frequency external clock frequency fCLK internal system clock frequency
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Figure 7-3. Example Using Oscillation Circuit Crystal/ceramic oscillation
PD784046(A)
External clock input EXTC OSTS
PD784046(A)
EXTC OSTS
PD784046(A)
µPD74HC04, etc.
Leave unconnected
Caution
When using clock oscillation circuit, wire portion enclosed dotted line above figure follows avoid adverse effects wiring capacitance. Keep wiring length short possible. cross wiring with other signal lines. route wiring vicinity lines through which high alternating current flows. Always keep ground point capacitor oscillation circuit same potential VSS. ground capacitor ground pattern through which high current flows. extract signals from oscillation circuit.
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Real-Time Output Port
real-time output port outputs data stored buffer synchronization with match interrupt timer This allows jitter-less pulse output obtained. Therefore, best suited applications that output patterns given intervals (such stepping motor open loop control,etc.). shown Figure 7-4, port port buffer register form core configuration. Figure 7-4. Block Diagram Real-Time Output Port
Internal
Real time output port control register (RTPC)
Port buffer register (P0L)
INTCM40 (from timer
Output trigger control circuit
Output latch (P0)
RTP3 RTP2 RTP1 RTP0
Timer/Counter
PD784046(A) contains 16-bit timer/counter units three 16-bit timer units. These units support total interrupt requests, which enable them function 15-channel timers. Table 7-2. Timer/Counter Function
Name Item Operating mode Interval timer External event counter Function Timer output Toggle output Set/reset output PWM/PPG output Real-time output Overflow interrupt Number interrupt requests Timer Timer Timer/ Timer/ Counter2 Counter Timer
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Figure 7-5. Block Diagram Timer/Counter (1/2) Timer
Timer register (TM0) INTP0 INTP0 Edge detection INTP1 INTP1 Edge detection INTP2 INTP2 Edge detection INTP3 INTP3 Edge detection
Coinci-
fCLK
Prescaler
INTOV0 INTCC00 Pulse INTCC01 output control TO00
Capter/compare register dence (CC00)
Coinci-
Capter/compare register dence (CC01)
CoinciCapter/compare register dence
TO01 INTCC02 TO02 Pulse INTCC03 output control TO03
(CC02)
Coinci-
Capter/compare register dence (CC03)
Prescaler: CLK/16, /32, fCLK Timer
Clear control Timer register (TM1)
Coinci-
fCLK
Prescaler
INTOV1 INTCM10 TO10 Pulse output control TO11 INTCM11
Compare register dence (CM10)
Coinci-
Compare register dence (CM11)
Prescaler: /16, fCLK /32, CLK/64, /128
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Figure 7-5. Block Diagram Timer/Counter (2/2) Timer/counter
Clear control Timer register (TM2)
CoinciCompare register dence
fCLK
Prescaler
Selector
INTCM20 TO20 Pulse output control TO21 INTCM21
(CM20) Compare register dence (CM21) TI2/INTP5 Edge detection INTP5
Coinci-
Prescaler: CLK/16, /32, fCLK Timer/counter
Clear control
fCLK
Prescaler
Selector
Timer register (TM3)
CoinciCompare register dence
INTCM30 TO30 Pulse output control TO31 INTCM31
(CM30)
Coinci-
Compare register dence (CM31) TI3/INTP6 Edge detection INTP6
Prescaler: CLK/16, /32, fCLK Timer
Clear control Timer register (TM4)
CoinciCompare register dence
fCLK
Prescaler
INTOV4 INTCM40 real-time output port
(CM40)
Coinci-
Compare register dence (CM41)
INTCM41
Prescaler: CLK/16, /32, fCLK
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Converter
PD784046(A) analog-to-digital (A/D) converter with multiplexed analog input pins (ANI0 through ANI15). This converter successive approximation type. result conversion stored retained 10-bit conversion result registers (ADCR0-ADCR7). Therefore, high-speed, high-accuracy conversion performed (conversion time: about 13.5 12.5 MHz). conversion operation started following modes: Hardware start Conversion started trigger input (INTP4). Software start Conversion started setting converter mode register (ADM). converter operates following modes: Scan mode Select mode Sequentially selects more analog input pins obtain data converted from pins. Selects only analog input obtain successive conversion values.
above modes stopping conversion specified ADM. When result conversion transferred ADCRn 0-7), interrupt request INTAD generated. using this interrupt request using macro service, converted value successively transferred memory. Figure 7-6. Block Diagram Converter
ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 ANI12 ANI13 ANI14 ANI15
Input selector Sample hold circuit
Series resistor string AVREF Voltage comparator
selector
Input selector Successive approximation register (SAR) Conversion trigger
INTP4
Edge detection circuit
Control circuit
INTAD
AVSS
Trigger enable
converter mode register (ADM)
ADCR0 ADCR1 ADCR2 ADCR3 ADCR4 ADCR5 ADCR6 ADCR7 Internal
Data Sheet U13121EJ1V1DS
conversion result register
µPD784044(A), 784046(A)
Serial Interface
PD784046(A) provided with independent serial interface channels. Asynchronous serial interface (UART)/3-wire serial (IOE) using these serial interface channels, communication with external device local communication within system performed same time (refer Figure 7-7). Figure 7-7. Example Serial Interface
PD784046(A) master
(UART) RS-232C driver/ receiver Port SCK2 INTPn Port Note (3-wire serial I/O) Port slave
Note
Handshake line
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
7.6.1 Asynchronous serial interface/3-wire serial (UART/IOE) serial interface channels from which asynchronous serial interface mode three-wire serial mode selected provided. Asynchronous serial interface mode this mode, 1-byte data following start transferred received. internal baud rate generator allows communication wide range baud rates. clock input ASCK also divided define baud rate. baud rate generator also baud rate conforming MIDI standard (31.25 kbps). Figure 7-8. Block Diagram Asynchronous Serial Interface Mode
Internal
Receive buffer
RXB, RXB2
RxD, RxD2
Receive shift register
Transmit shift register
TXS, TXS2
TxD, TxD2
Receive control Parity check
INTSR, INTSR2 INTSER, INTSER2
Transmit control Parity append
INTST, INTST2
Baud rate generator
1/2m fCLK ASCK, ASCK2
Selector
1/2n+1 1/2m
Remark fCLK: internal system clock
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
3-wire serial mode This mode start transmission when master device makes serial clock active communicate 1-byte data synchronization with this clock. interface this mode communicates with devices that have conventional clocked serial interface. Basically, communication performed using three lines: serial clock (SCK) serial data lines. connect more devices, handshake line necessary. Figure 7-9. Block Diagram 3-Wire Serial Mode
Internal
Direction control circuit
SIO1, SIO2 SI1, Shift register Output latch
SO1,
SCK1, SCK2
Serial clock counter
Interrupt generation circuit
INTCSI1, INTCSI2
Serial clock control circuit
Remark fCLK: internal system clock
Data Sheet U13121EJ1V1DS
Selector
1/2m
1/2n+1
fCLK
µPD784044(A), 784046(A)
Edge Detection Circuit
interrupt input pins (NMI INTP0 through INTP6) input only interrupt requests also trigger signals internal hardware. Because interrupts internal hardware operate detecting specific edges input signals, function detect edges provided. addition, noise rejection function also provided prevent detection wrong edge noise.
INTP0-INTP6 Either rising falling edge Either rising falling edge, both edges Detectable Edge Noise Rejected Analog delay Clock sampling Note
Note
sampling clock selected.
Watchdog Timer
watchdog timer provided detect hang-up CPU. This watchdog timer generates non-maskable interrupt unless cleared software within specified interval time. Once watchdog timer been enable operate, operation cannot stopped software. Moreover, specified whether interrupt watchdog timer interrupt from takes precedence. Figure 7-10. Block Diagram Watchdog Timer
fCLK/29
fCLK
Divider
fCLK/212 fCLK/213
Selector
fCLK/211
Watchdog timer bits)
Overflow
INTWDT
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
INTERRUPT FUNCTION
three types interrupt processing shown Table selected. Table 8-1. Interrupt Request Processing
Processing Mode Vectored interrupt Context switching Processed Software Processing Branches executes processing routine (any processing contents). Automatically selects register bank, branches executes processing routine (any processing contents). Firmware Executes data transfer between memory (any processing contents). Contents Saves restores to/from stack. Saves restores to/from fixed area register bank. Retained
Macro service
Interrupt Source
interrupt sources, twenty-seven sources listed Table 8-2, instruction execution, operand error available. Four priority levels interrupt processing selected, that nesting during interrupt processing levels interrupt requests that generated same time controlled. However, nesting always advances with macro service (i.e., nesting kept pending). default priority priority (fixed) processing interrupt requests that have occurred same time have same priority level (refer Table 8-2).
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Table 8-2. Interrupt Sources
Type Default Priority Software Name instruction BRKCS instruction Operand error result exclusive operands byte byte when STBC, #byte, WDM, #byte, LOCATION instruction executed Detection input edge Overflow watchdog timer Overflow timer Overflow timer Overflow timer Detection input edge (CC00 capture trigger) Generation TM0-CC00 coincidence signal Detection input edge (CC01 capture trigger) Generation TM0-CC01 coincidence signal Detection input edge (CC02 capture trigger) Generation TM0-CC02 coincidence signal Detection input edge (CC03 capture trigger) Generation TM0-CC03 coincidence signal Detection input edge (A/D converter conversion start trigger) Detection input edge (TM2 event counter input) Detection input edge (TM3 event counter input) Generation TM1-CM10 coincidence signal Generation TM1-CM11 coincidence signal Generation TM2-CM20 coincidence signal Generation TM2-CM21 coincidence signal Generation TM3-CM30 coincidence signal Generation TM3-CM31 coincidence signal Generation TM4-CM40 coincidence signal Generation TM4-CM41 coincidence signal Occurrence UART0 reception error UART0 reception 3-wire serial I/O1 transfer UART0 transfer Occurrence UART2 reception error UART2 reception 3-wire serial I/O2 transfer UART2 transfer converter conversion (transfer ADCR) Internal External Internal External Internal External Internal External Internal External External Internal Source Trigger Execution instruction Internal/ External Macro Service
Nonmaskable Maskable
INTWDT
(highest)
INTOV0 INTOV1 INTOV4 INTP0 INTCC00
INTP1 INTCC01
INTP2 INTCC02
INTP3 INTCC03
INTP4 INTP5 INTP6 INTCM10 INTCM11 INTCM20 INTCM21 INTCM30 INTCM31 INTCM40 INTCM41 INTSER INTSR INTCSI1
INTST INTSER2 INTSR2 INTCSI2
(lowest)
INTST2 INTAD
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Vectored Interrupt
Execution branches processing routine using memory contents vector table address corresponding interrupt source branch destination address. following operations performed that processes interrupt: branch Saves status (contents PSW) stack
returning Restores status from stack Execution returned from processing routine main routine RETI instruction. branch destination address must range FFFFH. Table 8-3. Vector Table Address
Interrupt Source instruction Operand error INTWDT INTOV0 INTOV1 INTOV4 INTP0 INTCC00 INTP1 INTCC01 INTP2 INTCC02 INTP3 INTCC03 INTP4 INTP5 INTP6 0014H 0016H 0018H 0012H 0010H 000EH Vector Table Address 003EH 003CH 0002H 0004H 0006H 0008H 000AH 000CH Interrupt Source INTCM10 INTCM11 INTCM20 INTCM21 INTCM30 INTCM31 INTCM40 INTCM41 INTSER INTSR INTCSI1 INTST INTSER2 INTSR2 INTCSI2 INTST2 INTAD 0034H 0036H 002EH 0030H 0032H Vector Table Address 001AH 001CH 001EH 0020H 0022H 0024H 0026H 0028H 002AH 002CH
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Context Switching
specific register bank selected hardware when interrupt request generated when BRKCS instruction executed. Execution branches vector address stored advance selected register bank, current contents program counter (PC) program status word (PSW) stacked register bank. branch destination address must range FFFFH. Figure 8-1. Context Switching Operation When Interrupt Request Generated
Register bank 0000B Transfer Register bank PC19-16 PC15_0 Exchange Save (bits through temporary register) Save Temporary register Save RSS0 Select register bank (RBS0 RBS2n)
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Macro Service
PD784046(A) total seven types macro service. Each macro service outlined below. Counter mode: EVTCNT Operation Increments decrements 8-bit macro service counter (MSC). vectored interrupt request generated when value reaches
Application example: Event counter, measurement number times capture Block transfer mode: BLKTRS Operation Transfers block data between buffer specified pointer (SFR.PTR). transfer source destination buffer. length data transferred byte word. number times data transferred (block size) specified MSC. auto-decremented (-1) each time macro service been executed. When value reached vectored interrupt request generated.
SFR.PTR Buffer
Buffer
Internal
Application example: Data transfer/reception serial interface
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Block transfer mode (with memory pointer): BLKTRS-P Operation This block transfer mode with memory pointer (MEM.PTR) appended. appended buffer area MEMP freely memory space. Remark MEM.PTR auto-incremented (+1: byte data transfer/+2: word data transfer) each time macro service been executed.
SFRP
Buffer
MEM.PTR Buffer
Internal
Application example: Same Data differential mode: DTADIF Operation Calculates difference between contents specified pointer (SFR.PTR) (current value) contents loaded last data buffer (LDB). Stores result calculation predetermined buffer area. Stores contents current value LDB. number times data transferred (block size) specified MSC. value auto-decremented (-1) each time macro service been executed. When value reached vectored interrupt request generated. Remark differential calculation performed only 16-bit configuration.
SFR.PTR Buffer
Buffer
Differential calculation
Internal
Application example: Measurement period pulse width capture register timer
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Data differential mode (with memory pointer): DTADIF-P Operation This data differential mode with memory pointer (MEM.PTR) appended. appended MEM.PTR buffer area which differential data stored memory space freely. Remarks differential calculation performed only 16-bit configuration. buffer specified result operation between MEM.PTR MSCNote. value MEM.PTR updated after data been transferred. Note MEM.PTR (MSC
SFR.PTR Buffer
MEM.PTR Buffer Differential calculation
Internal
Application example: Same monitoring mode0: SFLF0 Operation Checks internal operation CPU. When blocks operating normally, value given subtracting from initial value transferred specified pointer (SFR.PTR). Application example: Used self checking during normal operation. monitoring mode1: SELF1 Operation Checks internal operation CPU. When blocks operating normally, value given subtracting from initial value transferred specified pointer (SFR.PTR). Application example: Used self checking during normal operation.
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
LOCAL INTERFACE
PD784046(A) connected external memory (memory mapped I/O), supporting 1Mbyte memory space (refer Figure 9-1). Figure 9-1. Example Local Interface (with external 8-bit specified)
Address
PD784046(A)
A16-A19
SRAM PROM Character generator
AD0-AD7
Decoder
Data
ASTB
Latch
Address AD8-AD15
Gate array expansion Centronics I/F, etc.
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Memory Expansion
external program memory data memory expanded from bytes bytes seven steps. When external device connected, address/data read/write strobe signals controlled using ports through through pins. functions these ports pins memory expansion mode register (MM). Table 9-1. Setting Function
Memory Expansion Mode Register MM0-MM3 Port mode External memory expansion mode Port P40-P47 General-purpose port AD0-AD7 AD15 stepwise. Rest pins used general-purpose port pins. through stepwise. Rest pins used general-purpose port pins. ASTB Port P50-P57 Function Port P60-P63 P90-P93
Remark through AD15 used address bus. number pins ports that used address pins changed according size external memory connected (external address space), that external memory expanded stepwise. pins used address pins used general-purpose port pins (refer Table 9-2). external address space seven steps Table 9-2. Operations Ports external memory expansion mode)
Port Port bytes less Note bytes less Note AD10 AD11 AD12 AD13 AD14 AD15 bytes less Note bytes less Note bytes less 256K bytes less bytes less External address space
General-purpose port
Note
When external 16-bit specified, such that external address space this size. When external 16-bit specified, such that pins port (P50 through P57) used pins (AD8 through AD15).
Caution
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Memory Space
1M-byte memory space divided into following eight spaces logical addresses. Each space controlled using programmable wait function sizing function. Figure 9-2. Memory Space
512K bytes
256K bytes 128K bytes bytes bytes bytes bytes bytes
Programmable Wait
wait state inserted each eight memory spaces while LWR, signals active. Even memories with different access times connected, therefore, overall efficiency system degraded. addition, address wait function that extends active period ASTB signal also available extend address decode time (this function spaces).
Sizing Function
PD784046(A) change external data width between bits when external device connected. Even memory space divided eight, width each memory space specified independently.
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
STANDBY FUNCTION
PD784046(A) following standby function modes that reduce power consumption chip. HALT mode This mode stops operating clock CPU. reduce average power consumption through intermittent operation combination normal operation this mode. IDLE mode This mode stops entire system with operation oscillation circuit continuing. Normal program operation restored from this mode with power consumption close that STOP mode time equivalent that HALT mode. STOP mode This mode stops oscillator stops internal operations chip minimize power consumption level only leakage current. These modes programmable. Macro service started from HALT mode. Figure 10-1. Standby Status Transition
Waits stabilization oscillation
ilizati stab Oscillati expires time
Macro service request
Program operation
first processing macro service
Macro service
STOP (standby)
IDLE (standby)
Interrupt request masked interrupt
HALT (standby)
Note
Only unmasked interrupt request
Remark Only external input valid. watchdog timer cannot used release standby mode (STOP/HALT/IDLE).
Data Sheet U13121EJ1V1DS
rvic
ttin
µPD784044(A), 784046(A)
RESET FUNCTION
When level input RESET pin, internal hardware initialized (reset status). When RESET signal goes high, following data program counter (PC). Lower bits contents address 0000H Middle bits contents address 0001H Higher bits contents assumed branch destination address program execution started from this address. Therefore, program reset started from address. contents each register program necessary. prevent malfunctioning noise, noise rejection circuit provided RESET input circuit. This noise rejection circuit sampling circuit with analog delay. Figure 11-1. Accepting Reset
Delay
Delay
Delay
initialization
Instruction execution reset start address
RESET (input)
Internal reset signal
Reset starts
Reset ends
Keep RESET signal active until oscillation stabilization time (about elapses when executing reset operation power application when releasing STOP mode reset. Figure 11-2. Reset Operation Power Application
Oscillation stabilization time
Delay
Initializes
Instruction execution reset start address
RESET (input)
Internal reset signal
Reset ends
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
INSTRUCTION
8-bit instructions combination realized writing MOV, XCH, ADD, ADDC, SUB, SUBC, AND, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHKL, CHKLA Table 12-1. Instructions 8-Bit Addressing
Operand #byte Operand (MOV) (MOV) (MOV)Note (XCH)Note (XCH) (MOV) (XCH) ADDNote (XCH) saddr saddr' !addr16 !!addr24 [saddrp] [%saddrg] ADDNote PSWL PSWH (MOV) (XCH) (ADD)Note RORNote MULU DIVUW saddr (MOV)Note ADDNote ADDNote (ADD)Note ADDNote DBNZ PUSH CHKL CHKLA !addr16 !!addr24 [saddrp] [%saddrg] mem3 ROR4 ROL4 PSWL PSWH STBC, [TDE+] [TDE-] (MOV) (ADD)Note MOVMNote MOVBKNote DBNZ (MOV) ADDNote ADDNote ADDNote (ADD)Note ADDNote [WHL+] [WHL-] NoneNote
(ADD)Note (ADD)Note (ADD)Note (ADD)Note ADDNote (MOV) ADDNote ADDNote ADDNote (XCH)
(ADD)Note ADDNote
Notes ADDC, SUB, SUBC, AND, XOR, same ADD. Either second operand used, second operand operand address. ROL, RORC, ROLC, SHR, same ROR. XCHM, CMPME, CMPMNE, CMPMNC, CMPMC same MOVM. XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC same MOVBK. saddr saddr2 this combination, some instructions have short code length.
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
16-bit instructions combination realized writing MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW Table 12-2. Instructions 16-Bit Addressing
Operand #word Operand (MOVW) ADDW
Note
saddrp saddrp' (MOVW)Note (XCHW)Note
sfrp
!addr16 !!addr24
[saddrp] [%saddrg]
[WHL+]
byte
NoneNote
(MOVW) (XCHW)
(MOVW) (XCHW)
MOVW (XCHW)
(MOVW) XCHW
MOVW XCHW
(MOVW) (XCHW) MULWNote INCW DECW INCW DECW
(ADDW)Note (ADDW)Note (ADDW)Note (ADDW)Note MOVW ADDW
Note
(MOVW) (XCHW)
MOVW XCHW
MOVW XCHW ADDWNote MOVW XCHW ADDWNote
MOVW XCHW ADDWNote
MOVW
SHRW SHLW
(ADDW)Note ADDWNote saddrp MOVW ADDW
Note
(MOVW)Note MOVW (ADDW)Note ADDWNote
sfrp
MOVW
MOVW
MOVW
PUSH MOVTBLW
ADDWNote (ADDW)Note ADDWNote !addr16 !!addr24 [saddrp] [%saddrg] ADDWG SUBWG post MOVW MOVW (MOVW) MOVW
PUSH
PUSH PUSHU POPU
[TDE+] byte
(MOVW)
SACW MACW MACSW
Notes SUBW CMPW same ADDW. Either second operand used, second operand operand address. saddrp saddrp2 this combination, some instructions have short code length. MULUW DIVUX same MULW.
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
24-bit instructions combination realized writing MOVG, ADDG, SUBG, INCG, DECG, PUSH, Table 12-3. Instructions 24-Bit Addressing
Operand Operand (MOVG) (ADDG) (SUBG) MOVG ADDG SUBG (MOVG) (ADDG) (SUBG) (MOVG) (ADDG) (SUBG) #imm24 (MOVG) (ADDG) (SUBG) MOVG ADDG SUBG (MOVG) ADDG SUBG MOVG MOVG INCG DECG PUSH saddrg !!addr24 mem1 [%saddrg] MOVG (MOVG) (MOVG) MOVG MOVG MOVG INCG DECG MOVG MOVG (MOVG) MOVG MOVG MOVG saddrg !!addr24 mem1 [%saddrg] NoneNote
Note
Either second operand used, second operand operand address.
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BCLR, BFSET Table 12-4. Addressing Manipulation Instructions
Operand saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit !addr16.bit Operand !!addr24.bit MOV1 AND1 XOR1 saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit !addr16.bit !!addr24.bit MOV1 NOT1 SET1 CLR1 BTCLR BFSET /saddr.bit /sfr.bit /A.bit /X.bit /PSWL.bit /PSWH.bit /mem2.bit /!addr16.bit /!!addr24.bit AND1 NOT1 SET1 CLR1 NoneNote
Note
Either second operand used, second operand operand address.
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Call/return/branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BNZ, BNE, BNC, BNL, BNV, BPO, BPE, BLT, BGE, BLE, BGT, BNH, BTCLR, BFSET, DBNZ Table 12-5. Addressing Call/Return/Branch Instructions
Operand instruction address Basic instruction BCNote CALL CALL RETCS RETCSB Compound instruction BTCLR BFSET DBNZ CALL CALL CALL CALL CALL CALLF CALLT BRKCS RETI RETB $addr20 $!addr20 !addr16 !!addr20 [rp] [rg] !addr11 [addr5] None
Note
BNZ, BNE, BNC, BNL, BNV, BPO, BPE, BLT, BGE, BLE, BGT, BNH, same
Other instructions ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, SWRS
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
ELECTRICAL SPECIFICATIONS
Caution followings specifications µPD784044(A), (A1), (A2). µPD784046(A), (A1), (A2), these target specifications. Electrical specifications µPD784044(A), 784046(A) (1/6) Absolute Maximum Ratings
Parameter Supply voltage Symbol Input voltage Output voltage Low-level output current output pins Total output pins High-level output current output pins Total output pins Analog input voltage Note converter reference input voltage Operating temperature Storage temperature Note Conditions Ratings -0.5 +7.0 -0.5 -0.5 +0.5 -0.5 -0.5 -100 -0.5 -0.5 -0.5 -0.5 +150 Unit
Notes Pins other than pins Note Pins P70/ANI0-P77/ANI7, P80/ANI8-P87/ANI15 Caution parameters exceeds absolute maximum ratings, even momentarily, quality product impaired. absolute maximum ratings values that physically damage product(s). sure product(s) within ratings. Recommended Operating Conditions
Oscillation Frequency
Capacitance
Parameter Input capacitance Output capacitance capacitance Symbol except measured pins Conditions MIN. TYP. MAX. Unit
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Electrical specifications µPD784044(A), 784046(A) (2/6) Oscillation Circuit Characteristics
Resonator Ceramic resonator crystal resonator Recommended Circuit Item Oscillation frequency MIN. MAX. Unit
External clock
input frequency
OpenNote HCMOS inverter
input rise, fall time
input high-, low-level width
Note
When EXTC oscillation stabilization time specification register (OSTS) Input reverse phase clock when EXTC
Caution
When using system clock oscillation circuit, wire portion enclosed dotted line diagram above follows prevent adverse influence from wiring capacitance: Keep wiring length short possible. cross wiring with other signal lines. route wiring vicinity line through which high alternating current flows. Always keep ground potential capacitor oscillation circuit same potential VSS. ground capacitor ground pattern through which high current flows. extract signal from oscillation circuit.
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Electrical specifications µPD784044(A), 784046(A) (3/6) Characteristics
Parameter Low-level input voltage High-level input voltage Symbol Low-level output voltage High-level output voltage Input leakage current Analog input leakage current Output leakage current supply current LIAN Data retention voltage Data retention current DDDR DDDR Note Note -400 Note Note Operating mode MHz) HALT mode MHz) IDLE mode MHz) STOP mode STOP mode VDDDR VDDDR Pull-up resistor Conditions MIN. TYP. MAX. 0.45 Unit
Notes Pins other than pins Note P20/NMI, P21/INTP0/TO00, P22/INTP1/TO01, P23/INTP2/TO02, P24/INTP3/TO03, P25/INTP4, P26/ INTP5/TI2, P27/INTP6/TI3, P34/ASCK/SCK1, P37/ASCK2/SCK2, RESET Input pins (except P70/ANI0-P77/ANI7, P80/ANI8-P87/ANI15 used analog inputs) Pins P70/ANI0-P77/ANI7, P80/ANI8-P87/ANI15 (pins used analog input, only during nonsampling operation)
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Electrical specifications µPD784044(A), 784046(A) (4/6) Characteristics Read/write operation
Parameter System clock cycle time Address setup time (vs. ASTB) Address hold time (vs. ASTB) ASTB high-level width AddressRD delay time RDaddress float time Addressdata input time RDdata input time ASTBRD delay time Data hold time (vs. RDaddress active time low-level width AddressLWR, delay time LWR, HWRdata output time ASTBLWR, delay time Data setup time (vs. LWR, HWR) Data hold time (vs. LWR, HWR) LWR, ASTB delay time LWR, low-level width AddressWAIT input time ASTBWAIT input time ASTBWAIT hold time ASTBWAIT delay time RDWAIT input time RDWAIT hold time RDWAIT delay time LWR, HWRWAIT input time LWR, HWRWAIT hold time LWR, HWRWAIT delay time Symbol SAST HSTA WSTH DAID DRID DSTR HRID DWOD DSTW SODW HWOD DWST DAWT DSTWT HSTWT DSTWTH DRWT HRWT DRWTH DWWT HWWT DWWTH 0.5T (1.5 0.5T 1.5T (1.5 1.5T (1.5 (1.5 Note Note Note 0.5T (1.5 (2.5 (1.5 0.5T (0.5 0.5T (0.5 Expression MIN. MAX. Unit
Note
Specification when external wait inserted
Remarks tCYK 1/fCLK (fCLK internal system clock frequency) when address wait inserted, otherwise, indicates number wait cycles specifying external wait pins (WAIT) programmable wait control registers (PWC1, PWC2). tDSTWTH, tDRWTH, tDWWTH). Calculate values expression column with system clock cycle time used because these values depend system clock cycle time (tCYK values above expression column calculated based
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Electrical specifications µPD784044(A), 784046(A) (5/6) Serial Operation
Parameter Serial clock cycle time Symbol CYSK Conditions SCK1, SCK2 output SCK1, SCK2 input Serial clock low-level width WSKL External clock MIN. 0.5T SFT-40 0.5T SFT-40 MAX. Unit
SCK1, SCK2 output SCK1, SCK2 input External clock
Serial clock high-level width
WSKH
SCK1, SCK2 output SCK1, SCK2 input External clock
SI1, setup time (vs. SCK1, SCK2) SI1, hold time (vs. SCK1, SCK2) SCK1, SCK2SO1, output delay time
SSSK HSSK DSBSK
Remarks TSFT value software. minimum value tCYK tCYK 1/fCLK (fCLK internal system clock frequency) Other Operations
Parameter high, low-level width INTP0-INTP6 high, low-level width TI2, high, low-level width RESET high, low-level width Symbol WNIH WNIL WITH, WITL WTIH WTIL WRSH WRSL Conditions MIN. MAX. Unit
CYSMP CYSMP
Remarks tCYSMP sampling clock noise protection control register (NPC) software. When tCYSMP tCYK When tCYSMP tCYK tCYK 1/fCLK (fCLK internal system clock frequency) NIn: 0-6) Timing Test Point
Test point
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Electrical specifications µPD784044(A), 784046(A) (6/6) Converter Characteristics AVSS AVDD VDD)
Parameter Resolution Total error Note Quantization error Conversion time Sampling time Zero-scale error Note CONV SAMP Full-scale error Note Nonlinearity error Note Analog input voltage converter reference input voltage current supply current converter data retention current DDDR STOP mode DDDR DDDR -0.3 ±1.5 ±1.5 ±1.5 ±1.5 ±1.5 ±1.5 ±3.5 ±4.5 ±3.5 ±4.5 ±2.5 ±4.5 +0.3 Symbol Conditions MIN. ±0.5 ±0.7 ±1/2 TYP. MAX. Unit %FSR %FSR
Note
quantization error excluded.
Remark tCYK 1/fCLK (fCLK internal system clock frequency).
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Electrical specifications µPD784044(A1), 784046(A1) (1/6) Absolute Maximum Ratings
Parameter Supply voltage Symbol Input voltage Output voltage Low-level output current output pins Total output pins High-level output current output pins Total output pins Analog input voltage Note converter reference input voltage Operating temperature Storage temperature Note Conditions Ratings -0.5 +7.0 -0.5 -0.5 +0.5 -0.5 -0.5 -100 -0.5 -0.5 -0.5 -0.5 +110 +150 Unit
Notes Pins other than pins Note Pins P70/ANI0-P77/ANI7, P80/ANI8-P87/ANI15 Caution parameters exceeds absolute maximum ratings, even momentarily, quality product impaired. absolute maximum ratings values that physically damage product(s). sure product(s) within ratings. Recommended Operating Conditions
Oscillation Frequency +110
Capacitance
Parameter Input capacitance Output capacitance capacitance Symbol except measured pins Conditions MIN. TYP. MAX. Unit
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Electrical specifications µPD784044(A1), 784046(A1) (2/6) Oscillation Circuit Characteristics +110
Resonator Ceramic resonator crystal resonator Recommended Circuit Item Oscillation frequency MIN. MAX. Unit
External clock
input frequency
OpenNote HCMOS inverter
input rise, fall time
input high-, low-level width
Note
When EXTC oscillation stabilization time specification register (OSTS) Input reverse phase clock when EXTC
Caution
When using system clock oscillation circuit, wire portion enclosed dotted line diagram above follows prevent adverse influence from wiring capacitance: Keep wiring length short possible. cross wiring with other signal lines. route wiring vicinity line through which high alternating current flows. Always keep ground potential capacitor oscillation circuit same potential VSS. ground capacitor ground pattern through which high current flows. extract signal from oscillation circuit.
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Electrical specifications µPD784044(A1), 784046(A1) (3/6) Characteristics +110
Parameter Low-level input voltage High-level input voltage Symbol Low-level output voltage High-level output voltage Input leakage current Analog input leakage current Output leakage current supply current LIAN Data retention voltage Data retention current DDDR DDDR Note Note -400 Note Note Operating mode MHz) HALT mode MHz) IDLE mode MHz) STOP mode STOP mode VDDDR VDDDR Pull-up resistor 1000 Conditions MIN. TYP. MAX. 0.45 Unit
Notes Pins other than pins Note P20/NMI, P21/INTP0/TO00, P22/INTP1/TO01, P23/INTP2/TO02, P24/INTP3/TO03, P25/INTP4, P26/ INTP5/TI2, P27/INTP6/TI3, P34/ASCK/SCK1, P37/ASCK2/SCK2, RESET Input pins (except P70/ANI0-P77/ANI7, P80/ANI8-P87/ANI15 used analog inputs) Pins P70/ANI0-P77/ANI7, P80/ANI8-P87/ANI15 (pins used analog input, only during nonsampling operation)
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Electrical specifications µPD784044(A1), 784046(A1) (4/6) Characteristics +110 Read/write operation
Parameter System clock cycle time Address setup time (vs. ASTB) Address hold time (vs. ASTB) ASTB high-level width AddressRD delay time RDaddress float time Addressdata input time RDdata input time ASTBRD delay time Data hold time (vs. RDaddress active time low-level width AddressLWR, delay time LWR, HWRdata output time ASTBLWR, delay time Data setup time (vs. LWR, HWR) Data hold time (vs. LWR, HWR) LWR, ASTB delay time LWR, low-level width AddressWAIT input time ASTBWAIT input time ASTBWAIT hold time ASTBWAIT delay time RDWAIT input time RDWAIT hold time RDWAIT delay time LWR, HWRWAIT input time LWR, HWRWAIT hold time LWR, HWRWAIT delay time Symbol SAST HSTA WSTH DAID DRID DSTR HRID DWOD DSTW SODW HWOD DWST DAWT DSTWT HSTWT DSTWTH DRWT HRWT DRWTH DWWT HWWT DWWTH 0.5T (1.5 0.5T 1.5T (1.5 1.5T (1.5 (1.5 Note Note Note 0.5T (1.5 (2.5 (1.5 0.5T (0.5 0.5T (0.5 Expression MIN. MAX. Unit
Note
Specification when external wait inserted
Remarks tCYK 1/fCLK (fCLK internal system clock frequency) when address wait inserted, otherwise, indicates number wait cycles specifying external wait pins (WAIT) programmable wait control registers (PWC1, PWC2). tDSTWTH, tDRWTH, tDWWTH). Calculate values expression column with system clock cycle time used because these values depend system clock cycle time (tCYK values above expression column calculated based
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Electrical specifications µPD784044(A1), 784046(A1) (5/6) Serial Operation +110
Parameter Serial clock cycle time Symbol CYSK Conditions SCK1, SCK2 output SCK1, SCK2 input Serial clock low-level width WSKL External clock MIN. 0.5T SFT-40 0.5T SFT-40 MAX. Unit
SCK1, SCK2 output SCK1, SCK2 input External clock
Serial clock high-level width
WSKH
SCK1, SCK2 output SCK1, SCK2 input External clock
SI1, setup time (vs. SCK1, SCK2) SI1, hold time (vs. SCK1, SCK2) SCK1, SCK2SO1, output delay time
SSSK HSSK DSBSK
Remarks TSFT value software. minimum value tCYK tCYK 1/fCLK (fCLK internal system clock frequency) Other Operations +110
Parameter high, low-level width INTP0-INTP6 high, low-level width TI2, high, low-level width RESET high, low-level width Symbol WNIH WNIL WITH, WITL WTIH WTIL WRSH WRSL Conditions MIN. MAX. Unit
CYSMP CYSMP
Remarks tCYSMP sampling clock noise protection control register (NPC) software. When tCYSMP tCYK When tCYSMP tCYK tCYK 1/fCLK (fCLK internal system clock frequency) NIn: 0-6) Timing Test Point
Test point
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Electrical specifications µPD784044(A1), 784046(A1) (6/6) Converter Characteristics +110 AVSS AVDD VDD)
Parameter Resolution Total error Note Quantization error Conversion time Sampling time Zero-scale error Note CONV SAMP Full-scale error Note Nonlinearity error Note Analog input voltage converter reference input voltage current supply current converter data retention current DDDR STOP mode DDDR DDDR -0.3 ±1.5 ±1.5 ±1.5 ±1.5 ±1.5 ±1.5 ±3.5 ±4.5 ±3.5 ±4.5 ±2.5 ±4.5 +0.3 1000 Symbol Conditions MIN. ±0.5 ±0.7 ±1/2 TYP. MAX. Unit %FSR %FSR
Note
quantization error excluded.
Remark tCYK 1/fCLK (fCLK internal system clock frequency).
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Electrical specifications µPD784044(A2), 784046(A2) (1/6) Absolute Maximum Ratings
Parameter Supply voltage Symbol Input voltage Output voltage Low-level output current output pins Total output pins High-level output current output pins Total output pins Analog input voltage Note converter reference input voltage Operating temperature Storage temperature Note Conditions Ratings -0.5 +7.0 -0.5 -0.5 +0.5 -0.5 -0.5 -100 -0.5 -0.5 -0.5 -0.5 +125 +150 Unit
Notes Pins other than pins Note Pins P70/ANI0-P77/ANI7, P80/ANI8-P87/ANI15 Caution parameters exceeds absolute maximum ratings, even momentarily, quality product impaired. absolute maximum ratings values that physically damage product(s). sure product(s) within ratings. Recommended Operating Conditions
Oscillation Frequency +125
Capacitance
Parameter Input capacitance Output capacitance capacitance Symbol except measured pins Conditions MIN. TYP. MAX. Unit
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Electrical specifications µPD784044(A2), 784046(A2) (2/6) Oscillation Circuit Characteristics +125
Resonator Ceramic resonator crystal resonator Recommended Circuit Item Oscillation frequency MIN. MAX. Unit
External clock
input frequency
OpenNote HCMOS inverter
input rise, fall time
input high-, low-level width
Note
When EXTC oscillation stabilization time specification register (OSTS) Input reverse phase clock when EXTC
Caution
When using system clock oscillation circuit, wire portion enclosed dotted line diagram above follows prevent adverse influence from wiring capacitance: Keep wiring length short possible. cross wiring with other signal lines. route wiring vicinity line through which high alternating current flows. Always keep ground potential capacitor oscillation circuit same potential VSS. ground capacitor ground pattern through which high current flows. extract signal from oscillation circuit.
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Electrical specifications µPD784044(A2), 784046(A2) (3/6) Characteristics +125
Parameter Low-level input voltage High-level input voltage Symbol Low-level output voltage High-level output voltage Input leakage current Analog input leakage current Output leakage current supply current LIAN Data retention voltage Data retention current DDDR DDDR Note Note -400 Note Note Operating mode MHz) HALT mode MHz) IDLE mode MHz) STOP mode STOP mode VDDDR VDDDR Pull-up resistor 1000 Conditions MIN. TYP. MAX. 0.45 Unit
Notes Pins other than pins Note P20/NMI, P21/INTP0/TO00, P22/INTP1/TO01, P23/INTP2/TO02, P24/INTP3/TO03, P25/INTP4, P26/ INTP5/TI2, P27/INTP6/TI3, P34/ASCK/SCK1, P37/ASCK2/SCK2, RESET Input pins (except P70/ANI0-P77/ANI7, P80/ANI8-P87/ANI15 used analog inputs) Pins P70/ANI0-P77/ANI7, P80/ANI8-P87/ANI15 (pins used analog input, only during nonsampling operation)
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Electrical specifications µPD784044(A2), 784046(A2) (4/6) Characteristics +125 Read/write operation
Parameter System clock cycle time Address setup time (vs. ASTB) Address hold time (vs. ASTB) ASTB high-level width AddressRD delay time RDaddress float time Addressdata input time RDdata input time ASTBRD delay time Data hold time (vs. RDaddress active time low-level width AddressLWR, delay time LWR, HWRdata output time ASTBLWR, delay time Data setup time (vs. LWR, HWR) Data hold time (vs. LWR, HWR) LWR, ASTB delay time LWR, low-level width AddressWAIT input time ASTBWAIT input time ASTBWAIT hold time ASTBWAIT delay time RDWAIT input time RDWAIT hold time RDWAIT delay time LWR, HWRWAIT input time LWR, HWRWAIT hold time LWR, HWRWAIT delay time Symbol SAST HSTA WSTH DAID DRID DSTR HRID DWOD DSTW SODW HWOD DWST DAWT DSTWT HSTWT DSTWTH DRWT HRWT DRWTH DWWT HWWT DWWTH 0.5T (1.5 0.5T 1.5T (1.5 1.5T (1.5 (1.5 Note Note Note 0.5T (1.5 (2.5 (1.5 0.5T (0.5 0.5T (0.5 Expression MIN. MAX. Unit
Note
Specification when external wait inserted
Remarks tCYK 1/fCLK (fCLK internal system clock frequency) when address wait inserted, otherwise, indicates number wait cycles specifying external wait pins (WAIT) programmable wait control registers (PWC1, PWC2). tDSTWTH, tDRWTH, tDWWTH). Calculate values expression column with system clock cycle time used because these values depend system clock cycle time (tCYK values above expression column calculated based
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Electrical specifications µPD784044(A2), 784046(A2) (5/6) Serial Operation +125
Parameter Serial clock cycle time Symbol CYSK Conditions SCK1, SCK2 output SCK1, SCK2 input Serial clock low-level width WSKL External clock MIN. 0.5T SFT-40 0.5T SFT-40 MAX. Unit
SCK1, SCK2 output SCK1, SCK2 input External clock
Serial clock high-level width
WSKH
SCK1, SCK2 output SCK1, SCK2 input External clock
SI1, setup time (vs. SCK1, SCK2) SI1, hold time (vs. SCK1, SCK2) SCK1, SCK2SO1, output delay time
SSSK HSSK DSBSK
Remarks TSFT value software. minimum value tCYK tCYK 1/fCLK (fCLK internal system clock frequency) Other Operations +125
Parameter high, low-level width INTP0-INTP6 high, low-level width TI2, high, low-level width RESET high, low-level width Symbol WNIH WNIL WITH, WITL WTIH WTIL WRSH WRSL Conditions MIN. MAX. Unit
CYSMP CYSMP
Remarks tCYSMP sampling clock noise protection control register (NPC) software. When tCYSMP tCYK When tCYSMP tCYK tCYK 1/fCLK (fCLK internal system clock frequency) NIn: 0-6) Timing Test Point
Test point
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Electrical specifications µPD784044(A2), 784046(A2) (6/6) Converter Characteristics +125 AVSS AVDD VDD)
Parameter Resolution Total error Note Quantization error Conversion time Sampling time Zero-scale error Note CONV SAMP Full-scale error Note Nonlinearity error Note Analog input voltage converter reference input voltage current supply current converter data retention current DDDR STOP mode DDDR DDDR -0.3 ±1.5 ±1.5 ±1.5 ±1.5 ±1.5 ±1.5 ±3.5 ±4.5 ±3.5 ±4.5 ±2.5 ±4.5 +0.3 1000 Symbol Conditions MIN. ±0.5 ±0.7 ±1/2 TYP. MAX. Unit %FSR %FSR
Note
quantization error excluded.
Remark tCYK 1/fCLK (fCLK internal system clock frequency).
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Read Operation bits)
tCYK (CLK)
AD8-AD15 (Output) tSAST AD0-AD7 (Input/output) Hi-Z tDAID
High-order address
High-order address
Low-order address (output) tWSTH
Hi-Z
Data (input)
Hi-Z
Low-order address (output)
Hi-Z
tHRID
ASTB (Output) tHSTA tFRA (Output) tDSTR tDRID tDAR tWRL tDSTWTH tHSTWT tDSTWT tDRWT tDAWT WAIT (Input) tHRWT tDRWTH tDRA
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Write Operation bits)
tCYK (CLK)
AD8-AD15 (Output) tSAST Low-order address (Output) tWSTH ASTB (Output) tHSTA (Output) tDSTW
High-order address
High-order address
AD0-AD7 (Output)
Undefined
Data (Output) tHWOD
Low-order address (Output)
tDWST
tDWOD tDAW tDSTWTH tHSTWT tDSTWT tDWWT tHWWT tDWWTH tWWL
tSODW
tDAWT WAIT (Input)
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Read Operation bits)
tCYK (CLK)
tSAST AD8-AD15 AD0-AD7 (Input/output) Hi-Z
tDAID Hi-Z Data (Input) Hi-Z Address (Output) Hi-Z
Address (Output) tWSTH
tHRID
ASTB (Output) tHSTA tFRA (Output) tDSTR tDRID tDAR tDSTWTH tHSTWT tDSTWT tDRWT tDAWT WAIT (Input) tHRWT tDRWTH tWRL tDRA
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Write Operation bits)
tCYK (CLK)
AD8-AD15 AD0-AD7 (Output)
tSAST Address (Output) tWSTH Undefined Data (Output) tHWOD Address (Output)
ASTB (Output) tHSTA HWR, (Output) tDSTW tDWOD tDAW tDSTWTH tHSTWT tDSTWT tDWWT tHWWT tDWWTH tWWL tSODW tDWST
tDAWT WAIT (Input)
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Serial Operation
tCYSK tWSKL SCK1, SCK2 tDSBSK SO1, tWSKH
SI1, tSSSK tHSSK
Interrupt Input Timing
tWNIH tWNIL
tWITH
tWITL
INTP0-INTP6
Reset Input Timing
tWRSH tWRSL
RESET
Timer Input Timing
tWTIH tWTIL
TI2,
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
PACKAGE DRAWING
PLASTIC (14x14)
detail lead
NOTE
Each lead centerline located within 0.13 (0.005 inch) true position (T.P.) maximum material condition.
ITEM
MILLIMETERS 17.2±0.4 14.0±0.2 14.0±0.2 17.2±0.4 0.825 0.825 0.30±0.10 0.13 0.65 (T.P.) 1.6±0.2 0.8±0.2 0.15 +0.10 -0.05 0.10 2.7±0.1 0.1±0.1 5°±5° MAX.
INCHES 0.677±0.016 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.677±0.016 0.032 0.032 0.012 +0.004 -0.005 0.005 0.026 (T.P.) 0.063±0.008 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 +0.005 -0.004 0.004±0.004 5°±5° 0.119 MAX. S80GC-65-3B9-5
Remark package dimensions materials versions same those mass-production versions.
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
RECOMMENDED SOLDERING CONDITIONS
These products should soldered mounted under conditions recommended below. details soldering conditions, refer information document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended, please contact your representative. Table 15-1. Surface-Mount Type Soldering Conditions
80-pin plastic 80-pin plastic 80-pin plastic
Recommended Condition Symbol IR35-00-3
Soldering Method Infrared reflow Partial heating
Soldering Conditions Package peak temperature: Time: sec. max. (210 min.), Number times: max. temterature: max., sec. max. (per side device)
Caution
µPD784046(A), (A1), (A2) under development. Therefore, soldering conditions µPD784046(A), (A1), (A2) undefined.
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
APPENDIX DEVELOPMENT TOOLS
following development tools available developing systems using PD784046(A). Refer Cautions when development tools used. Language processing software
RA78K4 CC78K4 DF784046 CC78K4-L 78K/IV series common assembler package 78K/IV series common compiler package Device file PD784046 subseries 78K/IV series common compiler library source file
Flash memory writing tools
Flashpro (Part number: FL-PR2) FA-80GC Dedicated flash programmer microcomputers incorporating flash memory Adapter flash memory writing
Debugging tools When using IE-78K4-NS in-circuit emulator
IE-78K4-NS Note IE-70000-MC-PS-B IE-70000-98-IF-C Note IE-70000-CD-IF Note IE-70000-PC-IF-C Note IE-784046-NS-EM1 Note NP-80GC EV-9200GC-80 ID78K4-NS Note SM78K4 DF784046 78K/IV series common in-circuit emulator Power supply unit IE-78K4-NS Interface adapter necessary when PC-9800 series computer (except notebook-type personal computer) used host machine card interface cable necessary when PC-9800 series notebook-type personal computer used host machine Interface adapter necessary when PC/ATor compatible machine used host machine Emulation board emulating PD784046 subseries Emulation probe 80-pin plastic (GC-3B9 type) Socket mounted board target system 80-pin plastic (GC-3B9 type) Integrated debugger IE-78K4-NS 78K/IV series common system simulator Device file PD784046 subseries
Note
Under development
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
When using IE-784000-R in-circuit emulator
IE-784000-R IE-70000-98-IF-B IE-70000-98-IF-C Note IE-70000-98N-IF IE-70000-PC-IF-B IE-70000-PC-IF-C Note IE-78000-R-SV3 IE-784000-R-EM IE-784046-NS-EM1 Note IE-784046-R-EM1 IE78K4-R-EX2 Note EP-78230GC-R EV-9200GC-80 ID78K4 SM78K4 DF784046 78K/IV series common in-circuit emulator Interface adapter necessary when PC-9800 series computer (except notebook-type personal computer) used host machine Interface adapter cable necessary when PC-9800 series notebook-type personal computer used host machine Interface adapter necessary when PC/AT compatible machine used host machine Interface adapter cable necessary when used host machine 78K/IV series common emulation board Emulation board emulating PD784046 subseries Emulation probe conversion board necessary when IE-784046-NS-EM1 used IE-784000-R. necessary when IE-784046-R-EM1 used. Emulation probe 80-pin plastic (GC-3B9 type) Socket mounted board target system made 80-pin plastic (GC-3B9 type) Integrated debugger IE-784000-R 78K/IV series common system simulator Device file PD784046 subseries
Note Under development Real-time
RX78K/IV MX78K4 Real-time 78K/IV series 78K/IV series
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Cautions when development tools used ID-78K4-NS, ID78K4, SM78K4 used combination with DF784046. CC78K4 RX78K/IV used combination with RA78K4 DF784046. Flashpro FA-80GC, NP-80GC product Naito Densei Machida Mfg. Co., Ltd. (TEL: (044)8223813). Contact distributor when purchasing these products. Host machines compatible with software follows:
Host Machine [OS] PC-9800 Series [Windows Software RA78K4 CC78K4 ID78K4-NS ID78K4 SM78K4 RX78K/IV MX78K4
Note Note
HP9000 series [HP-UX SPARCstation [SunOS NEWS (RISC) [NEWS-OS
PC/AT compatible machines [Japanese/English Windows]
Note Note
Note
based software
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
APPENDIX RELATED DOCUMENTS
Device-related documents
Document Name Document This document U11447E U11515E U10905E U10095E
µPD784044(A), 784046(A) Data Sheet µPD78F4046 Preliminary Product Information µPD784046 Subseries User's Manual Hardware
78K/IV Series User's Manual Instruction 78K/IV Series Application Note Software Basics
Development tool-related documents (User's Manuals)
Document Name RA78K4 Assembler Package Operation Language Structured Assembler Preprocessor CC78K4 Compiler Operation Language IE-78K4-NS IE-784000-R IE-784046-NS-EM1 IE-784046-R-EM1 EP-78230 SM78K4 System Simulator Windows Based Reference SM78K Series System Simulator ID78K4-NS Integrated Debugger ID78K4 Integrated Debugger Windows Based External Part User Open Interface Specifications Reference Reference U11334E U11162E U11743E U11572E U11571E U13356E U12903E U13744E U11677E EEU-1515 U10093E U10092E U12796E U10440E Document
Caution
contents above related documents subject change without notice. sure latest edition document when designing your system.
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Embedded software-related documents (User's Manual)
Document Name 78K/IV Series Real-Time Fundamental Installation 78K/IV Series MX78K4 Fundamental U10603E U10604E U11779E Document
Other documents
Document Name SEMICONDUCTOR SELECTION GUIDE Products Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades Semiconductor Devices Semiconductor Device Reliability Quality Control Guide Prevent Damages Semiconductor Devices Electrostatic Discharge (ESD) X13769E C10535E C11531E C10983E C11892E Document
Caution
contents above related documents subject change without notice. sure latest edition document when designing your system.
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
[MEMO]
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
[MEMO]
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
Regional Information
Some information contained this document vary from country country. Before using product your application, pIease contact office your country obtain list authorized representatives distributors. They will verify:
Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements
addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-3067-5800 Fax: 01-3067-5899 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics (France) S.A. Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860
Electronics Singapore Pte. Ltd.
Novena Square, Singapore Tel: 253-8311 Fax: 250-3583
Electronics Taiwan Ltd. Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
Brasil S.A.
Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829
J01.2
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
IEBus trademark Corporation. Windows either registered trademark trademark Microsoft Corporation United States and/or other countries. PC/AT trademark Corporation. HP9000 Series HP-UX trademarks Hewlett-Packard Company. SPARCstation trademark SPARC International, Inc. SunOS trademark Microsystems Inc. NEWS NEWS-OS trademarks Sony Corporation.
Some related document preliminary, marked such. Please keep this mind refer this information export this product from Japan regulated Japanese government. export this product prohibited without governmental license, need which must judged customer. export re-export this product from country other than Japan also prohibited without license from that country. Please call sales representative.
Data Sheet U13121EJ1V1DS
µPD784044(A), 784046(A)
information this document current March, 2001. information subject change without notice. actual design-in, refer latest publications NEC's data sheets data books, etc., most up-to-date specifications semiconductor products. products and/or types available every country. Please check with sales representative availability additional information. part this document copied reproduced form means without prior written consent NEC. assumes responsibility errors that appear this document. does assume liability infringement patents, copyrights other intellectual property rights third parties arising from semiconductor products listed this document other liability arising from such products. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. assumes responsibility losses incurred customers third parties arising from these circuits, software information. While endeavours enhance quality, reliability safety semiconductor products, customers agree acknowledge that possibility defects thereof cannot eliminated entirely. minimize risks damage property injury (including death) persons arising from defects semiconductor products, customers must incorporate sufficient safety measures their design, such redundancy, fire-containment, anti-failure features. semiconductor products classified into following three quality grades: "Standard", "Special" "Specific". "Specific" quality grade applies only semiconductor products developed based customer-designated "quality assurance program" specific application. recommended applications semiconductor product depend quality grade, indicated below. Customers must check quality grade each semiconductor product before using particular application. "Standard": Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade semiconductor products "Standard" unless otherwise expressly specified NEC's data sheets data books, etc. customers wish semiconductor products applications intended NEC, they must contact sales representative advance determine NEC's willingness support given application. (Note) "NEC" used this statement means Corporation also includes majority-owned subsidiaries. "NEC semiconductor products" means semiconductor product developed manufactured defined above).

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