µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 78
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INTEGRATED CIRCUIT
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
16-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
µPD784214A, 784215A, 784216A, 784217A, 784218A products µPD784216A/784218A Subseries 78K/IV Series. Besides high-speed high performance CPU, these controllers have ROM, RAM, ports, 8-bit resolution converters, timers, serial interfaces, real-time output port, interrupt functions, various other peripheral hardware. µPD784214AY, 784215AY, 784216AY, 784217AY, 784218AY based µPD784216A/784218A Subseries with addition multimaster-supporting interface. µPD78F4218A 78F4218AY, products with flash memory instead internal mask versions, various development tools also available. Detailed function descriptions provided following user's manuals. sure read them before designing. µPD784216A, 784218A, 784216AY, 784218AY Subseries Hardware User's Manual: U13570E 78K/IV Series Instructions User's Manual: U10905E
FEATURES
78K/IV Series Inherits peripheral functions µPD78078, 78078Y Subseries Minimum instruction execution time (@fXX 12.5 operation with main system clock) (@fXT 32.768 operation with subsystem clock) port: pins Timer/event counter: 16-bit timer/event counter unit 8-bit timer/event counter units Serial interface: channels UART/IOE (3-wire serial I/O): channels (3-wire serial I/O, supporting multimaster Note): channels Note µPD784216AY/784218AY Subseries only Supply voltage: Standby function HALT/STOP/IDLE mode low-power consumption mode: HALT/IDLE mode (with subsystem clock) Clock division function Watch timer: channel Watchdog timer: channel Clock output function Selectable from fXX, fXX/2, fXX/22, fXX/23, fXX/24, fXX/25, fXX/26, fXX/27, Buzzer output function Selectable from fXX/2 fXX/2 fXX/2 fXX/2 converter: 8-bit resolution channels converter: 8-bit resolution channels
APPLICATIONS
Cellular phones, PHS, cordless telephones, CD-ROM, equipment Unless otherwise specified, references this document µPD784218A refer µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY.
information this document subject change without notice. Before using this document, please confirm that this latest version.
devices/types available every country. Please check with local representative availability additional information.
Document U14121EJ4V0DS00 (4th edition) Date Published 2002 CP(K) Printed Japan
mark
shows major revised points.
2000
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
ORDERING INFORMATION
Part Number Package 100-pin plastic LQFP (fine pitch) 100-pin plastic 100-pin plastic LQFP (fine pitch) 100-pin plastic 100-pin plastic LQFP (fine pitch) 100-pin plastic 100-pin plastic LQFP (fine pitch) 100-pin plastic 100-pin plastic LQFP (fine pitch) 100-pin plastic 100-pin plastic LQFP (fine pitch) 100-pin plastic 100-pin plastic LQFP (fine pitch) 100-pin plastic 100-pin plastic LQFP (fine pitch) 100-pin plastic 100-pin plastic LQFP (fine pitch) 100-pin plastic 100-pin plastic LQFP (fine pitch) 100-pin plastic Internal (Bytes) Internal (Bytes) 3,584 3,584 5,120 5,120 8,192 8,192 12,800 12,800 12,800 12,800 3,584 3,584 5,120 5,120 8,192 8,192 12,800 12,800 12,800 12,800
Remark indicates code suffix.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
78K/IV SERIES LINEUP
Products mass-production Supports Supports multimaster
PD784038Y PD784038
PD784225Y PD784225
80-pin, correction added Supports multimaster
Standard models
PD784026
Enhanced converter, 16-bit timer, power management
Enhanced internal memory capacity Pin-compatible with PD784026 Supports multimaster
µPD784216AY PD784216A
100-pin, enhanced internal memory capacity
µPD784218AY PD784218A
Enhanced internal memory capacity, correction added
PD784054 µPD784046
ASSP models
PD784956A
inverter control
On-chip 10-bit converter
PD784938A
Enhanced functions PD784908, enhanced internal memory capacity, correction added. Supports multimaster
PD784908
On-chip IEBuscontroller
PD784928Y µPD784915
Software servo control On-chip analog circuit VCRs Enhanced timer
PD784928
Enhanced functions PD784915
PD784976A
On-chip controller/driver
Remark (Vacuum Fluorescent Display) referred documents, functions same.
(Fluorescent Indicator Panel) some
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
OVERVIEW FUNCTIONS (1/2)
Part Number Item Number basic instructions (mnemonics) General-purpose registers Minimum instruction execution time Internal memory Memory space ports Total CMOS input CMOS N-ch open-drain Pins with additional functionsNote Pins with pull-up resistor direct drive output Middle-voltage
µPD784214A, µPD784214AY µPD784215A, µPD784215AY µPD784216A, µPD784216AY µPD784217A, µPD784217AY µPD784218A, µPD784218AY
bits registers banks, bits registers banks (memory mapping) (@fXX 12.5 operation with main system clock) (@fXT 32.768 operation with subsystem clock) 3,584 bytes 5,120 bytes 8,192 bytes 12,800 bytes
with program data spaces combined bits bits Timer/event counter: (16-bit) Timer counter Pulse output Capture/compare register output Square wave output One-shot pulse output Pulse output output Square wave output Pulse output output Square wave output Pulse output output Square wave output Pulse output output Square wave output Pulse output output Square wave output Pulse output output Square wave output
Real-time output port Timer/event counter
Timer/event counter Timer counter (8-bit) Compare register Timer/event counter Timer counter (8-bit) Compare register Timer/event counter Timer counter (8-bit) Compare register Timer/event counter Timer counter (8-bit) Compare register Timer/event counter Timer counter (8-bit) Compare register Timer/event counter Timer counter (8-bit) Compare register Serial interface converter converter
UART/IOE (3-wire serial I/O): channels (on-chip baud rate generator) (3-wire serial I/O, multimaster supporting busNote channel 8-bit resolution channels 8-bit resolution channels
Notes Pins with additional functions included with pins. µPD784216AY/784218AY Subseries only
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
OVERVIEW FUNCTIONS (2/2)
Part Number Item Clock output Buzzer output Watch timer Watchdog timer Standby Interrupt Hardware sources Software sources Non-maskable Maskable
µPD784214A, µPD784214AY µPD784215A, µPD784215AY µPD784216A, µPD784216AY µPD784217A, µPD784217AY µPD784218A, µPD784218AY
Selectable from fXX, fXX/2, fXX/22, fXX/23, fXX/24, fXX/25, fXX/26, fXX/27, Selectable from fXX/210, fXX/211, fXX/212, fXX/213 channel channel HALT/STOP/IDLE modes power consumption mode (with subsystem clock): HALT/IDLE modes (internal: external: instruction, BRKCS instruction, operand error Internal: external: Internal: external: programmable priority levels service modes: Vectored interrupt/macro service/context switching
Supply voltage Package
100-pin plastic LQFP (fine pitch) 100-pin plastic
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
CONTENTS
DIFFERENCES BETWEEN MODELS µPD784216A, 784216AY/784218A, 784218AY SUBSERIES. MAJOR DIFFERENCES FROM µPD78078Y SUBSERIES CONFIGURATION (TOP VIEW). BLOCK DIAGRAM FUNCTIONS Port Pins Non-Port Pins Circuits Recommended Connections Unused Pins
ARCHITECTURE Memory Space Registers.
6.2.1 General-purpose registers 6.2.2 Control registers.30 6.2.3 Special function registers (SFRs).31
PERIPHERAL HARDWARE FUNCTIONS. Ports Clock Generator. Real-Time Output Port Timer/Event Counter Converter Converter Serial Interface.
7.7.1 Asynchronous serial interface/3-wire serial (UART/IOE) 7.7.2 Clocked serial interface (CSI)
Clock Output Function. Buzzer Output Function. 7.10 Edge Detection Function 7.11 Watch Timer 7.12 Watchdog Timer INTERRUPT FUNCTIONS. Interrupt Sources. Vectored Interrupt Context Switching Macro Service Application Example Macro Service
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
LOCAL INTERFACE Memory Expansion Programmable Wait STANDBY FUNCTION RESET FUNCTION INSTRUCTION ELECTRICAL SPECIFICATIONS PACKAGE DRAWINGS RECOMMENDED SOLDERING CONDITIONS. APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTS.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
DIFFERENCES BETWEEN MODELS µPD784216A, 784216AY/784218A, 784218AY SUBSERIES
only difference between µPD784214A, 784215A, 784216A, 784217A, 784218A lies internal memory capacity. µPD784214AY, 784215AY, 784216AY, 784217AY, 784218AY models with addition control function. µPD78F4216A, 78F4216AY, 78F4218A, 78F4218AY provided with KB/256 flash memory instead mask above models. These differences summarized Table 1-1. Table 1-1. Differences Between Models µPD784216A, 784216AY/784218A, 784218AY Subseries
Part Number Item Internal
µPD784214A, µPD784214AY µPD784215A, µPD784215AY µPD784216A, µPD784216AY µPD784217A, µPD784217AY µPD784218A, µPD784218AY µPD78F4216A, µPD78F4216AY µPD78F4218A, µPD78F4218AY
(Mask ROM) 3,584 bytes
(Mask ROM)
(Mask ROM) 12,800 bytes
(Mask ROM)
(Flash memory) 8,192 bytes ProvidedNote
(Flash memory) 12,800 bytes
Internal
5,120 bytes
8,192 bytes
Internal memory size switching register (IMS) correction
provided
provided
Provided
provided provided
Provided
External access status function Supply voltage Electrical specifications Recommended soldering conditions
provided
Provided
Provided
Refer data sheet each device.
provided
Provided
provided provided Provided
Provided
TEST
Provided provided
Note internal flash memory capacity internal capacity changed using internal memory size switching register (IMS). Caution There differences noise immunity noise radiation between flash memory mask versions. When pre-producing application with flash memory version then mass-producing with mask version, sure conduct sufficient evaluations commercial samples (not engineering samples) mask version.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
MAJOR DIFFERENCES FROM µPD78078Y SUBSERIES
Series Name Item Minimum instruction execution time With main system clock With subsystem clock Memory space ports Total CMOS input CMOS N-ch open-drain Pins with additional functionsNote Pins with pull-up resistor direct drive output Middle-voltage Timer/counter
µPD784216A, 784216AY/784218A, 784218AY Subseries
16-bit (@12.5 operation) (@32.768 operation)
µPD78078Y Subseries
8-bit (@5.0 operation) (@32.768 operation)
16-bit timer/event counter unit 8-bit timer/event counter units UART/IOE (3-wire serial I/O) channels (3-wire serial I/O, multimaster supporting busNote channel
16-bit timer/event counter unit 8-bit timer/event counter units UART/IOE (3-wire serial I/O) channel (3-wire serial I/O, 2-wire serial I/O, bus) channel (3-wire serial I/O, 3-wire serial with automatic transmit/receive function) channel provided provided provided provided HALT/STOP modes
Serial interface
Interrupts
Macro service Context switching Programmable priority
Provided Provided Provided levels HALT/STOP/IDLE modes power consumption mode: HALT/IDLE modes 100-pin plastic LQFP (fine pitch) 100-pin plastic
Standby function
Package
100-pin plastic LQFP (fine pitch) 100-pin plastic 100-pin ceramic WQFN (µPD78P078Y only)
Notes Pins with additional functions included with pins. µPD784216AY/784218AY Subseries only
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
CONFIGURATION (TOP VIEW)
100-pin plastic LQFP (fine pitch)
P120/RTP0 P121/RTP1 P122/RTP2 P123/RTP3 P124/RTP4 P125/RTP5 P126/RTP6 P127/RTP7 RESET P00/INTP0 P01/INTP1 P02/INTP2/NMI P03/INTP3 P04/INTP4 P05/INTP5 P06/INTP6 AVDDNote AVREF0 P10/ANI0 P62/A18 P61/A17 P60/A16 P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1 P40/AD0 P87/A7 P86/A6 P85/A5 P84/A4 P83/A3
AVSSNote
Notes Connect TEST directly pull-down resistor. pull-down connection, recommended resistor with resistance ranging from Connect AVDD VDD. Connect AVSS VSS. SCL0 SDA0 pins available µPD784216AY/784218AY Subseries products only. available µPD784218A, 784218AY Subseries products only.
Data Sheet U14121EJ4V0DS
P130/ANO0 P131/ANO1 AVREF1 P70/RxD2/SI2 P71/TxD2/SO2 P72/ASCK2/SCK2 P20/RxD1/SI1 P21/TxD1/SO1 P22/ASCK1/SCK1 P23/PCL P24/BUZ P25/SI0/SDA0Note P26/SO0 P27/SCK0/SCL0Note P80/A0 P81/A1 P82/A2
P11/ANI1
P12/ANI2 P13/ANI3
P14/ANI4 P15/ANI5
P16/ANI6 P17/ANI7
TESTNote P37/EXANote P36/TI01 P35/TI00 P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 P103/TI8/TO8 P102/TI7/TO7 P101/TI6/TO6 P100/TI5/TO5 P67/ASTB P66/WAIT P65/WR P64/RD P63/A19
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
100-pin plastic
P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1 P40/AD0 P87/A7 P57/A15 P56/A14 P86/A6 P85/A5
P60/A16 P61/A17 P62/A18 P63/A19 P64/RD P65/WR P66/WAIT P67/ASTB P100/TI5/TO5 P101/TI6/TO6 P102/TI7/TO7 P103/TI8/TO8 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/TI00 P36/TI01 P37/EXANote TESTNote P120/RTP0 P121/RTP1 P84/A4 P83/A3 P82/A2 P81/A1 P80/A0 P27/SCK0/SCL0Note P26/SO0 P25/SI0/SDA0Note P24/BUZ P23/PCL P22/ASCK1/SCK1 P21/TxD1/SO1 P20/RxD1/SI1 P72/ASCK2/SCK2 P71/TxD2/SO2 P70/RxD2/SI2 AVREF1 P131/ANO1 P130/ANO0 AVSSNote P17/ANI7 P16/ANI6 P15/ANI5 P14/ANI4 P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0 AVREF0 AVDDNote
P122/RTP2 P123/RTP3
P124/RTP4 P125/RTP5
Notes Connect TEST directly pull-down resistor. pull-down connection, recommended resistor with resistance ranging from Connect AVDD VDD. Connect AVSS VSS. SCL0 SDA0 pins available µPD784216AY/784218AY Subseries products only. available µPD784218A, 784218AY Subseries products only.
P126/RTP6 P127/RTP7 RESET P00/INTP0 P01/INTP1 P02/INTP2/NMI P03/INTP3 P04/INTP4 P05/INTP5 P06/INTP6
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
A19: AD7: ANI0 ANI7: ANO0, ANO1: ASCK1, ASCK2: ASTB: AVDD: AVREF0, AVREF1: AVSS: BUZ:
Note
Address Address/data Analog input Analog output Asynchronous serial clock Address strobe Analog power supply Analog reference voltage Analog ground Buzzer clock
P120 P127: P130, P131: PCL: RESET: RTP0 RTP7: RxD1, RxD2: SCK0 SCK2: SCL0Note SDA0Note SI2: SO2: TEST: TI00, TI01, TI1, TI2, TI8: TxD1, TxD2: VDD: VSS: WAIT: XT1, XT2:
Port Port Programmable clock Read strobe Reset Real-time output port Receive data Serial clock Serial clock Serial data Serial input Serial output Test Timer input Transmit data Power supply Ground Wait Write strobe Crystal (main system clock) Crystal (subsystem clock)
External access status output Interrupt from peripherals Non-maskable interrupt Port Port Port Port Port Port Port Port Port Port Port
INTP0 INTP6: NMI: P06: P17: P27: P37: P47: P57: P67: P72: P87: P95: P100 P103:
TO2, TO8: Timer output
Notes SCL0 SDA0 pins available µPD784216AY/784218AY Subseries products only. available µPD784218A, 784218AY Subseries products only.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
BLOCK DIAGRAM
INTP2/NMI INTP0, INTP1, INTP3 INTP6 TI00 TI01 Programmable interrupt controller Timer/event counter bits) Timer/event counter bits) Timer/event counter bits) Timer/event counter bits) Timer/event counter bits) Timer/event counter bits) Timer/event counter bits) Watch timer Port Watchdog timer Port Port RTP0 RTP7 NMI/INTP2 ANO0 ANO1 AVREF1 AVSS ANI0 ANI7 AVREF0 AVDD AVSS P03/INTP3 Real-time output port Port Port converter Port Port Port converter 78K/IV core UART/IOE1 Baud-rate generator UART/IOE2 Baud-rate generator Clocked serial interfaceNote RxD1/SI1 TxD1/SO1 ASCK1/SCK1 RxD2/SI2 TxD2/SO2 ASCK2/SCK2 SI0/SDA0 SCK0/SCL0 TI5/TO5 WAIT ASTB EXANote Port Port Port Port Port P100 P103 P120 P127 P130, P131 RESET Clock output control Buzzer output System control TEST
TI6/TO6
TI7/TO7
TI8/TO8
Notes This function supports interface available µPD784216AY/784218AY Subseries
products only. available µPD784218A, 784218AY Subseries products only. Remark internal capacities differ depending product.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
FUNCTIONS Port Pins (1/2)
Name Input Alternate Function INTP0 INTP1 INTP2/NMI INTP3 INTP4 INTP5 INTP6 ANI0 ANI7 Port (P1): 8-bit input only port Port (P2): 8-bit port Input/output specified 1-bit units. Whether specifying input mode output mode, on-chip pull-up resistor specified 1-bit units means software setting. Function Port (P0): 7-bit port Input/output specified 1-bit units. Whether specifying input mode output mode, on-chip pull-up resistor specified 1-bit units means software setting.
RxD1/SI1 TxD1/SO1 ASCK1/SCK1 SI0/SDA0Note SCK0/SCL0Note
TI00 TI01 EXANote
Port (P3): 8-bit port Input/output specified 1-bit units. Whether specifying input mode output mode, on-chip pull-up resistor specified 1-bit units means software setting.
Port (P4): 8-bit port Input/output specified 1-bit units. pins input mode connected on-chip pull-up resistors means software setting. LEDs driven directly. Port (P5): 8-bit port Input/output specified 1-bit units. pins input mode connected on-chip pull-up resistors means software setting. LEDs driven directly.
Notes This function available µPD784216AY/784218AY Subseries products only. This function available µPD784218A, 784218AY Subseries products only.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Port Pins (2/2)
Name Alternate Function WAIT ASTB RxD2/SI2 TxD2/SO2 ASCK2/SCK2 Port (P7): 3-bit port Input/output specified 1-bit units. Whether specifying input mode output mode, on-chip pull-up resistor specified 1-bit units means software setting. Port (P8): 8-bit port Input/output specified 1-bit units. Whether specifying input mode output mode, on-chip pull-up resistor specified 1-bit units means software setting. interrupt control flag (KRIF) when falling edge detected this port. Port (P9): N-ch open-drain middle-voltage port 6-bit port Input/output specified 1-bit units. LEDs driven directly. Port (P10): 4-bit port Input/output specified 1-bit units. Whether specifying input mode output mode, on-chip pull-up resistor specified 1-bit units means software setting. Port (P12): 8-bit port Input/output specified 1-bit units. Whether specifying input mode output mode, on-chip pull-up resistor specified 1-bit units means software setting. Port (P13): 2-bit port Input/output specified 1-bit units. Function Port (P6): 8-bit port Input/output specified 1-bit units. pins input mode connected on-chip pull-up resistors means software setting.
P100 P101 P102 P103 P120 P127
TI5/TO5 TI6/TO6 TI7/TO7 TI8/TO8
RTP0 RTP7
P130, P131
ANO0, ANO1
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Non-Port Pins (1/2)
Name TI00 TI01 RxD1 RxD2 TxD1 TxD2 ASCK1 ASCK2 SDA0 SCK0 SCK1 SCK2 SCL0 INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 Input Output Input Input Output Input Output Input Alternate Function P100/TO5 P101/TO6 P102/TO7 P103/TO8 P100/TI5 P101/TI6 P102/TI7 P103/TI8 P20/SI1 P70/SI2 P21/SO1 P71/SO2 P22/SCK1 P72/SCK2 P25/SDA0 P20/RxD1 P70/RxD2 P21/TxD1 P71/TxD2 P25/SI0 P27/SCL0Note P22/ASCK1 P72/ASCK2 P27/SCK0 P02/INTP2 P02/NMI
Note
Function External count clock input 16-bit timer counter Capture trigger signal input capture/compare register External count clock input 8-bit timer counter External count clock input 8-bit timer counter External count clock input 8-bit timer counter External count clock input 8-bit timer counter External count clock input 8-bit timer counter External count clock input 8-bit timer counter 16-bit timer output (shared 14-bit output) 8-bit timer output (shared 8-bit output)
Serial data input (UART1) Serial data input (UART2) Serial data output (UART1) Serial data output (UART2) Baud rate clock input (UART1) Baud rate clock input (UART2) Serial data input (3-wire serial Serial data input (3-wire serial Serial data input (3-wire serial Serial data output (3-wire serial Serial data output (3-wire serial Serial data output (3-wire serial Serial data input/output (I2C bus) Serial clock input/output (3-wire serial Serial clock input/output (3-wire serial Serial clock input/output (3-wire serial Serial clock input/output (I2C bus) Non-maskable interrupt request input External interrupt request input
Note This function available µPD784216AY/784218AY Subseries products only.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Non-Port Pins (2/2)
Name RTP0 RTP7 WAIT ASTB EXANote RESET ANI0 ANI7 ANO0, ANO1 AVREF0 AVREF1 AVDD AVSS TEST Input Output Output Input Input Input Input Output P130, P131 converter analog input converter analog output converter reference voltage input converter reference voltage input converter positive power supply. Connect VDD. converter converter. Connect VSS. Positive power supply Connect this directly pull-down resistor. pull-down connection, recommended resistor with resistance ranging from (this test). Connecting crystal resonator subsystem clock oscillation Output Output Output Output Output Alternate Function P120 P127 Function Clock output (for trimming main system clock subsystem clock) Buzzer output Real-time output port that outputs data synchronization with trigger Lower address/data expanding memory externally Lower address expanding memory externally Middle address expanding memory externally Higher address expanding memory externally Strobe signal output reading from external memory Strobe signal output writing external memory Wait insertion external memory access Strobe output that externally latches address information output ports through access external memory Status signal output external memory access System reset input Connecting crystal resonator main system clock oscillation
Note This function available µPD784218A, 784218AY Subseries products only.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Circuits Recommended Connections Unused Pins
circuit type each recommended connections unused pins shown Table 5-1. each type circuit, refer Figure 5-1. Table 5-1. Types Circuits Recommended Connection Unused Pins (1/2)
Name P00/INTP0 P01/INTP1 P02/INTP2/NMI P03/INTP3 P06/INTP6 P10/ANI0 P17/ANI7 P20/RxD1/SI1 P21/TxD1/SO1 P22/ASCK1/SCK1 P23/PCL P24/BUZ P25/SI0/SDA0Note P26/SO0 P27/SCK0/SCL0
Note
Circuit Type
Recommended Connection Unused Pins Input: Independently connect resistor Output: Leave open
10-K 10-L 10-K 10-L
Input
Connect Input: Independently connect resistor Output: Leave open
10-K 10-L 10-K 12-E 10-M 12-E
P30/TO0 P32/TO2 P33/TI1, P34/TI2 P35/TI00, P36/TI01 P37/EXA
Note
P40/AD0 P47/AD7 P50/A8 P57/A15 P60/A16 P63/A19 P64/RD P65/WR P66/WAIT P67/ASTB P70/RxD2/SI2 P71/TxD2/SO2 P72/ASCK2/SCK2 P80/A0 P87/A7 P100/TI5/TO5 P101/TI6/TO6 P102/TI7/TO7 P103/TI8/TO8 P120/RTP0 P127/RTP7 P130/ANO0, P131/ANO1
10-M 12-E 13-D
12-E 12-F
Notes This function available µPD784216AY/784218AY Subseries products only. This function available µPD784218A, 784218AY Subseries products only.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Table 5-1. Types Circuits Recommended Connection Unused Pins (2/2)
Name RESET AVREF0 AVREF1 AVDD AVSS TEST Connect Connect this directly pull-down resistor. pull-down connection, recommended resistor with resistance ranging from Circuit Type Input Connect Leave open Connect Connect Recommended Connection Unused Pins
Remark Because circuit type numbers standardized among Series products, they sequential some models (i.e., some circuits provided).
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Figure 5-1. Circuits (1/2)
Type Type 10-K
Pull-up enable Data P-ch
P-ch
IN/OUT Open drain Output disable Schmitt-triggered input with hysteresis characteristics N-ch
Type
Type 10-L
Pull-up enable Data P-ch
P-ch
Pull-up enable Data IN/OUT P-ch
P-ch
IN/OUT Open drain Output disable N-ch
Output disable
N-ch
Input enable Type Type 10-M
Pull-up enable Data P-ch
P-ch
Pull-up enable Data IN/OUT P-ch
P-ch
IN/OUT Output disable N-ch
Output disable
N-ch
Type
Type 12-E
P-ch N-ch
Comparator
Pull-up enable Data P-ch
P-ch
IN/OUT (Threshold voltage) Output disable Input enable Input enable P-ch Analog output voltage N-ch
N-ch
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Figure 5-1. Circuits (2/2)
Type 12-F Data P-ch IN/OUT Output disable Input enable N-ch P-ch N-ch
Type Feedback cut-off P-ch
Analog output voltage
Type 13-D IN/OUT Data Output disable N-ch
P-ch
Middle-voltage input buffer
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
ARCHITECTURE Memory Space
memory space accessed. Mapping internal data area (special function registers internal RAM) specified LOCATION instruction. LOCATION instruction must always executed after reset cancellation, must used more than once. When LOCATION instruction executed Internal memory internal data area internal area mapped follows.
Part Number Internal Data Area 0F100H 0FFFFH 0EB00H 0FFFFH 0DF00H 0FFFFH 0CD00H 0FFFFH Internal Area 00000H 0F0FFH 10000H 17FFFH 00000H 0EAFFH 10000H 1FFFFH 00000H 0DEFFH 10000H 1FFFFH 00000H 0CCFFH 10000H 2FFFFH 00000H 0CCFFH 10000H 3FFFFH
µPD784214A, µPD784214AY µPD784215A, µPD784215AY µPD784216A, µPD784216AY µPD784217A, µPD784217AY µPD784218A, µPD784218AY
Caution following areas that overlap internal data area internal cannot used when LOCATION instruction executed.
Part Number Unusable Area 0F100H 0FFFFH (3,840 bytes) 0EB00H 0FFFFH (5,376 bytes) 0DF00H 0FFFFH (8,448 bytes) 0CD00H 0FFFFH (13,056 bytes)
µPD784214A, µPD784214AY µPD784215A, µPD784215AY µPD784216A, µPD784216AY µPD784217A, µPD784217AY µPD784218A, µPD784218AY
External memory external memory accessed external memory expansion mode.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
When LOCATION instruction executed Internal memory internal data area internal area mapped follows.
Part Number Internal Data Area FF100H FFFFFH FEB00H FFFFFH FDF00H FFFFFH FCD00H FFFFFH 00000H 2FFFFH 00000H 3FFFFH Internal Area 00000H 17FFFH 00000H 1FFFFH
µPD784214A, µPD784214AY µPD784215A, µPD784215AY µPD784216A, µPD784216AY µPD784217A, µPD784217AY µPD784218A, µPD784218AY
External memory external memory accessed external memory expansion mode.
Data Sheet U14121EJ4V0DS
execution LOCATION instruction
Figure 6-1. Memory µPD784214A, 784214AY
execution LOCATION instruction
Special FDFH Note FD0H
function registers (SFR) (256 bytes)
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
External memory (928
Note
General-purpose registers (128 bytes)
FFE8
Internal (3,584 bytes)
Internal
(32,768 bytes) Special function registers FDFH Note FD0H (256 bytes) Internal (3,584 bytes)
(SFR)
Macro service control word area bytes) Data area (512 bytes)
FFE0
Data Sheet U14121EJ4V0DS
Program/data area (3,072 bytes)
External memory (980,736 bytes)
Note
Note
Note
Program/data area CALLF entry area
Note
Internal (61,696 bytes)
CALLT table area bytes) Vector table area bytes)
Internal
Note
Notes Accessed external memory expansion mode. This 3,840-byte area used internal only when LOCATION instruction executed. execution LOCATION instruction: 94,464 bytes, execution LOCATION instruction: 98,304 bytes Base area entry area reset interrupt. However, internal area used reset entry area.
Figure 6-2. Memory µPD784215A, 784215AY
execution LOCATION instruction
execution LOCATION instruction
Special FDFH Note FD0H
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
function registers (SFR) (256 bytes)
External memory (896
Note
General-purpose registers (128 bytes)
FFE8 FEAF
Internal (5,120 bytes)
Special FDFH Note FD0H
Internal (65,536 bytes)
function registers (SFR) (256 bytes)
Macro service control word area bytes) Data area (512 bytes)
FFE0
Data Sheet U14121EJ4V0DS
Internal (5,120 bytes)
Program/data area (4,608 bytes)
External memory (912,128 bytes)
Note
Note
Note
Program/data area
Note
Internal (60,160 bytes)
CALLF entry area
CALLT table area bytes) Vector table area bytes)
Internal (128
Note
Notes Accessed external memory expansion mode. This 5,376-byte area used internal only when LOCATION instruction executed. execution LOCATION instruction: 125,696 bytes, execution LOCATION instruction: 131,072 bytes Base area entry area reset interrupt. However, internal area used reset entry area.
execution LOCATION instruction
Figure 6-3. Memory µPD784216A, 784216AY
execution LOCATION instruction
Special FDFH Note FD0H
function registers (SFR) (256 bytes)
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
External memory (896
Note
General-purpose registers (128 bytes)
FFE8
Internal (8,192 bytes)
Special FDFH Note FD0H
Internal (65,536 bytes)
function registers (SFR) (256 bytes)
Macro service control word area bytes) Data area (512 bytes)
FFE0
Data Sheet U14121EJ4V0DS
Internal (8,192 bytes)
Program/data area (7,680 bytes)
External memory (909,056 bytes)
Note
Note
Note
Program/data area
Note
Internal (57,088 bytes)
CALLF entry area
CALLT table area bytes) Vector table area bytes)
Internal (128
Note
Notes Accessed external memory expansion mode. This 8,448-byte area used internal only when LOCATION instruction executed. execution LOCATION instruction: 122,624 bytes, execution LOCATION instruction: 131,072 bytes Base area entry area reset interrupt. However, internal area used reset entry area.
Figure Memory µPD784217A, 784217AY
execution LOCATION instruction
execution LOCATION instruction
Special FDFH Note FD0H
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
function registers (SFR) (256 bytes)
External memory (928
Note
General-purpose registers (128 bytes)
FFE8
Internal (12,800 bytes)
Internal
(32,768 bytes) Special function registers FDFH Note FD0H (256 bytes) Internal (12,800 bytes)
(SFR)
Macro service control word area bytes) Data area (512 bytes)
FFE0
Data Sheet U14121EJ4V0DS
Program/data area (12,288 bytes)
External memory (838,912 bytes)
Note
Note
Note
Program/data area CALLF entry area
Note
Internal (52,480 bytes)
CALLT table area bytes) Vector table area bytes)
Internal (192
Note
Notes Accessed external memory expansion mode. This 13,056-byte area used internal only when LOCATION instruction executed. execution LOCATION instruction: 183,552 bytes, execution LOCATION instruction: 196,608 bytes Base area entry area reset interrupt. However, internal area used reset entry area.
Figure 6-5. Memory µPD784218A, 784218AY
execution LOCATION instruction
execution LOCATION instruction
Special FDFH Note FD0H
function registers (SFR)
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
(256 bytes)
External memory (768
Note
General-purpose registers (128 bytes)
FFE8
Internal (12,800 bytes)
Special FDFH Note FD0H
Internal (196,608 bytes)
function registers (SFR) (256 bytes)
Macro service control word area bytes) Data area (512 bytes)
FFE0
Data Sheet U14121EJ4V0DS
Internal (12,800 bytes)
Program/data area (12,288 bytes)
External memory (773,376 bytes)
Note
Note
Note
Program/data area
Note
Internal (52,480 bytes)
CALLF entry area
CALLT table area bytes) Vector table area bytes)
Internal (256
Note
Notes Accessed external memory expansion mode. This 13,056-byte area used internal only when LOCATION instruction executed. execution LOCATION instruction: 249,088 bytes, execution LOCATION instruction: 262,144 bytes Base area entry area reset interrupt. However, internal area used reset entry area.
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Registers
6.2.1 General-purpose registers Sixteen 8-bit general-purpose registers available. 8-bit registers also used pairs 16-bit register. 16-bit registers, four used combination with 8-bit register address expansion 24bit address specification registers. Eight banks these register sets available selected using software context switching function. general-purpose registers except registers address expansion mapped internal RAM. Figure 6-6. General-Purpose Register Format
(R1) (RP0) (R3) (RP1) (RG4) (RP4)
(R0) (R2)
(RP5) (RG5) (R13) (R12) (RP6) (RG6) (R15) (R14) banks (RG7) (RP7)
Names parentheses indicate absolute names.
Caution Registers RP2, used registers, respectively, setting recycling program 78K/III Series. However, this function only
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
6.2.2 Control registers Program counter (PC) program counter 20-bit register whose contents automatically updated when program executed. Figure 6-7. Format Program Counter (PC)
Program status word (PSW) This register holds statuses CPU. contents automatically updated when program executed. Figure 6-8. Format Program Status Word (PSW)
PSWH PSWL
RBS2
RBS1
RBS0
Note
Note This flag provided maintain compatibility with 78K/III Series. sure clear this flag except when software 78K/III Series used. Stack pointer (SP) This 24-bit pointer that holds first address stack. sure write higher bits this pointer. Figure 6-9. Format Stack Pointer (SP)
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
6.2.3 Special function registers (SFRs) special function registers, such mode registers control registers internal peripheral hardware, registers which special functions assigned. These registers mapped 256-byte space addresses 0FF00H 0FFFFHNote. Note execution LOCATION instruction. FFF00H FFFFFH execution LOCATION instruction. Caution access address this area which assigned. such address accessed mistake, µPD784218A enter deadlocked state. This deadlock state cleared only inputting RESET signal. Table lists special function registers (SFRs). meanings symbols this table follows. Symbol.Symbol indicating SFR. compiler (CC78K4). R/W.Indicates whether read-only, write-only, read/write. R/W: Read/write Read-only Write-only This symbol reserved NEC's assembler
(RA78K4). used variable means #pragma command
units manipulation .Bit units which value manipulated. SFRs that manipulated 16-bit units described operand sfrp instruction. specify address this SFR, describe even address. SFRs that manipulated 1-bit units described operand manipulation instruction. After reset .Indicates status register when RESET signal been input.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Table 6-1. Special Function Register (SFR) List (1/4)
AddressNote Special Function Register (SFR) Name Symbol Units Manipulation 0FF00H 0FF01H 0FF02H 0FF03H 0FF04H 0FF05H 0FF06H 0FF07H 0FF08H 0FF09H 0FF0AH 0FF0CH 0FF0DH 0FF10H 0FF11H 0FF12H 0FF13H 0FF14H 0FF15H 0FF16H 0FF18H 0FF1AH 0FF1CH 0FF20H 0FF22H 0FF23H 0FF24H 0FF25H 0FF26H 0FF27H 0FF28H 0FF29H 0FF2AH 0FF2CH 0FF2DH 0FF30H 0FF32H 0FF33H 0FF37H Capture/compare register (16-bit timer/event counter) Capture/compare register (16-bit timer/event counter) Capture/compare control register 16-bit timer mode control register 16-bit timer output control register Prescaler mode register Port mode register Port mode register Port mode register Port mode register Port mode register Port mode register Port mode register Port mode register Port mode register Port mode register Port mode register Port mode register Pull-up resistor option register Pull-up resistor option register Pull-up resistor option register Pull-up resistor option register CR00 Port Port Port Port Port Port Port Port Port Port Port Port Port 16-bit timer counter Bits Bits 0000H 00HNote After Reset
CR01
CRC0 TMC0 TOC0 PRM0 PM10 PM12 PM13
Notes When LOCATION instruction executed. "F0000H" this value when LOCATION instruction executed. Because each port initialized input mode after reset, "00H" actually read. output latch initialized "0".
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Table 6-1. Special Function Register (SFR) List (2/4)
AddressNote Special Function Register (SFR) Name Symbol Units Manipulation 0FF38H 0FF3AH 0FF3CH 0FF40H 0FF42H 0FF4EH 0FF50H 0FF51H 0FF52H 0FF53H 0FF54H 0FF55H 0FF56H 0FF57H 0FF60H 0FF61H 0FF62H 0FF63H 0FF64H 0FF65H 0FF66H 0FF67H 0FF68H 0FF69H 0FF6AH 0FF6BH 0FF6CH 0FF6DH 0FF6EH 0FF6FH 0FF70H 0FF71H 0FF72H 0FF73H 0FF74H Pull-up resistor option register Pull-up resistor option register Pull-up resistor option register Clock output control register Port function control register Pull-up resistor option register 8-bit timer counter 8-bit timer counter PU10 PU12 TM1W TM5W TM7W Bits Bits 0000H After Reset
Compare register (8-bit timer/event counter CR10 CR1W Compare register (8-bit timer/event counter CR20 8-bit timer mode control register 8-bit timer mode control register Prescaler mode register Prescaler mode register 8-bit timer counter 8-bit timer counter 8-bit timer counter 8-bit timer counter TMC1 TMC1W TMC2 PRM1 PRM1W PRM2
Compare register (8-bit timer/event counter CR50 CR5W Compare register (8-bit timer/event counter CR60 Compare register (8-bit timer/event counter CR70 CR7W Compare register (8-bit timer/event counter CR80 8-bit timer mode control register 8-bit timer mode control register 8-bit timer mode control register 8-bit timer mode control register Prescaler mode register Prescaler mode register Prescaler mode register Prescaler mode register Asynchronous serial interface mode register Asynchronous serial interface mode register Asynchronous serial interface status register Asynchronous serial interface status register Transmit shift register Receive buffer register TMC5 TMC5W TMC6 TMC7 TMC7W TMC8 PRM5 PRM5W PRM6 PRM7 PRM7W PRM8 ASIM1 ASIM2 ASIS1 ASIS2 TXS1 RXB1 TXS2 RXB2 BRGC1 BRGC2
0FF75H
Transmit shift register Receive buffer register
0FF76H 0FF77H
Baud rate generator control register Baud rate generator control register
Note When LOCATION instruction executed. "F0000H" this value when LOCATION instruction executed.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Table 6-1. Special Function Register (SFR) List (3/4)
AddressNote Special Function Register (SFR) Name Symbol Units Manipulation 0FF7AH 0FF80H 0FF81H 0FF83H 0FF84H 0FF85H 0FF86H 0FF87H 0FF88H 0FF89H 0FF8AH 0FF8BH 0FF8CH 0FF8DH 0FF90H 0FF91H 0FF92H 0FF94H 0FF95H 0FF96H 0FF98H 0FF99H 0FF9AH 0FF9BH 0FF9CH 0FFA0H 0FFA2H 0FFA8H 0FFA9H 0FFAAH 0FFACH 0FFADH 0FFAEH 0FFAFH 0FFB0H 0FFB2H 0FFB4H External type selection register External access status enable registerNote Serial operation mode register Serial operation mode register Serial operation mode register Serial shift register Serial shift register Serial shift register Real-time output buffer register Real-time output buffer register Real-time output port mode register Real-time output port control register Watch timer mode control register External interrupt rising edge enable register External interrupt falling edge enable register In-service priority register Interrupt select control register Interrupt mode control register Interrupt mask flag register Interrupt mask flag register Interrupt mask flag register Interrupt mask flag register control registerNote Prescaler mode register serial clock Slave address register EBTS EXAE CSIM0 CSIM1 CSIM2 SIO0 SIO1 SIO2 RTBL RTBH RTPM RTPC WEGP0 EGN0 ISPR SNMI MK0L MK0H MK1L MK1H IICC0 SPRM0 SVA0 FFFFH Oscillation mode selection register converter mode register converter input selection register conversion result register conversion value setting register conversion value setting register converter mode register converter mode register correction control registerNote correction address pointer HNote correction address pointer LNote ADIS ADCR DACS0 DACS1 DAM0 DAM1 CORC CORAH CORAL Bits Bits 0000H Undefined After Reset
Notes When LOCATION instruction executed. "F0000H" this value when LOCATION instruction executed. This register available µPD784218A, 784218AY Subseries products only. This register available µPD784216AY/784218AY Subseries products only.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Table 6-1. Special Function Register (SFR) List (4/4)
AddressNote Special Function Register (SFR) Name status registerNote Serial shift register Standby control register Watchdog timer mode register Memory expansion mode register Programmable wait control register Programmable wait control register Clock status register Oscillation stabilization time specification register External area Interrupt control register (INTWDTM) Interrupt control register (INTP0) Interrupt control register (INTP1) Interrupt control register (INTP2) Interrupt control register (INTP3) Interrupt control register (INTP4) Interrupt control register (INTP5) Interrupt control register (INTP6) Interrupt control register (INTIIC0/INTCSI0) Interrupt control register (INTSER1) Interrupt control register (INTSR1/INTCSI1) Interrupt control register (INTST1) Interrupt control register (INTSER2) Interrupt control register (INTSR2/INTCSI2) Interrupt control register (INTST2) Interrupt control register (INTTM3) Interrupt control register (INTTM00) Interrupt control register (INTTM01) Interrupt control register (INTTM1) Interrupt control register (INTTM2) Interrupt control register (INTAD) Interrupt control register (INTTM5) Interrupt control register (INTTM6) Interrupt control register (INTTM7) Interrupt control register (INTTM8) Interrupt control register (INTWT) Interrupt control register (INTKR) Symbol Units Manipulation 0FFB6H 0FFB8H 0FFC0H 0FFC2H 0FFC4H 0FFC7H 0FFC8H 0FFCEH 0FFCFH 0FFD0H 0FFDFH 0FFE0H 0FFE1H 0FFE2H 0FFE3H 0FFE4H 0FFE5H 0FFE6H 0FFE7H 0FFE8H 0FFE9H 0FFEAH 0FFEBH 0FFECH 0FFEDH 0FFEEH 0FFEFH 0FFF0H 0FFF1H 0FFF2H 0FFF3H 0FFF4H 0FFF5H 0FFF6H 0FFF7H 0FFF8H 0FFF9H 0FFFAH IICS0 IIC0 STBC PWC1 PWC2 OSTS WDTIC PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 CSIIC0 SERIC1 SRIC1 STIC1 SERIC2 SRIC2 STIC2 TMIC3 TMIC00 TMIC01 TMIC1 TMIC2 ADIC TMIC5 TMIC6 TMIC7 TMIC8 WTIC KRIC Bits Bits AAAAH After Reset
Notes When LOCATION instruction executed. "F0000H" this value when LOCATION instruction executed. This register available µPD784216AY/784218AY Subseries products only.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
PERIPHERAL HARDWARE FUNCTIONS Ports
ports shown Figure provided make various control operations possible. Table shows function each port. Ports through connected on-chip pull-up resistors means software when input mode. Figure 7-1. Port Configuration
Port
Pprt
Port
Port
Port
P100 P103 P120
Port
Port Port Port Port Port
Port
P127 P130 P131
Port
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Table 7-1. Port Functions
Port Name Name Function Input/output specified 1-bit units Input port Input/output specified 1-bit units Input/output specified 1-bit units Input/output specified 1-bit units LEDs driven directly Input/output specified 1-bit units LEDs driven directly Input/output specified 1-bit units Input/output specified 1-bit units Input/output specified 1-bit units N-ch open-drain port Input/output specified 1-bit units LEDs driven directly Input/output specified 1-bit units Input/output specified 1-bit units Input/output specified 1-bit units Specification Pull-up Resistor Connection Software specified 1-bit units specified 1-bit units specified 1-bit units specified 1-port units
Port Port Port Port Port
Port
specified 1-port units
Port Port Port Port
specified 1-port units specified 1-bit units specified 1-bit units
Port Port Port
P100 P103 P120 P127 P130, P131
specified 1-bit units specified 1-bit units
Clock Generator
on-chip clock generator necessary operation provided. This clock generator frequency divider. high-speed operation necessary, internal operating frequency lowered frequency divider reduce current consumption. Figure 7-2. Block Diagram Clock Generator
Subsystem clock oscillator Prescaler Main system clock oscillator
IDLE controller
Watch timer, clock output function
Frequency divider
Selector
Prescaler
Clock peripheral hardware
STOP (MCK) standby control register (STBC) when subclock selected clock
Selector
STOP, IDLE
controller
HALT controller
clock (fCPU) Internal system clock (fCLK)
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Figure 7-3. Example Using Main System Clock Oscillator
Crystal/ceramic oscillation
External clock
Crystal resonator ceramic resonator
External clock PD74HCU04
Figure 7-4. Example Using Subsystem Clock Oscillator
Crystal oscillation
External clock
32.768
External clock
µPD74HCU04
Caution
When using main system clock subsystem clock oscillator, wire follows area enclosed broken lines Figures avoid adverse effect from wiring capacitance. Keep wiring length short possible. cross wiring with other signal lines. route wiring near signal line through which high fluctuating current flows. Always make ground point oscillator capacitor same potential VSS. ground capacitor ground pattern through which high current flows. fetch signals from oscillator. Note that subsystem clock oscillator amplification factor reduce current consumption.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Real-Time Output Port
real-time output function transfer data advance real-time output buffer register output latch soon timer interrupt external interrupt occurred order output data external device. pins that output data external device constitute port called real-time output port. Because real-time output port output signals without jitter, ideal controlling stepper motor. Figure 7-5. Block Diagram Real-Time Output Port
Internal Real-time output port control register (RTPC) RTPOE BYTE EXTR
INTP2TRG INTTM1 INTTM2 Output trigger controller
Higher bits real-time output buffer register (RTBH)
Lower bits real-time output buffer register (RTBL) Real-time output port mode register (RTPM)
Port output latch
Real-time output port output latch
P120
RTP0
RTPOE
P12n/RTPn output
P120/ RTP7 RTP0
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Timer/Event Counter
unit 16-bit timer/event counter 8-bit timer/event counters provided. Because total eight interrupt requests supported, these timer/event counters used eight timer/counters. Table 7-2. Operations Timers
Name 8-Bit 8-Bit 8-Bit 8-Bit 8-Bit 8-Bit 16-Bit Timer/ Timer/ Timer/ Timer/ Timer/ Timer/ Timer/ Event Event Event Event Event Event Event Counter Counter Counter Counter Counter Counter Counter inputs
Item Count width bits bits Operation mode Interval timer External event counter Function Timer output output output Square wave output One-shot pulse output Pulse width measurement Number interrupt requests
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Figure 7-6. Block Diagram Timer/Event Counters 16-bit timer/event counter
fXX/4 fXX/16 INTTM3 Clear
Selector
16-bit timer counter (TM0)
Selector
TI01
Edge detector
INTTM00
INTTM01 TI00 Edge detector 16-bit capture/compare register (CR01)
Output controller
16-bit capture/compare register (CR00)
8-bit timer/event counter
fXX/22 fXX/23 Clear
Selector
fXX/24 fXX/25 fXX/27 fXX/29 Edge detector
8-bit timer counter (TMn)
Output controller
8-bit compare register (CRn0) INTTMn
Selector
INTTMn
Remarks OVF: Overflow flag 8-bit timer/event counter
fXX/22 fXX/23 fXX/24 fXX/2 fXX/2
Clear
Selector
8-bit timer counter (TMn)
Output controller
fXX/29 Edge detector 8-bit compare register (CRn0) INTTMn
Remarks OVF: Overflow flag
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Converter
converter converts analog signal input into digital signal. This microcontroller provided with converter with resolution bits eight channels (ANI0 ANI7). This converter successive approximation type result conversion stored 8-bit conversion result register (ADCR). converter started following ways: Hardware start Conversion started trigger input (P03). Software start Conversion started setting converter mode register (ADM). analog input channel selected from ANI0 ANI7 conversion. When conversion started means hardware start, conversion stopped after been completed. When conversion started means software start, conversion repeatedly executed. Each time conversion been completed, interrupt request (INTAD) generated. Figure 7-7. Block Diagram Converter
Series resistor string ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 AVSS Successive approximation register (SAR)
Selector
AVDD AVREF0 Sample hold circuit Voltage comparator
selector
INTP3/P03
Edge detector
Controller
INTAD
Edge detector
conversion result register (ADCR) INTP3 Internal
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Converter
converter converts digital signal input into analog signal. This microcontroller provided with voltage output type converter with resolution bits channels. conversion method R-2R resistor ladder type. conversion started setting DACE0 converter mode register (DAM0) DACE1 converter mode register (DAM1). converter operates following modes: Normal mode converter outputs analog voltage immediately after completed conversion. Real-time output mode converter outputs analog voltage synchronization with output trigger after completed conversion. Figure 7-8. Block Diagram Converter
DACS0 ANO0 AVREF1
Selector DACS1 ANO1
Selector AVSS
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Serial Interface
Three independent serial interface channels provided. Asynchronous serial interface (UART)/3-wire serial (IOE) Clocked serial interface (CSI) 3-wire serial (IOE) interface (I2C) (µPD784216AY/784218AY Subseries only) Therefore, communication with external system local communication within system simultaneously executed (refer Figure 7-9). Figure 7-9. Example Serial Interface UART
µPD784218AY (master) PD4711A
[UART] RS-232-C driver/receiver RxD1 TxD1
Port
µPD780078Y (slave)
SDA0 SCL0
[I2C]
µPD780308Y (slave)
PD4711A
[UART] RxD2 RS-232-C driver/receiver TxD2
Port
UART 3-wire serial
µPD784218AY (master)
PD4711A
[UART] RxD2 RS-232-C driver/receiver TxD2
PD753106 (slave)
[3-wire serial I/O] Note Port
SCK1 INTPm Port
Port
Note Handshake line
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
7.7.1 Asynchronous serial interface/3-wire serial (UART/IOE) channels serial interfaces which asynchronous serial interface mode 3-wire serial mode selected provided. Asynchronous serial interface mode this mode, data byte following start transmitted received. Because on-chip baud rate generator provided, wide range baud rates set. Moreover, clock input ASCK divided define baud rate. When baud rate generator used, baud rate conforming MIDI standard (31.25 Kbps) also obtained. Figure 7-10. Block Diagram Asynchronous Serial Interface Mode
Internal Receive buffer register (RXB1, RXB2) RxD1, RxD2 TxD1, TxD2 Receive control parity check Baud rate generator 5-bit counter transmit/ receive clock generation ASCK1, ASCK2 INTSR1, INTSR2 Transmit control parity addition INTST1, INTST2 Receive shift register (RX1, RX2) Transmit shift register (TXS1, TXS2)
Selector
fXX/25
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
3-wire serial mode this mode, master device starts transfer making serial clock active transfers 1-byte data synchronization with this clock. This mode used communicate with device having conventional clocked serial interface. Basically, communication established using three lines: serial clocks (SCK1 SCK2), serial data inputs (SI1 SI2), serial data outputs (SO1 SO2). necessary. Figure 7-11. Block Diagram 3-Wire Serial Mode connect more devices, handshake line
Internal
SI1,
Serial shift register (SIO1, SIO2)
SO1, SCK1, SCK2 Serial clock counter Serial clock controller Interrupt generator INTCSI1, INTCSI2 fXX/8 fXX/16
Selector
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
7.7.2 Clocked serial interface (CSI) this mode, master device starts transfer making serial clock active transfers 1-byte data synchronization with this clock. 3-wire serial mode This mode communicate with devices having conventional clocked serial interface. Basically, communication established this mode with three lines: serial clock (SCK0) serial data input (SI0), serial data output (SO0) lines. Generally, handshake line necessary check reception status. Figure 7-12. Block Diagram 3-Wire Serial Mode
Internal
Serial shift register (SIO0)
SCK0 Serial clock counter Serial clock controller Interrupt generator INTCSI0
Selector
fXX/8 fXX/16
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
(Inter mode (supporting multimaster) (µPD784216AY/784218AY Subseries only) This mode communication with devices conforming format. This mode transferring 8-bit data between more devices using lines: serial clock (SCL0) serial data (SDA0) lines. During transmission, "start condition", "data", "stop condition" output onto serial data bus. During reception, these data automatically detected hardware. Figure 7-13. Block Diagram Mode
Internal Direction controller SDA0 Serial shift register (SIO0) Output latch Slave address register (SVA0) Wake-up controller
Acknowledge generator Start condition/acknowledge detector Stop condition detector SCL0 Serial clock counter Serial clock controller TO2/18 TO2/68 fXX/24 fXX/178
Interrupt generator
INTIIC0
Selector
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Clock Output Function
Clocks following frequencies output clock output. 97.7 kHz/195 kHz/391 kHz/781 kHz/1.56 MHz/3.13 MHz/6.25 MHz/12.5 (@12.5 operation with main system clock) 32.768 (@32.768 operation with subsystem clock) Figure 7-14. Block Diagram Clock Output Function
fXX/2
fXX/24 fXX/25 fXX/2
Selector
fXX/22 fXX/23
Synchronization circuit
Output controller
fXX/27
Buzzer Output Function
Clocks following frequencies output buzzer output. kHz/3.1 kHz/6.1 kHz/12.2 (@12.5 operation with main system clock) Figure 7-15. Block Diagram Buzzer Output Function
Selector
fXX/210 fXX/211 fXX/212 fXX/213
Output controller
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
7.10 Edge Detection Function
interrupt input pins (INTP0, INTP1, NMI/INTP2, INTP3 INTP6) used only input interrupt requests also input trigger signals internal hardware units. Because these pins operate edge input signal, they have function detect edge. Moreover, noise elimination function also provided prevent erroneous detection noise.
Name INTP0 INTP6 Detectable Edge Either both rising falling edges Noise Elimination analog delay
7.11 Watch Timer
watch timer following functions: Watch timer Interval timer watch timer interval timer functions used same time. Watch timer watch timer sets WTIF flag interrupt control register (WTIC) time intervals seconds using 32.768 subsystem clock. Interval timer interval timer generates interrupt request (INTTM3) predetermined time intervals. Figure 7-16. Block Diagram Watch Timer
Selector
Prescaler
Selector
fXX/27
Selector
5-bit counter
INTWT
Selector
INTTM3 16-bit timer/counter
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
7.12 Watchdog Timer
watchdog timer provided detect runaway. This watchdog timer generates non-maskable maskable interrupt unless cleared software within specified interval time. Once enabled operate, watchdog timer cannot stopped software. Whether interrupt watchdog timer interrupt input from takes precedence specified. Figure 7-17. Block Diagram Watchdog Timer
fCLK
Timer
fCLK/221 fCLK/220 RUNNote HALT IDLE STOP
Selector
fCLK/219 fCLK/217
INTWDT
Note Write (RUN) watchdog timer (WDM) Remark fCLK: Internal system clock (fXX fXX/8)
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
INTERRUPT FUNCTIONS
three types interrupt request servicing shown Table selected program. Table 8-1. Servicing Interrupt Request
Servicing Mode Vectored interrupt Context switching Entity Servicing Software Servicing Branches executes servicing routine (servicing arbitrary) Automatically switches register bank, branches executes servicing routine (servicing arbitrary) Firmware Executes data transfer between memory (servicing fixed) Contents Saves restores from stack Saves restores from fixed area register bank Retained
Macro service
Interrupt Sources
Table shows interrupt sources available. shown, interrupts generated types sources, execution instruction, BRKCS instruction, operand error. priority interrupt servicing four levels, that nesting controlled during interrupt servicing that which more interrupts that simultaneously occur should serviced first determined. When macro service function used, however, nesting always proceeds. default priority priority (fixed) service that performed more interrupt requests, having same priority, simultaneously generated (refer Table 8-2). Table 8-2. Interrupt Sources (1/2)
Type Default Priority Source Name instruction BRKCS instruction Operand error Trigger Instruction execution Instruction execution result exclusive between operands byte byte when "MOV STBC, #byte" instruction, "MOV WDM, #byte" instruction, LOCATION instruction executed input edge detection Overflow watchdog timer Overflow watchdog timer input edge detection External Internal Internal External Internal/ External Macro Service
Software
Non-maskable
(highest)
INTWDT
Maskable
INTWDINTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTIIC0 INTCSI0
transfer CSI0 3-wire transfer CSI0 Occurrence UART reception error ASI1
Internal
INTSER1
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Table 8-2. Interrupt Sources (2/2)
Type Default Priority Source Name INTSR1 INTCSI1 INTST1 INTSER2 INTSR2 INTCSI2 (lowest) INTST2 INTTM3 INTTM00 INTTM01 INTTM1 INTTM2 INTAD INTTM5 INTTM6 INTTM7 INTTM8 INTWT INTKR Trigger UART reception ASI1 3-wire transfer CSI1 UART transmission ASI1 Occurrence UART reception error ASI2 UART reception ASI2 3-wire transfer CSI2 UART transmission ASI2 Reference time interval signal from watch timer Signal indicating match between 16-bit timer counter capture/compare register (CR00) Signal indicating match between 16-bit timer counter capture/compare register (CR01) Occurrence match signal 8-bit timer/event counter Occurrence match signal 8-bit timer/event counter conversion converter Occurrence match signal 8-bit timer/event counter Occurrence match signal 8-bit timer/event counter Occurrence match signal 8-bit timer/event counter Occurrence match signal 8-bit timer/event counter Overflow watch timer Detection falling edge port External Internal/ External Internal Macro Service
Maskable
Remarks ASI: Asynchronous Serial Interface CSI: Clocked Serial Interface There interrupt sources watchdog timer: non-maskable interrupts (INTWDT) maskable interrupts (INTWDTM). Either (but both) should selected actual use.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Vectored Interrupt
Execution branches servicing routine using memory contents vector table address corresponding interrupt source address branch destination. that performs interrupt servicing, following operations performed: branching: Saves status (contents PSW) stack returning: Restores status (contents PSW) from stack
return main routine from interrupt service routine, RETI instruction used. branch destination address range FFFFH. Table 8-3. Vector Table Address
Interrupt Source instruction TRAP0 (operand error) INTWDT (non-maskable) INTWD(maskable) INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTIIC0 INTCSI0 INTSER1 INTSR1 INTCSI1 0018H 001AH Vector Table Address 003EH 003CH 0002H 0004H 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H Interrupt Source INTST1 INTSER2 INSR2 INTCSI2 INTST2 INTTM3 INTTM00 INTTM01 INTTM1 INTTM2 INTAD INTTM5 INTTM6 INTTM7 INTTM8 INTWT INTKR 0022H 0024H 0026H 0028H 002AH 002CH 002EH 0030H 0032H 0034H 0036H 0038H 003AH Vector Table Address 001CH 001EH 0020H
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Context Switching
When interrupt request generated when BRKCS instruction executed, predetermined register bank selected hardware. Context switching function that branches execution vector address stored advance register bank, while same time stacking current contents program counter (PC) program status word (PSW) register bank. branch address range FFFFH. Figure 8-1. Context Switching Operation When Interrupt Request Generated
0000B Transfer Register bank PC19-16 PC15-0 Save (Bits temporary register) Exchange Save Temporary register Save
Register bank
Switching register bank (RBS0 RBS2
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Macro Service
This function transfer data between memory special function register (SFR) without intervention CPU. macro service controller accesses memory same transfer cycle directly transfers data without loading Because this function does save restore status CPU, load data, data transferred high speeds. Figure 8-2. Macro Service
Read Memory Write Macro service controller
Write Read
Internal
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Application Example Macro Service
Serial interface transmission
Transmit data storage buffer (memory) Data Data
Data Data
Internal
TxD1, TxD2
Transmit shift register TXS1, TXS2 (SFR)
Transmit control
INTST1, INTST2
Each time macro service requests INTST1 INTST2 generated, next transmit data transferred from memory TXS1 TXS2. When data (last byte) been transferred TXS1 TXS2 (when transmit data storage buffer become empty), vectored interrupt requests INTST1 INTST2 generated. Serial interface reception
Receive data storage buffer (memory) Data Data
Data Data
Internal
Receive buffer register RXB1, RXB2 (SFR)
RxD1, RxD2
Receive shift register
Receive control
INTSR1, INTSR2
Each time macro service requests INTSR1 INTSR2 generated, receive data transferred from RXB1 RXB2 memory. When data (last byte) been transferred memory (when receive data storage buffer become full), vectored interrupt requests INTSR1 INTSR2 generated.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
LOCAL INTERFACE
local interface connect external memory (memory mapped I/O) support memory space (refer Figure 9-1). Figure 9-1. Example Local Interface Multiplexed mode
PD784218A
SRAM Data I/O1 I/O8 Address Address latch
ASTB
Separate mode
PD784218A
SRAM
Address
I/O1 I/O8
Data
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Memory Expansion
External program memory data memory connected stages: connect external memory, ports through port used. external memory connected following modes: Multiplexed mode: external memory connected using time-division address/data bus. number ports used when external memory connected reduced this mode. Separate mode: external memory connected using address data independent each other. Because external latch circuit necessary, this mode useful reducing number components mounting area printed wiring board.
Programmable Wait
Wait state(s) inserted memory space (00000H FFFFFH) while signals active. addition, there address wait function that extends active period ASTB signal gain address decode time.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
STANDBY FUNCTION
This function reduce power consumption chip, used following modes: HALT mode: Stops supply operating clock CPU. This mode used combination with normal operation mode intermittent operation reduce average power consumption. IDLE mode: Stops entire system except oscillator, which continues operating. power consumption this mode close that STOP mode. However, time required restore normal program operation from this mode almost same that from HALT mode. STOP mode: Stops main system clock thereby stops internal operations chip. power consumption mode: Consequently, power consumption minimized with only leakage current flowing. main system clock stopped subsystem clock used system clock. operate subsystem clock reduce current consumption. power consumption HALT mode: This standby function power consumption mode stops operation clock CPU, reduce power consumption entire system. power consumption IDLE mode: This standby function power consumption mode stops entire system except oscillator, reduce power consumption entire system. These modes programmable. macro service started from HALT mode power consumption HALT mode. After macro service processing executed, system returns HALT mode again. transition standby status shown Figure 10-1.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Figure 10-1. Standby Function State Transitions
Macro service
sing rvic
power consumption power consumption HALT mode power IDLE mode power power consumption consumption NMI, INTP0 INTP6 input, mode consumption Note IDLE mode Note (Subsystem HALT mode INTWT, return interrupt Interrupt request clock operation) (Standby) (Standby) Interrupt request masked interrupt
ptio Retu norm pera
Interrupt request masked interrupt
Normal operation (Main system clock operation)
Macro service request One-time processing ends Macro service ends
Macro service
RESET inpu
STOP (Standby)
Interrupt request masked interrupt
IDLE (Standby)
Interrupt request masked interrupt
Interrupt request masked interrupt
HALT (Standby)
RESET input
Wait stable oscillation
Notes Only unmasked interrupt requests Only unmasked INTP0 INTP6, INTWT, return interrupt (P80 P87) Remark valid only external input. watchdog timer cannot used release standby (HALT mode/STOP mode/IDLE mode).
serv
Data Sheet U14121EJ4V0DS
RESET input
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
RESET FUNCTION
When low-level signal input RESET pin, system reset, each hardware unit initialized (reset). During reset period, oscillation main system clock unconditionally stopped. Consequently, current consumption entire system reduced. When RESET signal goes high, reset status cleared. after oscillation stabilization time (84.0 12.5 operation) elapses, contents reset vector table program counter (PC), execution branches address program execution started from that branch address. Therefore, program reset started from address. Figure 11-1. Oscillation Main System Clock During Reset Period
Main system clock oscillator Oscillation unconditionally stopped during reset period fCLK
RESET input Oscillation stabilization time
RESET input analog delay noise eliminator prevent malfunctioning noise. Figure 11-2. Acknowledgement Reset Signal
Time until clock starts oscillating Analog delay Oscillation stabilization time
Analog delay
Analog delay
RESET input
Internal reset signal
Internal clock
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
INSTRUCTION
8-bit instructions (instructions parentheses combinations realized describing MOV, XCH, ADD, ADDC, SUB, SUBC, AND, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC Table 12-1. Instruction List 8-Bit Addressing
Second Operand #byte First Operand (MOV)
Note
saddr saddr'
!addr16 !!addr24
[saddrp] [%saddrg]
PSWL PSWH
[WHL+] [WHL-]
None
Note
(MOV) (XCH) (ADD)
Note
(ADD)
Note Note
(MOV) (XCH) (ADD)
Note
(XCH) (ADD)
Note Note
(MOV) (XCH)
Note
Note
(MOV) (XCH) (ADD)
Note
Note Notes
Note
(MOV) (XCH) (ADD)
Note
Note
MULU DIVUW
Note
saddr
Note
(MOV) (ADD)
Note
Note
Note
DBNZ PUSH
Note
Note
(ADD)
Note
Note
!addr16 !!addr24 [saddrp] [%saddrg] mem3
(MOV)
Note
Note
ROR4 ROL4
PSWL PSWH STBC, [TDE+] [TDE-]
DBNZ (MOV) (ADD)
Note
MOVBK
Note
Note Note
MOVM
Notes operands ADDC, SUB, SUBC, AND, XOR, same that ADD. Either second operand used, second operand operand address. operands ROL, RORC, ROLC, SHR, same that ROR. operands XCHM, CMPME, CMPMNE, CMPMNC, CMPMC same that MOVM. operands XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC same that MOVBK. code length some instructions having saddr2 saddr this combination short.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
16-bit instructions (instructions parentheses combinations realized describing MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW Table 12-2. Instruction List 16-Bit Addressing
Second Operand #word First Operand (MOVW) ADDW
Note
saddrp saddrp'
sfrp
!addr16
[WHL+]
byte
None
Note
!!addr24 [saddrp] [%saddrg]
(MOVW) (XCHW) (ADD)
Note
(MOVW) (XCHW) (ADDW) MOVW XCHW ADDW
Note Note
(MOVW) (XCHW) (ADDW) MOVW XCHW ADDW
Note
MOVW (XCHW) (ADDW) MOVW XCHW ADDW
Note Note
(MOVW) MOVW XCHW XCHW
(MOVW) (XCHW)
Note Notes
MOVW ADDW
Note
(MOVW) (XCHW) (ADDW)
Note
MOVW
SHRW SHLW
MULU INCW
Note
Note
DECW INCW DECW
saddrp
MOVW ADDW
Note
(MOVW) (ADDW)
Note
MOVW ADDW
Note
MOVW XCHW ADDW
Note
Note
sfrp
MOVW ADDW
Note
MOVW (ADDW)
Note
MOVW ADDW
Note
PUSH MOVTBLW
!addr16 !!addr24 [saddrp] [%saddrg]
MOVW
(MOVW)
MOVW
MOVW
PUSH
ADDWG SUBWG
post
PUSH PUSHU POPU
[TDE+] byte
(MOVW)
SACW MACW MACSW
Notes operands SUBW CMPW same that ADDW. Either second operand used, second operand operand address. code length some instructions having saddrp2 saddrp this combination short. operands MULUW DIVUX same that MULW.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
24-bit instructions (instructions parentheses combinations realized describing MOVG, ADDG, SUBG, INCG, DECG, PUSH, Table 12-3. Instruction List 24-Bit Addressing
Second Operand #imm24 First Operand (MOVG) (ADDG) (SUBG) MOVG ADDG SUBG (MOVG) (ADDG) (SUBG) (MOVG) (ADDG) (SUBG) (MOVG) (ADDG) (SUBG) MOVG ADDG SUBG (MOVG) ADDG SUBG MOVG MOVG INCG DECG PUSH saddrg !!addr24 mem1 [%saddrg] MOVG (MOVG) (MOVG) MOVG MOVG MOVG INCG DECG MOVG MOVG (MOVG) MOVG MOVG MOVG saddrg !!addr24 mem1 [%saddrg] None
Note
Note Either second operand used, second operand operand address.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BTCLR, BFSET Table 12-4. Instruction List Manipulation Instruction Addressing
Second Operand saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit First Operand !addr16.bit !!addr24.bit MOV1 AND1 XOR1 saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit !addr16.bit !!addr24.bit MOV1 NOT1 SET1 CLR1 BTCLR BFSET /saddr.bit /sfr. /A.bit /X.bit /PSWL.bit /PSWH.bit /mem2.bit /!addr16.bit /!!addr24.bit AND1 NOT1 SET1 CLR1 None
Note
Note Either second operand used, second operand operand address.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Call return/branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BNZ, BNE, BNC, BNL, BNV, BPO, BPE, BLT, BGE, BLE, BGT, BNH, BTCLR, BFSET, DBNZ Table 12-5. Instruction List Call Return/Branch Instruction Addressing
Operand Instruction Address Basic instruction
Note
$addr20 $!addr20 !addr16
!!addr20
[rp]
[rg]
!addr11
[addr5]
None
CALL
CALL RETCS RETCSB
CALL
CALL
CALL
CALL
CALL
CALLF
CALLF
BRKCS
RETI RETB
Compound instruction
BTCLR BFSET DBNZ
Note operands BNZ, BNE, BNC, BNL, BNV, BPO, BPE, BLT, BGE, BLE, BGT, BNH, same that Other instructions ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, SWRS
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings 25°C)
Parameter Supply voltage Symbol AVDD AVSS AVREF0 AVREF1 Input voltage Analog input voltage Output voltage Output current, Total Total P10, P12, Total pins Output current, high Total pins Operating ambient temperature Storage temperature converter reference voltage input converter reference voltage input Other than Analog input N-ch open drain Conditions Ratings -0.3 +6.5 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 AVSS AVREF0 -0.3 +150 Unit
Tstg
Caution
Product quality suffer absolute maximum rating exceeded even momentarily parameter. That absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions that ensure that absolute maximum ratings exceeded.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Operating Conditions
Operating ambient temperature (TA): +85°C Power supply voltage clock cycle time: Figure 13-1 Power supply voltage with subsystem clock operation: Figure 13-1. Power Supply Voltage Clock Cycle Time (CPU Clock Frequency: fCPU)
10,000
8,000
Clock cycle time tCYK [ns]
Guaranteed operating range
Supply voltage
Capacitance 25°C,
Parameter Input capacitance Symbol Unmeasured pins returned Conditions Other than Port Port Other than Port Port capacitance Other than Port Port MIN. TYP. MAX. Unit
Output capacitance
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Main System Clock Oscillator Characteristics +85°C)
Resonator Ceramic resonator crystal resonator Recommended Circuit Parameter Oscillation frequency (fX) ENMP Conditions ENMP External clock input frequency (fX) ENMP ENMP
MIN.
TYP.
MAX. 12.5 6.25 12.5 6.25 3.125 12.5 6.25 12.5 6.25 3.125
Unit
PD74HCU04
input high-/low-level width (tWXH, tWXL) input rising/falling time (tXR, tXF)
Cautions When using main system clock oscillator, wire follows area enclosed broken lines above figures avoid adverse effect from wiring capacitance. Keep wiring length short possible. cross wiring with other signal lines. route wiring near signal line through which high fluctuating current flows. Always make ground point oscillator capacitor same potential VSS. ground capacitor ground pattern through which high current flows. fetch signals from oscillator. When main system clock stopped system operated subsystem clock, subsystem clock should switched back main system clock after oscillation stabilization time secured program.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Subsystem Clock Oscillator Characteristics +85°C)
Resonator Crystal resonator Recommended Circuit
Parameter Oscillation frequency (fXT) Oscillation stabilization timeNote
Conditions
MIN.
TYP. 32.768
MAX.
Unit
External clock
input frequency (fXT) input high-/lowlevel width (tXTH, tXTL)
PD74HCU04
14.3
15.6
Note Time required stabilize oscillation after applying supply voltage (VDD). Cautions When using subsystem clock oscillator, wire follows area enclosed broken lines above figures avoid adverse effect from wiring capacitance. Keep wiring length short possible. cross wiring with other signal lines. route wiring near signal line through which high fluctuating current flows. Always make ground point oscillator capacitor same potential VSS. ground capacitor ground pattern through which high current flows. fetch signals from oscillator. When main system clock stopped device operating subsystem clock, wait until oscillation stabilization time been secured program before switching back main system clock. Remark resonator selection oscillator constant, users required either evaluate oscillation themselves apply resonator manufacturer evaluation.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Recommended Oscillator Constant Main system clock: Ceramic resonator connection +85°C)
µPD784214A, 784215A, 784216A, 784214AY, 784215AY, 784216AY
Manufacturer Part Number Oscillation Frequency (MHz) Recommended Circuit Constant (pF) (pF) Oscillation Voltage Range MIN. MAX.(V) Oscillation Stabilization Time (MAX.) tOST (ms) Murata Mfg. Co., Ltd. CSTLS4M00G56-B0 CSTLS8M00G53-B0 CSTLA12M5T55-B0 12.5 On-chip On-chip On-chip On-chip On-chip On-chip 0.40 0.28 0.29
Caution
oscillator constant oscillation voltage range indicate conditions stable oscillation. Oscillation frequency precision guaranteed. applications requiring oscillation frequency precision, oscillation frequency must adjusted implementation circuit. details, please contact directly manufacturer resonator will use.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
µPD784217A, 784218A, 784217AY, 784218AY
Manufacturer Part Number Oscillation Frequency (MHz) Recommended Circuit Constant (pF) (pF) Oscillation Voltage Range MIN. MAX.(V)
(1/2)
Oscillation Stabilization Time (MAX.) tOST (ms)
Murata Mfg. Co., Ltd.
CSTCC2.00MG0H6 CSA2.00MG040 CST2.00MG040 CSTCC4.00MG0H6 CSTCC4.00MGU0H6 CSA4.00MG CST4.00MGW CSA4.00MG093 CST4.00MGW093 CSTLS4M00G56-B0 CSTLS4M00G56093-B0 CSTCC6.00MG0H6 CSTCC6.00MGU0H6 CSA6.00MG CST6.00MGW CSA6.00MG093 CST6.00MGW093 CSTLS6M00G56-B0 CSTLS6M00G56093-B0 CSTCC8.00MG CSTCC8.00MG093 CSA8.00MTZ CST8.00MTW CSA8.00MTZ093 CST8.00MTW093 CSTLS8M00G53-B0 CSTLS8M00G53093-B0 CSTCC10.0MG CSTCC10.0MG093 CSA10.0MTZ CST10.0MTW CSA10.0MTZ093 CST10.0MTW093 CSTCV12.5MTJ0C4
10.0 10.0 10.0 10.0 10.0 10.0 12.5
On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip
On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip
0.46 0.74 0.74 0.43 0.43 0.32 0.32 0.32 0.32 0.45 0.45 0.45 0.45 0.33 0.33 0.33 0.33 0.45 0.45 0.28 0.28 0.30 0.30 0.30 0.30 0.27 0.27 0.28 0.28 0.32 0.32 0.32 0.32 0.26
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
µPD784217A, 784218A, 784217AY, 784218AY
Manufacturer Part Number Oscillation Frequency (MHz) Recommended Circuit Constant (pF) (pF) Oscillation Voltage Range MIN. MAX.(V)
(2/2)
Oscillation Stabilization Time (MAX.) tOST (ms)
Murata Mfg. Co., Ltd.
CSA12.5MTZ CSTLA12M5T55-B0 CSA12.5MTZ093 CSTLA12M5T55093-B0
12.5 12.5 12.5 12.5 12.5 10.0
On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip
On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip
0.30 0.30 0.30 0.30 0.28 0.28
Kyocera Corporation
PBRC2.00AR-A PBRC4.00HR PBRC6.00HR SSR8.00CR-S24 SSR12.50CR-S24
FCR4.0MC5 FCR6.0MC5 FCR8.0MC5 FCR10.0MC5
Caution
oscillator constant oscillation voltage range indicate conditions stable oscillation. Oscillation frequency precision guaranteed. applications requiring oscillation frequency precision, oscillation frequency must adjusted implementation circuit. details, please contact directly manufacturer resonator will use.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Characteristics +85°C, AVDD AVSS (1/3)
Parameter Input voltage, Symbol VIL1 Note Conditions VIL2 P06, P20, P22, P33, P34, P70, P72, P100 P103, RESET (N-ch open drain) P17, P130, P131 VIL5 XT1, VIL6 P25, Input voltage, high VIH1 Note VIH2 P06, P20, P22, P33, P34, P70, P72, P100 P103, RESET (N-ch open drain) P17, P130, P131 VIH5 XT1, VIH6 P25, Output voltage, VOL1 pins other than P47, P57, mANote P47, Note µANote
Note
MIN. 0.7VDD 0.8VDD 0.8VDD 0.85VDD 0.7VDD 0.8VDD 0.7VDD 0.8VDD 0.8VDD 0.85VDD 0.7VDD 0.8VDD
TYP.
MAX. 0.3VDD 0.2VDD 0.2VDD 0.15VDD 0.3VDD 0.2VDD 0.3VDD 0.2VDD 0.2VDD 0.1VDD 0.3VDD 0.2VDD
Unit
VIL3
VIL4
VIH3
VIH4
mANote VOL2 Output voltage, high VOH1 Except XT1, XT1, Except XT1, XT1, (N-ch open drain)
-100 µANote Input leakage current, ILIL1 ILIL2 Input leakage current, high ILIH1 ILIH2 ILIH3 Output leakage current, Output leakage current, high ILOL1 ILOH1
Notes P21, P23, P24, P26, P32, P37, P47, P57, P67, P71, P87, P120 P127
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Characteristics +85°C, AVDD AVSS (2/3)
µPD784214A, 784215A, 784216A, 784214AY, 784215AY, 784216AY
Parameter Supply current Symbol IDD1 Operation mode Conditions 12.5 MHz, ±10% MHz, ±10% MHz, ±10% IDD2 HALT mode 12.5 MHz, ±10% MHz, ±10% MHz, ±10% IDD3 IDLE mode 12.5 MHz, ±10% MHz, ±10% MHz, ±10% IDD4 Operation modeNote kHz, ±10% kHz, ±10% kHz, ±10% IDD5 HALT modeNote kHz, ±10% kHz, ±10% kHz, ±10% IDD6 IDLE modeNote kHz, ±10% kHz, ±10% kHz, ±10% Data retention voltage Data retention current VDDDR IDDDR HALT, IDLE modes STOP mode ±10% ±10% Pull-up resistor MIN. TYP. MAX. Unit
Note When main system clock stopped subsystem clock operating. Remark Unless otherwise specified, characteristics alternate-function pins same those port pins.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Characteristics +85°C, AVDD AVSS (3/3)
µPD784217A, 784218A, 784217AY, 784218AY
Parameter Supply current Symbol IDD1 Operation mode Conditions 12.5 MHz, ±10% MHz, ±10% MHz, ±10% IDD2 HALT mode 12.5 MHz, ±10% MHz, ±10% MHz, ±10% IDD3 IDLE mode 12.5 MHz, ±10% MHz, ±10% MHz, ±10% IDD4 Operation modeNote kHz, ±10% kHz, ±10% kHz, ±10% IDD5 HALT modeNote kHz, ±10% kHz, ±10% kHz, ±10% IDD6 IDLE modeNote kHz, ±10% kHz, ±10% kHz, ±10% Data retention voltage Data retention current VDDDR IDDDR HALT, IDLE modes STOP mode ±10% ±10% Pull-up resistor MIN. TYP. MAX. Unit
Note When main system clock stopped subsystem clock operating. Remark Unless otherwise specified, characteristics alternate-function pins same those port pins.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Characteristics +85°C, AVDD AVSS
Read/write operation (1/3)
Parameter Cycle time Symbol tCYK Conditions Address setup time ASTB) tSAST ±10% ±10% ±10% Address hold time (from ASTB) tHSTLA ±10% ±10% ±10% ASTB high-level width tWSTH ±10% ±10% ±10% Address hold time (from tHRA ±10% ±10% ±10% Delay time from address tDAR ±10% ±10% ±10% Address float time (from tFAR ±10% ±10% ±10% Data input time from address tDAID ±10% ±10% ±10% Data input time from ASTB tDSTID ±10% ±10% ±10% Data input time from tDRID ±10% ±10% ±10% Delay time from ASTB tDSTR ±10% ±10% ±10% Data hold time (from tHRID ±10% ±10% ±10% 0.5T 0.5T 0.5T MIN. (0.5 (0.5 (0.5 0.5T 0.5T 0.5T (0.5 (0.5 (0.5 0.5T 0.5T 0.5T (2.5 (2.5 (2.5 (1.5 (1.5 (1.5 TYP. MAX. Unit
Remark tCYK 1/fXX (fXX: main system clock frequency) (during address wait), otherwise, Number waits
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Read/write operation (2/3)
Parameter Address active time from Symbol tDRA Conditions ±10% ±10% ±10% Delay time from ASTB tDRST ±10% ±10% ±10% low-level width tWRL ±10% ±10% ±10% Address active time from tDWA ±10% ±10% ±10% Delay time from address tDAW ±10% ±10% ±10% Address hold time (from tHWA ±10% ±10% ±10% Delay time from ASTB data tDSTOD output ±10% ±10% ±10% Delay time from data tDWOD output ±10% ±10% ±10% Delay time from ASTB tDSTW ±10% ±10% ±10% Data setup time tSODWR ±10% ±10% ±10% Data hold time (from tHWOD ±10% ±10% ±10% Delay time from ASTB tDWST ±10% ±10% ±10% low-level width tWWL ±10% ±10% ±10% 0.5T 0.5T 0.5T (1.5 (1.5 (1.5 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T (1.5 (1.5 (1.5 MIN. 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T (1.5 (1.5 (1.5 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T TYP. MAX. Unit
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Remark tCYK 1/fXX (fXX: main system clock frequency) (during address wait), otherwise, Number wait states Read/write operation (3/3)
Parameter Delay time from address Symbol tADEXD Conditions ±10% ±10% ±10% Delay time from ASTB tEXTAH ±10% ±10% ±10% Delay time from tEXRDS ±10% ±10% ±10% Delay time from tEXWDS ±10% ±10% ±10% Delay time from ASTB tEXADR ±10% ±10% ±10% MIN. 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T TYP. MAX. Unit
Remark tCYK 1/fXX (fXX: main system clock frequency)
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
External wait timing
Parameter Input time from address WAIT Symbol tDAWT Conditions ±10% ±10% ±10% Input time from ASTB WAIT tDSTWT ±10% ±10% ±10% Hold time from ASTB WAIT tHSTWT ±10% ±10% ±10% Delay time from ASTB WAIT tDRWTL tDSTWTH ±10% ±10% ±10% Input time from WAIT ±10% ±10% ±10% Hold time from WAIT tHRWT ±10% ±10% ±10% Delay time from WAIT tDRWTH ±10% ±10% ±10% Data input time from WAIT tDWTID ±10% ±10% ±10% Delay time from WAIT tDWTR ±10% ±10% ±10% Delay time from WAIT tDWTW ±10% ±10% ±10% Input time from WAIT tDWWTL ±10% ±10% ±10% Hold time from WAIT tHWWT ±10% ±10% ±10% Delay time from WAIT tDWWTH ±10% ±10% ±10% 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T (0.5 (0.5 (0.5 (1.5 (1.5 (1.5 MIN. TYP. MAX. 1.5T 1.5T 1.5T Unit
Remark tCYK 1/fXX (fXX: main system clock frequency) (during address wait), otherwise, Number wait states
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Serial operation +85°C, AVDD AVSS (1/2) 3-wire serial mode (SCK: Internal clock output)
Parameter cycle time Symbol tKCY1 Conditions high-/low-level width tKH1, tKL1 setup time SCK) tSIK1 hold time (from SCK) Delay time from output Hold time from output tHIK1 tDSO1 tHSO1 tKCY1/2 MIN. 1,280 2,560 4,000 1,180 1,900 TYP. MAX. Unit
3-wire serial mode (SCK: External clock input)
Parameter cycle time Symbol tKCY2 Conditions high-/low-level width tKH2 tKL2 setup time SCK) tSIK2 hold time (from SCK) Delay time from output Hold time from output tHIK2 tDSO2 tHSO2 tkcy2/2 MIN. 1,280 2,560 4,000 1,280 2,000 TYP. MAX. Unit
UART mode
Parameter ASCK cycle time Symbol tKCY3 Conditions ASCK high-/low-level width tKH3 tKL3 MIN. 1,667 TYP. MAX. Unit
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Serial operation +85°C, AVDD AVSS (2/2) mode
Parameter Symbol MIN. SCL0 clock frequency free time (between stop start conditions) Hold timeNote1 Low-level width SCL0 clock High-level width SCL0 clock Setup time start/restart conditions Data hold When using CBUStime compatible master When using Data setup time Rise time SDA0 SCL0 signals Fall time SDA0 SCL0 signals Setup time stop condition Pulse width spike restricted input filter Load capacitance each line fCLK tBUF Standard Mode MAX. 1,000 High-Speed Mode MIN. MAX. 0.9Note Unit
tLOW tHIGH
0Note
Note Note
0Note
0.1Cb
0.1CbNote
Notes start condition, first clock pulse generated after hold time. fill undefined area SCL0 falling edge, necessary device provide internal SDA0 signal VIHmin.) with least hold time. device does extend SCL0 signal low-level hold time (tLOW), only maximum data hold time needs satisfied. high-speed mode used standard mode system. this case, conditions described below must satisfied. device does extend SCL0 signal low-level hold time device extends SCL0 signal low-level hold time sure transmit data SDA0 line before SCL0 line released (tRmax. 1,000 1,250 standard mode specification) Total capacitance line (unit:
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Clock output operation +85°C, AVDD AVSS
Parameter cycle time high-/low-level width Symbol tCYCL tCLL tCLH tCLR tCLF Conditions 0.5T MIN. TYP. MAX. 31,250 15,615 Unit
rise/fall time
Remark tCYK 1/fXX (fXX: Main system clock frequency) Divided frequency ratio software When using main system clock: When using subsystem clock: Other operations +85°C, AVDD AVSS
Parameter high-/low-level width Symbol tWNIL tWNIH tWITL tWITH tWRSL tWRSH INTP0 INTP6 Conditions MIN. TYP. MAX. Unit
INTP input high-/low-level width
RESET high-/low-level width
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Converter Characteristics +85°C, AVDD AVSS
Parameter Resolution Overall error
Notes
Symbol
Conditions
MIN.
TYP.
MAX. ±1.2 ±1.6
Unit bits %FSR
AVREF0 VDD, AVDD AVREF0 VDD, AVDD
%FSR
Conversion time Sampling time Analog input voltage Reference voltage Resistance between AVREF0 AVSS
tCONV tSAMP VIAN AVREF0 RAVREF0 When converting
24/fXX AVSS
AVREF0 AVDD
Notes Quantization error (±1/2 LSB) included. Overall error indicated ratio full-scale value. Remark Main system clock frequency
Converter Characteristics +85°C, AVDD AVSS
Parameter Resolution Overall error
Notes
Symbol
Conditions
MIN.
TYP.
MAX. ±0.6 ±1.2
Unit Bits %FSR
AVREF1 VDD, AVDD AVREF1 VDD, AVDD
%FSR
Settling time
Load conditions:
AVREF1 AVREF1 AVREF1
Output resistance Reference voltage AVREF1 current
AVREF1 AIREF1
DACS0, only channel
Notes Quantization error (±1/2 LSB) included. Overall error indicated ratio full-scale value.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Data Retention Characteristics +85°C, AVDD AVSS
Parameter Data retention voltage Data retention current Symbol VDDDR IDDDR STOP mode VDDDR ±10% VDDDR ±10% rise time fall time hold time (from STOP mode setting) STOP release signal input time Oscillation stabilization wait time tRVD tFVD tHVD Conditions MIN. TYP. MAX. Unit
tDREL tWAIT Crystal resonator Ceramic resonator
0.9VDDDR 0.1VDDDR VDDDR
Low-level input voltage High-level input voltage
RESET, P00/INTP0 P06/INTP6
Timing Test Points
0.8VDD Test points
0.8VDD
0.45
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Timing Waveforms
Read operations
(CLK) tCYK
(Output)
Lower address
Lower address
(Output) tDAID
Higher address tHRA tDRA Hi-Z Data (Input) tHRID tFAR Hi-Z
Higher address
tDSTID (Input/output) Hi-Z Lower address (Output) tSAST ASTB (Output) tHSTLA
Lower address (Output)
tWSTH tDSTR tDAR tDRID tWRL tDRWTL tDAWT tDRWTH tHRWT tDWTR tDWTID tDRST
(Output)
WAIT (Input) tDSTWT tDSTWTH tHSTWT tADEXD tEXTAH tEXRDS tEXADR
Remark signal output from pins when unused.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Write operation
(CLK) tCYK
(Output)
Lower address
Lower address
(Output) tDAID
Higher address tHWA tDWA Hi-Z Data (Output) tHWOD tFAR tSODWR Hi-Z
Higher address
tDSTOD (Output) Hi-Z Lower address (Output) tSAST ASTB (Output) tHSTLA
Lower address (Output)
tWSTH tDSTW tDAW tDWOD tWWL tDWWTL tDAWT tDWWTH tHWWT tDWTW tDWTID tDWST
(Output)
WAIT (Input) tDSTWT tDSTWTH tHSTWT tADEXD tEXTAH tEXWDS tEXADR
Remark signal output from pins when unused.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Serial Operation
3-wire serial mode
tKCY1, tKH1, tKL1, tSIK1, tDSO1, tHIK1,
Input data tHSO1, Output data
UART mode
tKCY3 tKH3 ASCK tKL3
mode (µPD784216AY/784218AY Subseries only)
SCL0
tHIGH
SDA0 tBUF Stop condition Start condition Restart condition Stop condition
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Clock Output Timing
tCLH tCLL
CLKOUT tCLR tCYCL tCLF
Interrupt Input Timing
tWNIH tWNIL
tWITH
tWITL
INTP0 INTP6
Reset Input Timing
tWRSH
tWRSL
RESET
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Clock Timing
tWXH tWXL
1/fX
tXTH
tXTL
1/fXT
Data Retention Characteristics
STOP mode setting
tHVD tFVD
VDDDR tRVD tDREL tWAIT
RESET
(Cleared falling edge)
(Cleared rising edge)
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
PACKAGE DRAWINGS
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
detail lead
NOTE Each lead centerline located within 0.08 true position (T.P.) maximum material condition.
ITEM
MILLIMETERS 16.00±0.20 14.00±0.20 14.00±0.20 16.00±0.20 1.00 1.00 0.22 +0.05 -0.04 0.08 0.50 (T.P.) 1.00±0.20 0.50±0.20 0.17 +0.03 -0.07 0.08 1.40±0.05 0.10±0.05 1.60 MAX.
S100GC-50-8EU, 8EA-2
Remark external dimensions material version same those mass-produced version.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
100-PIN PLASTIC (14x20)
detail lead
NOTE Each lead centerline located within 0.15 true position (T.P.) maximum material condition.
ITEM
MILLIMETERS 23.6±0.4 20.0±0.2 14.0±0.2 17.6±0.4 0.30±0.10 0.15 0.65 (T.P.) 1.8±0.2 0.8±0.2 0.15+0.10 -0.05 0.10 2.7±0.1 0.1±0.1 5°±5° MAX.
P100GF-65-3BA1-4
Remark external dimensions material version same those mass-produced version.
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
RECOMMENDED SOLDERING CONDITIONS
µPD784218A should soldered mounted under following recommended conditions. details recommended soldering conditions, refer document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended below, contact sales representative. Table 15-1. Surface Mounting Type Soldering Conditions (1/2)
plastic LQFP(fine pitch) plastic LQFP(fine pitch) plastic LQFP(fine pitch) plastic LQFP(fine pitch) plastic LQFP(fine pitch) plastic LQFP(fine pitch)
Soldering Method Soldering Conditions Recommended Condition Symbol IR35-00-2
Infrared reflow
Package peak temperature: 235°C, Time: seconds max. 210°C higher), Count: times less Package peak temperature: 215°C, Time: seconds max. 200°C higher), Count: times less temperature: 300°C max., Time: seconds max. (per row)
VP15-00-2
Partial heating
Caution
different soldering methods together (except partial heating).
plastic LQFP(fine pitch) plastic LQFP(fine pitch) 100-pin plastic LQFP (fine pitch) 100-pin plastic LQFP (fine pitch)
Soldering Method Soldering Conditions Recommended Condition Symbol IR35-107-2
Infrared reflow
Package peak temperature: 235°C, Time: seconds max. 210°C higher), Count: times less, Exposure limit: daysNote (after that, prebake 125°C hours) Package peak temperature: 215°C, Time: seconds max. 200°C higher), Count: times less, Exposure limit: daysNote (after that, prebake 125°C hours) temperature: 300°C max., Time: seconds max. (per row)
VP15-107-2
Partial heating
Note After opening pack, store 25°C less less allowable storage period. Caution different soldering methods together (except partial heating).
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Table 15-1. Surface Mounting Type Soldering Conditions (2/2) plastic QFP(14 plastic QFP(14 plastic QFP(14 100-pin plastic 100-pin plastic plastic QFP(14 plastic QFP(14 plastic QFP(14 100-pin plastic 100-pin plastic
Soldering Method Soldering Conditions Recommended Condition Symbol IR35-00-2
Infrared reflow
Package peak temperature: 235°C, Time: seconds max. 210°C higher), Count: times less Package peak temperature: 215°C, Time: seconds max. 200°C higher), Count: times less Solder bath temperature: 260°C max., Time: seconds max., Count: Once, Preheating temperature: 120°C max. (package surface temperature) temperature: 300°C max., Time: seconds max. (per row)
VP15-00-2
Wave soldering
WS60-00-1
Partial heating
Caution
different soldering methods together (except partial heating).
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
APPENDIX DEVELOPMENT TOOLS
following development tools available system development using µPD784218A. Also refer Cautions using development tools. Language processing software
RA78K4 CC78K4 DF784218 CC78K4-L Assembler package common 78K/IV Series compiler package common 78K/IV Series Device file common µPD784216A, 784216AY, 784218A, 784218AY Subseries compiler library source file common 78K/IV Series
Flash memory writing tools
Flashpro (Part number: FL-PR3, PG-FP3) FA-100GF FA-100GC Dedicated flash programmer microcontroller incorporating flash memory Adapter writing 100-pin plastic (GF-3BA type) flash memory. Connection must performed accordance with target product. Adapter writing 100-pin plastic LQFP (GC-8EU type) flash memory. Connection must performed accordance with target product.
Debugging tools When IE-78K4-NS in-circuit emulator used
IE-78K4-NS IE-70000-MC-PS-B IE-70000-98-IF-C IE-70000-CD-IF-A IE-70000-PC-IF-C IE-70000-PCI-IF-A IE-784225-NS-EM1 NP-100GF NP-100GC EV-9200GF-100 TGC-100SDW ID78K4-NS SM78K4 DF784218 In-circuit emulator common 78K/IV Series Power supply unit IE-78K4-NS Interface adapter required when PC-9800 series (except notebook type) used host machine supported) card cable when PC-9800 series notebook used host machine (PCMCIA socket supported) Interface adapter required when using PC/ATcompatibles host machine (ISA supported) Interface adapter required when using that incorporates host machine Emulation board emulate µPD784216A, 784216AY, 784218A, 784218AY Subseries Emulation probe 100-pin plastic (GF-3BA type) Emulation probe 100-pin plastic LQFP (GC-8EU type) Socket mounted target system board made 100-pin plastic (GF-3BA type) Conversion adapter connect NP-100GC target system board which 100-pin plastic LQFP (GC-8EU type) mounted Integrated debugger IE-78K4-NS System simulator common 78K/IV Series Device file common µPD784216A, 784216AY, 784218A, 784218AY Subseries
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
When IE-784000-R in-circuit emulator used
IE-784000-R IE-70000-98-IF-C IE-70000-PC-IF-C IE-70000-PCI-IF-A IE-78000-R-SV3 IE-784225-NS-EM1 IE-784000-R-EM IE-78K4-R-EX3 EP-784218GF-R EP-78064GC-R EV-9200GF-100 TGC-100SDW ID78K4 SM78K4 DF784218 In-circuit emulator common 78K/IV Series Interface adapter required when PC-9800 series (except notebook type) used host machine supported) Interface adapter required when using PC/AT compatibles host machine (ISA supported) Interface adapter required when using that incorporates host machine Interface adapter cable required when used host machine Emulation board emulate µPD784216A, 784216AY, 784218A, 784218AY Subseries Emulation board common 78K/IV Series Emulation probe conversion board required when using IE-784225-NS-EM1 IE-784000-R. Emulation probe 100-pin plastic (GF-3BA type) Emulation probe 100-pin plastic LQFP (GC-8EU type) Socket mounted target system board made 100-pin plastic (GF-3BA type) Conversion adapter connect EP-78064GC-R target system board which 100-pin plastic LQFP (GC-8EU type) mounted Integrated debugger IE-784000-R System simulator common 78K/IV Series Device file common µPD784216A, 784216AY, 784218A, 784218AY Subseries
Real-time
RX78K4 Real-time 78K/IV Series
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Cautions using development tools ID78K4-NS, ID78K4, SM78K4 used combination with DF784218. CC78K4 RX78K4 used combination with RA78K4 DF784218. FL-PR3, FA-100GF, FA-100GC, NP-100GF, NP-100GC products made Naito Densei Machida Mfg. Co., Ltd. (TEL: +81-45-475-4191). TGC-100SDW product made TOKYO ELETECH CORPORATION. further information, contact Daimaru Kogyo, Ltd. Tokyo Electronic Division (TEL: +81-3-3820-7112) Osaka Electronic Division (TEL: +81-6-6244-6672) third party development tools, Single-Chip Microcontroller Development Tool Selection Guide (U11069E). host machine suitable each software follows.
Host Machine [OS] Software RA78K4 CC78K4 ID78K4-NS ID78K4 SM78K4 RX78K4 PC-9800 series [WindowsTM] PC/AT compatibles [Japanese/English Windows] Note
Note
HP9000 Series 700[HP-UXTM] SPARCstation[SunOSTM, SolarisTM]
Note
Note DOS-based software
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Notes target system design following shows diagram connection conditions between emulation probe, conversion socket, conversion connector. Design your system making allowances conditions such form parts mounted target system shown below.
Figure A-1. Distance Between In-Circuit Emulator Conversion Socket
In-circuit emulator IE-78K4-NS
Target system Emulation board IE-784225-NS-EM1
Emulation probe NP-100GF NP-100GC Note Note Note Note
Conversion socket: EV-9200GF-100 (for NP-100GF) Conversion connector: TGC-100SDW (for NP-100GC)
Notes position NP-100GF position NP-100GC
Data Sheet U14121EJ4V0DS
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
Figure A-2. Conditions Target System Connection
Emulation probe NP-100GF
In-circuit emulator IE
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