µPD780957(A), 780958(A) 8-BIT SINGLE-CHIP MICROCONTROLLERS D

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µPD780957(A), 780958(A) 8-BIT SINGLE-CHIP MICROCONTROLLERS D

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INTEGRATED CIRCUIT
µPD780957(A), 780958(A)
8-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
µPD780957(A) 780958(A) µPD780958 Subseries products 78K/0 Series. microcontrollers support ultra-low power consumption especially suitable meter control. Detailed function descriptions provided following user's manuals. sure read them before designing. U13655E µPD780958 Subseries User's Manual: 78K/0 Series User's Manual Instructions: U12326E These
FEATURES
Ultra-low power consumption supported. On-chip
Item Part Number Internal Internal High-Speed Internal Expansion Display
µPD780957(A) µPD780958(A)
1024 bytes
1024 bytes
bytes
Three channels clock generators: Main system clock oscillation)) Subsystem clock (32.768 kHz) Subsystem clock (4.91 MHz) ports (including segment signal output alternate function pins): controller/driver Serial interface: channels UART mode (with switching function): channel (communication enabled with subsystem clocks 3-wire serial mode: sampling function: channel Sampling output timer/detector: channel Timer: channels 16-bit timer/event counter: channels 8-bit timer: Watchdog timer: Standby function: HALT mode Supply voltage: channels channel channel
Real-time output function: 4-bit resolution channels
information this document subject change without notice. Before using this document, please confirm that this latest version.
devices/types available every country. Please check with local representative availability additional information.
Document U13739EJ1V0DS00 (1st edition) Date Published February 2001 CP(K) Printed Japan
mark
shows major revised points.
1999
µPD780957(A), 780958(A)
APPLICATIONS
Industrial meter control, etc.
ORDERING INFORMATION
Part Number Package 100-pin plastic LQFP (fine pitch) 100-pin plastic LQFP (fine pitch) Quality Grade Special Special
Remark
indicates code suffix.
details quality grades devices their applications, refer Quality Grades Semiconductor Devices (C11531E) published Corporation.
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
78K/0 SERIES LINEUP
products 78K/0 Series listed below. names enclosed boxes subseries names.
Products mass production Products under development subseries products compatible with bus. Control
PD78078 with reduced noise PD78054 with timer enhanced external interface function PD78070AY ROM-less version µPD78078 PD780018AY PD78078Y with enhanced serial restricted functions PD780058 PD780058Y PD78054 with enhanced serial 80-pin PD78058F PD78058FY PD78054 with reduced noise PD78054Y PD78018F with UART converter, enhanced PD78054 80-pin PD780024A with expanded PD780065 80-pin PD780078 PD780078Y PD780034A with timer enhanced serial 64-pin PD780034A PD780034AY PD780024A with enhanced converter 64-pin PD780024A PD780024AY PD78018F with enhanced serial 64-pin PD78014H PD78018F with reduced noise 64-pin 64-pin PD78018F PD78018FY Basic subseries control 42/44-pin PD78083 On-chip UART capable low-voltage (1.8 operation
100-pin 100-pin 100-pin 100-pin 80-pin
PD78075B
PD78078 PD78070A
PD78078Y
Inverter control 64-pin 100-pin 80-pin 80-pin 80-pin
PD780988
driving
On-chip inverter control circuit UART, noise reduced product
PD780208 PD780232 PD78044H PD78044F
driving
PD78044F with enhanced C/D. Total display outputs:
panel control on-chip C/D. Total display outputs: PD78044F with N-ch open-drain I/O. Total display outputs: Basic subseries driving. Total display outputs:
78K/0 Series
120-pin 120-pin 120-pin 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin
PD780338 PD780328 PD780318 PD780308 PD78064B PD78064 PD780948 PD78098B PD780701Y PD780833Y
Meter control
PD780308 with enhanced display function timer. Segment signal outputs: max. PD780308 with enhanced display function timer. Segment signal outputs: max. PD780308 with enhanced display function timer. Segment signal outputs: max. PD78064 with enhanced expanded PD78064 with reduced noise
Basic subseries driving on-chip UART On-chip DCAN controller
PD780308Y PD78064Y
interface supporting
PD78054 with IEBuscontroller, noise reduced product On-chip DCAN/IEBus controller
On-chip J1850 (CLASS2) controller industrial meter control On-chip controller/driver automobile meter driving automobile meter driving on-chip DCAN controller
100-pin 80-pin 80-pin
PD780958 PD780852 PD780824
Remark
(Vacuum Fluorescent Display) referred "FIP documents, functions same.
(Fluorescent Indicator Panel) some
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
major functional differences among subseries listed below.
Function Subseries Name Control Capacity Note (UART: (UART: (UART: (UART: (UART:
(time division UART:1
Timer
10-Bit 10-Bit 8-Bit
8-Bit 16-Bit Watch
Serial Interface
MIN. External Value Expansion
µPD78075B µPD78078 µPD78070A µPD780058 µPD78058F µPD78054 µPD780065 µPD780078 µPD780034A µPD780024A µPD78014H µPD78018F µPD78083
(UART: 1ch)
(UART:
Inverter control drive
µPD780988
µPD780208 µPD780232 µPD78044H µPD78044F
drive
µPD780338 µPD780328 µPD780318 µPD780308 µPD78064B µPD78064
(UART:
(time division UART:
(UART:
interface
µPD780948
(UART:
supported µPD78098B Meter control
Dash board µPD780852
(UART:
µPD780958
(UART: (UART:
control
µPD780824
Notes
16-bit timer: channels 10-bit timer: channel
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
OVERVIEW FUNCTIONS
Part Number Item Internal memory High-speed Expansion General-purpose registers Minimum instruction execution time 1024 bytes 1024 bytes bits registers bits registers banks) On-chip minimum instruction execution time variable function µs/4 µs/8 operation oscillation) with main system clock) 32.768 operation with subsystem clock 16-bit operation Multiply/divide bits bits, bits bits) manipulation (set, reset, test, Boolean operation) adjust, etc. Total: CMOS I/O: N-ch open-drain I/O: (VDD-level withstand voltage)
µPD780957(A)
µPD780958(A)
Instruction
ports
sampling function Sampling function Serial interface Timer
sampling output/phase detection function channel (can used interval timer attached 8-bit compare register) Sampling output timer/detector channel (can used interval timers attached 8-bit compare registers) UART mode (with switching function): channel 3-wire serial mode: channel 16-bit timer/event counter: 8-bit timer: Watchdog timer: channels channels channel
Timer outputs Clock output Real-time output controller/driver Vectored interrupt sources Maskable Non-maskable Software Power supply voltage Operating ambient temperature Package
(when sampling output sampling function used: 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 32.768 operation with subsystem clock channels bits buffers) segments commons (static, bias) Internal: External: Internal: +80°C 100-pin plastic LQFP (fine pitch)
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
CONTENTS CONFIGURATION (TOP VIEW) BLOCK DIAGRAM. FUNCTIONS
Port Pins. Non-port Pins. Input/Output Circuits Recommended Connection Unused Pins
MEMORY SPACE FEATURES PERIPHERAL HARDWARE FUNCTIONS.
Ports Clock Generator. Timer. Sampling Output Timer/Detector Sampling Function. Clock Output Controller Serial Interfaces. Controller/Driver. Real-Time Output Function
INTERRUPT FUNCTIONS. STANDBY FUNCTION RESET FUNCTION. MASK OPTION
INSTRUCTION SET. ELECTRICAL SPECIFICATIONS. PACKAGE DRAWING RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTS
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
CONFIGURATION (TOP VIEW)
100-pin plastic LQFP (fine pitch)
780958GC(A)-xxx-8EU
WDTOUT P95/S29 P94/S28 P93/S27 P92/S26 P91/S25 P90/S24 P87/S23 P86/S22 P85/S21 P84/S20 P83/S19 P82/S18 P81/S17 P80/S16 P77/S15 P76/S14 P75/S13 P74/S12 P73/S11 P72/S10 P71/S9 P70/S8
P00/INTP0 P01/INTP1 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5/SMP0/RxD20 P06/INTP6/RxD21 P20/TxD20 P21/TxD21 P22/SMP1 P23/SMP2 P24/SMP3 P25/SMP4 P26/MRI0 P27/MRI1 P30/TI01 P31/TI00/TO0 P32/TI2 P33/SMO0 P34/PCL P35/SI3 P36/SO3 P37/SCK3
10099
COM2 COM1 COM0 VLC1 VLC2 CAPH CAPL VROUT0 VROUT1 VDD1 VSS1
Caution Remark
Connect pins directly VSS0. When µPD780957(A) 780958(A) used applications where noise generated inside microcontroller needs reduced, implementation noise reduction measures, such supplying voltage VDD0 VDD1 individually connecting VSS0 VSS1 different ground lines, recommended.
P56/MRO0 P57/MRO1 VDD0 VSS0 P63/ENA P64/RTO0 P65/RTO1 P66/RTO2 P67/RTO3 RESET
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
CAPH, CAPL: CL1, CL2: COM0 COM2: ENA: IC0, IC1: INTP0 INTP6: MRI0, MRI1: MRO0, MRO1: P06: P27: P37: P47: P57: P67: P77: P87: P95: PCL:
Capacitor (for LCD) oscillator Common output Enable Internally connected External interrupt input sampling input sampling output Port Port Port Port Port Port Port Port Port Programmable clock
RESET: RTO0 RTO3: RxD20, RxD21: SCK3: SI3: SMP0 SMP4: SMO0: SO3: S29: TI00, TI01, TI2: TO0: TxD20, TxD21: VDD0, VDD1: VLC1, VLC2: VROUT0, VROUT1: VSS0, VSS1: WDTOUT: XT1, XT2: XT3, XT4:
Reset Real-time output port Receive data Serial clock Serial input Sampling input Sampling output Serial output Segment output Timer input Timer output Transmit data Power supply Power supply (for LCD) Capacitor (for regulator) Ground Watchdog timer output Crystal (subsystem clock Crystal (subsystem clock
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
BLOCK DIAGRAM
TI00/TO0/P31 TI01/P30 TI02/P32 16-bit timer/ event counter 16-bit timer/ event counter 8-bit timer Port 8-bit timer Port 8-bit timer 8-bit timer RTO1 SMO0/P33 SMP0/P05, SMP1/P22 SMP4/P25 MRO0/P56 MRO1/P57 MRI0/P26 MRI1/P27 WDTOUT RxD20/P05 RxD21/P06 TxD20/P20 TxD21/P21 SI3/P35 SO3/P36 SCK3/P37 INTP0/P00 INTP6/P06 PCL/P34 8-bit timer (SMTD0) 8-bit timer Port Port 78K/0 core Port Port 8-bit timer (MRTD0) Real-time output PORT (RTO1) RTO0/P64 RTO3/P67 ENA/P63 Watchdog timer UART controller/driver S8/P70 S15/P77 S16/P80 S23/P87 S24/P90 S29/P95 COM0 COM2 Serial interface SIO3 Interrupt control Clock output control System control MAIN SUB1 VDD0, VDD1 VSS0, VSS1 IC0, SUB2 VLC1 VLC2 CAPH CAPL RESET VROUT0 VROUT1 Port Port Port
Remark
internal capacity varies depending product.
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
FUNCTIONS
Port Pins (1/2)
Function Port 7-bit port. Input/output specified 1-bit units. on-chip pull-up resistor specified software. Port 8-bit port. Input/output specified 1-bit units. on-chip pull-up resistor specified software. After Reset Input Alternate Function INTP0 INTP4 INTP5/SMP0/RxD20 INTP6/RxD21 Input TxD20 TxD21 SMP1 SMP4 MRI0 MRI1 Port 8-bit port. Input/output specified 1-bit units. on-chip pull-up resistor specified software. Input TI01 TI00/TO0 SMO0 SCK3 Port 8-bit port. Input/output specified 1-bit units. on-chip pull-up resistor specified software. Port 8-bit port. Input/output specified 1-bit units. on-chip pull-up resistor specified software. Port 8-bit port. Input/output specified 1-bit units. N-ch open-drain input/output port (3.6 withstand voltage). on-chip pull-up resistor specified mask option. on-chip pull-up resistor specified software. Input
Name
Input MRO0 MRO1 Input
RTO0 RTO3
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Port Pins (2/2)
Function Port 8-bit port. Input/output specified 1-bit units. on-chip pull-up resistor specified software. Port 8-bit port. Input/output specified 1-bit units. on-chip pull-up resistor specified software. Port 6-bit port. Input/output specified 1-bit units. on-chip pull-up resistor specified software. After Reset Input Alternate Function
Name
Input
Input
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Non-port Pins (1/2)
Input Function External interrupt request input which valid edge (rising edge, falling edge, both rising falling edges) specified Serial data input asynchronous serial interface (UART2) After Reset Input Alternate Function P05/SMP0/RxD20 P06/RxD21 Input P05/INTP5/SMP0
Name INTP0 INTP4 INTP5 INTP6 RxD20
Input
RxD21
Serial data input asynchronous serial interface (UART2) (switching pin) Output Serial data output asynchronous serial interface (UART2)
Input
P06/INTP6
TxD20
Input
TxD21 SMP0 SMP1 SMP4 SMO0 MRI0 MRI1 MRO0 MRO1 TI00 Input Output Output Input Input
Serial data output asynchronous serial interface (UART2) (switching pin) Sampling input Input
P05/INTP5/RxD20
Sampling output Phase detection input
Input Input
sampling output External count clock input 16-bit timer/event counter Capture trigger input capture registers (CR00/CR01) 16-bit timer/event counter Capture trigger input capture register (CR00) 16-bit timer/event counter External count clock input 16-bit timer/event counter
Input
Input
P31/TO0
TI01 SCK3 COM0 COM2 Output Output Output Input Output Output Output
Input
16-bit timer output Serial interface serial data input Serial interface serial data output Serial interface serial clock input/output Clock output (for trimming subsystem clock Segment signal output controller
Input Input Input Input Input Output Input
P31/TI00
Common signal output controller output Real-time output port from which data output synchronization with trigger Overflow output watchdog timer System reset input
Output Input Input Output
RTO0 RTO3 Output WDTOUT RESET Output Input
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Non-port Pins (2/2)
Input Input Input Positive power supply ports Positive power supply (except ports) Ground potential ports Ground potential (except ports) Positive power supply controller Connecting capacitor internal regulator Connecting capacitor controller Internally connected. Connect directly VSS0 Connecting crystal resonator subsystem clock oscillation Function Connecting main system clock oscillation resister capacitor Connecting crystal resonator subsystem clock oscillation After Reset Alternate Function
Name VDD0 VDD1 VSS0 VSS1 VLC1, VLC2 VROUT0, VROUT1 CAPH, CAPL IC0,
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Input/Output Circuits Recommended Connection Unused Pins Table shows input/output circuit types recommended connection unused pins. Refer Figure configuration input/output circuit each type. Table 3-1. Input/Output Circuit Types Recommended Connection Unused Pins
Name P00/INTP0 P04/INTP4 P05/INTP5/SMP0/RXD20 P06/INTP6/RXD21 P20/TXD20 P21/TXD21 P22/SMP1 P25/SMP4 P26/MRI0 P27/MRI1 P30/TI01 P31/TI00/TO0 P32/TI2 P33/SMO0 P34/PCL P35/SI3 P36/SO3 P37/SCK3 P56/MRO0 P57/MRO1 13-Q Input: Independently connect VDD0 resistor. Output: Leave open. P63/ENA P64/RTO0 P67/RTO3 P70/S8 P77/S15 P80/S16 P87/S23 P90/S24 P95/S29 COM0 COM2 WDTOUT RESET CAPL, CAPH VLC1, VLC2 17-B 18-A 13-AC Input Independently connect resistor. Independently connect VDD1 resistor. Connect directly VSS0. Output Leave open. 17-C Input: Independently connect VDD0 VSS0 resistor. Output: Leave open. Input: Independently connect VDD0 VSS0 resistor. Output: Leave open. Circuit Type Recommended Connection Unused Pins Input: Independently connect VSS0 resistor. Output: Leave open.
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Figure 3-1. Input/Output Circuits (1/2)
Type VDD0 Mask option Pullup enable VDD0 Data Output disable Scmitt-triggered input with hysteresis characteristics. N-ch VSS0 P-ch IN/OUT P-ch Type
VDD0
Type
VDD0
Type 13-Q Mask option
VDD0
Pullup enable VDD0 Data P-ch
P-ch Data Output disable N-ch VSS0 IN/OUT
IN/OUT
Output disable
N-ch VSS0 Input enable
Input enable Type VDD0 Data P-ch IN/OUT Output disable
Type 13-AC
breakdown Data N-ch VSS0 VSS0
N-ch VSS0
Input enable
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Figure 3-1. Input/Output Circuits (2/2)
Type 17-B Type 17-C VDD0 VLC0 VLC1 P-ch N-ch data P-ch VLC2 N-ch N-ch Output disable VSS0 VSS1 Type 18-A VLC0 P-ch VLC1 N-ch P-ch N-ch P-ch P-ch VLC2 N-ch VSS1 VSS1 VLC2 N-ch data N-ch Input enable VLC0 P-ch VLC1 N-ch P-ch N-ch P-ch Data Pullup enable P-ch VDD0 P-ch IN/OUT
data
N-ch
P-ch
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
MEMORY SPACE
Figures show memory maps µPD780957(A) 780958(A). Figure 4-1. Memory (µPD780957(A))
FFFFH Special function registers (SFR) bits General-purpose registers bits Internal high-speed 1024 bits Reserved display bits Reserved
FF00H FEFFH FEE0H FEDFH FB00H FAFFH FA1EH FA1DH FA00H F9FFH Data memory space F800H F7FFH
F400H F3FFH C000H BFFFH
Internal expansion 1024 bits
BFFFH Program area 1000H 0FFFH CALLF entry area 0800H 07FFH Program area 0080H 007FH CALLT table area 0040H 003FH Vector table area
Reserved
Program memory space
Internal 49152 bits
0000H
0000H
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Figure 4-2. Memory (µPD780958(A))
FFFFH
FF00H FEFFH FEE0H FEDFH FB00H FAFFH FA1EH FA1DH FA00H F9FFH Data memory space F800H F7FFH
Special function registers (SFR) bits General-purpose registers bits Internal high-speed 1024 bits Reserved display bits Reserved
Internal expansion 1024 bits F400H F3FFH Reserved F000H EFFFH
EFFFH Program area 1000H 0FFFH CALLF entry area 0800H 07FFH Program area 0080H 007FH CALLT table area 0040H 003FH Vector table area
Program memory space
Internal 61440 bits
0000H
0000H
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
FEATURES PERIPHERAL HARDWARE FUNCTIONS
Ports
following types ports available. CMOS (Ports N-ch open-drain (P60 P62): Total: Table 5-1. Port Functions
Port Name Port Port Port Port Port Port Name Port Port Port Function port. Input/output specified 1-bit units. on-chip pull-up resistor specified software. port. Input/output specified 1-bit units. on-chip pull-up resistor specified software. port. Input/output specified 1-bit units. on-chip pull-up resistor specified software. port. Input/output specified 1-bit units. on-chip pull-up resistor specified software. port. Input/output specified 1-bit units. on-chip pull-up resistor specified software. N-ch open-drain port. Input/output specified 1-bit units. on-chip pull-up resistor specified mask option. port. Input/output specified 1-bit units. on-chip pull-up resistor specified software. port. Input/output specified 1-bit units. on-chip pull-up resistor specified software. port. Input/output specified 1-bit units. on-chip pull-up resistor specified software. port. Input/output specified 1-bit units. on-chip pull-up resistor specified software.
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Clock Generator
Three types generators, main system clock generator, subsystem clock generator subsystem clock generator, available. minimum instruction execution time changed. µs/4 µs/8 operation oscillation) with main system clock) 32.768 operation with subsystem clock Figure 5-1. Clock Generator Block Diagram
Subsystem clock oscillator Subsystem clock oscillator Main system clock oscillator Clock 16-bit timer/ event counter serial interfaces SIO3 UART, sampling function Clock output controller (CKU) Clock peripheral hardware Clock 8-bit timers Prescaler fXT1
fXT2
Prescaler
fXT1
Selector
STOP
Standby controller INTP0 sampling clock
clock (fCPU)
system clocks shown Table supplied peripheral hardware. Table 5-2. System Clock Supplied Each Peripheral Hardware
Peripheral Hardware Serial interface SIO3 Serial interface UART2 16-bit timer/event counter 16-bit timer/event counter 8-bit timer 8-bit timer 8-bit timer 8-bit timer Watchdog timer sampling function Sampling output timer/detector controller/driver Clock output controller Operates with subsystem clocks Operates with subsystem clock Operates with subsystem clock Operates with subsystem clock Operates with main system clock subsystem clock System Clock Operates with subsystem clocks
Remark
Main system clock: oscillation) Subsystem clock 32.768 Subsystem clock 4.91
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Timer
Seven timer channels incorporated. 16-bit timer/event counter: 8-bit timer: Watchdog timer: channels channels channel
following channels also used interval timers. Sampling output timer/detector: channels sampling function: channel Table 5-2. Timer Operation
16-Bit Timer/Event Counter Operation mode Interval timer External event counter Timer output output Pulse width measurement Square wave output Event input control function Interrupt sources channel channel output output inputs output 16-Bit Timer/Event Counter channel channel input
Note
8-Bit Timers channels
Watchdog Timer channel
Note
Sampling Output Timer/Detector
Sampling Function
Note
channelsNote channel output output
Function
Notes watchdog timer watchdog timer interval timer functions. However, watchdog timer selecting either watchdog timer function interval timer function. When used sampling output, interval timer invalid. When using sampling function, interval timer invalid. event input control function should used with 8-bit timer
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Figure 5-2. Block Diagram 16-Bit Timer/Event Counter
Internal
Selector
INTTM00
Selector
TI01/P30
Noise eliminator
16-bit timer capture/compare register (CR00) Match
Selector
fXT1 fXT1/2 fXT2/24
16-bit timer counter (TM0) Match
Clear Output controller TO0/TI00/P31
fXT1/22
Noise eliminator Noise eliminator 16-bit capture/compare register (CR01)
Selector
TI00/TO0/P31
INTTM01
Internal
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Figure 5-3. Block Diagram 16-Bit Timer/Event Counter
Internal Timer input control register (TICT2) TISL2 TIEN2 TM82 match signal Timer mode control register (TMC2)
TCE2 TCL21 TCL20
TI2/P32
fXT1 fXT1/23 fXT1/26 16-bit timer counter (TM2) Clear controller
Selector
Match INTTM2
16-bit timer compare register (CR2)
Internal
Figure 5-4. Block Diagram 8-bit Timers
fXT1
fXT1/22
Selector
fXT1/2
8-bit timer counter (TM8n)
Match
INTTM8n
8-bit compare register (CR8n)
TCE8n
TCL8n1 TCL8n0 8-bit timer control register (TMC8n) Internal
Caution count clocks figure above those 8-bit timers count clocks 8-bit timers refer Table 5-3. Remark
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Table 5-3. Count Clock Values 8-Bit Timers
8-Bit Timer fXT1 (30.5 fXT1/2 fXT1/2 (122
8-Bit Timer
8-Bit Timer fXT1/2 (3.9 fXT1/2 (15.6 fXT1/2 fXT1/2
8-Bit Timer fXT1 (30.5 fXT1/2 (244 fXT1/2 (1.95 fXT1/2 (15.6
(62.5 (0.25
Remarks Figures parentheses apply operation with fXT1 32.768 kHz. fCC: Main system clock oscillation frequency fXT1: Subsystem clock oscillation frequency Figure 5-5. Block Diagram Watchdog Timer
fXT1 fXT1/28 INTWDT RESET WDTOUT
Clock input controller
Divider fXT1/213 fXT1/219, fXT1/221
Divided clock selector
Output controller
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Sampling Output Timer/Detector
sampling output timer/detector function that outputs detects sampling pulse regular interval. there need activated unnecessary timing, such detection internal conditions (switch, etc.) meters, current consumption reduced. When sampling output used, 8-bit timer possible channels). Figure 5-6. Block Diagram Sampling Output Timer/Detector
SMTD compare register (CRSB0)
INTSB0 fXT1/22 fXT1/24 fXT1/26 Output controller SMO0/P33
Selector
fXT1
Input controller
SMTD timer counter (TMSB0)
SMTD compare register (CRSA0)
Selector
INTSA0 fXT1
Selector
fXT1/23 fXT1/210 fXT1/214
SMTD timer counter (TMSA0)
Prin
Enable control
Internal
SMP4/P25 SMP3/P24 SMP2/P23 SMP1/P22 SMP0/P05/INTP5/RxD20
SMD04 SMD03 SMD02 SMD01 SMD00
INTSMP4 INTSMP3 INTSMP2 INTSMP1 INTSMP0
SMS04
SMS03
SMS02
SMS01
SMS00
Internal
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Sampling Function
sampling function used drive sensor (magnetism sensor). When sampling output used, 8-bit timer possible channel). Figure 5-7. Block Diagram Sampling Function
Internal
MRTD compare register (CRM0)
INTMRT0 fXT1/23 fXT1/27 fXT2/24
Selector
fXT1
8-bit counter (TMMR0)
sampling control register (MRM0) MROE01 MROE00
Sampling generator
MRO0/P56 MRO1/P57
MRI0/P26
Sampling circuit
MRI1/P27
Sampling circuit
Edge detector
Phase discriminator
INTMRO0
MRD01 MRD00 sampling control register (MRM0) Internal
PRTY0
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Clock Output Controller
clock output controller (CKU) incorporated. Clocks with following frequencies output clock output. Hz/512 Hz/1.024 kHz/2.048 kHz/4.096 kHz/8.192 kHz/16.384 kHz/32.768 32.768 operation with subsystem clock Figure 5-8. Block Diagram Clock Output Controller
fXT1
Prescaler
fXT1-fXT1/27
Selector
Clock controller CLOE
PCL/P34
CLOE
CCS3
CCS2
CCS1
CCS0
Clock output selection register (CKS) Internal
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Serial Interfaces
serial interface channels incorporated. Serial interface UART2: channel (with switching function) Serial interface SIO3: Serial interface UART2 Serial interface UART2 operates asynchronous serial interface (UART) mode. Asynchronous serial interface (UART) mode This mode enables full-duplex operation wherein byte data transmitted received after start bit. on-chip dedicated UART baud rate generator enables communication using baud rates 32.768 operation with subsystem clock addition, using subsystem clock (4.91 operation) enables 2400 baud rate communication. channel
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Figure 5-9. Block Diagram Serial Interface UART2
Internal UART switching register (UTCH0) TSL2 Receive buffer register (RXB2) Asynchronous serial interface mode register (ASIM2) TXE2 RXE2 PS21 PS20 ISRM2 Asynchronous serial interface status register (ASIS2) OVE2 Transmit shift register (TXS2)
RxD20/P05/ INTP5/SMP0 RxD21/P06/ INTP6
Selector
Receive shift register (RX2)
TxD20/P20 TxD21/P21
Selector
Receive controller (parity check)
INTSR2
Transmit INTSER2 controller (parity add)
INTST2
Selector
8-bit baud rate generator/counter
fXT1 fXT1/28 fXT2/26
Prescaler (2-division) Compare register baud rate generator (BRCR2)
Asynchronous serial interface function register (ASIF2) TPS21TPS20 REV2 CL21 CL20
Internal
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Serial interface SIO3 Serial interface SIO3 operates 3-wire serial mode. 3-wire serial mode (fixed first) This 8-bit data transfer mode using three lines: serial clock line (SCK3), serial output line (SO3), serial input line (SI3). Since simultaneous transmit receive operations available 3-wire serial mode, processing time data transfer reduced. first 8-bit data serial transfer fixed MSB. 3-wire serial mode useful connection peripheral device that includes clocked serial interface, display controller, etc.
Figure 5-10. Block Diagram Serial Interface SIO3
Internal SI3/P35 Serial shift register (SIO3)
SO3/P36 SCK3/P37 Serial clock counter Serial clock controller Interrupt request signal generator INTCSI3 fXT2/210 fXT2/211 fXT1
Selector
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Controller/Driver Display mode: duty (1/3 bias), static mode segment signal outputs switched with port 1-bit units (P70/S8 P77/S15, P80/S16 P87/S23, P90/S24 P95/S29). Table 5-4. Maximum Number Display Pixels
Bias Method Time Division Common Signals Used COM0 COM2 Maximum Number Display Pixels segments commons)
controller/driver with following functions incorporated.
Figure 5-11. Block Diagram Controller/Driver
Internal Prescaler fXT1 fXT1 fXT1 fXT1 Timing controller Segment data memory Port output data LCDCL
Selector
fXT1
Display data memory
drive voltage generator Segment driver COM0 COM1 COM2 VLC1 VLC2 Common driver
S8/P70 S29/P95
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Real-Time Output Function
real-time output function function that transfers outputs externally data preset real-time output buffer registers output latch hardware upon generation timer interrupt (INTTM83). pins that output this data externally called real-time output port. Using real-time output port enables generation signals with jitter, making suitable control stepping motors, etc. Figure 5-12. Block Diagram Real-Time Output Function
Internal Real-time output buffer registers bits channels) RTO11 RTO11(L) RTO10 RTO10 Compare register (RTC1) Match
INTRTO1
INTTM83
count register
RTO1 output latch
RTO0/P64 RTO3/P67
ENA/P63 RCE1 FENA1 operation mode register (RTM1) Internal
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
INTERRUPT FUNCTIONS
total interrupt sources divided into following three types provided. Non-maskable: Maskable: Software: Table 6-1. Interrupt Source List (1/2)
Interrupt Type Default Note Priority Interrupt Source Name INTWDT INTWDT INTP0 INTMRO0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTTM00 Trigger Watchdog timer overflow (with nonmaskable interrupt selected) Watchdog timer overflow (with maskable interrupt selected) INTP0 input edge detection MRTD edge detection INTP1 input edge detection INTP2 input edge detection INTP3 input edge detection INTP4 input edge detection INTP5 input edge detection INTP6 input edge detection Generation matching signal CR00 (when compare register selected) TI01 valid edge detection (when capture register selected) Generation matching signal CR01 (when compare register selected) TI00 valid edge detection (when capture register selected) Occurrence serial interface UART2 reception error serial interface UART2 reception serial interface UART2 transmission serial interface SIO3 transfer Generation matching signal MRTD timer compare register Generation matching signal TM80 CR80 Generation matching signal TM81 CR81 Internal External Internal External 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H Internal/ External Internal Vector Table Address 0004H Basic Configuration Note Type
Non-maskable Maskable
INTTM01
0018H
INTSER2 INTSR2 INTST2 INTCSI3 INTMRT0 INTTM80 INTTM81
001AH 001CH 001EH 0020H 0022H 0024H 0026H
Notes Default priority priority order when several maskable interrupt requests generated same time. highest lowest. Basic configuration types correspond Figure 6-1. Remark watchdog timer interrupt sources (INTWDT): non-maskable interrupt maskable interrupt (internal), available, either which selected.
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Table 6-1. Interrupt Source List (2/2)
Interrupt Type Default Note Priority Interrupt Source Name INTTM82 INTTM83 INTTM2 INTSA0 Trigger Generation matching signal TM82 CR82 Generation matching signal TM83 CR83 Generation matching signal Generation matching signal Sampling timer compare register (CRSA0) Generation matching signal sampling timer compare register (CRSB0) Achievement reload count specified real-time output Sampling interrupt input Sampling interrupt input Sampling interrupt input Sampling interrupt input Sampling interrupt input Execution instruction External Internal/ External Internal Vector Table Address 0028H 002AH 002CH 002EH Basic Configuration Note Type
Maskable
INTSB0
0030H
Software
INTRTO1 INTSMP0 INTSMP1 INTSMP2 INTSMP3 INSMP4
0032H 0034H 0036H 0038H 003AH 003CH 003EH
Notes Default priority priority order when several maskable interrupt requests generated same time. highest order lowest order. Basic configuration types correspond Figure 6-1.
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Figure 6-1. Basic Configuration Interrupt Function (1/2) Internal non-maskable interrupt
Internal
Interrupt request
Priority controller
Vector table address generator
Standby release signal
Internal maskable interrupt
Internal
Interrupt request
Priority controller
Vector table address generator
Standby release signal
External maskable interrupt (INTP0 INTP6)
Internal
External interrupt edge enable register (EGP, EGN)
Interrupt request
Edge detector
Priority controller
Vector table address generator
Standby release signal
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Figure 6-1. Basic Configuration Interrupt Function (2/2) Software interrupt
Internal
Interrupt request
Priority controller
Vector table address generator
Interrupt request flag Interrupt enable flag
ISP: In-service priority flag Interrupt mask flag Priority specification flag
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
STANDBY FUNCTION
following standby function available further reduction system current consumption. HALT mode: this mode, operation clock stopped. average current consumption reduced intermittent operation combining this mode with normal operation mode. Caution STOP mode supported. Figure 7-1. Standby Function
Main system clock operation Subsystem clock operation
Interrupt request
HALT instruction
Interrupt request
HALT instruction
HALT mode Clock supply halted, oscillation maintained
HALT mode Clock supply halted, oscillation maintained
RESET FUNCTION
following reset methods available. External reset RESET Internal reset watchdog timer runaway time detection
MASK OPTION
mask option used specify connection on-chip pull-up resistor RESET pin, 1-bit units.
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
INSTRUCTION
8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
operand operand #byte
Note
saddr
!addr1 ADDC SUBC
[DE]
[HL]
[HL+byte [HL+B] [HL+C] $addr16
None
ADDC SUBC
ADDC SUBC ADDC SUBC
ADDC SUBC
ADDC SUBC
ADDC SUBC
RORC ROLC
saddr ADDC SUBC
DBNZ
DBNZ
!addr16 [DE] [HL] [HL+byte] [HL+B] [HL+C]
ROR4 ROL4 PUSH
MULU DIVUW
Note Except
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
operand operand
#word ADDW SUBW CMPW
rpNote MOVW XCHW
sfrp MOVW
saddrp MOVW
!addr16 MOVW
MOVW
None
MOVW
MOVW
Note
INCW, DECW PUSH,
sfrp saddrp !addr16
MOVW MOVW MOVW
MOVW MOVW MOVW MOVW
Note Only when manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BTCLR
operand operand A.bit
A.bit
sfr.bit
saddr.bit
PSW.bit
[HL].bit
MOV1
$addr16 BTCLR
None SET1 CLR1
sfr.bit
MOV1
BTCLR
SET1 CLR1
saddr.bit
MOV1
BTCLR
SET1 CLR1
PSW.bit
MOV1
BTCLR
SET1 CLR1
[HL].bit
MOV1
BTCLR
SET1 CLR1 SET1 CLR1 NOT1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Call instructions/branch instructions CALL, CALLF, CALLT, BNC, BNZ, BTCLR, DBNZ
operand operand Basic instruction Compound instruction
!addr16 CALL
!addr11 CALLF
[addr5] CALLT
$addr16 BTCLR, DBNZ
Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, HALT
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings 25°C)
Parameter Power supply voltage Input voltage Symbol P06, P27, P37, P47, P57, P67, P77, P87, P95, XT1, XT2, RESET N-ch open drain With pull-up resistor Output voltage Output current, high Output current, Operating ambient temperature Storage temperature Tstg Total pins Total pins Conditions Ratings -0.3 +3.6 -0.3
Note
Unit
-0.3 +3.6 -0.3 +150
Note
-0.3
Note below Caution Product quality suffer absolute maximum rating exceeded even momentarily parameter. That absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions that ensure that absolute maximum ratings exceeded. Remark Unless specified otherwise, characteristics alternate-function pins same those port pins.
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Main System Clock Oscillator Characteristics +80°C,
Resonator resonator Parameter Oscillation frequency (fCC)
Note
Conditions
MIN.
TYP.
MAX.
Unit
Note Indicates only oscillator characteristics. (capacitor) (resistor) error included. instruction execution time, refer Characteristics. Subsystem Clock Oscillator Characteristics +80°C,
Resonator Crystal resonator Parameter Oscillation frequency (fXT1)
Note Note
Conditions
MIN.
TYP. 32.768
MAX.
Unit
Oscillation stabilization time
Notes Indicates only oscillator characteristics. instruction execution time, refer Characteristics. Time required stabilize oscillation after reset. Make sure RESET holds level during this period. Subsystem Clock Oscillator Characteristics +80°C,
Resonator Crystal resonator External clock Oscillation frequency (fXT2)
Note Note
Parameter
MIN.
TYP.
MAX.
Unit
Oscillation stabilization time input frequency (fXT2)
input high-/low-level width (tXT2H, tXT2L)
Notes Indicates only oscillator characteristics. instruction execution time, refer Characteristics. Time required stabilize oscillation after reset. Recommended Oscillator Constant Subsystem Clock Ceramic resonator +85°C)
Manufacturer Part Number Frequency (kHz) Recommended Circuit Constant Seiko Epson Inc. C-002RX MC-206 MC-306 32.768 Oscillation voltage Range MIN.(V) MAX.(V) Remark
Caution oscillator constant oscillation voltage range indicate conditions stable oscillation. Oscillation frequency precision guaranteed. applications requiring oscillation frequency precision, oscillation frequency must adjusted implementation circuit. details, contact directly manufacturer resonator used.
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Characteristics +80°C,
Parameter Output current, high Output current, Input voltage, high Symbol VIH1 VIH2 VIH3 Input voltage, VIL1 VIL2 VIL3 Output voltage, high VOH1 pins pins P20, P21, P33, P34, P36, P47, P57, P67, P77, P87, P06, P27, P32, P35, P37, RESET XT3, P20, P21, P33, P34, P36, P47, P57, P67, P77, P87, P06, P27, P32, P35, P37, RESET XT3, -400 P06, P27, P37, P47, P54, P67, P77, P87, (N-ch open drain) P06, P27, P37, P47, P57, P67, P77, P87, P95, WDTOUT +60°C +60°C +60°C
Note Note
Conditions
MIN.
TYP.
MAX.
Unit
0.7VDD 0.8VDD
0.3VDD 0.2VDD
P56/MRO0, P57/MRO1
Output voltage,
VOL1
Power supply Note current
IDD1 IDD2 IDD3
oscillation Note operation mode 32.768 crystal oscillation Note operation mode 32.768 crystal oscillation Note HALT mode
12.0 18.0
+80°C +80°C +80°C
Note Note
Note Note
Subsystem clock oscillation current
ISUB2
(When subsystem clock oscillation enabled)
Notes Refers current flowing through VDD0 VDD1 pins. controller ports included. When 00H. When main system clock stopped.
current flowing through
Only during access (when subsystem clock oscillation peripheral functions stopped.) During access when peripheral functions operating when operation subsystem clock oscillation stopped.) When only sampling output timer/detector 8-bit timers operating when subsystem clock oscillation stopped.) When peripheral functions operating when operation subsystem clock oscillation stopped.) Remark Unless specified otherwise, characteristics alternate-function pins same those port pins.
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Characteristics +80°C,
Parameter Input leakage current, high Symbol ILIH1 ILIH2 Conditions XT1, XT2, XT3, P06, P27, P37, P47, P57, P67, P77, P87, P95, RESET XT1, XT2, XT3, XT4, (Other than when reading) P06, P27, P37, P47, P57, P67, P77, P87, P95, RESET VOUT VOUT RESET P06, P27, P37, P47, P57, P67, P77, P87, MIN. TYP. 0.03 MAX. Unit
Input leakage current,
ILIL1 ILIL2
-0.7 -0.03
Output leakage current, high Output leakage current, Mask option pull-up resistor Software pull-up resistor
ILOH ILOL
0.03 -0.03
Remark
Unless specified otherwise, characteristics alternate-function pins same those port pins.
Controller/Driver Characteristics +80°C,
Parameter drive voltage Power boosting time capacitor Note drive output voltage deviation Note (common) output voltage deviation Note (segment) Symbol VLCD tVCLD VLCD 0.47
Note
Conditions
MIN.
TYP.
MAX.
Unit
VODC
Static bias method
±0.2
VODS
Static bias method
±0.2
Notes Means time required capacitor boost after (LIP0) mode register (LCDM0) (power supply drive). capacitor connected VLC1 VLC2 between CAPH CAPL. power deviation difference between ideal segment common output values (VLCD1, VLCD2) output voltage. Voltage when there load.
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Characteristics Basic operation +80°C,
Parameter Cycle time (Minimum instruction execution time) TI00, TI01, input high/low-level width input frequency input high-/lowlevel width Interrupt input high/low-level width RESET input low-level width WDTOUT output lowlevel width Symbol Conditions Main system clock operation Subsystem clock operation tTIH0, tTIL0 fTI2 tTIH2, tTIL2 tINTH, tINTL tRSL tWDTL INTP0 INTP6 MIN. 1.33 57.1 2/fsam Note TYP. MAX. 62.5 Unit
Note each capture trigger, sampling performed with count clock selected bits (PRM00, PRM01) prescaler mode register (PRM0) (fsam fXT1, fXT1/2, fXT2/24). However, TI00 valid edge selected count clock, value becomes fsam fXT1/4. Timing Test Points (excluding inputs)
Test points
Clock Timing
1/fCC
input
1/fXT1, tXTL1, tXTH1,
XT1, inputs
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Timing
tTIL0 tTIH0
TI00, TI01
1/fTI2 tTIL2 tTIH2
Interrupt Request Input Timing
tINTL tINTH
INTP0 INTP6
RESET Input Timing
tRSL
RESET
WDTOUT Output Timing
tWDTL
WDTOUT
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Sampling output timer/detector
Parameter Sampling input setup time Sampling input hold time Symbol tSMPS tSMPH Conditions MIN. TYP. MAX. Unit
Sampling output timer/detector input timing
SMO0 tSMPS SMPn tSMPH
sampling function
Parameter Phase detection input setup time Phase detection input hold time Symbol tMRIS tMRIH Conditions MIN. TYP. MAX. Unit
sampling function input timing
MROn tMRIS MRIn tMRIH
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Serial interface UART mode (dedicated baud rate generator output)
Parameter Transfer rate
Symbol
Conditions Select subsystem clock input clock baud rate generator (ASIF2 TPS21 TPS20 Select subsystem clock input clock baud rate generator (ASIF2 TPS21 TPS20
MIN.
TYP.
MAX. 1200 4800
Unit
Remark
ASIF2: Asynchronous serial interface function register
3-wire serial mode (internal clock output)
Parameter SCK3 cycle time SCK3 high-/low-level width setup time SCK3) hold time (from SCK3) Delay time from SCK3 output
Symbol tKCY1 tKH1, tKL1 tSIK1 tKSI1 tKSO1
Note
Conditions
MIN. 30.5 tKCY1/2
TYP.
MAX.
Unit
Note load capacitance SCK3 output lines. 3-wire serial mode (external clock input)
Parameter SCK3 cycle time SCK3 high-/low-level width setup time SCK3) hold time (from SCK3) Delay time from SCK3 output
Symbol tKCY2 tKH2, tKL2 tSIK2 tKSI2 tKSO2
Note
Conditions
MIN. 1600
TYP.
MAX.
Unit
Note load capacitance output line.
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Serial Transfer Timing
3-wire serial mode:
tKCYm tKLm tKHm
SCK3
tSIKm
tKSIm
Input data
tKSOm
Output data
Remark
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
PACKAGE DRAWING
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
detail lead
NOTE Each lead centerline located within 0.08 true position (T.P.) maximum material condition.
ITEM
MILLIMETERS 16.00±0.20 14.00±0.20 14.00±0.20 16.00±0.20 1.00 1.00 0.22 +0.05 -0.04 0.08 0.50 (T.P.) 1.00±0.20 0.50±0.20 0.17 +0.03 -0.07 0.08 1.40±0.05 0.10±0.05 1.60 MAX.
S100GC-50-8EU, 8EA-2
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
RECOMMENDED SOLDERING CONDITIONS
µPD780957(A) 780958(A) should soldered mounted under following recommended conditions. details recommended soldering conditions, refer document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended below, contact sales representative. Table 13-1. Surface Mounting Type Soldering Conditions 100-pin plastic LQFP (fine pitch) 100-pin plastic LQFP (fine pitch)
Soldering Method Infrared reflow Partial heating Soldering Conditions Package peak temperature: 235°C, Time: sec. max. 210°C higher), Count: times less Package peak temperature: 215°C, Time: sec. max. 200°C higher), Count: times less temperature: 300°C max., Time: sec. max. (per row) Recommended Condition Symbol IR35-00-2 VP15-00-2
Caution
different soldering methods together (except partial heating).
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
APPENDIX DEVELOPMENT TOOLS
following development tools available system development using µPD780958 Subseries. Also refer Cautions Using Development Tools. Language Processing Software
RA78K0 CC78K0 DF780958 CC78K0-L Assembler package common 78K/0 Series compiler package common 78K/0 Series Device file µPD780958 Subseries compiler library source file common 78K/0 Series
Debugging Tools When IE-78K0-NS in-circuit emulator used
IE-78K0-NS IE-70000-MC-PS-B IE-78K0-NS-PA IE-70000-98-IF-C IE-70000-CD-IF-A IE-70000-PC-IF-C IE-70000-PCI-IF-A IE-780958-NS-EM4 IE-78K0-NS-P02 NP-100GC TGC-100SDW ID78K0-NS SM78K0 DF780958 In-circuit emulator common 78K/0 Series Power supply unit IE-78K0-NS Performance board enhance expand functions IE-78K0-NS Adapter necessary when using PC-9800 series (except notebook type) host machine supported) card interface cable necessary when using notebook host machine (PCMCIA socket supported) Adapter necessary when using PC/AT
compatible host machine (ISA supported)
Adapter necessary when using which incorporated host machine Emulation board emulate µPD780958 Subseries board emulate µPD780958 Subseries Emulation probe 100-pin plastic LQFP (fine pitch) (GC-8EU type) Conversion adapter connect NP-100GC target system board which 100-pin plastic LQFP (fine pitch) (GC-8EU type) mounted Integrated debugger IE-78K0-NS System simulator common 78K/0 Series Device file µPD780958 Subseries
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
When IE-78001-R-A in-circuit emulator used
IE-78001-R-A IE-70000-98-IF-C IE-70000-PC-IF-C IE-70000-PCI-IF-A IE-78000-R-SV3 IE-780958-NS-EM4 IE-78K0-NS-P02 IE-78K0-R-EX1 EP-78064GC-R TGC-100SDW ID78K0 SM78K0 DF780958 In-circuit emulator common 78K/0 Series Adapter necessary when using PC-9800 series (except notebook type) host machine supported) Adapter necessary when using PC/AT compatibles host machine (ISA supported) Adapter necessary when using which incorporated host machine Interface adapter cable necessary when using host machine Probe board emulate µPD780958 Subseries board necessary emulate µPD780958 Subseries Emulation probe conversion board necessary when using IE-780958-NS-EM4+IE-78K0-NS-P02 IE-78001-R-A Emulation probe 100-pin plastic LQFP (fine pitch) (GC-8EU type) Adapter mounted target system board made 100-pin plastic LQFP (fine pitch) (GC-8EU type) Integrated debugger IE-78001-R-A System simulator common 78K/0 Series Device file µPD780958 Subseries
Real-time
RX78K0 MX78K0 Real-time 78K/0 Series 78K/0 Series
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Cautions Using Development Tools ID78K0-NS, ID78K0, SM78K0 used combination with DF780958. CC78K0 RX78K0 used combination with RA78K0 DF780958. NP-100GC product made Naito Densei Machidas Mfg. Co., Ltd. (TEL +81-44-822-3813). TGC-100SDW product made TOKYO ELETECH CORPORATION. further information, contact: Daimaru Kogyo, Ltd. Tokyo Electronics Department (TEL +81-3-3820-7112) Osaka Electronics Department (TEL +81-6-6244-6672) TGC-100SDW sold single units. third party development tools, Single-Chip Microcontroller Development Tools Selection Guide (U11069E). host machine suitable each software follows:
Host Machine [OS] Software RA78K0 CC78K0 ID78K0-NS ID78K0 SM78K0 RX78K0 MX78K0 PC-9800 series [Japanese Windows PC/AT compatibles [Japanese/English Windows]
Note Note
HP9000 series [HP-UX SPARCstation [SunOS Solaris NEWS (RISC) [NEWS-OS
Note Note
Note DOS-based software
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
APPENDIX RELATED DOCUMENTS
related documents indicated this publication include preliminary versions. versions marked such. Documents Related Devices
Document Name Document U13655E This document U12326E
However, preliminary
µPD780958 Subseries User's Manual µPD780957(A), 780958(A) Data Sheet
78K/0 Series User's Manual Instructions
Documents Related Development Tools (User's Manuals)
Document Name RA78K0 Assembler Package Operation Language Structured Assembly Language CC78K0 Compiler Operation Language IE-78K0-NS In-Circuit Emulator IE-78001-R-A In-Circuit Emulator IE-780958-NS-EM4 Emulation Board EP-78064 Emulation Probe SM78K0S, SM78K0 System Simulator Ver. 2.10 Later Windows Based SM78K Series System Simulator Ver. 2.10 Later ID78K0-NS Integrated Debugger Ver. 2.00 Later Windows Based ID78K0-NS, ID78K0S-NS Integrated Debugger Ver. 2.20 Later Windows Based ID78K0 Integrated Debugger Windows Based Operation External Part User Open Interface Specifications Operation Operation Reference Guide Document U11802E U11801E U11789E U11517E U11518E U13731E prepared prepared EEU-1469 U14611E U15006E U14379E U14910E U11539E U11649E
Caution
related documents listed above subject change without notice. sure latest version each document designing.
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Documents Related Embedded Software (User's Manuals)
Document Name 78K/0 Series Real-Time Fundamental Installation 78K/0 Series MX78K0 Fundamental Document U11537E U11536E U12257E
Other Related Documents
Document Name SEMICONDUCTOR SELECTION GUIDE Products Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades Semiconductor Devices Semiconductor Device Reliability/Quality Control System Guide Prevent Damage Semiconductor Devices Electrostatic Discharge (ESD) Document X13769X C10535E C11531E C10983E C11892E
Caution
related documents listed above subject change without notice. sure latest version each document designing.
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
[MEMO]
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
IEBus trademarks Corporation. Windows either registered trademark trademark Microsoft Corporation United States and/or other countries. PC/AT trademark International Business Machines Corporation. HP9000 series HP-UX trademarks Hewlett-Packard Company. SPARCstation trademark SPARC International, Inc. Solaris SunOS trademarks Microsystems, Inc. NEWS NEWS-OS trademarks Sony Corporation.
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
Regional Information
Some information contained this document vary from country country. Before using product your application, pIease contact office your country obtain list authorized representatives distributors. They will verify:
Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements
addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 Fax: 01-30-67 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics (France) S.A. Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
Electronics Singapore Pte. Ltd.
United Square, Singapore Tel: 65-253-8311 Fax: 65-250-3583
Electronics Taiwan Ltd. Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
Brasil S.A.
Electron Devices Division Guarulhos-SP Brasil Tel: 55-11-6462-6810 Fax: 55-11-6462-6829
J00.7
Data Sheet U13739EJ1V0DS
µPD780957(A), 780958(A)
export this product from Japan regulated Japanese government. export this product prohibited without governmental license, need which must judged customer. export re-export this product from country other than Japan also prohibited without license from that country. Please call sales representative.
information this document current December, 2000. information subject change without notice. actual design-in, refer latest publications NEC's data sheets data books, etc., most up-to-date specifications semiconductor products. products and/or types available every country. Please check with sales representative availability additional information. part this document copied reproduced form means without prior written consent NEC. assumes responsibility errors that appear this document. does assume liability infringement patents, copyrights other intellectual property rights third parties arising from semiconductor products listed this document other liability arising from such products. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. assumes responsibility losses incurred customers third parties arising from these circuits, software information. While endeavours enhance quality, reliability safety semiconductor products, customers agree acknowledge that possibility defects thereof cannot eliminated entirely. minimize risks damage property injury (including death) persons arising from defects semiconductor products, customers must incorporate sufficient safety measures their design, such redundancy, fire-containment, anti-failure features. semiconductor products classified into following three quality grades: "Standard", "Special" "Specific". "Specific" quality grade applies only semiconductor products developed based customer-designated "quality assurance program" specific application. recommended applications semiconductor product depend quality grade, indicated below. Customers must check quality grade each semiconductor product before using particular application. "Standard": Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade semiconductor products "Standard" unless otherwise expressly specified NEC's data sheets data books, etc. customers wish semiconductor products applications intended NEC, they must contact sales representative advance determine NEC's willingness support given application. (Note) "NEC" used this statement means Corporation also includes majority-owned subsidiaries. "NEC semiconductor products" means semiconductor product developed manufactured defined above).

µPD780957(A), 780958(A) 8-BIT SINGLE-CHIP MICROCONTROLLERS D

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