µPD780833Y 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION

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µPD780833Y 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION

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INTEGRATED CIRCUIT
µPD780833Y
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
µPD780833Y member µPD780833Y Subseries 78K/0 Series, incorporates rich lineup peripheral hardware, including J1850 (CLASS2) controller, converter, timer, serial interface, interrupt controller. flash memory version, µPD78F0833Y, various development tools also available. Detailed function descriptions provided following user's manuals. sure read them before designing.
µPD780833Y Subseries User's Manual:
U13892E
78K/0 Series User's Manual Instructions: U12326E
FEATURES
On-chip J1850 (CLASS2) controller On-chip
Item Program Memory Internal Part Number Data Memory Internal HighSpeed 1024 bytes Internal Expansion 2048 bytes 80-pin plastic Package
µPD780833Y
Minimum instruction execution time changed from high speed (0.48 speed (7.68 ports: (N-ch open-drain: input/CMOS output: 8-bit resolution converter: channels Serial interface: channels Timer: channels Power supply voltage:
APPLICATIONS
audios, etc.
information this document subject change without notice. Before using this document, please confirm that this latest version. devices/types available every country. Please check with local representative availability additional information. Document U15012EJ1V0DS00 (1st edition) Date Published January 2001 CP(K) Printed Japan
2001
µPD780833Y
ORDERING INFORMATION
Part Number Package 80-pin plastic
Remark indicates code suffix.
Data Sheet U15012EJ1V0DS
µPD780833Y
78K/0 SERIES LINEUP
products 78K/0 Series listed below. names enclosed boxes subseries names.
Products mass production Products under development subseries products support bus. Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin
PD78075B PD78078 PD78070A PD780058 PD78058F µPD78054 µPD780065 PD780078
EMI-noise reduced version µPD78078
µPD78078Y PD78070AY PD780018AY PD780058Y PD78058FY PD78054Y
µPD78054 with added timer enhanced external interface
ROMless version µPD78078 µPD78078Y with enhanced serial limited functions
µPD78054 with enhanced serial
EMI-noise reduced version PD78054
PD780034A PD780024A µPD78014H µPD78018F PD78083
Inverter control
µPD78018F with added UART converter enhanced µPD780024A with increased capacity PD780034A with added timer enhanced serial PD780078Y PD780034AY µPD780024A with enhanced converter PD780024AY µPD78018F with enhanced serial EMI-noise reduced version PD78018F
PD78018FY
Basic subseries control On-chip UART, capable operating voltage (1.8
64-pin
µPD780988
drive
On-chip inverter controller UART. Reduced noise.
100-pin 78K/0 Series 80-pin 80-pin 80-pin
PD780208 PD780232 µPD78044H µPD78044F
drive
µPD78044F with enhanced C/D. Display output total:
panel control. On-chip C/D. Display output total:
µPD78044F with added N-ch open-drain I/O. Display output total: Basic subseries driving VFD. Display output total:
120-pin 120-pin 120-pin 100-pin 100-pin 100-pin
PD780338 PD780328 µPD780318 PD780308 µPD78064B µPD78064
PD780308 with enhanced display function timer. Segment signal output: pins max. PD780308 with enhanced display function timer. Segment signal output: pins max. PD780308 with enhanced display function timer. Segment signal output: pins max. µPD780308Y PD78064Y PD78064 with enhanced SIO, increased ROM, capacity EMI-noise reduced version PD78064
Basic subseries driving LCDs, on-chip UART
interface supported 100-pin 80-pin 80-pin 80-pin Meter control 100-pin 80-pin 80-pin
PD780948 PD78098B PD780701Y PD780833Y
On-chip D-CAN controller µPD78054 with added IEBuscontroller. Reduced noise. On-chip D-CAN/IEBus controller On-chip controller compliant with J1850 (CLASS2)
µPD780958 µPD780852 µPD780824
industrial meter control On-chip automobile meter controller/driver automobile meter driver. On-chip D-CAN controller
Remark (Vacuum Fluorescent Display) referred FIP(Fluorescent Indicator Panel) some documents, functions same.
Data Sheet U15012EJ1V0DS
µPD780833Y
major functional differences among subseries shown below.
Function Subseries Name Control Capacity Timer 8-Bit 10-Bit 8-Bit (UART: I2C: (I2C: Serial Interface External
8-Bit 16-Bit Watch
MIN. Value Expansion
µPD78078Y µPD78070AY
µPD780018AY µPD780058Y µPD78058FY µPD78054Y µPD780078Y
(Time division UART: I2C: (UART: I2C: (UART: I2C: (UART: I2C:
µPD780034AY µPD780024AY µPD78018FY
drive
(I2C:
µPD780308Y µPD78064Y
(Time division UART: I2C: (UART: I2C:
µPD780701Y interface supported µPD780833Y
(UART: I2C:
Data Sheet U15012EJ1V0DS
µPD780833Y
FUNCTION OVERVIEW
Item Internal memory High-speed Expansion Memory space General-purpose registers Minimum instruction execution time 1024 bytes 2048 bytes bits registers bits registers banks) On-chip variable function minimum instruction execution time 0.48 µs/0.96 µs/1.92 µs/3.84 µs/7.68 (@4.19 operation) 16-bit operation Multiply/divide bits bits,16 bits bits) manipulation (set, reset, test, Boolean operation) adjust, etc.
µPD780833Y
Instruction
ports
Total:
CMOS input: input/CMOS output: N-ch open-drain I/O: converter Serial interface 8-bit resolution channels 3-wire serial mode: channels UART mode: channel mode: channel 16-bit timer/event counter: 8-bit timer/event counter: Watch timer: Watchdog timer: channels channels channel channel
Timer
Timer outputs Clock output
(8-bit output capable: 32.8 kHz, 65.5 kHz, 130.9 kHz, 261.9 kHz, 523.6 kHz, 1.05 MHz, 2.10 MHz, 4.19 (@4.19 operation with system clock) interface compliant with J1850 (CLASS2) Maskable Non-maskable Software Internal: external: Internal: +85°C 80-pin plastic
controller Vectored interrupt source
Power supply voltage Operating ambient temperature Package
Data Sheet U15012EJ1V0DS
µPD780833Y
CONTENTS CONFIGURATION (TOP VIEW) BLOCK DIAGRAM FUNCTIONS Port Pins Non-Port Pins Circuits Recommended Connection Unused Pins.
MEMORY SPACE PERIPHERAL HARDWARE FUNCTION FEATURES Ports Clock Generator Timer Clock Output Controller Converter Serial Interface J1850 (CLASS2) Controller
INTERRUPT FUNCTIONS STANDBY FUNCTIONS RESET FUNCTIONS INSTRUCTION ELECTRICAL SPECIFICATIONS PACKAGE DRAWING RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTS
Data Sheet U15012EJ1V0DS
µPD780833Y
CONFIGURATION (TOP VIEW)
80-pin plastic
AVSS0 P97/ANI70 P96/ANI60 P95/ANI50 P94/ANI40 P93/ANI30 P92/ANI20 P91/ANI10 P90/ANI00 AVREF0 AVDD0 VDD1 VSS1 RESET C2TX C2RX
P70/PCL P71/SDA0 P72/SCL0 P73/TO01 P74/TI001 P75/TI011 P00/INTP0 P01/INTP1 P02/INTP2 P03/INTP3 AVREF1 P80/ANI01 P81/ANI11 P82/ANI21 P83/ANI31 P84/ANI41 P85/ANI51 P86/ANI61 P87/ANI71 AVSS1 P27/TI51/TO51 P26/ASCK0/TI52/TO52 P25/TxD0 P24/RxD0 P23/TI50/TO50 P07/INTP7 P06/INTP6 P05/INTP5 P04/INTP4 P22/SCK31 P21/SO31 P20/SI31
Cautions Connect (Internally Connected) directly VSS0 VSS1. Connect AVDD0 VDD0. Connect AVSS0 AVSS1 pins VSS0.
P30/SI30 P31/SO30 P32/SCK30 VDD0 VSS0 P34/TO00 P35/TI000 P36/TI010
Data Sheet U15012EJ1V0DS
µPD780833Y
ANI00 ANI70,: ANI01 ANI71 ASCK: AVDD0: AVREF0, AVREF1: AVSS0, AVSS1: C2RX: C2TX: INTP0 INTP7: P07: P27: P36: P47: P57: P67: P75: P87: Asynchronous serial clock Analog power supply Analog reference voltage Analog ground CLASS2 receive data CLASS2 transmit data Internally connected External interrupt input Port Port Port Port Port Port Port Port Analog input P97: PCL: RxD0: RESET: SCK30, SCK31: SCL0: SDA0: SI30, SI31: SO30, SO31: TI000, TI010, TI001,: TI011, TI50, TI51, TI52 TO00, TO01, TO50,: TO51, TO52 TxD0: VDD0, VDD1: VSS0, VSS1: Transmit data Power supply Ground Crystal Timer output Port Programmable clock Receive data Reset Serial clock Serial clock Serial data Serial input Serial output Timer input
Data Sheet U15012EJ1V0DS
µPD780833Y
BLOCK DIAGRAM
TO00/P34 TI000/P35 TI010/P36 TO01/P73 TI001/P74 TI011/P75 Port 8-bit timer/ event counter 16-bit timer/ event counter Port
16-bit timer/ event counter
TI50/TO50/P23
TI51/TO51/P27
8-bit timer/ event counter
Port
TI52/TO52/P26
8-bit timer/ event counter Port
Watchdog timer 78K/0 core Watch timer SI30/P30 SO30/P31 SCK30/P32 SI31/P20 SO31/P21 SCK31/P22 RxD0/P24 TxD0/P25 ASCK0/P26 SDA0/P71 SCL0/P72 ANI00/P90 ANI70/P97 AVDD0 AVSS0 AVREF0 ANI01/P80 ANI71/P87 AVSS1 AVREF1 C2RX C2TX INTP0/P00 INTP7/P07 PCL/P70 Port
Serial interface
Serial interface
UART0
Internal high-speed 1024 bytes
Internal expansion 2048 bytes
Port
Port
converter Port
converter
J1850 (CLASS2) Interrupt control Clock output control VDD0 VDD1 VSS0 VSS1
Port
System control
RESET
Data Sheet U15012EJ1V0DS
µPD780833Y
FUNCTIONS Port Pins (1/2)
Name Function Port 8-bit port Input/output specified 1-bit units. on-chip pull-up resistor specified means software. Port 8-bit port Input/output specified 1-bit units. on-chip pull-up resistor specified means software. After Reset Alternate Function Input INTP0 INTP7
Input
SI31 SO31 SCK31 TI50/TO50 RxD0 TxD0 ASCK0/TI52/TO52 TI51/TO51
Port 7-bit port Input/output specified 1-bit units.
on-chip pull-up resistor specified means software.
Input
SI30 SO30 SCK30
N-ch open-drain port LEDs driven directly. on-chip pull-up resistor specified means software. TO00 TI000 TI010 Port 8-bit port Input/output specified 1-bit units. on-chip pull-up resistor specified means software. interrupt request flag (KRIF) falling edge detection. Port 8-bit port level input/CMOS output Input/output specified 1-bit units. on-chip pull-up resistor specified means software. Port 4-bit port Input/output specified 1-bit units. on-chip pull-up resistor specified means software. Input
Input
Input
Data Sheet U15012EJ1V0DS
µPD780833Y
Port Pins (2/2)
Name Port 6-bit port Input/output specified 1-bit units. Function on-chip pull-up resistor specified means software. N-ch open-drain port After Reset Alternate Function Input
SDA0 SCL0
on-chip pull-up resistor specified means software.
TO01 TI001 TI011
Port 8-bit port Input/output specified 1-bit units. Port 8-bit port Input/output specified 1-bit units.
Input
ANI01 ANI71
Input
ANI00 ANI70
Non-Port Pins (1/2)
Name INTP0 INTP7 SI30 SI31 SO30 SO31 SDA0 SCK30 SCK31 SCL0 RxD0 TxD0 ASCK0 TI000 Input Output Input Input Output Input Function External interrupt request input which valid edge (rising edge, falling edge, both rising falling edges) specified Serial interface SIO30 serial data input Serial interface SIO31 serial data input Serial interface SIO30 serial data output Serial interface SIO31 serial data output Serial interface IIC0 serial data input/output Serial interface SIO30 serial clock input/output Serial interface SIO31 serial clock input/output Serial interface IIC0 serial clock input/output Serial data input asynchronous serial interface Serial data output asynchronous serial interface Serial clock input asynchronous serial interface External count clock input 16-bit timer/event counter Capture trigger input capture register (CR000 CR010) 16-bit timer/event counter Capture trigger input capture register (CR000) 16-bit timer/ event counter External count clock input 16-bit timer/event counter Capture trigger input capture register (CR001 CR011) 16-bit timer/event counter Capture trigger input capture register (CR001) 16-bit timer/ event counter External count clock input 8-bit timer/event counter External count clock input 8-bit timer/event counter External count clock input 8-bit timer/event counter Input Input Input Input Input Input Input After Reset Alternate Function Input
Input
Input
P26/TI52/TO52
TI010
TI001
TI011
TI50 TI51 TI52
P23/TO50 P27/TO51 P26/ASCK0/TO52
Data Sheet U15012EJ1V0DS
µPD780833Y
Non-Port Pins (2/2)
Name TO00 TO01 TO50 TO51 TO52 ANI00 ANI70 ANI01 ANI71 AVREF0 AVREF1 converter (AD00) reference voltage input converter (AD01) analog power supply reference voltage input AVDD0 AVSS0 converter (AD00) analog power supply converter (AD00) ground potential. same potential that VSS0 VSS1. converter (AD01) ground potential. same potential that VSS0 VSS1. Input Output Input Input Positive power supply ports Positive power supply (except ports) Ground potential ports Ground potential (except ports) Internally connected. Connect directly VSS0 VSS1. CLASS2 data input CLASS2 data output System reset input Crystal connection oscillation Output Input Output Function 16-bit timer/event counter output 16-bit timer/event counter output 8-bit timer/event counter output 8-bit timer/event counter output 8-bit timer/event counter output Clock output converter (AD00) analog input Input Input After Reset Alternate Function Input P23/TI50 P27/TI51 P26/ASCK0/TI52
converter (AD01) analog input
AVSS1
C2RX C2TX RESET VDD0 VDD1 VSS0 VSS1
Data Sheet U15012EJ1V0DS
µPD780833Y
Circuits Recommended Connection Unused Pins
circuit type each recommended connection unused pins shown Table 3-1. circuit configuration each type, Figure 3-1. Table 3-1. Types Circuits Recommended Connection Unused Pins
Name P00/INTP0 P07/INTP7 P20/SI31 P21/SO31 P22/SCK31 P23/TI50/TO50 P24/RxD0 P25/TxD0 P26/ASCK0/TI52/TO52 P27/TI51/TO51 P30/SI30 P31/SO30 P32/SCK30 P34/TO00 P35/TI000 P36/TI010 P70/PCL P71/SDA0 P72/SCL0 P73/TO01 P74/TI001 P75/TI011 P80/ANI01 P87/ANI71 P90/ANI00 P97/ANI70 C2RX C2TX RESET AVDD0 AVREF0 AVREF1 AVSS0 AVSS1 Connect directly VSS0 VSS1. Connect VSS0. Input Output Input Connect VDD0. Connect VSS0 resistor. Leave open. 11-E 13-R Input: Independently connect VDD0 resistor. Output: Leave open. Input: Independently connect VDD0 VSS0 resistor. Output: Leave open. Input: Independently connect VDD0 resistor. Output: Leave open. Input: Independently connect VDD0 VSS0 resistor. Output: Leave open. 13-P Input: Independently connect VDD0 resistor. Output: Leave open. Input: Independently connect VDD0 VSS0 resistor. Output: Leave open. Circuit Type Recommended Connection Unused Pins Input: Independently connect VSS0 resistor. Output: Leave open. Input: Independently connect VDD0 VSS0 resistor. Output: Leave open.
Data Sheet U15012EJ1V0DS
µPD780833Y
Figure 3-1. Circuits
TYPE TYPE
VDD0
Pull-up enable Data
P-ch VDD0 P-ch IN/OUT
Output disable Schmitt-triggered input with hysteresis characteristics
N-ch VSS0
TYPE
TYPE 11-E VDD0 VDD0 P-ch Data P-ch IN/OUT Output disable Comparator N-ch P-ch VSS0
Data N-ch VSS0
N-ch AVSS VREF (Threshold voltage) Input enable
TYPE
VDD0
TYPE 13-P IN/OUT
Pull-up enable Data
P-ch VDD0 P-ch IN/OUT
Data Output disable
N-ch VSS0
Output disable Input enable TYPE Pull-up enable
N-ch VSS0 Input enable VDD0 TYPE 13-R
P-ch IN/OUT VDD0 Data Output disable IN/OUT N-ch
Data
P-ch VSS0
Output disable input Input enable
N-ch VSS0
Data Sheet U15012EJ1V0DS
µPD780833Y
MEMORY SPACE
Figure shows memory µPD780833Y. Figure 4-1. Memory
FFFFH
FF00H FEFFH FEE0H FEDFH
Special function registers (SFRs) bits General-purpose registers bits
Internal high-speed 1024 bits
FB00H FAFFH
Reserved Data memory space
F800H F7FFH
Internal expansion 2048 bits
EFFFH Program area 1000H 0FFFH CALLF entry area
BFFFH EFFFH Program memory space
0800H 07FFH Program area Internal 61440 bits 0080H 007FH CALLT table area 0040H 003FH Vector table area 0000H
0000H
Data Sheet U15012EJ1V0DS
µPD780833Y
PERIPHERAL HARDWARE FUNCTION FEATURES Ports
following types ports available. CMOS (ports (excluding P33, P71, P72)): input/CMOS output (port N-channel open-drain (P33, P71, P72): Total: Table 5-1. Port Functions
Name Port Name Function port. Input/output specified 1-bit units. on-chip pull-up resistor specified means software. port. Input/output specified 1-bit units. on-chip pull-up resistor specified means software. port. Input/output specified 1-bit units. on-chip pull-up resistor specified means software. N-ch open-drain port. Input/output specified 1-bit units. LEDs driven directly. port. Input/output specified 1-bit units. on-chip pull-up resistor specified means software. interrupt request flag (KRIF) falling edge detection. Port TTL-level input/CMOS output port. Input/output specified 1-bit units. on-chip pull-up resistor specified means software. port. Input/output specified 1-bit units. on-chip pull-up resistor specified means software. Port P70, Port Port port. Input/output specified 1-bit units. on-chip pull-up resistor specified means software. port. Input/output specified 1-bit units. port. Input/output specified 1-bit units.
Port
Port
P32,
Port
Port
Data Sheet U15012EJ1V0DS
µPD780833Y
Clock Generator
system clock generator incorporated. minimum instruction execution time changed. 0.48 µs/0.95 µs/1.91 µs/3.81 µs/7.63 4.19 operation with system clock) Figure 5-1. Block Diagram Clock Generator
Prescaler
System clock oscillator
Prescaler
Selector
Clock peripheral hardware
Standby controller
clock (fCPU)
STOP
PCC2 PCC1 PCC0 Processor clock control register (PCC) Internal
Data Sheet U15012EJ1V0DS
µPD780833Y
Timer
Seven timer channels incorporated. 16-bit timer/event counter: channels 8-bit timer/event counter: Watch timer: Watchdog timer: channels channel channel Table 5-2. Operations Timer/Event Counter
16-Bit Timer/Event Counter Operation mode Function Interval timer External event counter Timer outputs outputs outputs Pulse width measurement Square-wave outputs One-shot pulse outputs Interrupt sources channels channels inputs 8-Bit Timer/Event Counter channels channels Watch Timer channelNote Watchdog Timer channelNote
Notes watch timer perform both watch timer interval timer functions same time. watchdog timer watchdog timer interval timer functions. However, watchdog timer selecting either watchdog timer function interval timer function.
Data Sheet U15012EJ1V0DS
µPD780833Y
Figure 5-2. Block Diagram 16-Bit Timer/Event Counter
Internal Capture/compare control register (CRC00) CRC002CRC001 CRC000
Selector
INTTM000
Selector
TI010/P36
Noise eliminator
16-bit capture/compare register (CR000) Match
Selector
fX/22 fX/26
16-bit timer counter (TM00) Match
Clear
Output controller
TO00/P34
fX/23
Noise eliminator
Noise eliminator
TI000/P35
16-bit capture/compare register (CR010)
Selector
INTTM010
CRC002 PRM001 PRM000 Prescaler mode register (PRM00) TMC003 TMC002 TMC001 OVF00 16-bit timer mode control register (TMC00) Internal OSPT0 OSPE0 TOC004 LVS00 LVR00 TOC001 TOE00 16-bit timer output control register (TOC00)
Figure 5-3. Block Diagram 16-Bit Timer/Event Counter
Internal Capture/compare control register (CRC01) CRC012CRC011 CRC010
Selector
INTTM001
Selector
TI011/P75
Noise eliminator
16-bit capture/compare register (CR001) Match
Selector
fX/22 fX/26
16-bit timer counter (TM01) Match
Clear Output controller TO01/P73
fX/23
Noise eliminator
Noise eliminator
TI001/P74
16-bit capture/compare register (CR011)
Selector
INTTM011
CRC012 PRM011 PRM010 Prescaler mode register (PRM01) TMC013 TMC012 TMC011 OVF01 16-bit timer mode control register (TMC01) Internal
Data Sheet U15012EJ1V0DS
OSPT1 OSPE1 TOC014 LVS01 LVR01 TOC011 TOE01 16-bit timer output control register (TOC01)
µPD780833Y
Figure 5-4. Block Diagram 8-Bit Timer/Event Counter
Internal
TI50/TO50/P23 fX/2 fX/22 fX/23 fX/25 fX/27 fX/211
Match
Selector
Mask circuit
8-bit compare register (CR50)
Selector
INTTM50
8-bit timer counter (TM50)
Selector
TO50/TI50/P23
Clear
Selector Level inversion
TCL502 TCL501 TCL500
Timer clock select register (TCL50)
TCE50 TMC506 TMC504 LVS50 LVR50 TMC501 TOE50
8-bit timer mode control register (TMC50)
Internal
Figure 5-5. Block Diagram 8-Bit Timer/Event Counter
Internal
TI51/TO51/P27 fX/2 fX/22 fX/25 fX/27 fX/29 fX/211
Match
Selector
8-bit timer counter (TM51)
Mask circuit
8-bit compare register (CR51)
Selector
INTTM51
Selector
TO51/TI51/P27
Clear
Selector Level inversion
TCL512 TCL511 TCL510
Timer clock select register (TCL51)
TCE51 TMC516 TMC514 LVS51 LVR51 TMC511 TOE51
8-bit timer mode control register (TMC51)
Internal
Data Sheet U15012EJ1V0DS
µPD780833Y
Figure 5-6. Block Diagram 8-Bit Timer/Event Counter
Internal
TI52/TO52/ASCK0/P26 fX/2 fX/23 fX/24 fX/26 fX/28 fX/210
Match
Selector
8-bit timer counter (TM52)
Mask circuit
8-bit compare register (CR52)
Selector
INTTM52
Selector
TO52/TI52/ASCK0/P26
Clear
Selector Level inversion
TCL522 TCL521 TCL520
Timer clock select register (TCL52)
TCE52 TMC526 TMC524 LVS52 LVR52 TMC521 TOE52
8-bit timer mode control register (TMC52)
Internal
Figure 5-7. Block Diagram Watch Timer
Clear
Selector
fX/26 fX/2
Selector
11-bit prescaler
5-bit prescaler
Clear
Selector
INTWTN0
Selector
INTWTNI0
WTNM07 WTNM06 WTNM05 WTNM04 WTNM03 WTNM02 WTNM01 WTNM00 Watch timer operation mode register (WTNM0)
Internal
Data Sheet U15012EJ1V0DS
µPD780833Y
Figure 5-8. Block Diagram Watchdog Timer
fX/28
Clock input controller
Division circuit
Divided clock selector
INTWDT Output controller RESET
Division mode selector
mode signal
OSTS2 OSTS1 OSTS0 Oscillation stabilization time select register (OSTS)
WDCS2 WDCS1 WDCS0
WDTM4 WDTM3
Watchdog timer clock select register (WDCS) Internal
Watchdog timer mode register (WDTM)
Clock Output Controller
clock output/buzzer output controller (CKU) incorporated. Clocks with following variation frequency output clock output. 32.8 kHz/65.6 kHz/131 kHz/262 kHz/524 kHz/1.05 MHz/2.10 MHz/4.19 4.19 operation with system clock) Figure 5-9. Block Diagram Clock Output Controller
Prescaler
Selector
fX/27
Clock controller
PCL/P70
CLOE
CLOE
CCS2
CCS1
CCS0
Clock output select register (CKS) Internal
Data Sheet U15012EJ1V0DS
µPD780833Y
Converter
converters 8-bit resolution channels (AD00 AD01) incorporated. conversion operation only started software. Figure 5-10. Block Diagram Converter (AD00)
Series resistor string ANI00/P90 ANI10/P91 ANI20/P92 ANI30/P93 ANI40/P94 ANI50/P95 ANI60/P96 ANI70/P97 Sample hold circuit
Selector selector
AVDD0 Voltage comparator AVREF0
Successive approximation register (SAR)
AVSS0
INTAD00
conversion result register (ADCR00)
ADS002 ADS001 ADS000
ADCS00 FR020 FR010 FR000 converter mode register (ADM00)
Analog input channel specification register (ADS00) Internal
Figure 5-11. Block Diagram Converter (AD01)
Series resistor string ANI01/P80 ANI11/P81 ANI21/P82 ANI31/P83 ANI41/P84 ANI51/P85 ANI61/P86 ANI71/P87 Sample hold circuit
Successive approximation register (SAR)
selector
Voltage comparator
AVREF1 (Alternative analog power supply)
Selector
AVSS1
INTAD01
conversion result register (ADCR01)
ADS012 ADS011 ADS010
ADCS01 FR021 FR011 FR001 converter mode register (ADM01)
Analog input channel specification register (ADS01) Internal
Data Sheet U15012EJ1V0DS
µPD780833Y
Serial Interface
Four serial interface channels incorporated. Serial interface UART0 Serial interface SIO30, Serial interface IIC0
Serial interface UART0 serial interface UART0 operates asynchronous serial interface (UART) mode. Asynchronous serial interface (UART) mode This mode enables full-duplex operation wherein byte data following start transmitted received. on-chip UART-dedicated baud rate generator enables communication using wide range selectable baud rates. addition, baud rate also defined dividing clock input ASCK0 pin. UART-dedicated baud rate generator also used generate MIDI-standard baud rate (31.25 Kbps). Figure 5-12. Block Diagram Serial Interface UART0
Internal
Asynchronous serial interface mode register (ASIM0)
Receive buffer register (RXB0) Asynchronous serial interface status register (ASIS0)
TXE0 RXE0 PS01 PS00
ISRM0
RxD0/P24
Receive shift register (RX0)
OVE0
Transmit shift register (TXS0)
TxD0/P25
Receive controller (parity check) Transmit
INTSER0 controller INTSR0
(parity addition)
INTST0
Baud rate generator
P26/ASCK0 fX/2 fX/27
Data Sheet U15012EJ1V0DS
µPD780833Y
Serial interface SIO30 serial interfaces SIO30 operate 3-wire serial mode. 3-wire serial mode (fixed first) This 8-bit data transfer mode using three lines: serial clock line (SCK3n), serial output line (SO3n), serial input line (SI3n). Since simultaneous transmit receive operations possible 3-wire serial mode, processing time data transfer reduced. first 8-bit data serial transfer fixed MSB. 3-wire serial mode useful connection peripheral devices that include clocked serial interface, display controllers, etc. Remark Figure 5-13. Block Diagram Serial Interface SIO30
Internal SI30/P30 Serial shift register (SIO30)
SO30/P31 SCK30/P32 Serial clock counter Serial clock controller Interrupt request signal generator INTCSI30 fX/23 fX/24 fX/26
Selector
Figure 5-14. Block Diagram Serial Interface SIO31
Internal SI31/P20 Serial shift register (SIO31)
SO31/P21 SCK31/P22 Serial clock counter Serial clock controller Interrupt request signal generator INTCSI31 fX/23 fX/24 fX/26
Selector
Data Sheet U15012EJ1V0DS
µPD780833Y
Serial interface IIC0 serial interface IIC0 operates (Inter mode (multimaster supported). mode (multimaster supported) This 8-bit data transfer mode using lines: serial clock line (SCL0) serial data line (SDA0). This mode complies with format, output "start condition", "data", "stop condition" during transmission serial data bus. This data automatically detected hardware during reception. Since SCL0 SDA0 open-drain outputs IIC0, pull-up resistors serial clock line serial data line required. Figure 5-15. Block Diagram Serial Interface IIC0
Internal status register (IICS0)
MSTS0 ALD0 EXC0 COI0 TRC0 ADKD0 STD0 SPD0
control register (IICC0) SDA0/P71 Noise eliminator Slave address register (SVA0) Match signal
IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0
CLEAR latch CL01, CL00
shift register (IIC0)
N-ch opendrain output
Data hold time correction circuit
Acknowledge detector
Wake-up controller Acknowledge detector
Start condition detector
Stop condition detector SCL0/P72 Noise eliminator Interrupt request signal generator INTIIC0
Serial clock counter
Serial clock controller N-ch opendrain output Prescaler
Serial clock wait controller
CLD0 DAD0 SMC0 DFC0 CL01 CL00 transfer clock select register (IICCL0) Internal
CLX0 function expansion register (IICX0)
Data Sheet U15012EJ1V0DS
µPD780833Y
J1850 (CLASS2) Controller
µPD780833Y includes controller compliant with J1850 (CLASS2). protocol J1850 (CLASS2) variable pulse width modulation (VPW) method. protocol conforms rules stated below. potential level changed each bit. logical value, determined potential level pulse width. logical value takes precedence. message begins with (start frame) symbol contains bytes data except block mode, which data length limited. Data transmitted serially descending order bits, that transmitted first, transmitted last. last bit, followed cyclic redundancy check (CRC) field. message concluded with (end frame). break signal single pulse. Examples message symbols shown below. Figure 5-16. Example Message
bytes
Byte
Table 5-3. Examples Symbols
Symbol Name Symbol (Example Symbols Normal Transmission Mode) Active Logical state
(Start Frame)
passive
active
active
passive
Logical state
(End Frame)
Passive
Break signal
Active
Data Sheet U15012EJ1V0DS
µPD780833Y
INTERRUPT FUNCTIONS
total interrupt sources provided, divided into following three types. Non-maskable: Maskable: Software: Table 6-1. Interrupt Source List (1/2)
Interrupt Type Nonmaskable Maskable Default PriorityNote Name INTWDT INTWDT INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTP7 INTSER0 INTSR0 INTST0 INTCSI30 INTCSI31 INTIIC0 INTC2 INTWTNI0 INTTM000 UART0 reception error generation UART0 reception UART0 transmission SIO30 transfer SIO31 transfer IIC0 transfer CLASS2 wake-up request, reception completion, sleep enable, reception error Reference time interval signal from watch timer Match between TM00 CR000 (when compare register specified). Valid edge detection TI000 (when capture register specified). Match between TM00 CR010 (when compare register specified). Valid edge detection TI010 (when capture register specified). Internal Interrupt Source Trigger Watchdog timer overflow (with watchdog timer mode selected) Watchdog timer overflow (with interval timer mode selected) input edge detection External 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H 0018H 001AH 001CH 001EH 0020H 0022H 0024H 0026H Vector Basic Table Configuration External Address TypeNote Internal/ Internal 0004H
INTTM010
0028H
Notes default priority priority order when more maskable interrupt requests generated simultaneously. highest lowest. Basic configuration types correspond Figure 6-1, respectively. Remark watchdog timer interrupt sources (INTWDT) available: non-maskable interrupt maskable interrupt (internal), either which selected.
Data Sheet U15012EJ1V0DS
µPD780833Y
Table 6-1. Interrupt Source List (2/2)
Interrupt Type Maskable Default PriorityNote Name INTTM001 Interrupt Source Trigger Match between TM01 CR001 (when compare register specified). Valid edge detection TI001 (when capture register specified). Match between TM01 CR011 (when compare register specified). Valid edge detection TI011 (when capture register specified). converter (AD00) conversion converter (AD01) conversion Watch timer overflow Port falling edge detection Match between TM50 CR50 Match between TM51 CR51 Match between TM52 CR52 instruction execution Vector Basic Table Configuration External Address TypeNote Internal/ Internal 002AH
INTTM011
002CH
Software
INTAD00 INTAD01 INTWTN0 INTKR INTTM50 INTTM51 INTTM52
002EH 0030H 0034H External 0036H Internal 0038H 003AH 003CH 003EH
Notes default priority priority order when more maskable interrupt requests generated simultaneously. highest lowest. Basic configuration types correspond Figure 6-1, respectively. Remark watchdog timer interrupt sources (INTWDT) available: non-maskable interrupt maskable interrupt (internal), either which selected.
Data Sheet U15012EJ1V0DS
µPD780833Y
Figure 6-1. Basic Configuration Interrupt Function (1/2) Internal non-maskable interrupt
Internal
Interrupt request
Priority controller
Vector table address generator Standby release signal
Internal maskable interrupt
Internal
Interrupt request
Priority controller
Vector table address generator Standby release signal
External maskable interrupt (INTP0 INTP7)
Internal
External interrupt edge enable register (EGP, EGN)
Interrupt request
Edge detector
Priority controller
Vector table address generator Standby release signal
Data Sheet U15012EJ1V0DS
µPD780833Y
Figure 6-1. Basic Configuration Interrupt Function (2/2) External maskable interrupt (INTKR)
Internal
Interrupt request
Falling edge detector
Priority controller
Vector table address generator Standby release signal
Software interrupt
Internal
Interrupt request
Priority controller
Vector table address generator
Interrupt request flag Interrupt enable flag
ISP: In-service priority flag Interrupt mask flag Priority specification flag
Data Sheet U15012EJ1V0DS
µPD780833Y
STANDBY FUNCTIONS
following standby functions provided reduce current consumption. HALT mode: operating clock stopped. average current consumption reduced intermittent operation combination with normal operating mode. STOP mode: system clock oscillation stopped. operations using system clock stopped, that system operates with ultra-low power consumption. Figure 7-1. Standby Function
System clock operation Interrupt request STOP instruction STOP mode (System clock oscillation stopped) Interrupt request HALT mode (Clock supply stopped, oscillation maintained) HALT instruction
RESET FUNCTIONS
following reset methods available. External reset RESET signal input Internal reset watchdog timer loop time detection
Data Sheet U15012EJ1V0DS
µPD780833Y
INSTRUCTION
8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Second operand First operand #byte
byte]
Note
saddr
!addr16
[DE]
[HL]
$addr16
None
ADDC SUBC
ADDC SUBC
ADDC SUBC
ADDC SUBC
ADDC SUBC
ADDC SUBC
RORC ROLC
ADDC SUBC
saddr ADDC SUBC !addr16
DBNZ
DBNZ
PUSH
[DE] [HL]
ROR4 ROL4
byte]
MULU DIVUW
Note Except
Data Sheet U15012EJ1V0DS
µPD780833Y
16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second operand First operand #word ADDW SUBW CMPW MOVW MOVW MOVW MOVW MOVWNote MOVW MOVW MOVW MOVW rpNote MOVW XCHW sfrp MOVW saddrp MOVW !addr16 MOVW MOVW None
sfrp saddrp !addr16
INCW, DECW PUSH,
Note Only when manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BTCLR
Second operand First operand A.bit A.bit sfr.bit saddr.bit PSW.bit [HL].bit MOV1 $addr16 BTCLR BTCLR BTCLR BTCLR BTCLR None SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1
sfr.bit
MOV1
saddr.bit
MOV1
PSW.bit
MOV1
[HL].bit
MOV1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
SET1 CLR1 NOT1
Call instructions/branch instructions CALL, CALLF, CALLT, BNC, BNZ, BTCLR, DBNZ
Second operand First operand Basic instruction Compound instruction !addr16 CALL !addr11 CALLF [addr5] CALLT $addr16 BTCLR DBNZ
Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, HALT, STOP
Data Sheet U15012EJ1V0DS
µPD780833Y
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings 25°C)
Parameter Supply voltage Symbol AVDD AVREF AVSS Input voltage P07, P27, P32, P36, P47, P57, P67, P75, P87, P97, C2RX, RESET N-ch open-drain -0.3 +0.3 -0.3 AVDD Conditions Ratings -0.3 +6.5 Unit
Output voltage
-0.3 -0.3
P07, P27, P36, P47, P57, P67, P75, P87, P97, C2TX ANI00 ANI70 ANI01 ANI71 Analog input
Analog input voltage
-0.3
Output current, high
P07, P27, P32, P36, P47, P57, P67, P70, P75, P87, P97, C2TX Total pins
Peak value value
Output current,
lowNote
P07, P27, P32, P36, P47, P57, P67, P75, P87, P97, C2TX
Peak value value
Total pins
Peak value value
Operating ambient temperature Storage temperature
Tstg
+150
Note value should calculated follows: [rms value] [Peak value] Duty Caution Product quality suffer absolute maximum rating exceeded even momentarily parameter. That absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions that ensure that absolute maximum ratings exceeded. Remark Unless specified otherwise, characteristics alternate-function pins same those port pins.
Data Sheet U15012EJ1V0DS
µPD780833Y
System Clock Oscillator Characteristics +85°C,
Resonator Ceramic resonator Recommended Circuit
TEST
Parameter Oscillation frequency (fX)Note
Conditions
MIN.
TYP.
MAX.
Unit
Oscillation stabilization timeNote
Crystal resonator
TEST
Oscillation frequency (fX)Note
Oscillation stabilization timeNote
Notes Indicates only oscillator characteristics. Time required stabilize oscillation after reset STOP mode release. Caution When using system clock oscillator, wire follows area enclosed broken lines above figures avoid adverse effect from wiring capacitance. Keep wiring length short possible. cross wiring with other signal lines. route wiring near signal line through which high fluctuating current flows. Always make ground point oscillator capacitor same potential VSS1. ground capacitor ground pattern through which high current flows. fetch signals from oscillator. Remark resonator selection oscillator constant, customers requested either evaluate oscillation themselves apply resonator manufacturer evaluation.
Data Sheet U15012EJ1V0DS
µPD780833Y
Capacitance 25°C,
Parameter Input capacitance Symbol Conditions Unmeasured pins returned Unmeasured pins returned P07, P27, P32, Unmeasured pins P36, P47, P57, returned P67, P75, P87, MIN. TYP. MAX. Unit
Output capacitance
COUT
capacitance
Remark Unless specified otherwise, characteristics alternate-function pins same those port pins.
Data Sheet U15012EJ1V0DS
µPD780833Y
Characteristics +85°C, AVDD AVREF
Parameter Input voltage, high Symbol VIH1 Conditions P21, P25, P31, P34, P47, P67, P73, P87, P07, P20, P24, P26, P27, P30, P32, P35, P36, P74, P75, RESET (N-ch open drain) C2RX P21, P25, P31, P34, P47, P67, P73, P87, P07, P20, P24, P26, P27, P30, P32, P35, P36, P74, P75, C2RX, RESET (N-ch open drain) -100 MIN. 0.7VDD TYP. MAX. Unit
VIH2
0.8VDD
VIH3 VIH4 VIH5 VIH6 Input voltage, VIL1
0.7VDD 0.8VDD
0.3VDD
VIL2
0.2VDD
VIL3 VIL4 VIL5 Output voltage, high VOH1
P07, P27, P32, P36, P47, P57, P67, P70, P75, P87, P97, C2TX P71, P07, P27, P32, P36, P47, P57, P67, P70, P75, P87, P97, C2TX P07, P36, P67, P97, C2RX, P27, P32, P47, P57, P75, P87, RESET
0.75 0.3VDD
VOH2
Output voltage,
VOL1 VOL2 VOL3
VOL4
Input leakage current, high
ILIH1
ILIH2 ILIH3 Input leakage current, ILIL1
P07, P36, P67, P97, C2RX, P27, P32, P47, P57, P75, P87, RESET
ILIL2 ILIL3
-3Note
Note low-level input leakage current -200 (MAX.) flows through only clock after executing read instruction port (P33). Other than that period, (MAX.) flows. Remark Unless specified otherwise, characteristics alternate-function pins same those port pins.
Data Sheet U15012EJ1V0DS
µPD780833Y
Characteristics +85°C, AVDD AVREF
Parameter Output leakage current, high Symbol ILOH VOUT Conditions P07, P36, P67, P97, P27, P32, P47, P57, P70, P75, P87, C2TX MIN. TYP. MAX. Unit
Output leakage current,
ILOL
VOUT
P07, P27, P36, P47, P57, P67, P75, P87, P97, C2TX P07, P27, P32, P36, P47, P57, P67, P70,
Software pull-up resistance
Supply currentNote
IDD1
4.19 crystal oscillation operating modeNote 8.38 crystal oscillation operating modeNote
1200
IDD2
4.19 crystal oscillation HALT
modeNote
8.38 crystal oscillation HALT modeNote IDD3 STOP mode
Notes Refers total current flowing internal power supplies (VDD1 VSS1). current flowing AVREF, AVDD, ports (on-chip pull-up resistors) included. High-speed mode operation (when processor clock control register (PCC) 00H) Low-speed mode operation (when processor clock control register (PCC) 04H). WTN0 operating current CLASS2 signal receive wait status operating current (when (C2SC1) (C2SC0) class clock selection register (C2CLK) 00B) included. Remark Unless specified otherwise, characteristics alternate-function pins same those port pins.
Data Sheet U15012EJ1V0DS
µPD780833Y
Characteristics Basic operation +85°C,
Parameter Cycle time (minimum instruction execution time) TI000, TI010, TI001, TI011 input high-/low-level width TI50, TI51, TI52 input frequency TI50, TI51, TI52 input high-/low-level width Interrupt request input high-/low-level width RESET low-level width Symbol Conditions When using ceramic resonator When using crystal resonator tTIH0 tTIL0 MIN. 0.238 0.476 2/fsam 0.1Note TYP. MAX. Unit
fTI5
tTIH5 tTIL5 tINTH tINTL tRSL INTP0 INTP7,
Note Selection fsam available with bits (PRM0n0, PRM0n1) prescaler mode register (PRM0n). However, TI00n valid edge selected count clock, value becomes fsam
Data Sheet U15012EJ1V0DS
µPD780833Y
Serial interface +85°C, SIO3 3-wire serial mode (internal clock output): SIO30, SIO31
Parameter SCK3 cycle time SCK3 high-/low-level width setup time SCK3) hold time (from SCK3) Delay time from SCK3 output tSIK1 Symbol tKCY1 tKH1, tKL1 Conditions MIN. tKCY1/2 TYP. MAX. Unit
tKSI1 pFNote
tKSO1
Note load capacitance SCK3 output lines. SIO3 3-wire serial mode (external clock input): SIO30, SIO31
Parameter SCK3 cycle time SCK3 high-/low-level width setup time SCK3) hold time (from SCK3) Delay time from SCK3 output tSIK2 Symbol tKCY2 tKH2, tKL2 Conditions MIN. TYP. MAX. Unit
tKSI2 pFNote
tKSO2
Note load capacitance output line. UART0 (dedicated baud rate generator output)
Parameter Transfer rate Symbol Conditions MIN. TYP. MAX. 131250 Unit
UART0 (external clock input)
Parameter ASCK0 cycle time ASCK0 high-/low-level width Transfer rate Symbol tKCY3 tKH3, tKL3 Conditions MIN. TYP. MAX. Unit
39063
Data Sheet U15012EJ1V0DS
µPD780833Y
mode
Standard Mode Parameter SCL0 clock frequency free time (between stop start condition) Hold timeNote SCL0 clock low-level width SCL0 clock high-level width Start/restart condition setup time Data hold time CBUS compatible master Data setup time SDA0 SCL0 signal rise time SDA0 SCL0 signal fall time Stop condition setup time Capacitive load line tSU:DAT tSU:STO tHD:STA tLOW tHIGH tSU:STA tHD:DAT 0Note 1000 0Note 100Note 0.9Note Symbol MIN. fSCL tBUF MAX. MIN. MAX. High-Speed Mode Unit
Notes start condition output, first clock pulse generated after this hold period. fill undefined area SCL0 falling edge, necessary device provide least hold time internally SDA0 signal VIHmin. SCL0 signal). device does extend SCL0 signal hold time (tLOW), only maximum data hold time tHD:DAT needs satisfied. high-speed mode available standard mode system. this time, conditions described below must satisfied. device does extend SCL0 signal state hold time tSU:DAT device extends SCL0 signal state hold time sure transmit next data SDA0 line before SCL0 line released (tRmax. tSU:DAT 1000 1250 standard mode specification).
Data Sheet U15012EJ1V0DS
µPD780833Y
CLASS2 +85°C, Internal clock count limit
Parameter Internal clock cycle time Symbol tCCLK Conditions MIN. TYP. MAX. Unit
normal mode
Parameter Rise time propagation delay (from C2TX C2RX) Fall time propagation delay (from C2TX C2RX) Symbol tPDR Conditions MIN. TYP. MAX. 62tCCLK Unit
tPDF
62tCCLK
quadruple-speed mode
Parameter Rise time propagation delay (from C2TX C2RX) Fall time propagation delay (from C2TX C2RX) Symbol tPDRX Conditions MIN. TYP. MAX. 8tCCLK Unit
tPDFX
8tCCLK
Transmission/reception pulse width normal mode)
Symbol When Passive: Active: When Passive: Active: When Active When Passive Idle point When Active Break tXMIN tXNOM tXMAX tRMIN above above tRMAX below below below 8tCCLK Unit
Transmission/reception pulse width quadruple-speed mode)
Symbol When Passive: Active: When Passive: Active: When Active When Passive Idle point When Passive: Active: tXMIN tXNOM tXMAX tRMIN tRMAX 8tCCLK Unit
Data Sheet U15012EJ1V0DS
µPD780833Y
Timing Test Points (Excluding Input)
0.8VDD 0.2VDD
Test points
0.8VDD 0.2VDD
Clock Timing
1/fX
VIH5 (MIN.) VIL5 (MAX.)
input
Timing
tTIL0 tTIH0
TI000, TI010, TI001, TI011
1/fTI5 tTIL5 tTIH5
TI50, TI51, TI52
Interrupt Request Input Timing
tINTL
tINTH
INTP0 INTP7
RESET Input Timing
tRSL
RESET
Data Sheet U15012EJ1V0DS
µPD780833Y
Serial Transfer Timing 3-wire serial mode:
tKCYn tKLn tKHn
SCK30, SCK31
tSIKn
tKSIn
SI30, SI31
Input data
tKSOn
SO30, SO31
Output data
UART mode (external clock input):
tKCY3 tKL3 tKH3
ASCK0
mode:
tLOW SCL0 tHIGH tHD:DAT tHD:STA SDA0 tBUF tSU:DAT tSU:STA tHD:STA tSU:STO
Stop condition
Start condition
Restart condition
Stop condition
Data Sheet U15012EJ1V0DS
µPD780833Y
CLASS2 propagation waveform (example short pulse width)
C2TX s-tPDF s-tPDR
tPDR
tPDF
tPDR
C2RX
C2TX s-tPDFX s-tPDRX
tPDRX
tPDFX
tPDRX
C2RX
Remarks meanings symbols above figure follows: tPDR: Rise time propagation delay normal mode CLASS2 transceiver tPDF: Fall time propagation delay normal mode CLASS2 transceiver tPDRX: Rise time propagation delay quadruple-speed mode CLASS2 transceiver tPDFX: Fall time propagation delay quadruple-speed mode CLASS2 transceiver values tPDR, tPDF, tPDRX, tPDFX, specified using class rise time propagation delay correction register (C2PDR) class fall time propagation delay correction register (C2PDF).
Data Sheet U15012EJ1V0DS
µPD780833Y
Converter Characteristics +85°C, AVDD AVREF AVSS
Parameter Resolution Overall errorNote tCONV VIAN RAIREF AVSS Symbol Conditions MIN. TYP. MAX. ±0.6 AVREF Unit %FSR
Conversion time Analog input voltage AVREF resistance
Note Excludes quantization error (±0.2%FSR). indicated ratio full-scale value. Data Memory STOP Mode Supply Voltage Data Retention Characteristics +85°C)
Parameter Data retention power supply voltage Data retention power supply current Release signal time Oscillation stabilization wait time tSREL tWAIT Release RESET Release interrupt request 217/fX Note Symbol VDDDR Conditions MIN. TYP. MAX. Unit
IDDDR
VDDDR
Note Selection 212/fX, 214/fX, 215/fX, 216/fX, 217/fX possible with bits (OSTS0 OSTS2) oscillation stabilization time select register (OSTS). Data Retention Timing (STOP Mode Release RESET)
Internal reset operation HALT mode STOP mode Operating mode
Data retention mode
STOP instruction execution RESET
VDDDR tSREL
tWAIT
Data Sheet U15012EJ1V0DS
µPD780833Y
Data Retention Timing (Standby Release Signal: STOP Mode Release Interrupt Request Signal)
HALT mode STOP mode Operating mode
Data retention mode
STOP instruction execution Standby release signal (interrupt request)
VDDDR
tSREL
tWAIT
Data Sheet U15012EJ1V0DS
µPD780833Y
PACKAGE DRAWING
80-PIN PLASTIC (14x14)
detail lead
ITEM MILLIMETERS 17.20±0.20 14.00±0.20 14.00±0.20 17.20±0.20 0.825 0.825 0.32±0.06 0.13 0.65 (T.P.) 1.60±0.20 0.80±0.20 0.17 +0.03 -0.07 0.10 1.40±0.10 0.125±0.075 1.70 MAX. P80GC-65-8BT-1
NOTE Each lead centerline located within 0.13 true position (T.P.) maximum material condition.
Data Sheet U15012EJ1V0DS
µPD780833Y
RECOMMENDED SOLDERING CONDITIONS
solder mounting method soldering conditions µPD780833Y, contact sales representative.
Data Sheet U15012EJ1V0DS
µPD780833Y
APPENDIX DEVELOPMENT TOOLS
following development tools available system development using µPD780833Y. Also refer Cautions using development tools. Language processing software
RA78K0 CC78K0 DF780833 CC78K0-L Assembler package common 78K/0 Series compiler package common 78K/0 Series Device file µPD780833Y Subseries compiler library source file common 78K/0 Series
Flash memory writing tools
Flashpro Flash programmer dedicated on-chip flash memory microcontrollers (Part No.: FL-PR2) Flashpro (Part No.: FL-PR3, PG-FP3) FA-80GC Adapter flash memory writing used connecting Flashpro Flashpro III. This 80-pin plastic (GC-8BT type).
Debugging tool When using in-circuit emulator IE-78K0-NS
IE-78K0-NS IE-70000-MC-PS-B IE-70000-98-IF-C In-circuit emulator common 78K/0 Series Power supply unit IE-78K0-NS Interface adapter when using PC-9800 series host machine (excluding notebook PCs) supported) IE-70000-CD-IF-A IE-70000-PC-IF-C IE-70000-PCI-IF-A IE-780833-NS-EM4 IE-78K0-NS-P02 NP-80GC EV-9200GC-80 card interface cable when using notebook host machine (PCMCIA socket supported) Interface adapter when using PC/ATcompatible host machine (ISA supported) Adapter necessary when using on-chip host machine Emulation board emulate µPD780833Y Subseries board necessary when using IE-780833-NS-EM4 Emulation probe 80-pin plastic (GC-8BT type) Conversion socket connect target system which 80-pin plastic (GC-8BT type) mounted NP-80GC Integrated debugger IE-78K0-NS System simulator common 78K/0 Series Device file µPD780833Y Subseries
ID78K0-NS SM78K0 DF780833
Data Sheet U15012EJ1V0DS
µPD780833Y
When using in-circuit emulator IE-78001-R-A
IE-78001-R-A IE-70000-98-IF-C In-circuit emulator common 78K/0 Series Interface adapter when using PC-9800 series host machine (excluding notebook PCs) supported) Interface adapter when using PC/AT compatible host machine (ISA supported) Adapter necessary when using on-chip host machine Interface adapter cable when using host machine Emulation board emulate µPD780833Y Subseries board necessary when using IE-780833-NS-EM4 Emulation probe conversion board necessary IE-780833-NS-EM4 IE-78K0-NS-P02 IE78001-R-A Emulation probe 80-pin plastic (GC-8BT type) Conversion socket connect target system board manufactured 80-pin plastic (GC-8BT type) EP-78230GC-R ID78K0 SM78K0 DF780833 Integrated debugger IE-78001-R-A System simulator common 78K/0 Series Device file µPD780833Y Subseries
IE-70000-PC-IF-C IE-70000-PCI-IF-A IE-78000-R-SV3 IE-780833-NS-EM4 IE-78K0-NS-P02 IE-78K0-R-EX1
EP-78230GC-R EV-9200GC-80
Real-time
RX78K0 MX78K0 Real-time 78K/0 Series 78K/0 Series
Data Sheet U15012EJ1V0DS
µPD780833Y
Cautions using development tools ID78K0-NS, ID78K0, SM78K0 used combination with DF780833. CC78K0 RX78K0 used combination with RA78K0 DF780833. FL-PR2, FL-PR3, FA-80GC, NP-80GC products Naito Densei Machida Mfg. Co., Ltd. (+8144-822-3813). third-party development tools, Single-chip Microcontroller Development Tool Selection Guide (U11069E). host machines supporting each software follows.
Host Machine [OS] Software RA78K0 CC78K0 ID78K0-NS ID78K0 SM78K0 RX78K0 MX78K0 PC-9800 series [Japanese PC/AT compatible [Japanese/English Windows] Note
Note
WindowsTM] HP9000 series 700[HP-UXTM] SPARCstation[SunOSTM, SolarisTM] NEWS(RISC) [NEWS-OSTM]
Note Note
Note DOS-based software
Data Sheet U15012EJ1V0DS
µPD780833Y
Conversion Socket (EV-9200GC-80) Drawing Footprints Figure A-1. EV-9200GC-80 Drawing (for Reference Only)
EV-9200GC-80
No.1 index
EV-9200GC-80-G1E ITEM MILLIMETERS 18.0 14.4 14.4 18.0 16.0 18.7 16.0 18.7 0.35 INCHES 0.709 0.567 0.567 0.709 0.079 0.031 0.236 0.63 0.736 0.236 0.63 0.736 0.323 0.315 0.098 0.079 0.014
0.091 0.059
Data Sheet U15012EJ1V0DS
µPD780833Y
Figure A-2. EV-9200GC-80 Footprints (for Reference Only)
EV-9200GC-80-P1E ITEM Caution MILLIMETERS 19.7 15.0 0.65±0.02 19=12.35±0.05 INCHES 0.776 0.591 0.026+0.001 -0.002 0.748=0.486+0.003 -0.002
0.65±0.02 19=12.35±0.05 0.026+0.001 0.748=0.486 +0.003 -0.002 -0.002 15.0 19.7 0.05 0.05 0.35 0.02 0.591 0.776 0.236+0.003 -0.002 0.236+0.003 -0.002 0.014+0.001 -0.001
2.36 0.03 1.57 0.03
0.093+0.001 -0.002 0.091 0.062+0.001 -0.002
Dimensions mount EV-9200 that target device (QFP) different some parts. recommended mount dimensions QFP, refer "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E).
Data Sheet U15012EJ1V0DS
µPD780833Y
APPENDIX RELATED DOCUMENTS
related documents indicated this publication include preliminary versions. However, preliminary versions marked such. Documents related devices
Document Name Document U13892E This document U15013E U12326E
µPD780833Y Subseries User's Manual µPD780833Y Data Sheet µPD78F0833Y Data Sheet
78K/0 Series User's Manual Instructions
Documents related development tools (user's manuals)
Document Name RA78K0 Assembler Package Operation Language Structured Assembly Language CC78K0 Compiler Operation Language IE-78K0-NS IE-78K0-R-EX1 IE-780833-NS-EM4 SM78K0S, SM78K0 System Simulator Windows Based SM78K Series System Simulator Ver. 2.10 later ID78K0-NS Integrated Debugger Ver. 2.00 later Windows Based ID78K0 Integrated Debugger Windows Based Operation External Part User Open Interface Specifications Operation Guide Reference U14379E U11649E U11539E Document U11802E U11801E U11789E U11517E U11518E U13731E prepared prepared U14611E prepared
Caution related documents listed above subject change without notice. sure read latest version each document before designing.
Data Sheet U15012EJ1V0DS
µPD780833Y
Documents related embedded software (user's manuals)
Document Name 78K/0 Series Real-time Fundamentals Installation 78K/0 Series MX78K0 Fundamental Document U11537E U11536E U12257E
Other related documents
Document Name SEMICONDUCTOR SELECTION GUIDE Products Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades Semiconductor Devices Semiconductor Device Reliability/Quality Control System Guide Prevent Damage Semiconductor Devices Electrostatic Discharge (ESD) Document X13769X C10535E C11531E C10983E C11892E
Caution related documents listed above subject change without notice. sure read latest version each document before designing.
Data Sheet U15012EJ1V0DS
µPD780833Y
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Purchase components conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips.
IEBus trademarks Corporation. Windows either registered trademark trademark Microsoft Corporation United States and/or other countries. PC/AT trademark International Business Machines Corporation. HP9000 series HP-UX trademarks Hewlett-Packard Company. SPARCstation trademark SPARC International, Inc. Solaris SunOS trademarks Microsystems, Inc. NEWS NEWS-OS trademarks Sony Corporation.
Data Sheet U15012EJ1V0DS
µPD780833Y
Regional Information
Some information contained this document vary from country country. Before using product your application, pIease contact office your country obtain list authorized representatives distributors. They will verify:
Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements
addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 Fax: 01-30-67 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics (France) S.A. Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
Electronics Singapore Pte. Ltd.
United Square, Singapore Tel: 65-253-8311 Fax: 65-250-3583
Electronics Taiwan Ltd. Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
Brasil S.A.
Electron Devices Division Guarulhos-SP Brasil Tel: 55-11-6462-6810 Fax: 55-11-6462-6829
J00.7
Data Sheet U15012EJ1V0DS
µPD780833Y
export this product from Japan regulated Japanese government. export this product prohibited without governmental license, need which must judged customer. export re-export this product from country other than Japan also prohibited without license from that country. Please call sales representative.
information this document current October, 2000. information subject change without notice. actual design-in, refer latest publications NEC's data sheets data books, etc., most up-to-date specifications semiconductor products. products and/or types available every country. Please check with sales representative availability additional information. part this document copied reproduced form means without prior written consent NEC. assumes responsibility errors that appear this document. does assume liability infringement patents, copyrights other intellectual property rights third parties arising from semiconductor products listed this document other liability arising from such products. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. assumes responsibility losses incurred customers third parties arising from these circuits, software information. While endeavours enhance quality, reliability safety semiconductor products, customers agree acknowledge that possibility defects thereof cannot eliminated entirely. minimize risks damage property injury (including death) persons arising from defects semiconductor products, customers must incorporate sufficient safety measures their design, such redundancy, fire-containment, anti-failure features. semiconductor products classified into following three quality grades: "Standard", "Special" "Specific". "Specific" quality grade applies only semiconductor products developed based customer-designated "quality assurance program" specific application. recommended applications semiconductor product depend quality grade, indicated below. Customers must check quality grade each semiconductor product before using particular application. "Standard": Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade semiconductor products "Standard" unless otherwise expressly specified NEC's data sheets data books, etc. customers wish semiconductor products applications intended NEC, they must contact sales representative advance determine NEC's willingness support given application. (Note) "NEC" used this statement means Corporation also includes majority-owned subsidiaries. "NEC semiconductor products" means semiconductor product developed manufactured defined above).

µPD780833Y 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION

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