µPD789800 8-BIT SINGLE-CHIP MICROCONTROLLER µPD789800 78K/0S

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µPD789800 8-BIT SINGLE-CHIP MICROCONTROLLER µPD789800 78K/0S

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INTEGRATED CIRCUIT
µPD789800
8-BIT SINGLE-CHIP MICROCONTROLLER
µPD789800 78K/0S series product designed keyboard (for ASSP). µPD789800 on-chip hardware compatible with keyboard, including (Universal Serial Bus) functions, regulator which powers driver/receiver, return signal detection circuit. µPD78F9801, product with on-chip flash memory which operate same supply voltage masked products various development tools also available. Detailed descriptions functions, etc., given following user's manuals. sure read them design purposes. µPD789800 Sub-Series User's Manual 78K/0S Series User's Manual, Instruction U12978E U11047E
FEATURES
On-chip functions Implements (Universal Serial Bus) connecting Host. Transfer speed: Mbps (when system clock operates MHz) On-chip regulator Controls port voltage using power supply (VREG ±0.3 dedicated driver/receiver. On-chip Internal bytes Internal high-speed bytes Minimum instruction execution time switched between high speed (0.33 speed (1.33 (when system clock operates MHz). port: Serial interface: channels function Timer: channels 8-bit timer Watchdog timer channel channel 8-bit timer/event counter: channel On-chip return signal detection circuit Supply voltage: Operating ambient temperature -40°C +85°C (when operating) +70°C (when operating) channel Three-wire serial mode channel
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Document U12627EJ3V0DS00 (3rd edition) Date Published September 2000 CP(K) Printed Japan
mark
shows major revised points.
1997, 2000
µPD789800
APPLICATIONS
keyboards, etc.
ORDERING INFORMATION
Part number Package 44-pin plastic 44-pin plastic LQFP
Remark
indicates code suffix.
Data Sheet U12627EJ3V0DS00
µPD789800
78K/0S SERIES DEVELOPMENT
78K/0S series products shown below. sub-series names indicated frames.
Products mass production Products under development subseries supports SMB.
Small-scale package, general-purpose applications 44-pin 42-/44-pin 30-pin 28-pin
PD789046 PD789026 PD789074 PD789014
PD789074 with subsystem clock PD789014 with enhanced timer function expanded PD789026 with enhanced timer function
On-chip UART capable low-voltage (1.8 operation
Small-scale package, general-purpose applications function 44-pin 44-pin 30-pin 30-pin 30-pin 30-pin 30-pin 30-pin
PD789177 PD789167 PD789156 µPD789146 PD789134A PD789124A PD789114A PD789104A
Inverter control
PD789177Y PD789167Y
PD789167 with enhanced converter PD789104A with enhanced timer PD789146 with enhanced converter PD789104A with EEPROMadded PD789124A with enhanced oscillation version µPD789104A PD789104A with enhanced converter PD789026 with converter multiplier
44-pin 78K/0S Series 52-pin
PD789842
On-chip inverter controller UART
drive
PD789871
Total display outputs:
drive 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin
PD789488 PD789417A µPD789407A PD789456 PD789446 PD789436 PD789426 PD789316 PD789306
drive
converter internal voltage boosting method PD789407A with enhanced converter converter resistance division method PD789446 with enhanced converter converter internal voltage boosting method PD789426 with enhanced converter converter internal voltage boosting method oscillation version µPD789306 Internal voltage boosting method
144-pin 88-pin
PD789835 PD789830
ASSP
Segment/common outputs: pins Segment: pins, common: pins
80-pin 52-pin 52-pin 44-pin 44-pin 20-pin 20-pin
PD789477 PD789467 PD789327 PD789800 PD789840 PD789861 PD789860
PD789488 with remote controller receive circuit added resistance division method remote controller. On-chip converter internal voltage boosting method remote controller. On-chip resistance division method keyboard. On-chip function pad. On-chip oscillation version µPD789860 keyless entry. On-chip return circuit
Data Sheet U12627EJ3V0DS00
µPD789800
major functional differences among subseries listed below.
Function Capacity 8-Bit 16-Bit Watch 8-Bit 10-Bit Serial Interface Value Remark
Subseries Name Small scale, generalpurpose applications Smallscale, generalpurpose applications function
µPD789046 µPD789026 µPD789074 µPD789014 µPD789177 µPD789167 µPD789156 µPD789146 µPD789134A µPD789124A µPD789114A µPD789104A µPD789842
(UART:
Note (UART: oscillation version (UART: (UART: (UART: On-chip EEPROM oscillation version (UART:
Inverter control
drive µPD789871 drive µPD789488
µPD789417A µPD789407A
µPD789456 µPD789446 µPD789436 µPD789426 µPD789316 µPD789306
drive ASSP
µPD789835 µPD789830 µPD789477 µPD789467 µPD789327 µPD789800 µPD789840 µPD789861
(UART:
(UART: (USB:
On-chip
oscillation version, onchip EEPROM On-chip EEPROM
µPD789860
Note 10-bit timer: channel
Data Sheet U12627EJ3V0DS00
µPD789800
FUNCTIONS
Item Internal memory High-speed Minimum instruction execution time General-purpose register Instruction bytes bytes 0.33 µs/1.33 (when system clock operates MHz) bits registers 16-bit operation manipulation (set, reset, test) etc. CMOS I/O: pins these, pins switched N-ch open-drain pins.) (Universal Serial Bus) function channel Three-wire serial mode channel 8-bit timer channel 8-bit timer/event counter channel Watchdog timer channel Incorporated (VREG ±0.3 Maskable Nonmaskable Internal: external: Internal: -40°C +85°C (when operating) +70°C (when operating) 44-pin plastic 44-pin plastic LQFP Function
ports
Serial interface
Timer
Regulator Vector interrupt source Power supply voltage Operating ambient temperature
Package
Data Sheet U12627EJ3V0DS00
µPD789800
CONTENTS
CONFIGURATION (TOP VIEW) BLOCK DIAGRAM FUNCTIONS
Port Pins. Non-Port Pins. Input/Output Circuits Handling Unused Pins
MEMORY SPACE PERIPHERAL HARDWARE FUNCTIONS
Ports Clock Generator. Timer. Serial Interface. Regulator. Return Signal Detection Circuit
INTERRUPT FUNCTION.21 STANDBY FUNCTION RESET FUNCTION INSTRUCTION OVERVIEW
Legend. Operations.
ELECTRICAL CHARACTERISTICS.31 PACKAGE DRAWINGS RECOMMENDED SOLDERING CONDITIONS.41 APPENDIX DEVELOPMENT TOOLS.42 APPENDIX RELATED DOCUMENTS
Data Sheet U12627EJ3V0DS00
µPD789800
CONFIGURATION (TOP VIEW)
44-pin plastic
44-pin plastic LQFP
VDD1 VSS1
P26/TI01/TO01/INTP0
P20/SCK10
P21/SO10
P22/SI10
USBDP USBDM REGC VDD0 VSS0 RESET P40/KR00 P41/KR01
P47/KR07
P46/KR06
P45/KR05
P44/KR04
P43/KR03
Caution
Connect (Internally Connected) directly VSS0 VSS1 pin. Internally connected SCK10 SI10 SO10 TI01 TO01 VDD0, VDD1 VSS0, VSS1 Serial clock input/output Serial data input Serial data output Timer input Timer output Power supply Ground Crystal
INTP0 Interrupt from peripherals KR00 KR07 return P00-P07 P10-P17 P20-P26 P40-P47 RESET REGC connection Port Port Port Port Reset Voltage regulator function
USBDM, USBDP Universal serial data
P42/KR02
Data Sheet U12627EJ3V0DS00
µPD789800
BLOCK DIAGRAM
KR00/P40-KR07/P47
RETURN0
8-bit TIMER00 PORT TI01/TO01/P26 8-bit TIMER/ EVENT COUNTER01 78K/0S CORE PORT WATCHDOG TIMER PORT REGC REGULATOR VREG USBDM USBDP SCK10/P20 SO10/P21 SI10/P22 INTP0/P26 FUNCTION0 RESET PORT P40-P47 P20-P26 P10-P17 P00-P07
SERIAL INTERFACE10 VDD0 VDD1 VSS0 VSS1
SYSTEM CONTROL
INTERRUPT CONTROL
Data Sheet U12627EJ3V0DS00
µPD789800
FUNCTIONS Port Pins
Port 8-bit input/output port Input output specifiable bit. When used input port, on-chip pull-up resistors specified software. CMOS output N-ch open-drain output specifiable 8-bit units. P10-P17 Port 8-bit input/output port Input output specifiable bit. When used input port, on-chip pull-up resistors specified software. CMOS output N-ch open-drain output specifiable 8-bit units. P23-P25 P40-P47 Port 7-bit input/output port Input output specifiable bit. When used input port, on-chip pull-up resistors specified software. Only P26, CMOS output N-ch open-drain output specifiable bit. Port 8-bit input/output port Input output specifiable bit. When used input port, on-chip pull-up resistors specified software. Input SI10 INTP0/TI01/TO01
KR00 KR07
name P00-P07
Function
When reset Input
Also used
Input
Input
SCK10
SO10
Data Sheet U12627EJ3V0DS00
µPD789800
Non-Port Pins
name INTP0
KR00 KR07
Input Input
Function External interrupt request input which effective edges (rising and/or falling edges) specified Input detecting return signals Internally generated power supply driving driver/receiver. Connect this through 220- resistor 0.1-µF capacitor. System reset input Serial clock input/output serial interface Serial data input serial interface Serial data output serial interface External count clock input 8-bit timer/event counter Timer output from 8-bit timer/event counter Serial data input/output (negative side) function. pull-up resistor (1.5 USBDM must connected REGC pin. Serial data input/output (positive side) function Connected crystal system clock oscillator
When reset Input Input
Also used P26/TI01/TO01 P40-P47
REGC
RESET SCK10
Input Input Output Input Output
Input Input Input Input Input Input Input
SI10 SO10 TI01 TO01 USBDM
P26/INTP0/TO01 P26/INTP0/TI01
USBDP VDD0 VDD1 VSS0 VSS1
Input
Input Input
Positive supply voltage ports Positive supply voltage circuits other than ports Ground potential ports Ground potential circuits other than ports Internally connected. Connect this directly VSS0. internally connected. Leave this open.
Data Sheet U12627EJ3V0DS00
µPD789800
Input/Output Circuits Handling Unused Pins
Table lists types input/output circuits each explains unused pins handled. Figure shows configuration each type input/output circuit. Table 3-1. Type Input/Output Circuit Each
name P00-P07 P10-P17 P20/ SCK10 P21/SO10 P22/SI10 P23, P26/INTP0/TI01/TO01 P40/ KR00 -P47/ KR07 USBDM USBDP
RESET
circuit type
Input
Recommended connection unused pins Connect these pins separately VDD0, VDD1, VSS0, VSS1 respective resistors. Output Leave these pins open.
24-A Connect this REGC pin. Connect this VSS0 VSS1 resistors. Input Connect this directly VSS0 VSS1. Leave this open. Connect this USBDM pin.
REGC
Data Sheet U12627EJ3V0DS00
µPD789800
Figure 3-1. Input/Output Circuits
Type Type
VDD0
Pull-up enable P-ch Output data VDD0
P-ch
P-ch IN/OUT
Schmitt trigger input with hysteresis
Output disable VSS0
N-ch
Type Pull-up enable P-ch Output data VDD0 P-ch
VDD0
Type 24-A
P-ch VREG
TXDXP RXDX IN/OUT TXDXN
P-ch IN/OUT N-ch
Output disable VSS0 Input enable
N-ch VSS0
Type VDD0 Pull-up enable VDD0 Output data P-ch IN/OUT Output disable P-ch
N-ch VSS0
Data Sheet U12627EJ3V0DS00
µPD789800
MEMORY SPACE
Figure shows memory µPD789800. Figure 4-1. Memory
FFFFH Special function register bits FF00H FEFFH Internal high-speed bits FE00H FDFFH
Data memory space
Unusable
1FFFH 2000H 1FFFH Program area
Program memory space
Internal 8,192 bits
0080H 007FH CALLT table area 0040H 003FH Program area 001AH 0019H Vector table area
0000H
0000H
Data Sheet U12627EJ3V0DS00
µPD789800
PERIPHERAL HARDWARE FUNCTIONS Ports
ports listed below. CMOS input/output ports (ports port pins these, pins (pins ports P25, P26) switched N-ch open-drain input/output pins. Table 5-1. Port Functions
Name Port name P00-P07 Function Input/output port. Input output specifiable bit. When used input port, on-chip pull-up resistors specified software. CMOS output N-ch open-drain output specifiable 8-bit units. Input/output port. Input output specifiable bit. When used input port, on-chip pull-up resistors specified software. CMOS output N-ch open-drain output specifiable 8-bit units. Input/output port. Input output specifiable bit. When used input port, on-chip pull-up resistors specified software. Input/output port. Input output specifiable bit. When used input port, on-chip pull-up resistors specified software. Only P26, CMOS output N-ch open-drain output specifiable. Input/output port. Input output specifiable bit. When used input port, on-chip pull-up resistors specified software.
Port
P10-P17
Port
P20-P24
P25,
Port
P40-P47
Clock Generator
µPD789800 on-chip system clock generator. possible change minimum instruction execution time. 0.33 1.33 (when system clock operates MHz) Figure 5-1. Block Diagram Clock Generator
Prescaler
System clock oscillator
Clock peripheral hardware Prescaler
Selector
Standby control circuit
Wait control circuit
clock (fCPU)
STOP
Data Sheet U12627EJ3V0DS00
µPD789800
Timer
µPD789800 three on-chip timers. 8-bit timer Watchdog timer channel channel Table 5-2. Timer Operation
8-bit timer Operation mode Interval timer External event counter Function Timer output Square wave output Interrupt request channel 8-bit timer/event counter channel channel output output Watchdog timer channel
8-bit timer/event counter channel
Figure 5-2. Block Diagram 8-Bit Timer
Internal
8-bit compare register (CR00) Match INTTM00
Selector
fX/2
fX/29
8-bit timer counter (TM00) Clear
Internal
Data Sheet U12627EJ3V0DS00
µPD789800
Figure 5-3. Block Diagram 8-Bit Timer/Event Counter
Internal
8-bit compare register (CR01) Match INTTM01 fX/28 TI01/P26/ INTP0/TO01
Selector
fX/2
8-bit timer counter (TM01) Clear
Output control circuit
TO01/P26/INTP0/ TI01
Internal
Figure 5-4. Block Diagram Watchdog Timer
Prescaler Clear INTWDT maskable interrupt request RESET INTWDT nonmaskable interrupt request
7-bit counter
Serial Interface
channels serial interface chip. function µPD789800 supports Mbps transfer speed with system clock incorporates NRZI (Non Return Zero Invert) decode/encode function, stuffing function, (Cyclic Redundancy Check) function specified (Universal Serial Bus) communication protocol. Figure shows block diagram. Serial interface (SIO10) SIO10 following modes: Operation stop mode Three-wire serial mode (The first switched between LSB.) Figure shows block diagram.
Data Sheet U12627EJ3V0DS00
Control circuit
Selector
µPD789800
Figure 5-5. Block Diagram Function
Internal Transmit reservation registers (HTXRSV, DTXRSV)
receiver enable register (USBMOD)
Data/handshake packet receive mode register (URXMOD)
Counter
Remote wake-up control register (REMWUP)
Transmit/receive pointers (USBPOB, USBPOW) Each handshake packet SYNC packet NRZI encoder Output latch Transmit buffer
USBDP
Selector
generation/detection resume reset detection control
USBDM
SYNC detection/USB clock generator clock
Receive bank switching detection buffer
Receive buffer
stuff/bit strip control circuit Overflow
timer (7-bit counter) Start
INTUSB
Compare register INTUSBRD ENDP detection circuit circuit
timer start reservation control register (USBTCL)
Receive result storage register (DRXRSL)
Packet receive status register (RXSTAT)
Internal
Data Sheet U12627EJ3V0DS00
µPD789800
Figure 5-6. Block Diagram Serial Interface
Internal
SI10/P22
Serial shift register (SIO10)
SO10/P21 SCK10/P20 Serial clock counter Interrupt request signal generator INTCSI10
Selector
Selector
Serial clock control circuit
fX/22 fX/23
Regulator
µPD789800 incorporates regulator which powers driver/receiver. features follows: Generates VREG (3.3 ±0.3 from VDD0 VDD1 (4.0 outputs REGC pin. Supports power-saving mode, reducing current dissipation during STOP mode. Figure 5-7. Block Diagram Regulator Driver/Receiver
PD789800
VDD0 REGC VSS0 VDD0
Regulator
VREG
TXDP TXDM TXEN RXEN VSS0 USBDM driver/ receiver
USBDP
Cautions settle VREG voltage, connect REGC 220- resistor 0.1-µF capacitor. Connect pull-up resistor (1.5 USBDM pin, REGC pin.
Data Sheet U12627EJ3V0DS00
µPD789800
Return Signal Detection Circuit
µPD789800 incorporates return signal detection circuit that detect return signals input P40/KR00-P47/KR07 pins. Specify whether detect return signals P40/KR00-P47/KR07 pins means return mode register (KRM00). Inhibit interrupts before setting KRM00 (see Caution KRM00 1-bit memory operation instruction 8-bit memory operation instruction. (KRM000) corresponds KR00/P40-KR03/P43 pins. setting common these four pins. Bits (KRM004-KRM007) correspond KR04/P44-KR07/P47 pins respectively bit. Inputting RESET signal clears KRM00 00H. Figure shows format return mode register Figure shows block diagram falling edge detection circuit. Figure 5-8. Format Return Mode Register
Symbol KRM000 Address FFF5H When reset
KRM00 KRM007 KRM006 KRM005 KRM004
KRM00n detection
Selection return signal detection P4n/KR0n
Detection (detecting falling edges P4n/KR0n signals)
KRM000 detection
Selection return signal detection P40/KR00-P43/KR03 pins
Detection (detecting falling edges P40/KR00-P43/KR03 signals)
Cautions sure bits When KRM00 pull-up resistor forcibly connected corresponding pin. However, when placed output mode, pull-up resistor disconnected. Before setting KRM00, inhibit interrupts (set interrupt mask flag register (MK0) (KRMK00 After setting KRM00, clear interrupt request flag register (IF0) (KRIF00 then permit interrupts (clear (KRMK00 0)).
Data Sheet U12627EJ3V0DS00
µPD789800
Figure 5-9. Block Diagram Falling Edge Detection Circuit
return mode register (KRM00)Note
P40/KR00 P41/KR01
Selector
P42/KR02 P43/KR03 P44/KR04 P45/KR05 P46/KR06 P47/KR07
Falling edge detection circuit
KRIF00 signal
KRMK00
Standby release signal
Note Register that selects used falling edge input
Data Sheet U12627EJ3V0DS00
µPD789800
INTERRUPT FUNCTION
There types sources interrupt function shown below. Nonmaskable interrupt: source Maskable interrupts sources Table 6-1. Interrupt Source List
Interrupt source Priority Note
Type interrupt Nonmaskable
Internal/ external Internal
Name INTWDT
Trigger Watchdog timer overflow (when watchdog timer mode selected) Watchdog timer overflow (when interval timer mode selected) timer overflow detection when token packet received detection when data/handshake packet received detection when data/handshake packet sent Detection transition from state state Detection input edge three-wire interface transmission reception Generation 8-bit timer counter match signal Generation 8-bit timer/event counter match signal Detection return signal
Vector table address 0004H
Basic configuration Note type
Maskable
INTWDT
INTUSBINTUSBRT
0006H 0008H
INTUSBRD
000AH
INTUSBST
000CH
INTUSBRE
000EH
INTP0 INTCSI10
External Internal
0010H 0012H
INTTM00
0014H
INTTM01
0016H
INTKR00
External
0018H
Notes priority order priority when multiple maskable interrupts generated simultaneously. highest priority lowest priority. Types basic configuration correspond Figure 6-1, respectively. Remark Only watchdog timer interrupt sources, non-maskable maskable (internal), selected.
Data Sheet U12627EJ3V0DS00
µPD789800
Figure 6-1. Basic Configuration Interrupt Function Internal nonmaskable interrupt
Internal
Interrupt request
Vector table address generator
Standby release signal
Internal maskable interrupt
Internal
Interrupt request
Vector table address generator
Standby release signal
External maskable interrupt
Internal
INTM0, KRM00
Interrupt request
Edge detection circuit
Vector table address generator
Standby release signal
INTM0 External interrupt mode register KRM00 return mode register Interrupt request flag Interrupt enable flag Interrupt mask flag
Data Sheet U12627EJ3V0DS00
µPD789800
STANDBY FUNCTION
standby function function reduce current consumption there kinds standby function shown below. HALT mode STOP mode Stops operating clock CPU. Intermittent operation together with normal operation reduce average current consumption. Stops oscillation system clock. Stops entire operation system clock minimizes power consumption. Figure 7-1. Standby Function
System clock operation
HALT instruction Interrupt request STOP instruction
Interrupt request HALT mode Clock supply stopped, while oscillation continues
STOP mode Oscillation system clock stopped
RESET FUNCTION
system reset following ways. External reset RESET Internal reset detection inadvertent program loop time watchdog timer
Data Sheet U12627EJ3V0DS00
µPD789800
INSTRUCTION OVERVIEW
instruction µPD789800 listed later.
Legend
9.1.1 Operand formats descriptions description made operand field each instruction conforms operand format instructions listed below (the details conform with assembly specification). more than operand format listed instruction, selected. Uppercase letters, pair used specify keywords, which must written exactly they appear. meanings these special characters follows: Immediate data specification Relative address specification Absolute address specification Indirect address specification Immediate data should described using appropriate values labels. specification values labels must accompanied pair Operand registers, expressed formats, described using both functional names etc.) absolute names (R0, other names listed Table 9-1). Table 9-1. Operand Formats Descriptions
Format saddr saddrp addr16 addr5 word byte Description (R0), (R1), (R2), (R3), (R4), (R5), (R6), (R7) (RP0), (RP1), (RP2), (RP3) Special function register symbol FE20H FF1FH: Immediate data label FE20H FF1FH: Immediate data label (even addresses only) 0000H FFFFH: Immediate data label (only even address 16-bit data transfer instructions) 0040H 007FH: Immediate data label (even addresses only) 16-bit immediate data label 8-bit immediate data label 3-bit immediate data label
Data Sheet U12627EJ3V0DS00
µPD789800
9.1.2 Descriptions operation field NMIS register (8-bit accumulator) register register register register register register register register pair (16-bit accumulator) register pair register pair register pair Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Interrupt request enable flag Flag indicate that nonmaskable interrupt being handled Contents memory location indicated parenthesized address register name Logical product (AND) Logical (OR) Exclusive Inverted data
Upper lower bits 16-bit register
addr16 16-bit immediate data label jdisp8 Signed 8-bit data (displacement value) 9.1.3 Description flag operation field (blank) change cleared cleared according result restored previous value
Data Sheet U12627EJ3V0DS00
µPD789800
Operations
Flag Mnemonic #byte saddr, #byte sfr, #byte saddr saddr, sfr, !addr16 !addr16, PSW, #byte PSW, [DE] [DE], [HL] [HL], byte] byte], saddr [DE] [HL] byte] MOVW #word saddrp saddrp,
Note Note Note
Operand
Byte
Clock byte (saddr) byte byte (saddr) (saddr) (addr16) (addr16) byte (DE) (DE) (HL) (HL) byte) byte) (saddr) (sfr) (DE) (HL) byte) word (saddrp) (saddrp)
Operation
Note
Note
Notes Except when Except when Only when Remark instruction clock cycle based clock (fCPU), specified processor clock control register (PCC).
Data Sheet U12627EJ3V0DS00
µPD789800
Flag Mnemonic XCHW #byte saddr, #byte saddr !addr16 [HL] byte] ADDC #byte saddr, #byte saddr !addr16 [HL] byte] #byte saddr, #byte saddr !addr16 [HL] byte] SUBC #byte saddr, #byte saddr !addr16 [HL] byte] #byte saddr, #byte saddr !addr16 [HL] byte] Operand
Note
Byte
Clock byte
Operation
(saddr), (saddr) byte (saddr) (addr16) (HL) byte) byte (saddr), (saddr) byte (saddr) (addr16) (HL) byte) byte (saddr), (saddr) byte (saddr) (addr16) (HL) byte) byte (saddr), (saddr) byte (saddr) (addr16) (HL) byte) byte (saddr) (saddr) byte (saddr) (addr16) (HL) byte)
Note Only when Remark instruction clock cycle based clock (fCPU), specified processor clock control register (PCC).
Data Sheet U12627EJ3V0DS00
µPD789800
Flag Mnemonic #byte saddr, #byte saddr !addr16 [HL] byte] #byte saddr, #byte saddr !addr16 [HL] byte] #byte saddr, #byte saddr !addr16 [HL] byte] ADDW SUBW CMPW #word #word #word saddr saddr INCW DECW RORC ROLC Operand Byte Clock byte (saddr) (saddr) byte (saddr) (addr16) (HL) byte) byte (saddr) (saddr) byte (saddr) (addr16) (HL) byte) byte (saddr) byte (saddr) (addr16) (HL) byte) word word word rr+1 (saddr) (saddr) rr-1 (saddr) (saddr) (CY, Am-1 (CY, Am+1 Am-1 Am+1 Operation
Remark instruction clock cycle based clock (fCPU), specified processor clock control register (PCC).
Data Sheet U12627EJ3V0DS00
µPD789800
Flag Mnemonic SET1 saddr. sfr. PSW. [HL]. CLR1 saddr. sfr. PSW. [HL]. SET1 CLR1 NOT1 CALL !addr16 Operand Byte Clock (saddr. bit) sfr. PSW. (HL). (saddr. bit) sfr. PSW. (HL). 3)H, 3)L, addr16, 1)H, 1)L, (00000000, addr5 (00000000, addr5), (SP), (SP), NMIS PSW, rpH, rpL, (SP), (SP), addr16 jdisp8 Operation
CALLT
[addr5]
RETI
PUSH
MOVW
!addr16 $addr16
Remark instruction clock cycle based clock (fCPU), specified processor clock control register (PCC).
Data Sheet U12627EJ3V0DS00
µPD789800
Flag Mnemonic $addr16 $addr16 $addr16 $addr16 saddr. bit, $addr16 Operand Byte Clock Operation jdisp8 jdisp8 jdisp8 jdisp8 jdisp8 (saddr. bit) jdisp8 sfr. jdisp8 jdisp8 PSW. jdisp8 (saddr. bit) jdisp8 sfr. jdisp8 jdisp8 PSW. then jdisp8 then jdisp8 (saddr) (saddr) then jdisp8 (saddr) Operation (Enable Interrupt) (Disable Interrupt) HALT Mode STOP Mode
sfr. bit, $addr16 bit, $addr16 PSW. bit, $addr16 saddr. bit, $addr16
sfr. bit, $addr16 bit, $addr16 PSW. bit, $addr16 DBNZ $addr16
$addr16
saddr, $addr16
HALT STOP
Remark instruction clock cycle based clock (fCPU), specified processor clock control register (PCC).
Data Sheet U12627EJ3V0DS00
µPD789800
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS 25°C)
Parameter Supply voltage Input voltage Output voltage Output high current Symbol Each Total pins Output current Each Total pins Operating ambient temperature Storage temperature Tstg Conditions Rated value -0.3 +6.5 -0.3 -0.3 +150 Unit
Caution
Absolute maximum ratings rated values beyond which physical damage will caused product; rated value parameters above table exceeded, even momentarily, quality product deteriorate. Always product within rated values.
Remark characteristics dual-function differ between port function secondary function, unless otherwise stated.
Data Sheet U12627EJ3V0DS00
µPD789800
CHARACTERISTICS SYSTEM CLOCK OSCILLATION CIRCUIT -40°C +85°C,
Recommended circuit
Resonator Crystal
Parameter Oscillator frequency (fX)
Note
Conditions
MIN.
TYP.
MAX.
Unit
Oscillation settling time
Note
External clock
input frequency (fX)
Note
OPEN
input high/low level width (tXH, tXL)
Notes Only characteristics oscillation circuit indicated. characteristics instruction execution time.
description
Time required oscillation settle once reset sequence ends STOP mode deselected. resonator that settle oscillation before oscillation settling time expires. Caution When using system clock oscillation circuit, observe following conditions wiring that section enclosed dotted lines above diagrams, avoid influence wiring capacitance. Keep wiring short possible. allow signal wires cross another. Keep wiring away from wires that carry high, non-stable current. Keep grounding point capacitors same level VSS0. connect grounding point grounding wire that carries high current. extract signal from oscillation circuit. Remark resonator selection oscillator constant, customers requested either evaluate oscillation themselves apply resonator manufacturer evaluation.
Data Sheet U12627EJ3V0DS00
µPD789800
CHARACTERISTICS -40°C +85°C,
Parameter Output high current Output current Input high voltage Symbol VIH1 VIH2 VIH3 VIH4 Input voltage VIL1 VIL2 VIL3 VIL4 Output high voltage VOH1 VOH2 Output voltage VOL1 VOL2 High-level input leakage current ILIH1 ILIH2 ILIH3 Low-level input leakage current ILIL1 ILIL2 ILIL3 High-level output leakage current Low-level output leakage current Software pull-up resistor Regulator output voltage Note Supply current ILOH ILOL VREG IDD1 IDD2 IDD3 Each Total pins Each Total pins P00-P07, P10-P17 RESET, P20-P26, P40-P47 USBDM, USBDP +70°C P00-P07, P10-P17 RESET, P20, P22, P40-P47 USBDM, USBDP +70°C Pins other than USBDM USBDP USBDM, USBDP +70°C, Note (connected VSS) Pins other than USBDM USBDP USBDM, USBDP +70°C, Note (connected VDD) Pins other than USBDM, USBDP USBDM, USBDP +70°C Pins other than USBDM, USBDP USBDM, USBDP +70°C 6.0-MHz crystal oscillation (operating mode) 6.0-MHz crystal oscillation (HALT mode) STOP mode
Note Note
Conditions
MIN.
TYP.
MAX.
Unit
0.7VDD 0.8VDD
0.3VDD 0.2VDD
VREG VREG
When function disabled When function enabled +70°C)
Notes resistor connected line. power supply current does include current flowing through on-chip pull-up resistor. During high-speed mode operation (when processor clock control register (PCC) cleared 00H) Remark characteristics dual-function differ between port function secondary function, unless otherwise stated.
Data Sheet U12627EJ3V0DS00
µPD789800
CHARACTERISTICS Basic operations -40°C +85°C,
Parameter Symbol Conditions When MHz) When MHz) MIN. 0.333 1.333 TYP. 0.333 1.333 MAX. 0.333 1.333 Unit
Cycle time (minimum instruction execution time)
TI01 input frequency
TI01 input high/low tTIH, tTIL level width Interrupt input high/low level width
RESET input
tINTH, tINTL INTP0
tRSL
level width
Serial interface function +70°C,
Parameter USBDM USBDP rise time USBDM USBDP fall time matching Differential output signal cross-over point Data transfer rate Transmission differential signal jitter Symbol
Note
Conditions
MIN.
TYP.
MAX.
Unit
Note
Note
tRFM VCRS tR/tF
Note
tDRATE
When microcontroller operates system clock (fX) Upon transferring next Upon transferring following next
Mbps
tUDJ1 tUDJ2
-150 1.25
1.33
1.50
Transmission tEOPT1 width Reception width Reception reset width tEOPR1 tEOPR2 tURES1 tURES2 width eliminated width detected reset width eliminated reset width detected
Note capacitance USBDM USBDP output lines.
Data Sheet U12627EJ3V0DS00
µPD789800
Three-wire serial mode -40°C +85°C, SCK10 .Internal clock output (when MHz)
Parameter
SCK10 cycle time
Symbol tKCY1 When TPS100 When TPS100
Note
Conditions
MIN. 1,333
TYP. 1,333
MAX. 1,333
Unit
Note
SCK10 high/low
level width SI10 setup time SI10 hold time
tKH1, tKL1 tSIK1 tKSI1
When TPS100 When TPS100
Note
Note
Relative SCK10 Relative SCK10 When TPS100
Note
When TPS100 SO10 output dalay tKSO1 Relative SCK10
Note
Note
Notes serial operation mode register (CSIM10) capacitance output line. (ii) SCK10 .External clock output
Parameter
SCK10 cycle time SCK10 high/low
Symbol tKCY2 tKH2, tKL2 tSIK2 tKSI2 tKSO2
Conditions
MIN.
TYP.
MAX.
Unit
level width SI10 setup time SI10 hold time SO10 output delay
Relative SCK10
Note
Note capacitance output line.
Data Sheet U12627EJ3V0DS00
µPD789800
TIMING MEASUREMENT POINTS (except input function)
0.8VDD 0.2VDD Measurement points 0.8VDD 0.2VDD
CLOCK TIMING
1/fX VIH3 (MIN.) VIL3 (MAX.)
input
TIMING
1/fTI tTIL tTIH
TI01
INTERRUPT INPUT TIMING
tINTL tINTH
INTP0
RESET INPUT TIMING
tRSL
RESET
Data Sheet U12627EJ3V0DS00
µPD789800
SERIAL TRANSFER TIMING Function: USBDM USBDP rise/fall time
USBDM, USBDP 0.1VDD
0.9VDD
Transmission different signal jitter
1,333 USBDM, USBDP Next following next
tUDJ1
tUDJ2
Differential output signal cross-over point, transmission width, reception width, reception reset width
USBDM, USBDP
VCRS
tEOPT1, tEOPRm, tURESm
Three-Wire Serial Mode:
tKCYm tKLm tKHm
0.8VDD SCK10 0.2VDD
tSIKm SI10
tKSIm
Input data
tKSOm
SO10
Output data
Data Sheet U12627EJ3V0DS00
µPD789800
DATA HOLD CHARACTERISTICS DATA MEMORY VOLTAGE STOP MODE -40°C +85°C)
Item Data hold supply voltage Release signal time Oscillation settling Note time Symbol VDDDR tSREL tWAIT Reset RESET Reset interrupt request Conditions MIN. Note
TYP.
MAX.
Unit
Notes
During oscillation settling time, operations disabled prevent them from becoming unstable upon start oscillation. 212/fX, 215/fX, 217/fX selected according setting bits (OSTS0 OSTS2) oscillation settling time selection register.
Remark System clock oscillation frequency DATA HOLD TIMING (STOP mode release RESET
Internal reset operation HALT mode STOP mode Data hold mode Operating mode
VDDDR STOP instruction execution
tSREL
RESET
tWAIT
DATA HOLD TIMING (standby release signal: STOP mode release interrupt signal)
HALT mode STOP mode Data hold mode Operating mode
VDDDR STOP instruction execution Standby release signal (interrupt request)
tSREL
tWAIT
Data Sheet U12627EJ3V0DS00
µPD789800
PACKAGE DRAWINGS
44-PIN PLASTIC (10x10)
detail lead
NOTE Each lead centerline located within 0.16 true position (T.P.) maximum material condition.
ITEM
MILLIMETERS 13.2±0.2 10.0±0.2 10.0±0.2 13.2±0.2 0.37 +0.08 -0.07 0.16 (T.P.) 1.6±0.2 0.8±0.2 0.17 +0.06 -0.05 0.10 2.7±0.1 0.125±0.075 MAX. S44GB-80-3BS-2
Data Sheet U12627EJ3V0DS00
µPD789800
PLASTIC LQFP
detail lead
NOTE Each lead centerline located within 0.16 true position (T.P.) maximum material condition.
ITEM MILLIMETERS 12.0±0.2 10.0±0.2 10.0±0.2 12.0±0.2 0.37 +0.08 -0.07 (T.P.) 1.0±0.2 0.17 +0.03 -0.06 0.10 1.4±0.05 0.1±0.05 MAX. 0.6±0.15 S44GB-80-8ES-1
Data Sheet U12627EJ3V0DS00
µPD789800
RECOMMENDED SOLDERING CONDITIONS
µPD789800 should soldered mounted under conditions recommended table below. detail recommended soldering conditions, refer information document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended below, contact sales representatives. Table 12-1. Surface Mounting Type Soldering Conditions 44-pin plastic
Soldering method Infrared reflow Soldering conditions Package peak temperature: 235°C Duration: sec. max. 210°C above) Maximum allowable number reflow processes: Package peak temperature: 215°C Duration: sec. max. 200°C above) Maximum allowable number reflow processes: Solder bath temperature: 260°C max. Duration: sec. max. Number times: Once Preliminary heat temperature: 120°C max. (Package surface temperature) Terminal temperature: 300°C max. Duration: sec. max. (per device side) Symbol IR35-00-3
VP15-00-3
Wave soldering
WS60-00-1
Partial heating method
Caution
more than soldering method should avoided (except partial heating method).
44-pin plastic LQFP
Soldering method Infrared reflow Soldering conditions Package peak temperature: 235°C Duration: sec. max. 210°C above) Maximum allowable number reflow processes: Package peak temperature: 215°C Duration: sec. max. 200°C above) Maximum allowable number reflow processes: Solder bath temperature: 260°C max. Duration: sec. max. Number times: Once Preliminary heat temperature: 120°C max. (Package surface temperature) Terminal temperature: 300°C max. Duration: sec. max. (per device side) Symbol IR35-00-2
VP15-00-2
Wave soldering
WS60-00-1
Partial heating method
Caution
more than soldering method should avoided (except partial heating method).
Data Sheet U12627EJ3V0DS00
µPD789800
APPENDIX DEVELOPMENT TOOLS
following development tools available developing systems using µPD789800. LANGUAGE PROCESSING SOFTWARE
RA78K0S
Notes Notes Notes Notes
Assembler package common 78K/0S series compiler package common 78K/0S series Device file µPD789800 sub-series compiler library source file common 78K/0S series
CC78K0S
DF789801
CC78K0S-L
FLASH MEMORY WRITE TOOLS
Flashpro FA-44GB
Note Note
Dedicated flash writer Flash memory write adapter (GB-3BS type) Flash memory write adapter (GB-8ES type)
FA-44GB-8ES
DEBUGGING TOOLS (1/2)
IE-78K0S-NS In-circuit emulator IE-70000-MC-PS-B adapter IE-70000-98-IF-C Interface adapter IE-70000-CD-IF-A card interface IE-70000-PC-IF-C Interface adapter IE-70000-PCI-IF Interface adapter IE-789801-NS-EM1 Emulation board In-circuit emulator debugging hardware software application system using 78K/0S Series. Supports integrated debugger (ID78K0S-NS). Used combination with adapter, emulation probe, interface adapter connecting host machine. This adapter supplying power from outlet VAC. This adapter needed when PC-9800 series (excluding notebook models) used host machine IE-78K0S-NS. (Compatible with bus) This card interface cable needed when notebook-type personal computer used host machine IE-78K0S-NS. (Compatible with PCMCIA socket) This adapter needed when PC/AT compatibles used host machine IE-78K0S-NS. (Compatible with bus) This adapter needed when personal computer with built-in used host machine IE-78K0S-NS. Emulation board emulating peripheral hardware inherent device. Used combination with in-circuit emulator.
Notes Based PC-9800 series (Japanese Windows
Based PC/AT compatibles (Japanese/English Windows)
Based HP9000 series (HP-UX SPARCstation (SunOS Solaris NEWS
(NEWS-OSTM) Product manufactured Naito Densei Machida Mfg. Co., Ltd. (044-822-3813) Remark RA78K0S CC78K0S used combination with DF789801.
Data Sheet U12627EJ3V0DS00
µPD789800
DEBUGGING TOOLS (2/2)
NP-44GB Emulation prove EV-9200G-44 Conversion socket NP-44GB-TQ Emulation prove
Notes Notes
This probe used connect in-circuit emulator target system designed 44-pin plastic QFP. should used combination with EV-9200G-44. This conversion socket connects NP-44GB target system board designed mount 44-pin plastic (GB-3BS, GB-8ES type). This probe used connect in-circuit emulator target system designed 44-pin plastic QFP. should used combination with TGB-044SAP.
Note
TGB-044SAP Conversion socket SM78K0S
Notes Notes
This conversion socket connects NP-44GB-TQ target system board designed mount 44-pin plastic (GB-3BS, GB-8ES type). System simulator common 78K/0S series Integrated debugger common 78K/0S series Device file µPD789800 sub-series
ID78K0S-NS DF789801
Notes
REAL-TIME
MX78K0S
Notes
78K/0S series
Notes Product manufactured Naito Densei Machida Mfg. Co., Ltd. (044-822-3813) Either probe socket combination selected use. Product manufactured TOKYO ELETEC Corporation further information, consult: Tokyo Electronic Div. (TEL (03) 3820-7112), Osaka Electronic Div. (TEL (06) 6244-6672) Daimaru Kogyo Corporation. Based PC-9800 series (Japanese Windows) Based PC/AT compatibles (Japanese/English Windows) Remark SM78K0S used combination with DF789801.
Data Sheet U12627EJ3V0DS00
µPD789800
APPENDIX RELATED DOCUMENTS
DOCUMENTS RELATED DEVICES
Document name Document Japanese U12627J U12626J U12978J U11047J English This manual U12626E U12978E U11047E
µPD789800 Data Sheet
µPD78F9801 Data Sheet
µPD789800 Sub-Series User's Manual
78K/0S Series User's Manual, Instruction
DOCUMENTS RELATED DEVELOPMENT TOOLS (USER'S MANUAL)
Document name RA78K0S Assembler Package Operation Assembly Language Structured Assembly Language CC78K0S Compiler SM78K0S System Simulator PC/AT (Windows) SM78K Series System Simulator ID78K0S-NS Integrated Debugger Windows-Based IE-78K0S-NS In-circuit Emulator IE-789801-NS-EM1 Emulation Board Operation Language Reference
External Parts User Open Interface Specifications
Document Japanese U11622J U11599J U11623J U11816J U11817J U11489J U10092J U12901J U13549J U13390J English U11622E U11599E U11623E U11816E U11817E U11489E U10092E U12901E U13549E U13390E
Reference
DOCUMENTS RELATED SOFTWARE INCORPORATED INTO PRODUCT (USER'S MANUAL)
Document name 78K/0S Series MX78K0S Basic Document Japanese U12938J English U12938E
OTHER DOCUMENTS
Document name SEMICONDUCTOR SELECTION GUIDE Products Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades Semiconductor Device Semiconductor Device Reliability/Quality Control System Guide Prevent Damage Semiconductor Devices Electrostatic Discharge (ESD) Semiconductor Device Quality Control/Reliability Handbook Guide Products Related Micro-Computer: Other Companies Document Japanese X13769X C10535J C11531J C10983J C11892J C12769J U11416J C10535E C11531E C10983E C11892E English
Caution
above documents revised without notice. latest versions when design application systems.
Data Sheet U12627EJ3V0DS00
µPD789800
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
EEPROM trademark Corporation. Windows either registered trademark trademark Microsoft Corporation United States and/or other countries. PC/AT trademark Corporation. HP9000 series HP-UX trademarks Hewlett-Packard Company. SPARCstation trademark SPARC International, Inc. Solaris SunOS trademarks Microsystems, Inc. NEWS NEWS-OS trademarks SONY Corporation.
Data Sheet U12627EJ3V0DS00
µPD789800
Regional Information
Some information contained this document vary from country country. Before using product your application, pIease contact office your country obtain list authorized representatives distributors. They will verify:
Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements
addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 Fax: 01-30-67 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics (France) S.A. Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
Electronics Singapore Pte. Ltd.
United Square, Singapore Tel: 65-253-8311 Fax: 65-250-3583
Electronics Taiwan Ltd. Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
Brasil S.A.
Electron Devices Division Guarulhos-SP Brasil Tel: 55-11-6462-6810 Fax: 55-11-6462-6829
J00.7
Data Sheet U12627EJ3V0DS00
µPD789800
[MEMO]
Data Sheet U12627EJ3V0DS00
µPD789800
Some related documents preliminary versions. preliminary indicated this document.
export this product from Japan regulated Japanese government. export this product prohibited without governmental license, need which must judged customer. export re-export this product from country other than Japan also prohibited without license from that country. Please call sales representative.
Note, however, that whether related document
information this document current September, 2000. information subject change without notice. actual design-in, refer latest publications NEC's data sheets data books, etc., most up-to-date specifications semiconductor products. products and/or types available every country. Please check with sales representative availability additional information. part this document copied reproduced form means without prior written consent NEC. assumes responsibility errors that appear this document. does assume liability infringement patents, copyrights other intellectual property rights third parties arising from semiconductor products listed this document other liability arising from such products. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. assumes responsibility losses incurred customers third parties arising from these circuits, software information. While endeavours enhance quality, reliability safety semiconductor products, customers agree acknowledge that possibility defects thereof cannot eliminated entirely. minimize risks damage property injury (including death) persons arising from defects semiconductor products, customers must incorporate sufficient safety measures their design, such redundancy, fire-containment, anti-failure features. semiconductor products classified into following three quality grades: "Standard", "Special" "Specific". "Specific" quality grade applies only semiconductor products developed based customer-designated "quality assurance program" specific application. recommended applications semiconductor product depend quality grade, indicated below. Customers must check quality grade each semiconductor product before using particular application. "Standard": Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade semiconductor products "Standard" unless otherwise expressly specified NEC's data sheets data books, etc. customers wish semiconductor products applications intended NEC, they must contact sales representative advance determine NEC's willingness support given application. (Note) "NEC" used this statement means Corporation also includes majority-owned subsidiaries. "NEC semiconductor products" means semiconductor product developed manufactured defined above).

µPD789800 8-BIT SINGLE-CHIP MICROCONTROLLER µPD789800 78K/0S

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