µPD789830 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION

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µPD789830 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION

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INTEGRATED CIRCUIT
µPD789830
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
µPD789830 ASSP microcontroller 78K/0S series intended card readers. bare chip version µPD789830 also available. This microcontroller internal driver segment common) ideal products that have display such card readers. flash memory model, µPD78F9831, that operates same voltage mask model, various development tools under development. functions µPD789830 explained detail following User's Manuals. sure read these manuals when designing your system.
µPD789830 Subseries User's Manual: U13679E
78K/0S Series User's Manual Instruction: U11047E
FEATURES
Bare chip capacities
Internal display bytes bytes Internal high-speed byte
Minimum instruction execution time variable from high speed (0.4 with 5.0-MHz main system clock)
speed (122 with 32.768-kHz subsystem clock)
port: pins Serial interface (UART00): channel controller/driver
Segment signal output: pins MAX. Common signal output: pins MAX. bias mode
Timer: channels
16-bit timer 8-bit timer Watch timer channel channel channel
Watchdog timer channel
Pulse output Clock output/buzzer output return signal detector circuit Supply voltage:
information this document subject change without notice. Before using this document, please confirm that this latest version.
devices/types available every country. Please check with local representative availability additional information.
Document U13284EJ1V0DSJ1 (1st edition) Date Published October 2000 CP(K) Printed Japan
mark
shows major revised points.
1998, 1999
µPD789830
APPLICATIONS
Card readers
ORDERING INFORMATION
Part Number Package 88-pin bare chip
Remark indicates code suffix.
Data Sheet U13284EJ1V0DS00
µPD789830
Development 78K/0S series
following models available 78K/0S series. outlined part numbers indicate name subseries.
Products under mass production Products under development subseries supports SMB.
Small, general-purpose pins 42/44 pins pins
PD789046 PD789026 PD789014
PD789026 with subsystem clock added PD789014 with timer reinforced expanded
UART. Low-voltage (1.8-V) operation
Small, general-purpose 44/48 pins 44/48 pins pins pins pins pins pins pins pins pins
PD789177 PD789167 PD789156 PD789146 PD789134A PD789124A PD789114A PD789104A
PD789217AY PD789197AY PD789177Y PD789167Y
oscillation model PD789197AY PD789177 with internal EEPROMµ PD789167 with improved PD789104A with improved timer PD789146 with improved PD789104A with EEPROM added PD789124A with improved oscillation model PD789104A PD789104A with improved PD789026 with multiplier added
inverter control pins 78K/0S series pins pins pins pins pins pins pins pins pins
PD789842
driving
Internal inverter control circuit UART
PD789830 PD789417A PD789407A PD789456 PD789446 PD789436 PD789426 PD789316 PD789306
ASSP
Internal UART, PD789407A with improved PD789456 with improved PD789446 with improved PD789426 with improved display output PD789426 with improved PD789306 with added oscillation model PD789306 Basic subseries driving
pins pins pins pins
PD789800 PD789840 PD789861 PD789860
keyboard. Internal function pad. Internal oscillation model µPD789860 keyless entry. Internal return circuit
Data Sheet U13284EJ1V0DS00
µPD789830
major differences between subseries shown below.
Function Subseries Name Value
Capacity
Timer 8-bit 16-bit Watch
8-bit
10-bit
Serial Interface
Remark
Small, µPD789046 generalµPD789026 K-16 purpose µPD789014 Small, µPD789177 K-24 generalµPD789167 purpose µPD789156 K-16
(UART:1
pins
pins (UART: pins pins Internal EEPROM oscillation version (UART: pins
µPD789146 µPD789134A µPD789124A µPD789114A µPD789104A
inverter control
µPD789842 K-16
Note
µPD789830 driving µPD789417A K-24
(UART: pins pins
µPD789407A
µPD789456 K-16 µPD789446 µPD789436 µPD789426 µPD789316 µPD789306
ASSP
(UART: pins oscillation version pins (UART: pins
µPD789800 µPD789840 µPD789861 µPD789860
(USB:
pins pins pins
oscillation version
Note 10-bit timer: channel
Data Sheet U13284EJ1V0DS00
µPD789830
FUNCTIONAL OUTLINE
Item Internal memory High-speed display Minimum instruction execution time bytes bytes bytes µs/1.6 (main system clock: MHz) (subsystem clock: 32.768 kHz) bits registers 16-bit operation manipulation (set, reset, test), etc. Total pins pins CMOS N-ch open drain UART mode: channel Segment signal output pins max. Common signal output pins bias mode 16-bit timer 8-bit timer Watch timer Watchdog timer channel channel channel channel Function
General-purpose register Instruction
port
Serial interface controller/driver
Timers
Pulse output Vectored interrupt source Supply voltage Operating temperature Package Maskable Non-maskable
Clock output/buzzer output Internal: external: Internal: 88-pin bare chip
Data Sheet U13284EJ1V0DS00
µPD789830
CONTENTS
CONFIGURATION (Top View).
BLOCK DIAGRAM FUNCTION LIST. Port Pins Pins Other Than Port Pins Circuit Type Each Recommended Connections Unused Pins
ARCHITECTURE PERIPHERAL HARDWARE FUNCTIONS Ports. Clock Generation Circuit Timer. Clock Output Circuit Serial Interface. Controller/Driver.
INTERRUPT FUNCTIONS. STANDBY FUNCTION RESET FUNCTION. OUTLINE INSTRUCTION Conventions Operation List.
ELECTRICAL SPECIFICATIONS APPENDIX DEVELOPMENT TOOLS. APPENDIX RELATED DOCUMENTS
Data Sheet U13284EJ1V0DS00
µPD789830
CONFIGURATION (Top View)
88-pin bare chip
Minimum interval 110.04 Opening 80.04
axis
axis
2.85
2.85
coordinates (unit: center coordinates) (1/2)
Name COM14 COM15 Axis -1085.40 -975.40 -865.30 -755.30 -645.20 -535.20 -425.20 Axis -1303.90 -1303.90 -1303.90 -1303.90 -1303.90 -1303.90 -1303.90 Name Axis -315.10 -205.10 -95.00 15.00 125.00 235.10 345.10 Axis -1303.90 -1303.90 -1303.90 -1303.90 -1303.90 -1303.90 -1303.90
Data Sheet U13284EJ1V0DS00
µPD789830
coordinates (unit: center coordinates) (2/2)
Name P57/S32 P56/S33 P55/S34 P54/S35 P53/S36 P52/S37 P51/S38 P50/S39 VDD1 VSS1 Axis 455.20 565.20 675.20 785.30 895.30 1005.40 1115.40 1303.90 1303.90 1303.90 1303.90 1303.90 1303.90 1303.90 1303.90 1303.90 1303.90 1303.90 1303.90 1303.90 1303.90 1303.90 1303.90 1303.90 1303.90 1303.90 1303.90 1303.90 1303.90 1303.90 1294.30 1039.80 929.80 819.70 709.70 599.60 489.60 Axis -1303.90 -1303.90 -1303.90 -1303.90 -1303.90 -1303.90 -1303.90 -1227.00 -1117.00 -1006.90 -896.90 -786.80 -676.80 -566.80 -456.70 -346.70 -236.60 -126.60 -16.60 93.50 203.50 313.60 423.60 533.60 643.70 753.70 863.80 973.80 1083.80 1193.90 1303.90 1303.90 1303.90 1303.90 1303.90 1303.90 1303.90 Name RESET VSS0 VDD0 P26/RxD00 P25/TxD00 P23/PCL P22/INTP2/BUZ P21/INTP1 P20/INTP0 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 Axis 379.60 269.50 159.50 49.40 -60.60 -170.60 -280.70 -390.70 -500.80 -610.80 -720.80 -830.90 -940.90 -1051.00 -1303.90 -1303.90 -1303.90 -1303.90 -1303.90 -1303.90 -1303.90 -1303.90 -1303.90 -1303.90 -1303.90 -1303.90 -1303.90 -1303.90 -1303.90 -1303.90 -1303.90 -1303.90 -1303.90 -1303.90 -1303.90 -1303.90 -1303.90 Axis 1303.90 1303.90 1303.90 1303.90 1303.90 1303.90 1303.90 1303.90 1303.90 1303.90 1303.90 1303.90 1303.90 1303.90 1303.90 1193.90 1083.80 973.80 863.80 687.90 577.90 467.80 357.80 247.70 137.70 27.70 -82.40 -192.40 -302.50 -412.50 -522.50 -632.60 -742.60 -852.70 -962.70 -1072.70 -1182.80
Data Sheet U13284EJ1V0DS00
µPD789830
COM0-COM15 INTP0-INTP2 P00-P07 P10, P20-P26 P30-P34 P50-P57 Buzzer Clock Common Output Internally Connected Interrupt from Peripherals Port0 Port1 Port2 Port3 Port5 RESET RxD00 S0-S39 TxD00 VDD0, VDD1 VSS0, VSS1 XT1, Programming Clock Reset Receive Data Segment Output Transmit Data Power Supply Ground Crystal (Main system Clock) Crystal (Subsystem Clock)
Data Sheet U13284EJ1V0DS00
µPD789830
BLOCK DIAGRAM
8-bit TIMER00 PORT0 P00-P07
16-bit TIMER40 78K/0S CORE
PORT1
P10,P11
PCL/P23 BUZ/P22 /INTP2 RxD00/P26 TxD00/P25
PCL/BUZZER UNIT (PBU)
PORT2
P20-P26
UART00
PORT3
P30-P34
WATCH TIMER WATCHDOG TIMER S0-S31 S32/P57-S39/P50 COM0-COM15
PORT5
P50-P57
SYSTEM CONTROL CONTROLLER/ DRIVER VDD0 VSS0 VDD1 VSS1 INTERRUPT CONTROL
RESET INTP0/P20 INTP1/P21 INTP2/BUZ/P22
Data Sheet U13284EJ1V0DS00
µPD789830
FUNCTION LIST Port Pins
Name P00-P07 Port 8-bit port. input output mode 1-bit units. this port input port, internal pull-up resistor connected software. P10, Port 2-bit port. input output mode 1-bit units. this port input port, internal pull-up resistor connected software. P30-P34 Port 5-bit port. input output mode 1-bit units. this port input port, internal pull-up resistor connected software. P50-P57 Port 8-bit port. input output mode 1-bit units. Input S39-S32 Input TxD00 RxD00 Port 7-bit port. input output mode 1-bit units. N-ch open-drain port pin. Input INTP0 INTP1 INTP2/BUZ Input Function Reset Input Shared with:
Data Sheet U13284EJ1V0DS00
µPD789830
Pins Other Than Port Pins
Name INTP0 INTP1 INTP2 RxD00 TxD00 S0-S31 S32-S39 COM0COM15 RESET VDD0 VDD1 VSS0 VSS1 Input Input System reset input Positive power supply ports Positive power supply (except ports) Ground ports Ground (except ports) Internally connected. Directly connect this VSS0 VSS1. Output Common signal output controller/driver Output Crystal connection subsystem clock oscillation Input Input Output Output Output Output Serial data input asynchronous serial interface Serial data output asynchronous serial interface Buzzer output Clock output Segment signal output controller/driver Input Input Input Input Output Input Function External interrupt input whose valid edge specified (rising edge, falling edge, both rising falling edges) Reset Input Shared with: P22/BUZ P22/INTP2 P57-P50
Input
Crystal connection main system clock oscillation
Data Sheet U13284EJ1V0DS00
µPD789830
Circuit Type Each Recommended Connections Unused Pins
Table shows circuit type each recommended connections unused pins. configuration circuit each type, refer Figure 3-1. Table 3-1. Circuit Type Each Recommended Connections Unused Pins
Name P00-P07 P10, P20/INTP0 P21/INTP1 P22/INTP2/BUZ P23/PCL 13-AB Input Individually connected VDD0 VDD1 resistor. Circuit Type Input Recommended Connections Unused Pins Individually connected VDD0/VDD1 VSS0/VSS1 resistor.
Output Leave unconnected.
Output Leave unconnected. P25/TxD00 P26/RxD00 P30-P34 P50/S39-P57/S32 S0-S31 COM0-COM15 RESET 17-I 17-H 18-C Input Input Connected VSS0 VSS1. Connected VSS0 VSS1. Leave unconnected. Output Leave unconnected. Input Individually connected VDD0/VDD1 VSS0/VSS1 resistor.
Output Leave unconnected.
Data Sheet U13284EJ1V0DS00
µPD789830
Figure 3-1. Circuit Type Each (1/2)
Type
Type
VDD0
Pull-up enable VDD0 Data P-ch
P-ch
IN/OUT Schmitt-trigger input with hysteresis characteristics Output disable VSS0 N-ch
Type
VDD0
Type
Pull-up enable VDD0 Data P-ch
P-ch Data
VDD0 P-ch IN/OUT IN/OUT Output disable VSS0 N-ch
Output disable VSS0 Input enable Type
N-ch
Type 13-AB
VDD0 Data P-ch IN/OUT Output disable VSS0 Input enable Port Read Middle-high voltage input buffer P-ch N-ch Data Output disable N-ch VSS0 VDD0
IN/OUT
Data Sheet U13284EJ1V0DS00
µPD789830
Figure 3-1. Circuit Type Each (2/2)
Type feedback cut-off Type 17-I VDD0 Data P-ch IN/OUT P-ch Output disable VSS0 Input enable VLC0 Type 17-H VLC0 VLC3 P-ch N-ch P-ch N-ch P-ch data VLC2 N-ch VSS1 Type 18-C VLC0 VLC1 P-ch N-ch P-ch N-ch P-ch data VLC4 N-ch VSS1 P-ch N-ch N-ch N-ch P-ch P-ch N-ch N-ch N-ch P-ch VLC3 P-ch N-ch P-ch N-ch P-ch N-ch N-ch
data VLC2 P-ch N-ch
N-ch
P-ch
N-ch VSS1
Data Sheet U13284EJ1V0DS00
µPD789830
ARCHITECTURE
µPD789830 access memory space bytes. Figure shows memory map. Figure Memory
FFFFH Special function register bits FF00H FEFFH Internal high-speed 1024 bits
FB00H FAFFH FA50H FA4FH Data memory space FA00H F9FFH 6000H 5FFFH
Cannot used display bits 5FFFH Cannot used
Program area
Program memory space
Internal 24576 bits
0080H 007FH CALLT table area 0040H 003FH Program area 0020H 001FH Vector table area
0000H
0000H
Data Sheet U13284EJ1V0DS00
µPD789830
PERIPHERAL HARDWARE FUNCTIONS Ports
µPD789830 following types ports. CMOS Total pins pins Table 5-1. Port Functions
Name Port Name P00-P07 Function port. input output mode 1-bit units. When this port used input port, internal pull-up resistor connected software. port. input output mode 1-bit units. When this port used input port, internal pull-up resistor connected software. port. input output mode 1-bit units. N-ch open-drain port. port. input output mode 1-bit units. When this port used input port, internal pull-up resistor connected software. port. input output mode 1-bit units.
N-ch open-drain
Port
P10,
Port
P20-P26
Port
P30-P34
Port
P50-P57
Clock Generation Circuit
circuit that generates system clock provided. Moreover, minimum instruction execution time changed follows: µs/1.6 (main system clock: MHz) (subsystem clock: 32.768 kHz) Figure 5-1. Block Diagram Clock Generation Circuit
Subsystem clock oscillator
Watch timer Clock output circuit controller/driver Prescaler
Main system clock oscillator
Clock peripheral hardware Prescaler
Selector
Standby control circuit
Wait control circuit
clock (fCPU)
STOP
Data Sheet U13284EJ1V0DS00
µPD789830
Timer
following four timer channels provided: 16-bit timer 8-bit timer Watch timer Watchdog timer channel channel channel channel
Figure 5-2. Block Diagram 16-Bit Timer
Overflow control circuit
INTTM41
Clock control circuit
fX/22 fX/25 fX/210
16-bit timer/counter (TM40) Coincidence Clear
INTTM40 INTTM4
16-bit compare register (CR40)
Internal
Figure 5-3. Block Diagram 8-Bit Timer
Internal
8-bit compare register (CR00) Coincidence
INTTM00
Selector
fX/25
8-bit timer/ counter (TM00)
Clear
Internal
Data Sheet U13284EJ1V0DS00
µPD789830
Figure 5-4. Block Diagram Watch Timer
Clear
Selector
fX/27
9-bit prescaler
Selector
5-bit counter Clear
INTWT
INTWTI
WTM0Note
Note watch timer mode control register (WTM) Figure 5-5. Block Diagram Watchdog Timer
Prescaler RUNNote INTWDT maskable interrupt request Control circuit RESET INTWDT non-maskable interrupt request
Selector
Clear 7-bit counter
Note watchdog timer mode register (WDTM)
Data Sheet U13284EJ1V0DS00
µPD789830
Clock Output Circuit
clock output circuit following functions: output Outputs pulse clock PCL/P23.
Buzzer output Outputs buzzer frequency BUZ/P22/INTP2 Figure 5-6. Block Diagram Clock Output Circuit
Selector
Selector
fX/29 fX/2
Output control circuit
Divider
BUZ/P22 /INTP2
fX/2 fX/2
Serial Interface
serial interface (UART00) following modes: Operation stop mode Asyncronous serial interface (UART) mode Figure 5-7. Block Diagram Serial Interface (UART00)
Internal Receive buffer register (RXB00)
Clock control circuit
PCL/P23
Selector
TXE00 RXE00 PS001 PS000 CL00 SL00 ISRM00 Asynchronous serial interface status register (ASIS00) Transmit shift register (TXS00) Asynchronous serial interface mode register (ASIM00)
P26/RXD00
Receive shift PE00 FE00 OVE00 register (RXS00)
P25/TXD00 Receive control circuit (parity check) INTSER00 INTSR00 Transmit control circuit (parity append) Baud rate generator 5-bit prescaler INTST00 fX/2-fX/2
Data Sheet U13284EJ1V0DS00
µPD789830
Controller/Driver
controller/driver following functions: Automatically output segment common signals automatically reading display data memory. Operates display mode 1/16 duty (1/5 bias). Maximum number display pixels: segment common) Four frame frequencies selectable segment signal output pins through S39) common signal output pins (COM0 through COM15). Eight segment signal output pins also used port pins (P50/S39 through P57/S32) 1-bit units. also operate with subsystem clock. Figure 5-8. Block Diagram Controller/Driver
Internal
fX/27 fX/28 fX/2
Selector
fCLK fCLK
Prescaler fCLK fCLK fCLK
Segment select circuit clock selector circuit
Display data memory
fLCD
Timing controller Regulator
Segment data selector
drive voltage control circuit
Common driver
Segment driver
COM0
COM15
S39/P50
Data Sheet U13284EJ1V0DS00
µPD789830
INTERRUPT FUNCTIONS
following types interrupt functions total interrupt sources available. Non-maskable Maskable Table 6-1. Interrupt Sources
Interrupt Type
Priority
Note
Interrupt Source Internal/External Name Trigger Overflow watchdog timer (when Internal watchdog timer mode selected) Overflow watchdog timer (when interval timer mode selected) Detection input edge External
Vector Table Address 0004H
Basic Configuration Note Type
Non-maskable
INTWDT
Maskable
INTWDT
INTP0 INTP1 INTP2 INTSER00
0006H 0008H 000AH
Occurrence reception error serial interface (UART00) Completion reception serial interface (UART00) Completion transmission serial interface (UART00) Generation coincidence signal 16-bit timer Occurrence overflow 16-bit timer Logical between coincidence signal overflow signal 16-bit timer Generation coincidence signal 8-bit timer Interval timer interrupt Watch timer interrupt Detection return signal
Internal
000CH
INTSR00
000EH
INTST00
0010H
INTTM40
0012H
INTTM41
0014H
INTTM4
0016H
INTTM00
0018H
INTWTI INTWT INTKR00
001AH 001CH External 001EH
Notes more maskable interrupts occur same time, they processed according these priorities. Priority highest, while lowest. through Basic Configuration Type correspond through Figure 6-1. Remark Either non-maskable maskable interrupt (internal) selected interrupt source watchdog timer (INTWDT).
Data Sheet U13284EJ1V0DS00
µPD789830
Figure 6-1. Basic Configuration Interrupt Function Internal non-maskable interrupt
Internal
Interrupt request
Vector table address generation circuit
Standby release signal
Internal maskable interrupt
Internal
Interrupt request
Vector table address generation circuit
Standby release signal
External maskable interrupt
Internal
INTM0,KRM00
Interrupt request
Edge detection circuit
Vector table address generation circuit
Standby release signal
INTM0 External interrupt mode register KRM00 return mode register Interrupt request flag Interrupt enable flag Interrupt mask flag
Data Sheet U13284EJ1V0DS00
µPD789830
STANDBY FUNCTION
standby function used lower current consumption used following modes: HALT mode: this mode, operation clock stopped. using this mode together with normal operation mode operate system intermittently, average current consumption reduced. STOP mode: this mode, oscillation main system clock stopped, that internal operations based main system clock stopped current consumption minimized. Figure 7-1. Standby Function
CSS0Note Main system clock operation CSS0
Note
Subsystem clock operation HALT instruction
Note
HALT instruction
Interrupt request
STOP instruction Interrupt request Interrupt request HALT mode Clock supply stops. Oscillation continues. HALT mode Clock supply stops. Oscillation continues.
STOP mode Main system clock oscillation stops.
Notes subclock control register (CSS) Current consumption reduced stopping main system clock. When operates using subsystem clock, stop main system clock using (MCC) processor clock control register (PCC). STOP instruction cannot used. Caution Make sure software that specified oscillation stabilization time elapsed before main system clock selected again main system clock been stopped subsystem clock being used.
RESET FUNCTION
microcontroller reset following ways: External reset using RESET Internal reset detecting hang-up watchdog timer
Data Sheet U13284EJ1V0DS00
µPD789830
OUTLINE INSTRUCTION
This section shows list instructions µPD789830.
Conventions
9.1.1 Operand Formats Syntax more operands written operand field each instruction accordance with operand format syntax that instruction (for details, refer assembler specifications). more operands shown, select them. uppercase characters, symbols keywords must written shown. meanings these symbols follows: Specifies immediate data. Specifies absolute address. Specifies relative address.
Specifies indirect address.
specify immediate data, write appropriate value label. When using label, sure symbols register syntax operands specified either function name (such absolute name (such shown parentheses table below). Table 9-1. Operand Formats Syntax
Format saddr saddrp addr16 addr5 word byte Syntax (R0), (R1), (R2), (R3), (R4), (R5), (R6), (R7) (RP0), (RP1), (RP2), (RP3) Special function register symbol FE20H FF1FH FE20H FF1FH 0000H FFFFH 0040H 007FH Immediate data label Immediate data label (even address only) Immediate data label (even address only when 16-bit data transfer instruction used) Immediate data label (even address only)
16-bit immediate data label 8-bit immediate data label 3-bit immediate data label
Data Sheet U13284EJ1V0DS00
µPD789830
9.1.2 Explanation symbols operation field NMIS register; 8-bit accumulator register register register register register register register register pair; 16-bit accumulator register pair register pair register pair Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Interrupt request enable flag Non-maskable interrupt processing flag Contents memory addressed address register contents High-order bits low-order bits 16-bit register Logical product (AND) Logical (OR) Exclusive logical (exclusive Inverted data addr16 16-bit immediate data label jdisp8 Signed 8-bit data (displacement value)
9.1.3 Explanation symbols flag operation field (Blank) affected Cleared cleared depending result Previously saved value stored.
Data Sheet U13284EJ1V0DS00
µPD789830
Operation List
Flag Mnemonic #byte saddr, #byte sfr, #byte saddr saddr, sfr, !addr16 !addr16, PSW, #byte PSW, [DE] [DE], [HL] [HL], [HL+byte] [HL+byte], saddr [DE] [HL] [HL+byte] MOVW #word saddrp saddrp, XCHW
Note Note Note Note Note Note
Operand
Bytes
Clocks rbyte (saddr)byte sfrbyte A(saddr) (saddr)A Asfr sfrA A(addr16) (addr16)A PSWbyte APSW PSWA A(DE) (DE)A A(HL) (HL)A A(HL+byte) (HL+byte)A A(saddr) A(sfr) A(DE) A(HL) A(HL+byte) rpword AX(saddrp) (saddrp)AX AXrp rpAX AXrp
Operation
Notes Except Except only Remark clock instruction equivalent clock (fCPU) selected processor clock control register (PCC).
Data Sheet U13284EJ1V0DS00
µPD789830
Flag Mnemonic #byte saddr, #byte saddr !addr16 [HL] [HL+byte] ADDC #byte saddr, #byte saddr !addr16 [HL] [HL+byte] #byte saddr, #byte saddr !addr16 [HL] [HL+byte] SUBC #byte saddr, #byte saddr !addr16 [HL] [HL+byte] #byte saddr, #byte saddr !addr16 [HL] [HL+byte] Operand Bytes Clocks CYA+byte (saddr), CY(saddr)+byte CYA+r CYA+(saddr) CYA+(addr16) CYA+(HL) CYA+(HL+byte) CYA+byte+CY (saddr), CY(saddr)+byte+CY CYA+r+CY CYA+(saddr)+CY CYA+(addr16)+CY CYA+(HL)+CY CYA+(HL+byte)+CY CYA-byte (saddr), CY(saddr)-byte CA-r CYA-(saddr) A-(addr16) CYA-(HL) CYA-(HL+byte) CYA-byte-CY (saddr), CY(saddr)-byte-CY CYA-r-CY CYA-(saddr)-CY CYA-(addr16)-CY CYA-(HL)-CY CYA-(HL+byte)-CY AAbyte (saddr)(saddr)byte AA(saddr) AA(addr16) AA(HL) AA(HL+byte) Operation
Remark clock instruction equivalent clock (fCPU) selected processor clock control register (PCC).
Data Sheet U13284EJ1V0DS00
µPD789830
Flag Mnemonic #byte saddr, #byte saddr !addr16 [HL] [HL+byte] #byte saddr, #byte saddr !addr16 [HL] [HL+byte] #byte saddr, #byte saddr !addr16 [HL] [HL+byte] ADDW SUBW CMPW #word #word #word saddr saddr INCW DECW RORC ROLC Operand Bytes Clocks AAbyte (saddr)(saddr)byte (saddr) AA(addr16) AA(HL) AA(HL+byte) AAbyte (saddr)(saddr)byte AA(saddr) AA(addr16) AA(HL) AA(HL+byte) A-byte (saddr)-byte A-(saddr) A-(addr16) A-(HL) A-(HL+byte) CYAX+word CYAX-word AX-word rr+1 (saddr)(saddr)+1 rr+1 (saddr)(saddr)-1 rprp+1 rprp-1 (CY, A7A0, Am-1Am) (CY, A0A7, Am+1Am) (CYA0, A7CY Am-1Am) (CYA7, A0CY Am+1Am) Operation
Remark clock instruction equivalent clock (fCPU) selected processor clock control register (PCC).
Data Sheet U13284EJ1V0DS00
µPD789830
Flag Mnemonic SET1 saddr. sfr. PSW. [HL]. CLR1 saddr. sfr. PSW. [HL]. SET1 CLR1 NOT1 CALL !addr16 Operand Bytes Clocks (saddr. bit)1 sfr. bit1 bit1 PSW. bit1 (HL). bit1 (saddr. bit)0 sfr. bit0 bit0 PSW. bit0 (HL). bit0 CYCY (SP-1)(PC+3)H, (SP-2)(PC+3)L, PCaddr16, SPSP-2 CALLT [addr5] (SP-1)(PC+1)H, (SP-2)(PC+1)L, PCH(00000000, addr5+1), PCL(00000000, addr5), SPSP-2 PCH, (SP+1), PCL(SP), SPSP+2 RETI PCH, (SP+1), PCL(SP), PSW(SP+2), SPSP+3, NMIS0 PUSH (SP-1)PSW, SPSP-1 (SP-1)rpH, (SP-2)rpL, SPSP-2 PSW(SP), SPSP+1 rpH(SP+1), (SP), SPSP+2 MOVW !addr16 $addr16 SPAX AXSP PCaddr16 PCPC+2+jdisp8 PCHA, PCL2 Operation
Remark clock instruction equivalent clock (fCPU) selected processor clock control register (PCC).
Data Sheet U13284EJ1V0DS00
µPD789830
Flag Mnemonic $addr16 $addr16 $addr16 $addr16 saddr. bit, $addr16 Operand Bytes Clocks Operation PCPC+2+jdisp8 PCPC+2+jdisp8 PCPC+2+jdisp8 PCPC+2+jdisp8 PCPC+4+jdisp8 (saddr. bit) sfr. bit, $addr16 bit, $addr16 PSW. bit, $addr16 saddr. bit, $addr16 PCPC+4+jdisp8 sfr. PCPC+3+jdisp8 PCPC+4+jdisp8 PSW. PCPC+4+jdisp8 (saddr. bit) sfr. bit, $addr16 bit, $addr16 PSW. bit, $addr16 DBNZ $addr16 PCPC+4+jdisp8 sfr. PCPC+3+jdisp8 PCPC+4+jdisp8 PSW. BB-1, then PCPC+2+jdisp8 $addr16 CC-1, then PCPC+2+jdisp8 saddr, $addr16 (saddr)(saddr)-1, then PCPC+3+jdisp8 (saddr)0 HALT STOP Operation (Enable Interrupt) (Disable Interrupt) HALT Mode STOP Mode
Remark clock instruction equivalent clock (fCPU) selected processor clock control register (PCC).
Data Sheet U13284EJ1V0DS00
µPD789830
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter Supply voltage Input voltage Symbol P00-P07, P10, P11, P20-P23, P25, P26, P30-P34, P50-P57, XT1, XT2, RESET (N-ch open drain) Condition Ratings -0.3 +6.5 -0.3 -0.3 -0.3 Total pins Low-level output current Total pins Operating temperature Storage temperature Tstg +150 Unit
Output voltage High-level output current
Caution parameters exceeds absolute maximum ratings, even momentarily, quality product impaired. absolute maximum ratings values that physically damage product(s). sure product(s) within ratings. Remark Unless otherwise specified, characteristics shared with port same port pin.
Data Sheet U13284EJ1V0DS00
µPD789830
Main System Clock Oscillator Characteristics
Resonator Ceramic resonator Recommended Circuit Parameter Oscillation frequency Note (fX) Oscillation stabilization Note time Oscillation frequency Note (fX) Oscillation stabilization Note time input frequency Note (fX) input high- lowlevel widths (tXH, tXL) Condition oscillation voltage range MIN. TYP. MAX. Unit
After reached MIN. oscillation start voltage
Crystal resonator
External clock
OPEN
Notes These parameters indicate only characteristics oscillator. instruction execution time, refer Characteristics. This time required oscillation stabilize after reset been cleared STOP mode been released. resonator that stabilizes within specified oscillation wait time. Cautions When using main system clock oscillator, wire portion enclosed dotted line above figures follows avoid adverse influence wiring capacitance. Keep wiring length short possible. cross wiring with other signal lines. Keep away from line through which high alternating current flows. Always keep ground point capacitor oscillator same potential VSS0. ground wiring pattern through which high current flows. extract signal from oscillator. Make sure software that specified oscillation stabilization time elapsed before main system clock selected again main system clock been stopped subsystem clock being used. Remark resonator selection oscillator constant, customers requested either evaluate oscillation themselves apply resonator manufacturer evaluation.
Data Sheet U13284EJ1V0DS00
µPD789830
Subsystem clock oscillator characteristics
Resonator Crystal resonator Recommended Circuit
Parameter Oscillation frequency Note (fXT) Oscillation stabilization Note time input frequency Note (fXT) input high- low-level widths (tXTH, tXTL)
Condition
MIN.
TYP. 32.768
MAX.
Unit
External clock
14.3
15.6
Notes These parameters indicate only characteristics oscillator. instruction execution time, refer Characteristics. This time required oscillation stabilize after reset been cleared STOP mode been released. resonator that stabilizes within specified oscillation wait time. Cautions When using subsystem clock oscillator, wire portion enclosed dotted line above figures follows avoid adverse influence wiring capacitance. Keep wiring length short possible. cross wiring with other signal lines. Keep away from line through which high alternating current flows. Always keep ground point capacitor oscillator same potential VSS0. ground wiring pattern through which high current flows. extract signal from oscillator. subsystem clock oscillator designed have amplification factor order lower current consumption. Consequently, more susceptible noise than main system clock oscillator. Therefore, utmost care must exercised wiring when using subsystem clock oscillator. Remark resonator selection oscillator constant, customers requested either evaluate oscillation themselves apply resonator manufacturer evaluation.
Data Sheet U13284EJ1V0DS00
µPD789830
Characteristics (1/2)
Parameter High-level output current Low-level output current High-level input voltage Symbol Total pins Total pins VIH1 VIH2 VIH3 VIH4 VIH5 Low-level input voltage VIL1 VIL2 VIL3 VIL4 VIL5 High-level output voltage Low-level output voltage P00-P07, P10, P11, P23, P25, P50-P57 RESET, P20-P22, P26, P30-34 (N-ch open drain) P00-P07, P10, P11, P23, P25, P50-P57 RESET, P20-P22, P26, P30-P34 (N-ch open drain) XT1, -100 VOL1 Pins other than VOL2 P24(N-ch open drain) VDD-0.1 VDD-0.1 VDD-1.0 VDD-0.5 Condition MIN. TYP. MAX. Unit
Remark Unless otherwise specified, characteristics shared with port same port pin.
Data Sheet U13284EJ1V0DS00
µPD789830
Characteristics (2/2)
Parameter High-level input leakage current Symbol ILIH1 ILIH2 ILIH3 Low-level input leakage current ILIL1 Condition P00-P07, P10, P11, P20-P23, P25, P26, P30-P34, P50-P57, RESET XT1, (N-ch open drain) P00-P07, P10, P11, P20-P23, P25, P26, P30-P34, P50-P57, RESET, (N-ch open drain), except during read XT1, (N-ch open drain), during read VOUT MIN. TYP. MAX. Unit
ILIL2 ILIL3 High-level output leakage current Low-level output leakage current Software pull-up resistor Supply current
Note
Note Note
ILOH ILOL IDD1
VOUT P00-P07, P10, P11, P30-P34 5.0-MHz crystal oscillation operation mode 5.0-MHz crystal oscillation HALT mode 32.768-kHz crystal oscillation Note operation mode 32.768-kHz crystal oscillation HALT Note mode STOP mode ±10% ±10% ±10% ±10% ±10% ±10% ±10% ±10% ±10% ±10% 0.45 0.05
IDD2
Note Note
IDD3
IDD4
IDD5
Notes Does include when operation (LCDON20 (bit LCD20 mode register (LCDM20)) LIPS20 (bit LCDM20) port current (including current flowing through internal pull-up resistor). current when operation, refer Operating Current Characteristics. high-speed mode (when processor clock control register (PCC) 00H) low-speed mode (when 02H) When main system clock stopped Remark Unless otherwise specified, characteristics shared with port same port pin.
Data Sheet U13284EJ1V0DS00
µPD789830
Characteristics
Parameter drive voltage Symbol VLCD VLCD Condition VAON20 VAON20 Segment output Note voltage VODS When VLC0 selected When VLC2 selected When VLC3 selected Common output Note voltage VODC When VLC0 selected When VLC1 selected When VLC4 selected Segment output resistance Common output resistance input frequency RSEG RCOM fLCD VLCn SEGp VLCn COMq VAON20 VAON20 operating Note current ILCD1 ILCD2 VAON20 VAON20 7.81 MIN. VLCD VLCD VLCD VLCD VLCD VLCD 12.5 10.0 78.13 78.13 TYP. MAX. Unit
Notes Voltage under load Including current flowing into divider resistor. supply current when LCDON20 LIPS20 (display OFF, internal drive voltage supply OFF) included Supply current IDD5 (STOP mode) Characteristics. Remark
Data Sheet U13284EJ1V0DS00
µPD789830
Characteristics Basic operation
Parameter Symbol With main system clock With subsystem clock INTP0-INTP2 Condition MIN. TYP. MAX. Unit
Cycle time (minimum instruction execution time) Interrupt input highand low-level widths RESET input lowlevel width tINTH, tINTL tRSL
(Main system clock)
Cycle time
Guaranteed operating range
Supply voltage
Serial interface UART mode (dedicated baud rate generator output)
Parameter Transfer rate Symbol Condition MIN. TYP. MAX. 78125 Unit
Data Sheet U13284EJ1V0DS00
µPD789830
Timing Test Points (Except input)
Test points
Clock Timing
1/fX VIH4 (MIN.) VIL4 (MAX.)
input
1/fXT tXTL tXTH VIH5 (MIN.) VIL5 (MAX.)
input
Interrupt Input Timing
tINTL tINTH
INTP0-INTP2
RESET Input Timing
tRSL
RESET
Low-Voltage Data Retention Characteristics Data Memory STOP Mode
Parameter Data retention voltage Release signal time Symbol VDDDR tSREL Released RESET Released interrupt request Condition MIN. Note
TYP.
MAX.
Unit
Oscillation stabilization wait tWAIT Note time
Notes oscillation stabilization wait time time after oscillation started during which stopped prevent unstable operation.
/fX, /fX, selected using bits through (OSTS0 through OSTS2)
oscillation stabilization time select register (OSTS). Remark Main system clock oscillation frequency
Data Sheet U13284EJ1V0DS00
µPD789830
Data Retention Timing (Releasing STOP mode RESET)
Internal reset operation HALT mode STOP mode Data retention mode Operation mode
VDDDR STOP instruction execution
tSREL
RESET
tWAIT
Data Retention Timing (Standby release signal: Releasing STOP mode interrupt signal)
HALT mode STOP mode Data retention mode Operation mode
VDDDR STOP instruction execution
tSREL
Standby release signal (interrupt request) tWAIT
Data Sheet U13284EJ1V0DS00
µPD789830
APPENDIX DEVELOPMENT TOOLS
following development tools available development system using µPD789830. Language processor software
RA78K0S
Notes
Common assembler package 78K/0S series Common compiler package 78K/0S series Device file µPD789830 subseries Common compiler library source file 78K/0S series
CC78K0S
Notes
DF789831
Notes
CC78K0S-L
Notes
Flash memory writing tools
FlashproIII (FL-PR3
Note
Flash programmer microcontrollers with flash memory PG-FP3) Flash memory writing adapter
FA-100GC
Note
Debugging tools
IE-78K0S-NS in-circuit emulator In-circuit emulator debugging hardware software application system using 78K/0S series. Supports integrated debugger (ID78K0S-NS). Used with adapter, emulation probe, interface adapter that connects host machine. Adapter that distributes power from 240-V outlet.
IE-70000-MC-PS-B adapter IE-70000-98-IF-C interface adapter IE-70000-CD-IF-A card interface IE-70000-PC-IF-C interface adapter IE-70000-PCI-IF interface adapter IE-789831-NS-EM1 emulation board NP-100GC
Note
Adapter necessary when using PC-9800 series (except notebook type) host machine IE-78K0S-NS (supports bus). card interface cable necessary when notebook type personal computer used host machine IE-78K0S-NS (supports PCMCIA socket). Adapter necessary when PC/AT IE-78K0S-NS (supports bus). Adapter necessary when using personal computer with used host machine IE-78K0S-NS. Board emulating device-specific peripheral hardware. Used with in-circuit emulator.
compatible machine used host machine
emulation probe SM78K0S
Notes
Probe connecting in-circuit emulator target system. 100-pin plastic QFP. Common system simulator 78K/0S series Device file µPD789830 subseries
DF789831
Notes
Real-time
MX78K0S
Notes
78K/0S series
Notes PC-9800 series (Japanese/English Windows based PC/AT compatible machine (Japanese/English Windows) based HP9000 series based This product Naito Densei Machida Mfg. Co., Ltd. (Tel: 044-822-3813). Consult Naito Densei Machida Mfg. Co., Ltd. purchasing. Remark RA78K0S, CC78K0S, SM78K0S used with DF789831.
(HP-UX based, SPARCstation
(SunOS Solaris based, NEWS
(NEWS-
Data Sheet U13284EJ1V0DS00
µPD789830
APPENDIX RELATED DOCUMENTS
Device-Related Documents
Document Document Name Japanese English This document U13477E U13679E U11047E
µPD789830 Data Sheet µPD78F9831 Preliminary Product Information µPD789830 Subseries User's Manual
78K/0S Series User's Manual Instructions
U13284J U13447J U13679J U11047J
Documents Development Tools (User's Manual)
Document Document Name Japanese RA78K0S Assembler Package Operation Assembly language Structured assembly language CC78K0S Compiler Operation Language SM78K0S System Simulator, Windows-based SM78K Series System Simulator ID78K0S-NS Integrated Debugger, Windows-based IE-78K0S-NS IE-789831-NS-EM1 Reference External part user open interface specifications Reference U11622J U11599J U11623J U11816J U11817J U11489J U10092J U12901J U13549J U14202J English U11622E U11599E U11623E U11816E U11817E U11489E U10092E prepared U13549E U14202E
Documents Embedded Software (User's Manual)
Document Document Name Japanese 78K/0S Series MX78K0S Fundamental U12938J English U12938E
Other Documents
Document Document Name Japanese SEMICONDUCTORS SELECTION GUIDE Products Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades Semiconductor Devices Semiconductor Device Reliability/Quality Control System Guide Prevent Damage Semiconductor Devices Electrostatic Discharge (ESD) Semiconductor Device Quality/Reliability Handbook Guide Microcomputer-Related Products Third Party X13769X C10535J C11531J C10983J C11892J C12769J U11416J C10535E C11531E C10983E C11892E English
Caution contents above related documents subject change without notice. sure latest edition document when designing your system.
Data Sheet U13284EJ1V0DS00
µPD789830
[MEMO]
Data Sheet U13284EJ1V0DS00
µPD789830
[MEMO]
Data Sheet U13284EJ1V0DS00
µPD789830
[MEMO]
Data Sheet U13284EJ1V0DS00
µPD789830
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
related documents referred this publication include preliminary versions. preliminary versions marked such. EEPROM trademark Corporation.
However,
Windows either registered trademark trademark Microsoft Corporation United States and/or other countries. PC/AT trademark Corporation. HP9000 series HP-UX trademarks Hewlett-Packard SPARCstation trademark SPARC International, Inc. Solaris SunOS trademarks Microsystems, Inc. NEWS NEWS-OS trademarks Sony Corporation.
Data Sheet U13284EJ1V0DS00
µPD789830
Regional Information
Some information contained this document vary from country country. Before using product your application, pIease contact office your country obtain list authorized representatives distributors. They will verify:
Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements
addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 Fax: 01-30-67 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics (France) S.A. Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
Electronics Singapore Pte. Ltd.
United Square, Singapore Tel: 65-253-8311 Fax: 65-250-3583
Electronics Taiwan Ltd. Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
Brasil S.A.
Electron Devices Division Guarulhos-SP Brasil Tel: 55-11-6462-6810 Fax: 55-11-6462-6829
J00.7
Data Sheet U13284EJ1V0DS00
µPD789830
export this product from Japan regulated Japanese government. export this product prohibited without governmental license, need which must judged customer. export re-export this product from country other than Japan also prohibited without license from that country. Please call sales representative.
information this document current December, 1999. information subject change without notice. actual design-in, refer latest publications NEC's data sheets data books, etc., most up-to-date specifications semiconductor products. products and/or types available every country. Please check with sales representative availability additional information. part this document copied reproduced form means without prior written consent NEC. assumes responsibility errors that appear this document. does assume liability infringement patents, copyrights other intellectual property rights third parties arising from semiconductor products listed this document other liability arising from such products. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. assumes responsibility losses incurred customers third parties arising from these circuits, software information. While endeavours enhance quality, reliability safety semiconductor products, customers agree acknowledge that possibility defects thereof cannot eliminated entirely. minimize risks damage property injury (including death) persons arising from defects semiconductor products, customers must incorporate sufficient safety measures their design, such redundancy, fire-containment, anti-failure features. semiconductor products classified into following three quality grades: "Standard", "Special" "Specific". "Specific" quality grade applies only semiconductor products developed based customer-designated "quality assurance program" specific application. recommended applications semiconductor product depend quality grade, indicated below. Customers must check quality grade each semiconductor product before using particular application. "Standard": Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade semiconductor products "Standard" unless otherwise expressly specified NEC's data sheets data books, etc. customers wish semiconductor products applications intended NEC, they must contact sales representative advance determine NEC's willingness support given application. (Note) "NEC" used this statement means Corporation also includes majority-owned subsidiaries. "NEC semiconductor products" means semiconductor product developed manufactured defined above).

µPD789830 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION

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