LC72135M Frequency Synthesizer Electronic Tuning Overview

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LC72135M Frequency Synthesizer Electronic Tuning Overview

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Ordering number EN5175A
LC72135M
Frequency Synthesizer Electronic Tuning
Overview
LC72135M frequency synthesizer tuners stereo similar applications. Highperformance AM/FM tuners easily implemented with this product.
Functions
High-speed programmable dividers FMIN: .pulse swallower (built-in divide-by-two prescaler) AMIN: .pulse swallower .direct division counter HCTR .AM/FM counter LCTR Hz.AM counter Reference frequencies Twelve selectable frequencies (4.5 crystal) 3.125, 6.25, 12.5, Phase comparator Dead zone control Unlock detection circuit Deadlock clear circuit Built-in transistor forming active low-pass filter ports Dedicated output ports: Input output ports: Input ports (LCTR) Support clock time base output
Serial data Support format communication with system controller. Operating ranges Supply voltage.4.5 Operating temperature.-40 +85°C Package MFP20
Package Dimensions
unit: 3036B-MFP20
[LC72135M]
SANYO: MFP20
trademark SANYO ELECTRIC CO., LTD. SANYO's original format addresses controlled SANYO.
SANYO products described contained herein have specifications that handle applications that require extremely high levels reliability, such life-support systems, aircraft's control systems, other applications whose failure reasonably expected result serious physical and/or material damage. Consult with your SANYO representative nearest before using SANYO products described contained herein such applications. SANYO assumes responsibility equipment failures that result from using products values that exceed, even momentarily, rated values (such maximum ratings, operating condition ranges, other parameters) listed products specifications SANYO products described contained herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
83098HA (OT)/22896HA (OT) 5175-1/24
LC72135M Assignment
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LC72135M Block Diagram
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LC72135M
Specifications
Absolute Maximum Ratings 25°C,
Parameter Maximum supply voltage Symbol VIN1 Maximum input voltage VIN2 VIN3 Maximum output voltage Maximum output current Allowable power dissipation Operating temperature Storage temperature Topr Tstg XIN, FMIN, AMIN, HCTR, LCTR/I1 XOUT, BO4, IO2, AOUT AOUT, BO4, 85°C Pins Ratings -0.3 +7.0 -0.3 +7.0 -0.3 -0.3 -0.3 +7.0 -0.3 -0.3 10.0 +125 Unit
Allowable Operating Ranges +85°C,
Parameter Supply voltage Symbol VIH1 Input high-level voltage VIH2 VIH3 Input low-level voltage Output voltage fIN1 fIN2 Input frequency fIN3 fIN4 fIN5 fIN6 VIN1 VIN2-1 VIN2-2 VIN3 Input amplitude VIN4 VIN5-1 VIN5-2 VIN6-1 VIN6-2 Supported crystals Xtal LCTR/I1 IO2, LCTR/I1 BO4, IO2, AOUT FMIN AMIN AMIN HCTR LCTR/I1 FMIN FMIN AMIN AMIN HCTR HCTR LCTR/I1 LCTR/I1 XIN, XOUT VIN1 VIN2 VIN3, VIN4, VIN5 VIN6 fIN1 fIN3, fIN4, fIN5, fIN5, fIN6, fIN6, Pins Conditions +6.5 1500 1500 1500 1500 1500 1500 1500 1500 1500 Unit mVrms mVrms mVrms mVrms mVrms mVrms mVrms mVrms mVrms
Note: Recommended crystal oscillator values: (For crystal) (For crystal) <Sample Oscillator Circuit> Crystal oscillator: HC-49/U (manufactured Kinseki, Ltd.), circuit constants crystal oscillator circuit depend crystal used, printed circuit board pattern, other items. Therefore recommend consulting with manufacturer crystal about evaluation reliability.
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LC72135M Electrical Characteristics Allowable Operating Ranges +85°C,
Parameter Symbol Built-in feedback resistance Built-in pull-down resistor Hysteresis Output high-level voltage Rpd1 Rpd2 VHIS VOH1 VOL1 VOL2 VOL3 FMIN AMIN HCTR LCTR/I1 FMIN AMIN IO2, LCTR/I1 VOL4 VOL5 IIH1 IIH2 IIH3 Input high-level current IIH4 IIH5 IIH6 IIH7 IIL1 IIL2 Input low-level current IIL3 IIL4 IIL5 IIL6 IIL7 Output leakage current High-level three-state leakage current Low-level three-state leakage current Input capacitance IOFF1 IOFF2 IOFFH IOFFL IDD1 BO4, AOUT LCTR/I1 FMIN, AMIN HCTR, LCTR/I1 LCTR/I1 FMIN, AMIN HCTR, LCTR/I1 BO4, AOUT, FMIN Xtal MHz, fIN2 MHz, VIN2 mVrms block stopped (PLL INHIBIT), Xtal oscillator operating (Xtal MHz) block stopped Xtal oscillator stopped VDD, L/I1 VDD, L/I1 L/I1 L/I1 0.01 0.01 Pins Conditions Unit
Output low-level voltage
Current drain
IDD2
IDD3
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LC72135M Functions
Symbol Type Functions Circuit configuration
XOUT
Xtal
Crystal resonator connection (4.5/7.2 MHz)
FMIN
Local oscillator signal input
FMIN selected when serial data input input frequency range from MHz. input signal passes through internal divide-bytwo prescaler input swallow counter. divisor range 65535. However, since signal passed through divide-by-two prescaler, actual divisor twice value.
AMIN
Local oscillator signal input
AMIN selected when serial data input When serial data input input frequency range MHz. signal directly input swallow counter. divisor range 65535, divisor used will value set. When serial data input input frequency range MHz. signal directly input 12-bit programmable divider. divisor range 4095, divisor used will value set.
Chip enable
this high when inputting (DI) outputting (DO) serial data.
Clock
Used synchronization clock when inputting (DI) outputting (DO) serial data.
Data input
Inputs serial data transferred from controller LC72135M.
Data output
Outputs serial data transferred from LC72135M controller. content output data determined serial data DOC0 DOC2.
Power supply
LC72135M power supply (VDD power reset circuit operates when power first applied.
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LC72135M
Continued from preceding page.
Symbol
Type
Functions
Circuit configuration
Ground
LC72135M ground
Output port
Dedicated output pins output states determined bits serial data. Data: open, output ports open state following power-on reset. time base signal output from pin. (When serial data Care required when using pin, since higher impedance that other output ports (pins BO4).
port
dual-use pins direction (input output) determined IOC2 serial data. Data: input port, output port When specified input ports: state input transmitted controller over pin. Input state: data value high data value When specified output ports: output states determined serial data. Data: open, function input following power-on reset.
Charge pump output
charge pump output When frequency generated dividing local oscillator frequency higher than reference frequency, high level output from pin. Similarly, when that frequency lower, level output. goes high-impedance state when frequencies match.
AOUT
amplifier transistor
n-channel transistor used active low-pass filter.
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LC72135M
Continued from preceding page.
Symbol
Type
Functions
Circuit configuration
HCTR
counter
HCTR selected when LCTS serial data Accepts input frequency range MHz. input signal directly transmitted counter. result output starting counter using pin. Four measurement periods supported:
counter
LCTR/I1
Input port
LCTR selected when LCTS serial data (Set L/I1 serial data when using counter.) input frequency range kHz. signal directly transmitted counter. result, starting with counter, output serially through pin. There four measurement times: L/I1 serial data LCTR/I1 functions input port state that input transmitted controller from pin. When input state low, data will when state high, data will
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LC72135M Serial Data Methods LC72135M inputs outputs data using Sanyo (computer control bus) audio serial format. This adopts 8-bit address format CCB.
mode Address Function Control data input mode (serial data input) data bits input. Control Data (serial data input) Structure" item details meaning input data. Control data input mode (serial data input) data bits input. Control Data (serial data input) Structure" item details meaning input data. Data output mode (serial data output) number bits output equal number clock cycles. Output Data (Serial Data Output) Structure" item details meaning output data.
(82)
(92)
(A2)
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LC72135M Control Data (Serial Data Input) Structure Mode
Mode
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LC72135M Control Data Functions
Control block/data Functions Related data
Programmable divider data Data that sets programmable divider. binary value which MSB. changes depending SNS. don't care) DVS, Divisor setting 65535 65535 4095 Actual divisor Twice value setting value setting value setting
Note: ignored when LSB. Selects signal input (AMIN FMIN) programmable divider, switches input frequency range. don't care) Input FMIN AMIN Input frequency range
AMIN Note: "Programmable Divider" item more information. Reference divider data Reference frequency (fref) selection data. Reference frequency (kHz) 12.5 6.25 3.125 3.125 INHIBIT Xtal STOP
INHIBIT Note: INHIBIT programmable divider block counter block stopped, FMIN, AMIN, HCTR LCTR pins pull-down state (ground), charge pump goes high impedance state. Crystal resonator selection frequency selected after power-on reset. counter measurement start data Counter start Counter reset Determines counter measurement period. counter selection data LCTS L/I1 Measurement time (ms) Wait time (ms)
counter control data GT0,
Note: Counter" item more information. Data that specifies counter input (and mode). LCTS HCTR, LCTS LCTR L/I1 (Input port), L/I1 LCTR counter) LCTS L/I1 LCTR/I1 (input port) (pulled down) (input port) LCTR counter) HCTR HCTR (FM/AM counter) (pulled down)
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LC72135M
Continued from preceding page.
Control block/data port specification data IOC2 Output port data BO4, Functions Specifies direction bidirectional IO2. Data: input mode, output mode Data that determines output from BO4, output ports Data: open, data (open) state selected after power-on reset. control data DOC0, DOC1, DOC2 Data that determines output DOC2 DOC1 DOC0 state Open when unlock state detected end-UC*1 Open Open LCTR/I1 state*2 state*3 Open IOC2 Related data
open state selected after power-on reset. Note: end-UC: Check counter measurement completion UL0, UL1, CTE, IOC2
When end-UC counter started (i.e., when changed from zero one), automatically goes open state. When counter measurement completes, goes indicate measurement completion state. Depending serial data (CE: high) goes open state. Goes open state LCTR/I1 AM-IF counter function (L/I1 Goes open state specified output port. Caution: state during data input period mode period with high) will open, regardless state control data (DOC0 DOC2). Also, during data output period mode period with high) will output contents internal serial data synchronization with signal, regardless state control data (DOC0 DOC2). Unlock detection data UL0, Selects phase error detection width checking lock. phase error excess specified detection width seen unlocked state. detection width Stopped ±0.55 ±1.11 Open output directly extended extended Detector output DOC0, DOC1, DOC2
Note: unlocked state goes serial data becomes zero. Phase comparator control data DZ0, Controls phase comparator dead zone. Dead zone mode
Dead zone widths: Clock time base Charge pump control data Setting causes duty clock time base signal output from pin. (BO1 data invalid this mode.) Forcibly controls charge pump output. (10) Normal operation Forced Charge pump output
Note: deadlock occurs control voltage (Vtune) going zero oscillator stopping, deadlock cleared forcing charge pump output setting Vtune VCC. (This deadlock clearing circuit.)
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LC72135M
Continued from preceding page.
Control block/data counter control data Functions This data should during normal operation. Note that this value zero system enters input sensitivity degradation mode, sensitivity reduced rms. Counter Operation" item details. test data TEST0 TEST1 These values must TEST2 These test data automatically after power-on reset. (13) Don't care. This data must Related data
(11)
(12)
test data TEST
Output Data (Serial Data Output) Mode
Output Data
Control block/data port data Functions Latched from states LCTR/I1 input port (L/I1 port. These values follow states regardless input output setting. Data latched when data output mode entered. High: LCTR/I1 state state Low: Latched from state unlock detection circuit. Unlocked Locked detection stopped mode Latched from value counter (20-bit binary counter). binary counter binary counter Related data
L/I1 IOC2
unlock data counter binary data
UL0, CTE, GT0,
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LC72135M Serial Data Input (IN1/IN2) tSU, tHD, tEL, tES, 0.75 0.75
Serial Data Output (OUT) tSU, tHD, tEL, tES, 0.75 tDC, 0.35
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LC72135M
Serial Data Timing
Parameter Data setup time Data hold time Clock low-level time Clock high-level time wait time setup time hold time Data latch change time
Symbol
Pins
Conditions
0.75 0.75 0.75 0.75 0.75 0.75 0.75
Unit
0.75 Differs depending value pull-up resistor printed circuit board capacitances.
Data output time
0.35
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LC72135M Programmable Divider Structure
Input FMIN AMIN AMIN
divisor 65535 65535 4095
Actual divisor: Twice value value value
Input frequency range (MHz)
Note: Don't care.
Programmable Divider Calculation Examples steps (DVS FMIN selected) 90.0 +10.7 MHz) 100.7 fref 100.7 VCO) (fref) (FMIN: divide-by-two prescaler) 2014 07DE (HEX)
steps (DVS AMIN high-speed side selected) 21.75 +450 kHz) 22.20 fref 22.2 VCO) (fref) 4440 1158 (HEX)
steps (DVS AMIN low-speed side selected) 1000 +450 kHz) 1450 fref 1450 VCO) (fref) (HEX)
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LC72135M Counter Structure LC72135M counter 20-bit binary counter that accepts input from either HCTR (for counting) LCTR/I1 (for counting). result count read serially through starting with MSB.
Measurement time Measurement period (GT) (ms) Wait time (tWU) (ms)
frequency (Fc) measured determining many pulses were input counter specified measurement period, Count value (number pulses)
Counter Frequency Calculation Examples When measurement period (GT) count 53980 hexadecimal (342400 decimal): frequency (Fc) 342400 10.7
When measurement period (GT) count hexadecimal (3600 decimal): frequency (Fc) 3600
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LC72135M Counter Operation
Before starting count, counter must reset advance setting serial data count started changing serial data from serial data latched LC72135M when dropped from high low. signal must supplied HCTR LCTR pins period between point goes wait time latest. Next, value counter measurement period must read during period that This because counter reset when Note: When operating counter, control microprocessor must first check state IF-IC (station detect) signal only after determining that signal present turn buffer output execute count operation. Autosearch techniques that only counter recommended, since possible buffer leakage output cause incorrect stops points where there station. Note that LC72135M input sensitivity controlled with serial data. Reduced sensitivity mode (IFS must selected when this used conjunction with IF-IC that does provide output auto-search implemented using only counting. HCTR minimum input sensitivity standard
(MHz) Normal mode Degradation mode mVrms (0.1 mVrms) mVrms mVrms) mVrms mVrms mVrms mVrms) mVrms mVrms)
Note: Values parentheses actual performance values presented reference data.
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LC72135M Unlock Detection Timing Unlock Detection Determination Timing Unlocked state detection performed reference frequency (fref) period (interval). Therefore, principle, unlock determination requires time longer than period reference frequency. However, immediately after changing divisor (frequency) unlock detection must performed after waiting least periods reference frequency.
Figure Unlocked State Detection Timing example, fref kHz, i.e., period after changing divisor system must wait least before checking unlocked state.
Figure Circuit Structure
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LC72135M Unlock Detection Software
Figure Unlocked State Data Output Using Serial Data Output LC72135M, once unlocked state occurs, unlocked state serial data (UL) will reset until data input output) operation performed. data output point Figure although frequency stabilized (locked), since data output been performed since divisor changed unlocked state data remains unlocked state. result, even though frequency stabilized (locked), system remains (from standpoint data) unlocked state. Therefore, unlocked state data acquired data output which occurs immediately after divisor changed, should treated dummy data output ignored. second data output (data output following outputs valid data.
Locked State Determination Flowchart Directly Outputting Unlocked State Data from (Set control data) Since locking state (high locked, unlocked) output directly from pin, dummy data processing described section above required. After changing divisor locking state checked after waiting least reference frequency periods.
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LC72135M Clock Time Base Usage Notes pull-up resistor used clock time base output (BO1) should least This prevent degrading characteristics when loop filter formed using built-in low-pass filter transistor. Since clock time base output low-pass filter have common ground internal necessary minimize time base output current fluctuations suppress their influence low-pass filter. Also, prevent chattering recommend using Schmitt input controller (microprocessor) that receives this signal.
Other Items
Dead zone mode Charge pump ON/ON ON/ON OFF/OFF OFF/OFF Dead zone
Notes Phase Comparator Dead Zone
Since correction pulses output from charge pump even locked when charge pump ON/ON state, loop easily become unstable. This point requires special care when designing application circuits. following problems occur ON/ON state. Side band generation reference frequency leakage Side band generation both correction pulse envelope frequency leakage Schemes which dead zone present (OFF/OFF) have good loop stability, have problem that acquiring high ratio difficult. other hand, although easy acquire high ratio with schemes which there dead zone, difficult achieve high loop stability. Therefore, effective select DZB, which have dead zone, applications which require ratio excess which increased stereo pilot margin desired. other hand, recommend selecting DZD, which provide dead zone, applications which require such high signal-to-noise ratio which either stereo used adequate stereo pilot margin achieved.
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LC72135M Dead Zone phase comparator compares reference frequency (fr) shown Figure Although characteristics this circuit (see Figure such that output voltage proportional phase difference (line region (the dead zone) which possible compare small phase differences occurs actual internal circuit delays other factors (line dead zone small possible desirable products that must provide high ratio. However, since larger dead zone makes this circuit easier use, larger dead zone appropriate popularlypriced products. This because possible signals leak from mixer modulate popularly-priced products presence strong inputs. When dead zone narrow, circuit outputs correction pulses this output further modulate generate beat frequencies with signal.
Figure
Figure
Notes FMIN, AMIN, HCTR LCTR/I1 Pins Coupling capacitors must placed close possible their respective pins. capacitance about desirable. particular, capacitance 1000 over used HCTR LCTR/I1 pins, time reach bias level will increase incorrect counting occur relationship with wait time. Notes Counting must used conjunction with counting time When using counting, always implement counting having microprocessor determine presence IF-IC (station detect) signal turn counter buffer only signal present. Schemes which auto-searches performed with only counting recommended, since they stop points where there signal leakage output from counter buffer. Usage Techniques addition data output mode times, also used check counter count completion unlock detection output. Also, input state output unchanged through input controller. Power Supply Pins capacitor least 2000 must inserted between power supply pins noise exclusion. This capacitor must placed close possible pins. Setup Applications must designed that (local oscillator) does stop, even control voltage (Vtune) goes possible oscillator stop, application must control data (DLC) temporarily force Vtune prevent deadlock from occurring. (Deadlock clear circuit)
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LC72135M States after Power Reset
Application System Example
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LC72135M
Specifications SANYO products described contained herein stipulate performance, characteristics, functions described products independent state, guarantees performance, characteristics, functions described products mounted customer's products equipment. verify symptoms states that cannot evaluated independent device, customer should always evaluate test devices mounted customer's products equipment. SANYO Electric Co., Ltd. strives supply high-quality high-reliability products. However, semiconductor products fail with some probability. possible that these probabilistic failures could give rise accidents events that could endanger human lives, that could give rise smoke fire, that could cause damage other property. When designing equipment, adopt safety measures that these kinds accidents events cannot occur. Such measures include limited protective circuits error prevention circuits safe design, redundant design, structural design. event that SANYO products described contained herein fall under strategic products (including services) controlled under Foreign Exchange Foreign Trade Control Japan, such products must exported without obtaining export license from Ministry International Trade Industry accordance with above law. part this publication reproduced transmitted form means, electronic mechanical, including photocopying recording, information storage retrieval system, otherwise, without prior written permission SANYO Electric Co., Ltd. information described contained herein subject change without notice product/technology improvement, etc. When designing equipment, refer "Delivery Specification" SANYO product that intend use. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties.
This catalog provides information August, 1998. Specifications information herein subject change without notice. 5175-24/24

LC72135M Frequency Synthesizer Electronic Tuning Overview

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