LC75884E, LC75884W Duty Display Drivers with Input Function
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Ordering number EN6086
LC75884E, LC75884W
Duty Display Drivers with Input Function
Overview
LC75884E LC75884W duty display drivers that directly drive segments control four general-purpose output ports. These products also incorporate scan circuit that accepts input from keys reduce printed circuit board wiring.
Package Dimensions
unit: QFP80E
[LC75884E]
23.2 20.0
0.35
0.15
input function keys scan performed only when pressed.) 1/4duty 1/2bias 1/4duty 1/3bias drive schemes controlled from serial data segments). Sleep mode segments functions that controlled from serial data. Segment output port/general-purpose output port function switching that controlled from serial data. Serial data supports format communication with system controller. Direct display display data without decoder provides high generality. Independent VLCD driver block (VLCD range VDD-0.5 volts.) Provision on-chip voltage-detection type reset circuit prevents incorrect displays. provided forcibly initializing internal circuits. oscillator circuit.
17.2 14.0
Features
3.0max
21.6
SANYO: QFP80E(QIP80E)
unit: SQFP80
[LC75884W]
1.25 1.25 14.0 12.0 0.135 1.25
1.25
14.0 12.0
1.6max
trademark SANYO ELECTRIC CO., LTD. SANYO's original format addresses controlled SANYO.
SANYO: SQFP80
SANYO products described contained herein have specifications that handle applications that require extremely high levels reliability, such life-support systems, aircraft's control systems, other applications whose failure reasonably expected result serious physical and/or material damage. Consult with your SANYO representative nearest before using SANYO products described contained herein such applications. SANYO assumes responsibility equipment failures that result from using products values that exceed, even momentarily, rated values (such maximum ratings, operating condition ranges, other parameters) listed products specifications SANYO products described contained herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
22299RM (OT) 6086-1/27
15.6
LC75884E, LC75884W
Specifications
Absolute Maximum Ratings Ta=25°C, VSS=0V
Parameter Maximum supply voltage Symbol VLCD VIN1 Input voltage VIN2 VIN3 VOUT1 Output voltage VOUT2 VOUT3 IOUT1 Output current IOUT2 IOUT3 IOUT4 Allowable power dissipation Operating temperature Storage temperature Topr Tstg VLCD OSC,TEST VLCD1, VLCD2, S55, COM1 COM4, KS6, COM1 COM4 85°C Conditions Ratings -0.3 +7.0 -0.3 +7.0 -0.3 +7.0 -0.3 +0.3 -0.3 VLCD +0.3 -0.3 +7.0 -0.3 +0.3 -0.3 VLCD +0.3 +125 Unit
Allowable Operating Ranges +85°C, VSS=0V
Parameter Symbol VLCD VLCD1 VLCD2 VIH1 VIH2 ROSC COSC fOSC VLCD VLCD1 VLCD2 RES, RPU=4.7k, CL=10pF RPU=4.7k, CL=10pF :Figure :Figure :Figure :Figure :Figure :Figure :Figure :Figure :Figure :Figure :Figure Conditions Ratings VLCD VLCD VLCD VLCD VLCD Unit
Supply voltage
Input voltage
Input high level voltage Input level voltage Recommended external resistance Recommended external capacitance Guaranteed oscillator range Data setup time Data hold time wait time setup time hold time High level clock pulse width level clock pulse width Rise time Fall time output delay time rise time
Note: Since open-drain output, these values depend resistance pull-up resistor load capacitance
6086-2/27
LC75884E, LC75884W Electrical Characteristics Allowable Operating Ranges
Parameter Hysteresis Power-down detection voltage Input high level current Input level current Input floating voltage Pull-down resistance Output leakage current Symbol VDET IOFFH VOH1 Output high level voltage VOH2 VOH3 VOH4 VOL1 VOL2 Output level voltage VOL3 VOL4 VOL5 VMID1 VMID2 Output middle level voltage VMID3 VMID4 VMID5 Oscillator frequency fosc IDD1 IDD2 ILCD1 Current drain ILCD2 ILCD3 RES: 6.0V RES: KI5: 5.0V 6.0V KS6: -500µA -1mA S55: -20µA COM1 COM4: -100µA KS6: 25µA S55: 20µA COM1 COM4: 100µA COM1 COM4: 1/2bias, ±100µA S55: 1/3bias,IO ±20µA S55: 1/3bias, ±20µA COM1 COM4: 1/3bias,IO ±100µA COM1 COM4: 1/3bias,IO ±100µA OSC: ROSC 43k, COSC 680pF :Sleep mode VDD: 6.0V, output open,fosc 50kHz VLCD Sleep mode VLCD: VLCD 6.0V, output open, 1/2bias, fosc 50kHz VLCD: VLCD 6.0V, output open, 1/3bias, fosc 50kHz 1/2VLCD 2/3VLCD 1/3VLCD 2/3VLCD 1/3VLCD -5.0 0.05 VLCD VLCD VLCD VLCD VLCD VLCD 1/2VLCD 2/3VLCD 1/3VLCD 2/3VLCD 1/3VLCD Conditions RES, Ratings Unit
Nete: Excluding bias voltage generation divider resistor built into VLCD1 VLCD2. (See Figure
6086-3/27
LC75884E, LC75884W
Figure
When stopped level
When stopped high level
Figure
6086-4/27
LC75884E, LC75884W Assignment
6086-5/27
LC75884E, LC75884W Block Diagram
6086-6/27
LC75884E, LC75884W Functions
S1/P1 S2/P2 S3/P3 S4/P4 COM1 COM2 COM3 COM4 LC75884E LC75884W Function Segment outputs displaying display data transferred serial data input. S1/P1 S4/P4 pins used general-purpose output ports under serial data control. Active Handling when unused
OPEN
Common driver outputs frame frequency given (fOSC/512)Hz.
OPEN
KS1/S54 KS2/S55
scan outputs Although normal scan timing lines require diodes inserted timing lines prevent shorts, since these outputs unbalanced CMOS transistor outputs, these outputs will damaged shorting when these outputs used form matrix. KS1/S54 KS2/S55 pins used segment outputs when specified control data. scan inputs These pins have built-in pull-down resistors. Oscillator connection oscillator circuit formed connecting external resistor capacitor this pin. Serial data interface connections controller. Note that being open-drain output, requires pull-up resistor. :Chip enable :Synchronization clock :Transfer data :Output data Reset signal input RES=low Display scan disabled data reset RES=high Display scan enabled However, serial data transferred when low. This must connected ground. Used applying drive bias voltage externally. Must connected VLCD2 when bias drive scheme used. Used applying drive bias voltage externally. Must connected VLCD1 when bias drive scheme used. Logic block power supply connection. Provide voltage between 6.0V. driver block power supply connection. Provide voltage between VDD-0.5 6.0V. Power supply connection. Connect ground.
OPEN
OPEN
TEST VLCD1 VLCD2 VLCD
OPEN
OPEN
6086-7/27
LC75884E, LC75884W Serial Data Input When stopped level
Note: B3,A0 address Direction data
6086-8/27
LC75884E, LC75884W When stopped high level
Note: B3,A0 address Direction data address D220 Display data S0,S1 Sleep control data K0,K1 scan output/segment output selection data Segment output port/general-purpose output port selection data Segment on/off control data bias bias drive selection data
6086-9/27
LC75884E, LC75884W Control Data Functions Sleep control data These control data bits switch between normal mode sleep mode states scan outputs during scan standby.
Control data Mode Normal Sleep Sleep Sleep oscillator Operating Stopped Stopped Stopped Segment outputs Common outputs Operating Output states during scan standby
Note: This assumes that KS1/S54 KS2/S55 output pins selected scan output.
scan output /segment output selection data These control data bits switch functions KS1/S54 KS2/S55 output pins between scan output segment output.
Control data Output state KS1/S54 KS2/S55 Maximum number input keys
don't care Note: KSn(n=1 scan output (n=54 55): Segment output
Segment output port/general-purpose output port selection data These control data bits switch functions S1/P1 S4/P4 output pins between segment output port general-purpose output port.
Control data S1/P1 Output state S2/P2 S3/P3 S4/P4
Note: Sn(n=1 Segment output port Pn(n=1 General-purpose output port table below lists correspondence between display data output pins when these pins selected general-purpose output ports.
Output S1/P1 S2/P2 S3/P3 S4/P4
Corresponding display data
example, S4/P4 output selected general-purpose output port, S4/P4 output will output high level (VLCD) when display data will output level (Vss) when
6086-10/27
LC75884E, LC75884W Segment on/off control data This control data controls on/off state segments.
Display state
However, note that when segments turned setting segments turned outputting segment waveforms from segment output pins.
bias bias drive selection data This control data switches between bias bias drive.
Drive scheme bias drive bias drive
Display Data Output Correspondence
Output S1/P1 S2/P2 S3/P3 S4/P4 COM1 D101 D105 D109 COM2 D102 D106 D110 COM3 D103 D107 D111 COM4 D100 D104 D108 D112 Output KS1/S54 KS2/S55 COM1 D113 D117 D121 D125 D129 D133 D137 D141 D145 D149 D153 D157 D161 D165 D169 D173 D177 D181 D185 D189 D193 D197 D201 D205 D209 D213 D217 COM2 D114 D118 D122 D126 D130 D134 D138 D142 D146 D150 D154 D158 D162 D166 D170 D174 D178 D182 D186 D190 D194 D198 D202 D206 D210 D214 D218 COM3 D115 D119 D123 D127 D131 D135 D139 D143 D147 D151 D155 D159 D163 D167 D171 D175 D179 D183 D187 D191 D195 D199 D203 D207 D211 D215 D219 COM4 D116 D120 D124 D128 D132 D136 D140 D144 D148 D152 D156 D160 D164 D168 D172 D176 D180 D184 D188 D192 D196 D200 D204 D208 D212 D216 D220
Note: This case where output pins S1/P1 S4/P4, KS1/S54 KS2/S55 selected segment outputs.
6086-11/27
LC75884E, LC75884W example, table below lists segment output states output pin.
Display data Output state (S11) segments COM1,COM2,COM3 COM4 off. segment COM4 segment COM3 segments COM3 COM4 segment COM2 segments COM2 COM4 segments COM2 COM3 segments COM2,COM3 COM4 segment COM1 segments COM1 COM4 segments COM1 COM3 segments COM1,COM3 COM4 segments COM1 COM2 segments COM1,COM2 COM4 segments COM1,COM2 COM3 segments COM1,COM2,COM3 COM4
Serial Data Output When stopped level
Note: address
When stopped high level
Note: address address KD30 data Sleep acknowledge data Note: data read operation executed when high, read data (KD1 KD30) sleep acknowledge data(SA) will invalid.
6086-12/27
LC75884E, LC75884W Output Data KD30 data When matrix keys formed from output pins input pins those keys pressed, output data corresponding that will table shows relationship between those pins data bits.
KS1/S54 KS2/S55 KD11 KD16 KD21 KD26 KD12 KD17 KD22 KD27 KD13 KD18 KD23 KD28 KD14 KD19 KD24 KD29 KD10 KD15 KD20 KD25 KD30
When KS1/S54 KS2/S55 output pins selected segment outputs control data bits matrix keys formed using output pins input pins, KD10 data bits will Sleep acknowledge data This output data state when pressed. Also, while will this case, serial data input mode normal sleep mode) during this period, that mode will set. will sleep mode normal mode. Sleep Mode Functions Sleep mode setting control data segment outputs will common outputs will also low, oscillator will stop will started press). This reduces power dissipation. This mode cleared sending control data with both However, note that S1/P1 S4/P4 outputs used general-purpose output ports according state control data bits, even sleep mode. (See control data description details.)
6086-13/27
LC75884E, LC75884W Scan Operation Functions scan timing scan period 384T(s). reliably determine on/off state keys, LC75884E/W scans keys twice determines that been pressed when data agrees. outputs data read request level 800T(s) after starting scan. data dose agree pressed that point, scans keys again. Thus LC75884E/W cannot detect press shorter than 800T(s).
Note: *3.In sleep mode high/low state these pins determined bits control data. scan output signals output from pins that low.
normal mode pins high. When pressed scan started keys scanned until keys released. Multiple presses recognized determining whether multiple data bits set. pressed longer than 800T(s) (Where LC75884E/W outputs data read request fosc level controller. controller acknowledges this request reads data. However, high during serial data transfer, will high. After controller reads data, data read request cleared high) LC75884E/W performs another scan. Also note that being open-drain output, requires pull-up resistor (between
6086-14/27
LC75884E, LC75884W sleep mode pins high bits control data. (See control data description details.) lines corresponding which high pressed, oscillator started scan performed. Keys scanned until keys released. Multiple presses recognized determining whether multiple data bits set. pressed longer than 800T(s)(Where LC75884E/W outputs data read request fosc level controller. controller acknowledges this request reads data. However, high during serial data transfer, will high. After controller reads data, data read request cleared high) LC75884E/W performs another scan. However, this dose clear sleep mode. Also note that being open-drain output, requires pull-up resistor (between Sleep mode scan example Example: S0=0, S1=1 (sleep with only high)
Note: *4.These diodes required reliable recognize multiple presses line when sleep mode state with only high, above example. That these diodes prevent incorrect operations sneak currents scan output signal when keys lines pressed same time.
Multiple Presses Although LC75884E/W capable scanning without inserting diodes dual presses, triple presses input lines, multiple presses output lines, multiple presses other than these cases result keys that were pressed recognized having been pressed. Therefore, diode must inserted series with each key. Applications that recognize multiple presses three more keys should check data three more bits ignore such data.
6086-15/27
LC75884E, LC75884W Duty, Bias Drive Technique
COM1
VLCD VLCD1, VLCD2 VLCD VLCD1, VLCD2 VLCD VLCD1, VLCD2 VLCD VLCD1, VLCD2 VLCD VLCD1, VLCD2 VLCD VLCD1, VLCD2 VLCD VLCD1, VLCD2 VLCD VLCD1, VLCD2 VLCD VLCD1, VLCD2 VLCD VLCD1, VLCD2 VLCD VLCD1, VLCD2 VLCD VLCD1, VLCD2 VLCD VLCD1, VLCD2 VLCD VLCD1, VLCD2 VLCD VLCD1, VLCD2
COM2
COM3
COM4
driver output when segments corresponding COM1, COM2, COM3 COM4 turned off.
driver output when only segments corresponding COM1
driver output when only segments corresponding COM2
driver output when segments corresponding COM1 COM2
driver output when only segments corresponding COM3
driver output when segments corresponding COM1 COM3
driver output when segments corresponding COM2 COM3
driver output when segments corresponding COM1, COM2 COM3
driver output when only segments corresponding COM4
driver output when segments corresponding COM2 COM4
driver output when segments corresponding COM1, COM2, COM3 COM4
Duty, Bias Waveforms
6086-16/27
LC75884E, LC75884W Duty, Bias Drive Technique
COM1
COM2
VLCD VLCD1 VLCD2 VLCD VLCD1 VLCD2 VLCD VLCD1 VLCD2 VLCD VLCD1 VLCD2 VLCD VLCD1 VLCD2 VLCD VLCD1 VLCD2 VLCD VLCD1 VLCD2 VLCD VLCD1 VLCD2 VLCD VLCD1 VLCD2 VLCD VLCD1 VLCD2 VLCD VLCD1 VLCD2 VLCD VLCD1 VLCD2 VLCD VLCD1 VLCD2 VLCD VLCD1 VLCD2 VLCD VLCD1 VLCD2
COM3
COM4
driver output when segments corresponding COM1, COM2, COM3 COM4 turned off.
driver output when only segments corresponding COM1
driver output when only segments corresponding COM2
driver output when segments corresponding COM1 COM2
driver output when only segments corresponding COM3
driver output when segments corresponding COM1 COM3
driver output when segments corresponding COM2 COM3
driver output when segments corresponding COM1, COM2 COM3
driver output when only segments corresponding COM4
driver output when segments corresponding COM2 COM4
driver output when segments corresponding COM1, COM2, COM3 COM4
Duty, Bias Waveforms
6086-17/27
LC75884E, LC75884W Voltage Detection Type Reset Circuit (VDET) This circuit generates output signal resets system when logic block power first applied when voltage drops, i.e., when logic block power supply voltage less than equal power down detection voltage VDET, which 3.0V, typical. assure that this function operates reliably, capacitor must added logic block power supply line that logic block power supply voltage rise time when logic block power first applied logic block power supply voltage fall time when voltage drops both least (See Figure Power Supply Sequence following sequences must observed when power turned off. (See Figure Power :Logic block power supply(VDD) driver block power supply(VLCD) Power off:LCD driver block power supply(VLCD) Logic block power supply(VDD) However, logic driver block shared power supply, then power supplies turned same time. System Reset LC75884E/W supports reset methods described below. When system reset applied, display turned off, scanning stopped, data reset low. When reset cleared, display turned scanning become possible. Reset methods Reset power-on power-down least assured logic block supply voltage rise time when logic block power applied, system reset will applied VDET output signal when logic block supply voltage brought least assured logic block supply voltage fall time when logic block power drops, system reset will applied same manner VDET output signal when supply voltage lowered. Note that reset cleared point when serial data (the display data D220 control data) been transferred, i.e., fall signal transfer last direction data, after direction data been transferred. However, above operations will performed regardless state (high low) pin. high, reset will cleared point above operations completed. other hand, low, system will remain reset period long high, even above operations completed. (See Figure
6086-18/27
LC75884E, LC75884W
Note: [ms] (Logic block power supply voltage rise time) [ms] (Logic block power supply voltage fall time)
Reset when logic block power supply voltage allowable operating range (VDD 6.0V) system reset when low, reset cleared setting high. LC75884E/W internal block states during reset period CLOCK GENERATOR Reset applied base clock stopped. However, state (normal sleep mode) determined after control data bits transferred. COMMON DRIVER, SEGMENT DRIVER LATCH Reset applied display turned off. However, display data input latch circuit this state. SCAN Reset applied, circuit initial state, same time scan operation disabled. BUFFER Reset applied data low. INTERFACE, CONTROL REGISTER, SHIFT REGISTER Since serial data transfer possible, these circuits reset.
6086-19/27
LC75884E, LC75884W
Output states during reset period
Output S1/P1 S4/P4 COM1 COM4 KS1/S54, KS2/S55 State during reset
don't care Note: *5.These output pins forcibly segment output function held low. *6.When power first applied, these output pins undefined until control data bits have been transferred. *7.Since this output open-drain output, pull-up resistor between required. This remains high during reset period even data read operation performed.
6086-20/27
LC75884E, LC75884W Sample Application Circuit bias (for with normal panels)
Note:
capacitor logic block power supply line that logic block power supply voltage rise time when power applied logic block power supply voltage fall time when power drops both least LC75884E/W reset VDET. used system reset, must connected logic block power supply VDD. *10. pin, being open-drain output, requires pull-up resistor. Select resistance (between appropriate capacitance external wiring that signal waveforms degraded.
6086-21/27
LC75884E, LC75884W Sample Application Circuit bias (for with large panels)
Note:
capacitor logic block power supply line that logic block power supply voltage rise time when power applied logic block power supply voltage fall time when power drops both least LC75884E/W reset VDET. used system reset, must connected logic block power supply VDD. *10. pin, being open-drain output, requires pull-up resistor. Select resistance (between appropriate capacitance external wiring that signal waveforms degraded.
6086-22/27
LC75884E, LC75884W Sample Application Circuit bias (for with normal panels)
Note:
capacitor logic block power supply line that logic block power supply voltage rise time when power applied logic block power supply voltage fall time when power drops both least LC75884E/W reset VDET. used system reset, must connected logic block power supply VDD. *10. pin, being open-drain output, requires pull-up resistor. Select resistance (between appropriate capacitance external wiring that signal waveforms degraded.
6086-23/27
LC75884E, LC75884W Sample Application Circuit bias (for with large panels)
Note:
capacitor logic block power supply line that logic block power supply voltage rise time when power applied logic block power supply voltage fall time when power drops both least LC75884E/W reset VDET. used system reset, must connected logic block power supply VDD. *10. pin, being open-drain output, requires pull-up resistor. Select resistance (between appropriate capacitance external wiring that signal waveforms degraded.
Notes transferring display data from controller display data 220) transferred LC75884E/W four operations. display data should transferred within maintain quality displayed image.
6086-24/27
LC75884E, LC75884W Notes controller data read techniques Timer based data acquisition Flowchart
Timing chart
scan execution time when data agreed scans. (800T(s)) scan execution time when data agree scans scan executed again. (1600T(s)) address (43H) transfer time data read time fosc Explanation this technique, controller uses timer determine on/off states read data. controller must check state when every period without fail. low, controller recognizes that been pressed executes data read operation. period this technique must satisfy following condition. t9>t6+t7+t8 data read operation executed when high, read data (KD1 KD30) sleep acknowledge data (SA) will invalid.
6086-25/27
LC75884E, LC75884W Interrupt based data acquisition Flowchart
Timing chart
scan execution time when data agreed scans. (800T(S)) scan execution time when data agree scans scan executed again. (1600T(S)) address (43H) transfer time data read time fosc
6086-26/27
LC75884E, LC75884W Explanation this technique, controller uses interrupts determine on/off states read data. controller must check state when low. low, controller recognizes that been pressed executes data read operation. After that next on/off determination performed after time elapsed checking state when reading data. period this technique must satisfy following condition. data read operation executed when high, read data (KD1 KD30) sleep acknowledge data (SA) will invalid.
Specifications SANYO products described contained herein stipulate performance, characteristics, functions described products independent state, guarantees performance, characteristics, functions described products mounted customer's products equipment. verify symptoms states that cannot evaluated independent device, customer should always evaluate test devices mounted customer's products equipment. SANYO Electric Co., Ltd. strives supply high-quality high-reliability products. However, semiconductor products fail with some probability. possible that these probabilistic failures could give rise accidents events that could endanger human lives, that could give rise smoke fire, that could cause damage other property. When designing equipment, adopt safety measures that these kinds accidents events cannot occur. Such measures include limited protective circuits error prevention circuits safe design, redundant design, structural design. event that SANYO products (including technical data, services) described contained herein controlled under applicable local export control laws regulations, such products must exported without obtaining export license from authorities concerned accordance with above law. part this publication reproduced transmitted form means, electronic mechanical, including photocopying recording, information storage retrieval system, otherwise, without prior written permission SANYO Electric Co., Ltd. information described contained herein subject change without notice product/technology improvement, etc. When designing equipment, refer "Delivery Specification" SANYO product that intend use. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties.
This catalog provides information February, 1999. Specifications information herein subject change without notice. 6086-27/27
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