µPD78011H(A), 78012H(A), 78013H(A), 78014H(A) 8-BIT SINGLE-CHIP M

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µPD78011H(A), 78012H(A), 78013H(A), 78014H(A) 8-BIT SINGLE-CHIP M

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INTEGRATED CIRCUIT
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
Compared µPD78011H, 78012H, 78013H, 78014H (standard models), µPD78011H(A), 78012H(A), 78013H(A), 78014H(A) employ stricter quality-assurance program. (NEC calls this quality grade "special grade"). µPD78011H(A), 78012H(A), 78013H(A), 78014H(A) products µPD78014H subseries within 78K/0 series. Compared with older µPD78018F subseries, this subseries reduces (Electro Magnetic Interface) noise generated from microcontroller. Functions described detail following User's Manual, which should read when carring design work. µPD78014H Subseries User's Manual: Planned publish 78K/0 Series User's Manual Instruction: IEU-1372
FEATURES
noise model Large on-chip
Item Product Name
Program Memory (ROM) bytes bytes bytes bytes
Data Memory Internal HighSpeed bytes Internal Buffer bytes Package 64-pin plastic shrink (750 mil) 64-pin plastic 1024 bytes
µPD78011H(A) µPD78012H(A) µPD78013H(A) µPD78014H(A)
External memory expansion space bytes Instruction execution time varied from high-speed (0.4 ultra-low-speed (122 ports: (N-ch open-drain 8-bit resolution converter channels Serial interface channels Timer channels Supply voltage
APPLICATION FIELD
Control unit automotive, leak breaker, safety devices, etc.
information this document subject change without notice. Document U12174EJ1V0DS00 (1st edition) Date Published March 1997 Printed Japan
1997
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
ORDERING INFORMATION
Part Number Package 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin plastic plastic plastic plastic plastic plastic plastic plastic shrink shrink shrink shrink (750 mil) (750 mil) (750 mil) (750 mil)
Remark indicates code
Please refer "Quality Grades Semiconductor Devices" (Document C11531E) published Corporation know specification quality grade devices recommended applications.
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
78K/0 Series Expansion following shows 78K/0 Series products development. Subseries name shown inside frames.
Products mass production Products under development subseries products compatible with bus. Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin
PD78075B PD78078 PD78070A
µPD78075BY µPD78078Y PD78070AY
EMI-noise reduced version PD78078 timer added PD78054 external interface enhanced ROM-less version µPD78078 Serial PD78078 enhanced function limited. Serial PD78054 enhanced EMI-noise reduced. EMI-noise reduced version PD78054 UART converter were enhanced PD78014 enhanced converter PD780024 enhanced Serial PD78018F added EMI-noise reduced. EMI-noise reduced version µPD78018F Low-voltage (1.8 operation version µPD78014, with larger selection capacities converter 16-bit timer were added µPD78002 converter added µPD78002 Basic subseries control On-chip UART, capable operating voltage (1.8
PD780018Note PD780018YNote PD780058 PD780058YNote PD78058F PD78058FY µPD78054 PD78054Y µPD780034 µPD780034Y PD780024Y PD780024 PD78014H µPD78018F µPD78014 PD780001 µPD78002 PD78083
Inverter control
µPD78018FY PD78014Y PD78002Y
64-pin 64-pin
µPD780964 µPD780924
FIPdrive
converter PD780924 enhanced On-chip inverter control circuit UART. EMI-noise reduced.
100-pin 100-pin 78K/0 Series 80-pin 80-pin
PD780208 PD780228 PD78044H µPD78044F
drive
PD78044F were enhanced, Display output total: PD78044H were enhanced, Display output total:
N-ch open drain added PD78044F, Display output total:
Basic subseries driving FIP, Display output total:
100-pin 100-pin 100-pin
PD780308 µPD78064B µPD78064
µPD780308Y PD78064Y
µPD78064 enhanced, ROM, capacity increased EMI-noise reduced version PD78064 Basic subseries driving LCDs, On-chip UART
IEBussupported 80-pin
PD78098
IEBus controller added µPD78054
64-pin
PD78P0914
On-chip output, digital code decoder, Hsync counter
Note Under planning
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
following lists main functional differences between subseries products.
Function Subseries Name Control Capacity 32K-40K 48K-60K 48K-60K 24K-60K 48K-60K 16K-60K 8K-32K (UART: 1ch, time division 3-wire: 1ch) 8K-60K 8K-32K 8K-16K 8K-32K Note 32K-60K 48K-60K 32K-48K 16K-40K 48K-60K 16K-32K 32K-60K (UART: 1ch) (time division UART: 1ch) (UART: 1ch) (UART: 1ch) (UART: 2ch) (time division 3-wire: 1ch) 8-bit 10-bit 8-bit 8-bit 16-bit Watch Timer Serial Interface MIN. Value External Expansion
µPD78075B µPD78078 µPD78070A µPD780018 µPD780058 µPD78058F µPD78054 µPD780034 µPD780024 µPD78014H µPD78018F µPD78014 µPD780001 µPD78002 µPD78083
(UART: 1ch)
(time division UART: 1ch) (UART: 1ch)
Inverter control drive
µPD780964 µPD780924 µPD780208 µPD780228 µPD78044H µPD78044F
drive
µPD780308 µPD78064B µPD78064
IEBus supported
µPD78098
µPD78P0914
Note 10-bit timer: channel
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
OVERVIEW FUNCTION
Item Product Name High-speed Buffer
µPD78011H(A)
bytes
µPD78012H(A)
bytes bytes
µPD78013H(A)
bytes
µPD78014H(A)
bytes
Internal memory
1024 bytes
bytes bytes bits registers bits registers banks) On-chip instruction execution time cycle modification function µs/0.8 µs/1.6 µs/3.2 µs/6.4 10.0 operation) 32.768 operation) 16-bit operation Multiplication/division bits bits,16 bits bits) manipulation (set, reset, test, boolean operation) correction, etc.
Memory space General-purpose registers Instruction cycle When main system clock selected When subsystem clock selected Instruction
ports
Total CMOS input CMOS N-channel open-drain withstand voltage)
converter
8-bit resolution channels Operable over wide power supply voltage range: AVDD 3-wire serial I/O/SBI /2-wire serial mode selectable: channel 3-wire serial mode (on-chip max. bytes automatic data transmit/receive function): channel 16-bit timer/event counter 8-bit timer/event counter Watch timer Watchdog timer channel channels channel channel
Serial interface
Timer
Timer output Clock output
(14-bit output 39.1 kHz, 78.1 kHz, kHz, kHz, kHz, 1.25 main system clock: 10.0 operation), 32.768 subsystem clock: 32.768 operation) kHz, kHz, main system clock: 10.0 operation) Internal Internal Internal External External
Buzzer output Vectored interrupt sources Test input Supply voltage Operating ambient temperature Package Maskable Non-maskable Software
+85°C 64-pin plastic shrink (750 mil) 64-pin plastic
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
TABLE CONTENTS
CONFIGURATION (Top View) BLOCK DIAGRAM FUNCTIONS
PORT PINS OTHER PORTS CIRCUIT RECOMMENDED CONNECTION UNUSED PINS
MEMORY SPACE PERIPHERAL HARDWARE FUNCTION FEATURES
PORTS CLOCK GENERATOR TIMER/EVENT COUNTER CLOCK OUTPUT CONTROL CIRCUIT BUZZER OUTPUT CONTROL CIRCUIT CONVERTER SERIAL INTERFACES
INTERRUPT FUNCTIONS TEST FUNCTIONS
INTERRUPT FUNCTIONS TEST FUNCTIONS
EXTERNAL DEVICE EXPANSION FUNCTIONS STANDBY FUNCTIONS RESET FUNCTIONS
INSTRUCTION ELECTRICAL SPECIFICATIONS PACKAGE DRAWINGS RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTS
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
CONFIGURATION (Top View)
64-Pin Plastic Shrink (750 mil)
P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13
P17/ANI7 P16/ANI6 P15/ANI5 P14/ANI4 P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0 P04/XT1 P03/INTP3 P02/INTP2 P01/INTP1 P00/INTP0/TI0 RESET P67/ASTB P66/WAIT P65/WR P64/RD P57/A15 P56/A14
Cautions Always connect (Internally Connected) directly. AVDD multiplexed with converter power port power pin. application where noise generated from microcontroller must reduced, connect AVDD power supply same voltage VDD. AVSS multiplexed with converter ground port ground pin. application where noise generated from microcontroller must reduced, connect AVSS ground line separate from VSS.
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
64-Pin Plastic
P26/SO0/SB1
P25/SI0/SB0
P24/BUSY
P27/SCK0
P22/SCK1
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6
P12/ANI2
P21/SO1
P23/STB
P20/SI1
P11/ANI1 P10/ANI0 P04/XT1 P03/INTP3 P02/INTP2 P01/INTP1 P00/INTP0/TI0 RESET P67/ASTB P66/WAIT
P56/A14
P57/A15
P64/RD
P47/AD7
P52/A10
P53/A11
P54/A12
P55/A13
Cautions Always connect (Internally Connected) directly. AVDD multiplexed with converter power port power pin. application where noise generated from microcontroller must reduced, connect AVDD power supply same voltage VDD. AVSS multiplexed with converter ground port ground pin. application where noise generated from microcontroller must reduced, connect AVSS ground line separate from VSS.
P65/WR
P50/A8
P51/A9
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
A8-A15 AD0-AD7 ANI0-ANI7 ASTB AVDD AVREF AVSS BUSY INTP0-INTP3 P00-P04 P10-P17 P20-P27 P30-P37 P40-P47 P50-P57
Address Address/Data Analog Input Address Strobe Analog Power Supply Analog Reference Voltage Analog Ground Busy Buzzer Clock Internally Connected Interrupt from Peripherals Port Port Port Port Port Port
P60-P67 RESET SB0, SCK0, SCK1 SI0, SO0, TI0-TI2 TO0-TO2 WAIT XT1,
Port Programmable Clock Read Strobe Reset Serial Serial Clock Serial Input Serial Output Strobe Timer Input Timer Output Power Supply Ground Wait Write Strobe Crystal (Main System Clock) Crystal (Subsystem Clock)
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
BLOCK DIAGRAM
TO0/P30 TI0/INTP0/P00 TO1/P31 TI1/P33 TO2/P32 TI2/P34
16-bit TIMER/ EVENT COUNTER
PORT0 P01-P03
8-bit TIMER/ EVENT COUNTER
PORT1
P10-P17
8-bit TIMER/ EVENT COUNTER
PORT2
P20-P27
WATCHDOG TIMER
PORT3
P30-P37
WATCH TIMER 78K/0 CORE SERIAL INTERFACE
PORT4
P40-P47
SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 SERIAL INTERFACE
PORT5
P50-P57
PORT6
P60-P67 AD0/P40AD7/P47 A8/P50A15/P57
ANI0/P10ANI7/P17 CONVERTER AVREF
EXTERNAL ACCESS
RD/P64 WR/P65 WAIT/P66 ASTB/P67 RESET
INTP0/P00INTP3/P03
INTERRUPT CONTROL
SYSTEM CONTROL
BUZ/P36
BUZZER OUTPUT
PCL/P35
CLOCK OUTPUT CONTROL
AVDD AVSS
Remark Internal capacity varies depending product.
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
FUNCTIONS
PORT PINS (1/2)
Name P04Note Input Input/ output Input only Port 8-bit input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software.Note Port 8-bit input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software. Input Input Input Input/ output Port 5-bit port Input only Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software. Function Reset Input Input DualFunction INTP0/TI0 INTP1 INTP2 INTP3 ANI0 ANI7
Input/ output
Input
SCK1 BUSY SI0/SB0 SO0/SB1 SCK0
Input/ output
Port 8-bit input/output port. Input/output specified 1-bit units. When used input port, on-chip pull-up resistor used software.
Input
Input/ output
Port 8-bit input/output port. Input/output specified 8-bit unit. When used input port, on-chip pull-up resistor used software. Test input flag (KRIF) falling edge detection.
Input
Notes When using P04/XT1 input port pin, (FRC) processor clock control register (PCC) internal feedback resistor subsystem clock oscillation circuit). When using P10/ANI0 through P17/ANI7 pins analog input pins converter, internal pull-up resistors automatically used.
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
PORT PINS (2/2)
Name Input/ output Function Port 8-bit input/output port. driven directly. Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software. Port 8-bit input/output port. Input/output specified bit-wise. N-ch open-drain input/output port. On-chip pull-up resistor specified mask option. driven directly. Reset Input DualFunction
Input/ output
Input
When used input port, on-chip pull-up resistor used software.
WAIT ASTB
Caution manipulate pins multiplexed with port follows during conversion; otherwise, rated total error during conversion satisfied. Rewriting contents output latch when used output port pin. Changing output level used output even when used port pin. OTHER PORTS (1/2)
Name INTP0 INTP1 INTP2 INTP3 SCK0 SCK1 BUSY Input /output Input /output Output Input Serial interface serial data input/output. Input Output Serial interface serial data output. Input Input Input Function External interrupt request input which effective edge (rising edge, falling edge, both rising edge falling edge) specified. Falling edge detection external interrupt request input. Serial interface serial data input. Input Reset Input DualFunction P00/TI0 P25/SB0 P26/SB1 P25/SI0 P26/SO0 Serial interface serial clock input/output. Input Serial interface automatic transmit/receive strobe output. Serial interface automatic transmit/receive busy input. Input Input
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
OTHER PORTS (2/2)
DualFunction P00/INTP0 Input Input Input Input Input Input Input Input
Name WAIT ASTB
Input
Function External count clock input 16-bit timer (TM0). External count clock input 8-bit timer (TM1). External count clock input 8-bit timer (TM2).
Reset Input
Output
16-bit timer (TM0) output (multiplexed with 14-bit output). 8-bit timer (TM1) output. 8-bit timer (TM2) output.
Output Output Input /output Output Output
Clock output (for main system clock, subsystem clock trimming). Buzzer output. Low-order address/data external memory expansion. High-order address external memory expansion. External memory read operation strobe signal output. External memory write operation strobe signal output.
Input Output
Wait insertion external memory access. Strobe output which latches address information output port port access external memory. converter analog input. converter reference voltage input. converter analog power supply (multiplexed with port power pin). converter ground potential (multiplexed with port ground pin). System reset input. Main system clock oscillation crystal connection.
ANI0 ANI7 AVREF AVDD AVSS RESET
Input Input Input Input Input
Input
Subsystem clock oscillation crystal connection.
Input
Positive power supply (except port pins). Ground potential (except port pins). Internal connection. Connected directly.
Cautions AVDD multiplexed with converter power port power pin. application where noise generated from microcontroller must reduced, connect AVDD power supply same voltage VDD. AVSS multiplexed with converter ground port ground pin. application where noise generated from microcontroller must reduced, connect AVSS ground line separate from VSS.
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
CIRCUITS RECOMMENDED CONNECTION UNUSED PINS input/output circuit type each recommended connection unused pins shown Table 3-1. input/output circuit configuration each type, Figure 3-1. Table 3-1. Input/Output Circuit Type Each
Name P00/INTP0/TI0 P01/INTP1 P02/INTP2 P03/INTP3 P04/XT1 P10/ANI0 P17/ANI7 P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P40/AD0 P47/AD7 P50/A8 P57/A15 P64/RD P65/WR P66/WAIT P67/ASTB RESET AVREF AVDD AVSS Input Leave open. Connected Connected Connected Connected directly. 13-I Individually connected resistor. Individually connected resistor. Individually connected resistor. Individually connected resistor. 11-C 10-C Input Input/output Connected VSS. Individually connected resisitor. Input/output Circuit Type Input Input/output Recommended Connection when Used Connected Individually connected resistor.
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Figure 3-1. Input/Output Circuits
Type Type 10-C pullup enable data open drain output disable AVDD P-ch Schmitt-Triggered Input with Hysteresis Characteristic N-ch AVSS
P-ch
Type
pullup enable AVDD data output disable input enable
AVDD P-ch
Type 11-C
pullup enable data
P-ch AVDD P-ch N-ch P-ch AVSS N-ch AVSS VREF (Threshold Voltage)
P-ch N-ch AVSS
output disable Comparator
input enable
Type AVDD pullup enable data output disable P-ch AVDD P-ch N-ch AVSS
Type 13-I
Mask Option N-ch AVSS P-ch
data output disable
Middle-High Voltage Input Buffer
Type AVDD pullup enable data output disable P-ch N-ch AVSS Type
feedback cut-off
P-ch
P-ch
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
MEMORY SPACE
memory µPD78011H(A), 78012H(A), 78013H(A), 78014H(A) shown Figure 4-1.
Figure 4-1. Memory
FFFFH Special Function Registers (SFR) Bits FF00H FEFFH General-Purpose Registers Bits FEE0H FEDFH
Internal High-Speed RAMNote
mmmmH mmmmH-1 Prohibited FAE0H Data Memory Space FADFH FAC0H FABFH FA80H FA7FH Program Memory Space nnnnH+1 nnnnH Buffer Bits
nnnnH Program Area 1000H 0FFFH CALLF Entry Area Prohibited 0800H 07FFH Program Area External Memory 0080H 007FH CALLT Table Area 0040H 003FH Internal ROMNote Vector Table Area 0000H
0000H
Note
Internal internal high-speed capacities vary depending product (see table below).
Product Name
Intenal Address nnnnH 1FFFH 3FFFH 5FFFH 7FFFH
Internal High-Speed Start Address mmmmH FD00H
µPD78011H(A) µPD78012H(A) µPD78013H(A) µPD78014H(A)
FB00H
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
PERIPHERAL HARDWARE FUNCTION FEATURES
PORTS port following three types CMOS input (P00, P04) CMOS input/output (P01 P03, port port P67) N-ch open-drain input/output(15V withstand voltage) (P60 P63) Total
Table 5-1. Functions Ports
Port Name Port Name P00, Port Port Port Port Dedicated Input port Input/output ports. Input/output specified bit-wise. When used input port, pull-up resistor used software. Input/output ports. Input/output specified bit-wise. When used input port, pull-up resistor used software. Input/output ports. Input/output specified bit-wise. When used input port, pull-up resistor used software. Input/output ports. Input/output specified bit-wise. When used input port, pull-up resistor used software. Input/output ports. Input/output specified 8-bit units. When used input port, pull-up resistor used software. Test input flag (KRIF) falling edge detection. Input/output ports. Input/output specified bit-wise. When used input port, pull-up resistor used software. driven directly. N-ch open-drain input/output port. Input/output specified bit-wise. On-chip pull-up resistor specified mask option. driven directly. Input/output ports. Input/output specified bit-wise. When used input port, pull-up resistor used software. Function
Port
Port
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
CLOCK GENERATOR There types clock generator: main system clock subsystem clock. instruction exection time changed. 0.4µs/0.8µs/1.6µs/3.2µs/6.4µs (Main system clock: 10.0 operation) 122µs (Subsystem clock: 32.768 operation)
Figure 5-1. Clock Generator Block Diagram
XT1/P04
Subsystem Clock Osicillator
Watch Timer Clock Output Function Prescaler
Main System Clock Osicillator
Prescaler
Clock Peripheral Hardware
STOP
Selector
Standby Control Circuit
Wait Control Circuit
Clock (fCPU)
INTP0 Sampling Clock
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
TIMER/EVENT COUNTER following five channels incorporated timer/event counter. 16-bit timer/event counter 8-bit timer/event counter Watch timer Watchdog timer channel channels channel channel
Table 5-2. Types Functions Timer/Event Counter
16-bit Timer/Event Counter Type Interval timer Externanal event counter Functions Timer output output Pulse width mesurement Sqare wave output Interrupt request Test input channel channel output output input output 8-bit Timer/Event Counter channels channels outputs outputs
Watch Timer channel
Watchdog Timer channel
Figure 5-2. 16-bit Timer/Enent Counter Block Diagram
Internal
16-Bit Compare Register (CR00) Pulse Output Control Circuit 16-Bit Timer Register (TM0) Clear Selector Output Control Circuit
INTTM0
Match
TO0/P30
fX/2 fX/22 fX/23 TI0/INTP0/P00
Edge Detection Circuit Selector
INTP0 16-Bit Capture Register (CR01)
Internal
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Figure 5-3. 8-bit Timer/Enent Counter Block Diagram
Internal INTIM1 8-Bit Compare Register (CR10)
8-Bit Compare Register (CR20) Selector
Match
Output Control Circuit
TO2/P32 INTTM2
fX/22-fX/210 fX/212 TI1/P33
Selector 8-Bit Timer Register (TM1) Clear Selector 8-Bit Timer Register (TM2) Clear Selector Selector Output Control Circuit Internal
fX/22-fX/210 fX/212 TI2/P34
TO1/P31
Figure 5-4. Watch Timer Block Diagram
fX/28
Selector
Selector
5-Bit Counter
Selector INTWT
Prescaler
Selector
INTTM3
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Figure 5-5. Watchdog Timer Block Diagram
Prescaler
INTWDT Maskable Interrupt Request Selector 8-Bit Counter Control Circuit RESET INTWDT Non-Maskable Interrupt Request
CLOCK OUTPUT CONTROL CIRCUIT clock with following frequencies output clock output. 39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 (Main system clock: 10.0 operation) 32.768 (Subsystem clock: 32.768 operation)
Figure 5-6. Clock Output Control Block Diagram
fX/23 fX/24 fX/25 fX/26 fX/27 fX/28
Selector Synchronization Circuit Output Control Circuit PCL/P35
BUZZER OUTPUT CONTROL CIRCUIT clock with following frequencies output buzzer output. kHz/4.9 kHz/9.8 (Main system clock: 10.0 operation)
Figure 5-7. Buzzer Output Control Block Diagram
fX/210 fX/211 fX/212
Selector Output Control Circuit BUZ/P36
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
CONVERTER converter on-chip eight 8-bit resolution channels. There following method start conversion. Hardware starting Software starting
Figure 5-8. Converter Block Diagram
Series Resistor String ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 Succesive Approximation Register (SAR) AVSS Selector Selector Sample Hold Circuit Voltage Comparator AVDD AVREF
INTP3/P03
Falling Edge Detector
Control Circuit
INTAD INTP3
Conversion Result Register (ADCR)
Internal
Caution manipulate pins multiplexed with port (refer PORT PINS) during conversion; otherwise, rated total error during conversion satisfied. Rewriting contents output latch when used output port pin. Changing output level used output even when used port pin.
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
SERIAL INTERFACES There on-chip clocked serial interfaces follows. Serial Interface channel Serial Interface channel Table 5-3. Type Function Serial Interface
Function 3-wire serial mode 3-wire serial mode with automatic data transmit/ receive function (Serial Interface) mode 2-wire serial mode (MSB-first) (MSB-first) Serial Interface Channel (MSB/LSB-first switchable) Serial Interface Channel (MSB/LSB-first switchable) (MSB/LSB-first switchable)
Figure 5-9. Serial Interface Channel Block Diagram
Internal
SI0/SB0/P25
Selector
SO0/SB1/P26
Serial Shift Register (SIO0)
Output Latch
Selector
Release/Command/ Acknowledge Detection Circuit Serial Clock Counter
Busy/Acknowledge Output Circuit
SCK0/P27
Interrupt Request Signal Generator
INTCSI0
fx/22-fx/29
Serial Clock Control Circuit
Selector
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Figure 5-10. Serial Interface Channel Block Diagram
Internal
Automatic Data Transmit/ Receive Address Pointer (ADTP)
Buffer
SI1/P20
Serial Shift Register (SIO1)
SO1/P21
STB/P23
BUSY/P24
Handshake Control Circuit
SCK1/P22
Serial Clock Counter
Interrupt Request Signal Generator
INTCSI1
fX/22 fX/29 Serial Clock Control Circuit Selector
µPD78011H(A), 78012H(A), 78013FH(A), 78014H(A)
INTERRUPT FUNCTIONS TEST FUNCTIONS
INTERRUPT FUNCTIONS There interrupt sources different kind shown below. Non-maskable Maskable Software
Table 6-1. Interrupt Source List
Default Priority Note Interrupt Source Name INTWDT Trigger Watchdog timer overflow (with watchdog timer mode selected) Watchdog timer overflow (with interval timer mode selected) input edge detection External 0006H 0008H 000AH 000CH Serial interface channel transfer Serial interface channel transfer Reference time interval signal from watch timer timer/event counter match signal generation 8-bit timer/event counter match signal generation 8-bit timer/event counter match signal generation converter conversion instruction execution Internal 000EH 0010H 0012H Internal/ External Vector Table Address Basic Configuratin Type Note Internal 0004H
Interrupt Type
Non-maskable
Maskable
INTWDT
INTP0 INTP1 INTP2 INTP3 INTCSI0 INTCSI1 INTTM3
INTTM0
0014H
INTTM1
0016H
INTTM2
0018H
Software
INTAD
001AH 003EH
Notes default pririty priority applicable when more than maskable interrupt generated. highest priority lowest. Basic configuration types correspond next page.
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Figure 6-1. Basic Interrupt Function Configuration (1/2)
Internal Non-Maskable Interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
Internal Maskable Interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
External Maskable Interrupt (INTP0)
Internal
Sampling Clock Select Register (SCS)
External Interrupt Mode Register (INTM0)
Interrupt Request
Sampling Clock
Edge Detector
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
µPD78011H(A), 78012H(A), 78013FH(A), 78014H(A)
Figure 6-1. Basic Interrupt Function Configuration (2/2) External Maskable Interrupt (Except INTP0)
Internal
External Interrupt Mode Register (INTM0)
Interrupt Request
Edge Detector
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
Software Interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator
Interrupt request flag Interrupt enable flag In-service priority flag Interrupt mask flag Priority spcification flag
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
TEST FUNCTIONS There test functions shown Table 6-2.
Table 6-2. Test Source List
Test Source Internal/External Name INTWT INTPT4 Trigger Watch timer overflow Port falling edge detection Internal External
Figure 6-2. Test Function Basic Configuration
Internal
Test Input
Standby Release Signal
Test input flag
Test mask flag
µPD78011H(A), 78012H(A), 78013FH(A), 78014H(A)
EXTERNAL DEVICE EXPANSION FUNCTIONS
external device expansion function used connect external devices areas other than internal ROM, SFR. Ports used connection with external devices.
STANDBY FUNCTIONS
There following standby functions reduce current dissipation. HALT mode operating clock stopped. average consumption current reduced intermittent operation combination with normal operat mode. STOP mode main system clock oscillation stopped. whole operation main system clock stopped, that system operates withultra-low power consumption using only subsystem clock.
Figure 8-1. Standby Functions
Main System Clock Operation Interrupt Request STOP Instruction Interrupt Request
CSS=1 CSS=0 HALT Instruction
Subsystem Clock OperationNote HALT Instruction
Interrupt Request
STOP Mode (Main system clock oscillation stopped)
HALT Mode (Clock supply stopped, oscillation)
HALT ModeNote (Clock supply stopped, oscillation)
Note power consumption reduced stopping main system clock. When operating subsystem clock, stop main system clock. STOP instruction cannot used.
Caution
When main system clock stopped system operated subsystem clock, subsystem clock should switched again main system clock after oscillation stabilization time secured program program.
RESET FUNCTIONS
There following reset methods. External reset input RESET pin. Internal reset watchdog timer runaway time detection.
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
INSTRUCTION
8-Bit Instruction MOV, XCH, ADD, ADDC, SUB, SUBC, AND, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Operand #byte Operand ADDC SUBC ADDC SUBC ADDC SUBC sadder DBNZ DBNZ ADDC SUBC ADDC SUBC ADDC SUBC Note saddr !addr16 [DE] [HL] [HL+byte] [HL+B] $adder16 [HL+C] ADDC SUBC None
RORC ROLC
ADDC SUBC
!adder16
PUSH
[DE] [HL]
ROR4 ROL4
[HL+byte] [HL+B] [HL+C]
MULU DIVUW
Note Except
µPD78011H(A), 78012H(A), 78013FH(A), 78014H(A)
16-Bit Instruction MOVW, XCHW ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Operand Operand #byte ADDW SUBW CMPW MOVW MOVWNote INCW, DECW PUSH, Note MOVW XCHW saddrp MOVW !addr16 MOVW MOVW None MOVW
sfrp saddrp !addr16
MOVW MOVW
MOVW MOVW MOVW
MOVW
MOVW
Note Only when rp=BC, Manipulation Instruction MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BTCLR
Operand A.bit Operand A.bit MOV1 BTCLR BTCLR BTCLR BTCLR BTCLR SET1 CLR1 sfr.bit saddr.bit PWS.bit [HL].bit $addr16 None
sfr.bit
MOV1
SET1 CLR1
saddr.bit
MOV1
SET1 CLR1
PSW.bit
MOV1
SET1 CLR1
[HL].bit
MOV1
SET1 CLR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
SET1 CLR1 NOT1
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Call Instruction/Branch Instruction CALL, CALLF, CALLT, BNC, BNZ, BTCLR, DBNZ
Operand Operand Basic instruction CALL, CALLF CALLT BNC, BTCLR, DBNZ !addr16 !addr11 [addr5] $addr16
Compound instruction
Other Instruction ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, HALT, STOP
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter Supply voltage Symbol AVDD AVREF AVSS Input voltage Output voltage Analog input voltage Output current high P17, P27, total P03, P47, P57, total Output current Peak value P47, total Peak value P03, P56, P57, IOLNote total P03, total Peak value Peak value Analog input P04, P17, P27, toP47, P57, P67, Open-drain -0.3 -0.3 -0.3 AVREF Test Conditions Rating -0.3 -0.3 -0.3 -0.3 -0.3 Unit
P17, P27, Peak value total Operating ambient temperature Storage temperature
Tstg
+150
Note should calculated follows: [rms] [peak value] duty Caution Product quality suffer absolute maximum rating exceeded even single parameter even momentarily. That absolute maximuam ratings rated values which product verge suffering physical damage, therefore product must used under conditions which ensure that absolute maximum ratings exceeded.
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Capacitance
Parameter Input capacitance capacitance Symbol Test Conditions Unmeasured pins returned P03, P17, Unmeasured P27, toP37, pins returned toP47, P57, MIN. TYP. MAX. Unit
Remark
characteristics dual-function port same unless specified otherwise.
Main System Clock Oscillation Circuit Characteristics
Resonator Ceramic resonator Recommended Circuit
Parameter Oscillator frequency (fX) Note Oscillation stabilization time Note Oscillator frequency (fX) Note Oscillation stabilization time Note input frequency (fX) Note input high/low level width (tXH tXL)
Test Conditions After reaches oscillator voltage range MIN.
MIN.
TYP.
MAX.
Unit
Crystal resonator
External clock
10.0
PD74HCU04
Notes Indicates only oscillation circuit characteristics. Refer Characteristics instruction execution time. Time required stabilize oscillation after reset STOP mode release. Cautions When using main system clock oscillator, wirinin area enclosed with dotted line should carried follows avoid adverse effect from wiring capacitance. Wiring should short possible. Wiring should cross other signal lines. Wiring should placed close varying high current. potential oscillator capacitor ground should same VSS. ground wiring ground pattern which high current flows. fetch signal from oscillator. When main system clock stopped system operated subsystem clock, subsystem clock should switched again main system clock after oscillation stabilization time secured program.
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Subsystem Clock Oscillation Circuit Characteristics
Resonator Crystal resonator Recommended Circuit
Parameter Oscillator frequency (fXT) Note Oscillation stabilization time Note input frequency (fXT) Note input high/low level width (tXTH tXTL)
Test Conditions
MIN.
TYP.
MAX.
Unit
32.768
External clock
Notes Indicates only oscillation circuit characteristics. Refer Characteristics instruction execution time. Time required stabilize oscillation after reaches oscillator voltage MIN. Cautions When using subsystem clock oscillator, wiring area enclosed with dotted line should carried follows avoid adverse effect from wiring capacitance. Wiring should short possible. Wiring should cross other signal lines. Wiring should placed close varying high current. potential oscillator capacitor ground should same VSS. ground wiring ground pattern which high current flows. fetch signal from oscillator. subsystem clock oscillation circuit circuit with amplification level,more prone misoperation noise than main system clock. Particular care therefore required with wiring method when subsystem clock used.
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Characteristics
Parameter Input voltage high Symbol VIH1 Test Conditions P10-P17, P21, P23, P30-P32, P35-P37, P40-P47, P50-P57, P64-67 VIH2 P00-P03, P20, P22, P24-P27, P33, P34, RESET VIH3 P60-P63 (N-ch open-drain) VIH4 Note Input voltage VIL1 P10-P17, P21, P23, P30-P32, P35-P37, P40-P47, P50-P57, P64-67 VIL2 P00-P03, P20, P22, P24-P27, P33, P34, RESET VIL3 P60-P63 VIL4 Note Output voltage high Output voltage P03, P17, P37, P47, VOL2 SB0, SB1, SCK0 VOL1 VOH1 -100 P57, open-drain pulled-up VOL3 VIL5 XT1/P04, 0.15 0.85 VIH5 XT1/P04, MIN. TYP. MAX. Unit
Note
When using XT1/P04 P04, input inverse using inverter. characteristics dual-function port same unless specified otherwise.
Remark
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Characteristics
Parameter Symbol Test Conditions P03, P17, P27, P37, P47, P57, P67, RESET ILIH2 ILIH3 Input leakege ILIL1 current XT1/P04, P03, P17, P27, P37, P47, P57, P67, RESET ILIL2 ILIL3 Output leakage ILOH1 current high Output leakage ILOL current Mask option pull-up resister Software pull-up resister P03, P17, P27, P37, P47, P57, VOUT VOUT XT1/P04, Note MIN. TYP. MAX. Unit
Input leakage ILIH1 current high
Note P60-P63, pull-up resistor provided (specifiable mask option) low-level input leak current -200 (MAX.) flows only during clocks (no-wait time) after instruction been executed read port (P6) port mode register (PM6). Outside period clocks following execution read-out instruction, current (MAX.). Remark characteristics dual-function port same unless specified otherwise.
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Characteristics
Parameter Supply current
Note
Symbol IDD1 10.00 crystal
Test Conditions Note
Note Note
MIN.
TYP.
MAX. 18.0
Unit
oscillation operation mode IDD2 10.00 crystal oscillation HALT mode IDD3 32.768 crystal oscillation operation mode
Note
Note Note
Note Note
IDD4
32.768 crystal oscillation HALT mode
Note
Note Note Note Note
IDD5
STOP mode when using feedback resistor
0.05 0.05
IDD6
STOP mode when using feedback resistor
Notes Current flowing into AVDD pins. However, current flowing into converter internal pullup resistors included. When operating high-speed mode (when processor clock control register (PCC) 00H) When operating low-speed mode (when 04H) When main system clock stopped.
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Characteristics Basic Operation
Parameter Cycle time (Min. instruction execution time) Operating subsystem clock input frequency tTIH0 tTIL0 TI1, input frequency TI1, input high/low-level width Interrupt input tINTH high/low-level width INTP1-INTP3, KR0-KR7 tINTL INTP0 tTIH1 tTIL1 2/fsam+0.1 Note 2/fsam+0.2 Note 2/fsam+0.5 RESET level width tRSL
Note
Symbol
Test Conditions Operating main system clock
MIN. 2/fsam+0.1 2/fsam+0.2
Note Note
TYP.
MAX.
Unit
2/fsam+0.5 Note
fTI1
Note combination with bits (SCS0) (SCS1) sampling clock select register, selection fsam possible between fX/2N+1, fX/64 fx/128 (when
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
main system clock operation)
60.0
10.0
Operation Guaranteed Range
Cycle Time
Supply voltage
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Read/Write Operation
Parameter ASTB high-level width Address setup time Address hold time Data input time from address Symbol tASTH tADS tADH tADD1 tADD2 Data input time from tRDD1 tRDD2 Read data hold time low-level width tRDH tRDL1 tRDL2 WAIT input time from tRDWT1 tRDWT2 WAIT input time from WAIT low-level width Write data setup time Write data hold time low-level width delay time from ASTB delay time from ASTB ASTB delay time from external fetch Address hold time from external fetch Write data output time from tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR tRDAST tRDADH tRDWD Load resistor (0.5+2n)tCY+10 (2.5+2n) 0.5tCY-30 1.5tCY-30 tCY-10 0.5tCY+5 0.5tCY+15 Write data output time from tWRWD Address hold time from tWRADH delay time from WAIT delay time from WAIT tWTRD tWTWR 0.5tCY 0.5tCY tCY+40 tCY+50 0.5tCY+30 0.5tCY+90 tCY+60 tCY+100 2.5tCY+80 2.5tCY+80 (1.5+2n)tCY-20 (2.5+2n) tCY-20 0.5tCY 1.5tCY 0.5tCY (2+2n)tCY Test Conditions MIN. 0.5tCY 0.5tCY-30 (2.5+2n)tCY-50 (3+2n)tCY-100 (1+2n)tCY-25 (2.5+2n)tCY-100 MAX. Unit
Remarks TCY/4 indicates number waits.
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Serial Interface Serial Interface Channel 3-wire serial mode (SCK0. Internal clock output)
Parameter SCK0 cycle time Symbol tKCY1 Conditions MIN. 1600 3200 4800 SCK0 high/low-level width setup time SCK0) tKH1 tKL1 tSIK1 tKCY1/2-50 tKCY1/2-100 hold time (from SCK0) output delay time from SCK0 tKSO1 Note tKSI1 TYP. MAX. Unit
Note load capacitance SCK0 output line. (ii) 3-wire serial mode (SCK0. External clock input)
Parameter SCK0 cycle time Symbol tKCY2 Test Conditions MIN. 1600 3200 4800 SCK0 high/low-level width tKH2 tKL2 1600 2400 setup time SCK0) hold time (from SCK0) output delay time from SCK0 SCK0 rise, fall time When external device expansion function used When external When 16-bit timer tKSO2 Note tKSI2 tSIK2 TYP. MAX. Unit
device expansion output function function used used When 16-bit timer output function used 1000
Note load capacitance output line.
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
(iii) mode (SCK0. Internal clock output)
Parameter SCK0 cycle time Symbol tKCY3 Test Conditions MIN. 3200 4800 SCK0 high/low-level width SB0, setup time SCK0) tKH3 tKL3 tSIK3 tKCY3/2-50 tKCY3/2-150 SB0, hold time (from SCK0) SB0, SB1output delay time from SCK0 SB0, from SCK0 tKSB SCK0 from SB0, tSBK SB0, high-level width SB0, low-level width tSBL tKCY3 tSBH tKSO3 Note tKCY3 tKCY3 tKCY3 1000 tKSI3 tKCY3/2 TYP. MAX. Unit
Note load resistors load capacitance SB0, SCK0 output line.
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
(iv) mode (SCK0. External clock input)
Parameter SCK0 cycle time Symbol tKCY4 Test Conditions MIN. 3200 4800 SCK0 high/low-level width tKH4 tKL4 1600 2400 SB0, setup time SCK0) tSIK4 SB0, hold time (from SCK0) SB0, output delay time from SCK0 SB0, from SCK0 tKSB SCK0 from SB0, tSBK SB0, high-level width SB0, low-level width SCK0 rise, fall time When external device expansion function used When external When 16-bit timer tSBL tKCY4 tSBH tKSO4
Note
TYP.
MAX.
Unit
tKSI4
tKCY4/2
tKCY4 tKCY4 tKCY4
1000
device expansion output function function used used When 16-bit timer output function used 1000
Note load resistors load capacitance output line.
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
2-wire serial mode (SCK0. Internal clock output)
Parameter SCK0 cycle time Symbol tKCY5 Test Conditions MIN. 1600 3200 4800 SCK0 high-level width tKH5 tKCY5/2-160 tKCY5/2-190 SCK0 low-level width tKL5 tKCY5/2-50 tKCY5/2-100 SB0, setup time SCK0) tSIK5 SB0, hold time (from SCK0) SB0, output delay time from SCK0 tKSO5 tKSI5 TYP. MAX. Unit
Note
Note load resistors load capacitance SCK0, output line.
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
(vi) 2-wire serial mode (SCK0. External clock input)
Parameter SCK0 cycle time Symbol tKCY6 Test Conditions MIN. 1600 3200 4800 SCK0 high-level width tKH6 1300 2100 SCK0 low-level width tKL6 1600 2400 SB0, setup time SCK0) SB0, hold time (from SCK0) SB0, output delay time from SCK0 tKSO6 SCK0 rise, fall time When external device expansion function used When external When 16-bit timer Note tKSI6 tSIK6 tKCY6/2 TYP. MAX. Unit
device expansion output function function used used When 16-bit timer output function used 1000
Note load resistors load capacitance output line.
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Serial Interface Channel 3-wire serial mode (SCK1. Internal clock output)
Parameter SCK1 cycle time Symbol tKCY7 Test Conditions MIN. 1600 3200 4800 SCK1 high/low-level width setup time SCK1) tKH7 tKL7 tSIK7 tKCY7/2-50 tKCY7/2-100 hold time (from SCK1) output delay time from SCK1 tKSO7 Note tKSI7 TYP. MAX. Unit
Note load capacitance SCK1 output line. (ii) 3-wire serial mode (SCK1. External clock input)
Parameter SCK1 cycle time Symbol tKCY8 Test Conditions MIN. 1600 3200 4800 SCK1 high/low-level width tKH8 tKL8 1600 2400 setup time SCK1) hold time (from SCK1) output delay time from SCK1 SCK1 rise, fall time When external device expansion function used When external When 16-bit timer tKSO8 Note tKSI8 tSIK8 TYP. MAX. Unit
device expansion output function function used used When 16-bit timer output function used 1000
Note load capacitance output line.
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
(iii) 3-wire serial mode with automatic transmit/receive function (SCK1. Internal clock output)
Parameter SCK1 cycle time Symbol tKCY9 Test Conditions MIN. 1600 3200 4800 SCK1 high/low-level width setup time SCK1) tKH9 tKL9 tSIK9 tKCY9/2-50 tKCY9/2-100 hold time (from SCK1) output delay time from SCK1 from SCK1 Strobe signal high-level width tSBD tSBW tKCY9/2-100 tKCY9-30 tKCY9-60 tKCY9-90 Busy signal setup time busy signal detection timing) Busy signal hold time (from busy signal detection timing) tBYH SCK1 from busy inactive tSPS 2tKCY9 tBYS tKCY9/2+100 tKCY9+30 tKCY9+60 tKCY9+90 tKSO9 Note tKSI9 TYP. MAX. Unit
Note load capacitance SCK1 output line.
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
(iv) 3-wire serial mode with automatic transmit/receive function (SCK1. External clock input)
Parameter SCK1 cycle time Symbol tKCY10 Test Conditions MIN. 1600 3200 4800 SCK1 high/low-level width tKH10, tKL10 1600 2400 setup time SCK1) hold time (from SCK1) output delay time from SCK1 SCK1 rise, fall time tR10, tF10 When external device expansion function used When external device expansion function used 1000 tKSO10 Note tKSI10 tSIK10 TYP. MAX. Unit
Note load capacitance output line.
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Timing Test Point (Excluding Input)
Test Points
Clock Timing
1/fX
Input
VIH4 (MIN.) VIL4 (MAX.)
1/fXT tXTL tXTH
Input
VIH5 (MIN.) VIL5 (MAX.)
Timing
tTIL0
tTIH0
1/fTI1 tTIL1 tTIH1
TI1,TI2
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Read/Write Operation External fetch wait):
A8-A15
Higher 8-Bit Address tADD1 Hi-Z Lower 8-Bit
Address
AD0-AD7 tADS tASTH ASTB
Operation Code tRDD1 tRDADH tRDAST
tADH
tASTRD tRDL1 tRDH
External fetch (Wait insertion):
A8-A15
Higher 8-Bit Address tADD1
AD0-AD7 tADS tASTH ASTB
Lower 8-Bit Address
Hi-Z tRDD1
Operation Code tRDADH tRDAST
tADH
tASTRD WAIT tRDWT1 tWTL tWTRD tRDL1 tRDH
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
External data access wait):
A8-A15 tADD2 AD0-AD7 tADS tASTH ASTB
Lower 8-Bit Address
Higher 8-Bit Address
Hi-Z tRDD2
Read Data
Hi-Z
Write Data
Hi-Z
tADH
tRDH
tASTRD tASTWR tWRL1 tRDL2 tRDWD tWRWD tWDS tWDH tWRADH
External data access (Wait insertion):
A8-A15 tADD2 AD0-AD7 tADS tADH tASTH ASTB tASTRD tRDL2 tASTWR WAIT tRDWT2 tWTL tRDD2
Lower 8-Bit Address
Higher 8-Bit Address Hi-Z Hi-Z Hi-Z
Read Data
Write Data
tRDH
tRDWD
tWDS tWRWD tWRL1
tWDH
tWRADH
tWTRD tWRWT
tWTL
tWTWR
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Serial Transfer Timing 3-wire serial mode:
tKLm
tKCYm tKHm
SCK0,SCK1
tSIKm
tKSIm
SI0,SI1
Input Data
tKSOm
SO0,SO1
Output Data
mode (Bus release signal transfer):
tKCY3, tKL3, SCK0 tKSB tSBL tSBH tSBK tSIK3, tKSI3, tKH3,
SB0, tKSO3,
Mode (command signal transfer):
tKCY3, tKL3, SCK0 tSIK3, tKH3,
tKSB
tSBK
tKSI3,
SB0, tKSO3,
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
2-wire serial mode:
tKCY5,6 tKL5,6 SCK0 tKSO5,6 SB0, tSIK5,6 tKSI5,6 tKH5,6
3-wire serial mode with automatic transmit/receive function:
tSIK9,10 tKSO9,10
tKSI9,10 tKH9,10 tF10
SCK1 tKL9,10 tKCY9,10 tR10 tSBD tSBW
3-wire serial mode with automatic transmit/receive function (busy processing):
SCK1
Note
tBYS
Note
tBYH
Note
tSPS
BUSY (Active High)
Note signal actually driven here; shown such indicate timing.
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
converter characteristics AVDD AVSS
Parameter Resolution Overall error Note AVREF AVDD AVREF Conversion time tCONV AVDD AVDD Sampling time Analog input voltage Reference voltage AVREF-AVSS resistance tSAMP VIAN AVREF RAIREF 19.1 38.2 24/fX AVSS AVREF AVDD Symbol Test Conditions MIN. TYP. MAX. Unit
Note Overall error excluding quantization error (±1/2 LSB). indicated ratio full-scale value. Data Memory STOP Mode Supply Voltage Data Retention Characteristics
Parameter Data retention supply voltage Data retention supply current IDDDR VDDDR Subsystem clock stop feedback resister disconnected Release signal time Oscillation stabilization wait time tSREL tWAIT Release RESET Release interrupt Note
Symbol VDDDR
Test Conditions
MIN.
TYP.
MAX.
Unit
Note combination with (OSTS0 OSTS2) oscillation stabilization time select register, selection 213/ 215/fX 218/fX possible.
Data Retention Timing (STOP Mode Release RESET)
Internal Reset Operation HALT Mode STOP Mode Data Retension Mode Operating Mode
STOP Instruction Execution
VDDDR
tSREL
RESET tWAIT
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Data Retention Timing (Standby Release Signal STOP Mode Release Interrupt Signal)
HALT Mode STOP Mode Data Retension Mode Operating Mode
VDDDR STOP Instruction Execition
tSREL
Standby Release Signal (Interrupt Request) tWAIT
Interrupt Input Timing
tINTL INTP0-INTP2 tINTH
tINTL
INTP3
RESET Input Timing
tRSL
RESET
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
PACKAGE DRAWINGS
PLASTIC SHRINK (750 mil)
NOTE Each lead centerline located within 0.17 (0.007 inch) true position (T.P.) maximum material condition. Item center leads when formed parallel.
ITEM MILLIMETERS 58.68 MAX. 1.78 MAX. 1.778 (T.P.) 0.50±0.10 MIN. 3.2±0.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 19.05 (T.P.) 17.0 0.25 +0.10 -0.05 0.17 0~15°
INCHES 2.311 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.035 MIN. 0.126±0.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.750 (T.P.) 0.669 0.010 +0.004 -0.003 0.007 0~15° P64C-70-750A,C-1
Remark
Dimensions materials products same those mass-production products.
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
PLASTIC
detail lead
P64GC-80-AB8-2 ITEM MILLIMETERS 17.6 14.0 14.0 17.6 0.35 0.10 0.15 (T.P.) 0.15+0.10 -0.05 0.10 2.55 2.85 MAX. INCHES 0.693 0.016 0.551 +0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.039 0.039 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.071 0.008 0.031+0.009 -0.008 0.006 +0.004 -0.003 0.004 0.100 0.004 0.004 0.112 MAX.
NOTE Each lead centerline located within 0.15 (0.006 inch) true position (T.P.) maximum material condition.
Remark
Dimensions materials products same those mass-production products.
5°±5°
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
RECOMMENDED SOLDERING CONDITIONS
These products should soldered mounted under conditions recommended table below. detail recommended soldering conditions, refer information document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended below, contact salespersonnel. Table 13-1. Surface Mounting Type Soldering Conditions
64-Pin Plastic 64-Pin Plastic 64-Pin Plastic 64-Pin Plastic
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: Duration: sec. max. above), Number times: Thrice max. Package peak temperature: Duration: sec. max. above), Number times: Thrice max. Solder bath temperature: max. Duration: sec. max. Number times: Once Preliminary heat temperature: max. (Package surface temperature)
Recommended Condition Symbol IR35-00-3
VP15-00-3
Wave soldering
WS60-00-1
Partial heating
temperature: max., Duration: sec. max. (per device side)
Caution more than soldering method should avoided (except case partial heating). Table 13-2. Insertion Type Soldering Conditions
Soldering Method Wave soldering (pin only) Partial heating
64-Pin Plastic Shrink (750 mil) 64-Pin Plastic Shrink (750 mil) 64-Pin Plastic Shrink (750 mil) 64-Pin Plastic Shrink (750 mil)
Soldering Conditions
Solder bath temperature: 260°C max., Duration: sec. max.
temperature: 300°C max., Duration: sec. max. (per pin)
Caution
Wave soldering only lead part order that solder contact with chip directly.
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
APPENDIX DEVELOPMENT TOOLS
following development tools available development systems using µPD78014H subseries. Language processor software
RA78K/0 Notes CC78K0 Notes DF78014 Notes CC78K0-L Notes Assembler package common 78K/0 series compiler package common 78K/0 series Device file common µPD78014 subseries compiler library source file common 78K/0 series
Debugging tools
IE-78000-R IE-78000R-A IE-78000-R-BK IE-78014-R-EM-A EP-78240CW-R EV-9200GC-64 In-circuit emulator common 78K/0 series In-circuit emulator common 78K/0 series (for integrated debugger) Break board common 78K/0 series Emulation board common µPD78018F 78018FY subseries (VDD Emulation probe common µPD78244 subseries Socket mounted printed wiring board target system created 64-pin plastic (GC-AB8 type) SM78K0 Notes ID78K0 Notes SD78K/0 Notes DF78014 Notes System emulator common 78K/0 series Integrated debugger common 78K/0 series Screen debugger IE-78000-R Device file common µPD78014 subseries
Real-Time
RX78K/0 Notes MX78K0 Notes Real-time 78K/0 series 78K/0 series
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Fuzzy Inference Devleopment Support System
FE9000 Note 1/FE9200 Note FT9080 Note 1/FT9085 Note FI78K0 Notes FD78K0 Notes Fuzzy knowledge data creation tool Translator Fuzzy inference module Fuzzy inference debugger
Notes PC-9800 series (MS-DOSTM) based PC/ATand compatible machine DOSTM/IBM DOSTM/MS-DOS) based HP9000 series 300(HP-UXTM) based HP9000 series 700(HP-UX) based, SPARCstation(SunOSTM) based, EWS-4800 series (EWS-UX/V) based PC-9800 series (MS-DOS WindowsTM) based PC/AT compatible machine DOS/IBM DOS/MS-DOS Windows) based NEWS(NEWS-OSTM) based Remarks development tools manufactured third party, refer 78K/0 Series Selection Guide (U11126E). RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0, RX78K/0 used combination with DF78014.
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
APPENDIX RELATED DOCUMENTS
Device Related Documents
Document Name Document Japanese English Planned publish This document IEU-1372
µPD78014H Subseries User's Manual µPD78011H(A), 78012H(A), 78013H(A), 78014H(A) Data Sheet
78K/0 Series User's Manual Instruction 78K/0 Series Instruction List 78K/0 Series Instruction
Planned publish U12174J IEU-849 U10903J U10904J Planned publish
µPD78014H Subseries Special Function Register List
Development Tools Documents (User's Manual)
Document Name RA78K Series Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor RA78K0 Assembler Package Operation Assembly Language Structural Assembly Language CC78K Series Compiler Operation Language CC78K/0 Compiler Operation Language CC78K/0 Compiler Application Note CC78K Series Library Source File IE-78000-R IE-78000-R-A IE-78000-R-BK IE-78014-R-EM-A EP-78240 SM78K0 System Simulator Windows Based SM78K Series System Simulator ID78K0 Integrated Debugger Based ID78K0 Integrated Debugger Based ID78K0 Integrated Debugger Windows Based SD78K/0 Screen Debugger PC-9800 Series (MS-DOS) Based SD78K/0 Screen PC/AT DOS) Based Reference External Components User Open Interface Reference Reference Guide Introduction Reference Introduction Reference Programming Know-how Document Japanese EEU-809 EEU-815 EEU-817 U11802J U11801J U11789J EEU-656 EEU-655 11517J 11518J EEA-618 EEU-777 EEU-810 U10057J EEU-867 EEU-962 EEU-986 U10181J U10092J U11151J U11539J U11649J EEU-852 U10952J EEU-5024 U11279J English EEU-1399 EEU-1404 EEU-1402 U11802E U11081E U11789E EEU-1280 EEU-1284 EEA-1208 U11376E U10057E EEU-1427 U10418E U10332E U10181E U10092E U11539E U11649E EEU-1414 U11279E
Caution contents above related documents subject change without notice. latest documents should used design, etc.
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Embedded Software Documents (User's Manual)
Document Name 78K/0 Series Real-Time Fundamental Installation Technical 78K/0 Series MX78K0 Fuzzy Knowledge Data Creation Tool 78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System Translator 78K/0 Series Fuzzy Inference Development Suport System Fuzzy Inference Module 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Debugger EEU-921 EEU-1458 EEU-858 EEU-1441 Fundamental Document Japanese U11537J U11536J U11538J EEU-5010 EEU-829 EEU-862 English EEU-1438 EEU-1444
Other Documents
Document Name Package Manual Semiconductor Device Mounting Technology Manual Quality Grades Semiconductor Device Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide Quality Assurance Semiconductor Device Guide Products Related Micro-Computer: Other Companies Document Japanese C10943X C10535J C11531J C10983J MEM-539 C11893J U11416J C10535E C11531E C10983E MEI-1202 English
Caution
contents above related documents subject change without notice. latest documents should used design, etc.
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Regional Information
Some information contained this document vary from country country. Before using product your application, please contact office your country obtain list authorized representatives distributors. They will verify: Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 Fax: 01-30-67 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290
Electronics (France) S.A.
Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics Taiwan Ltd. Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
Brasil S.A.
Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689
J96.
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
IEBus trademarks Corporation. MS-DOS Windows trademarks Microsoft Corporation. IBM-DOS, PC/AT, trademarks Corporation. HP9000 Series 300, HP9000 series 700, HP-UX trademarks Hewlett-Packard Company. SPARCstation tradmark SPARC International, Inc. SunOS tradmark Microsystems, Inc. NEWS NEWS-OS trademarks Sony Corporation. Some related decuments preliminary versions. This document, however, indicated preliminary.
export this product from Japan regulated Japanese government. export this product prohibited without governmental license, need which must judged customer. export reexport this product from country other than Japan also prohibited without license from that country. Please call sales representative.
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance. Anti-radioactive design implemented this product.
96.5

µPD78011H(A), 78012H(A), 78013H(A), 78014H(A) 8-BIT SINGLE-CHIP M

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