µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), µPD780031AY(A), 780

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µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), µPD780031AY(A), 780

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INTEGRATED CIRCUIT
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), µPD780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
8-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A) 780034AY(A) products which quality assurance program more stringent than that used µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY 780034AY (standard models) applied (NEC classifies these products "special" quality grade models). µPD780031A(A), 780032A(A), 780033A(A), 780034A(A) members µPD780034A Subseries 78K/0 Series. Only selected functions existing µPD78054 Subseries provided, serial interface enhanced. µPD780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A) µPD780034A Subseries with multimaster supporting interface, which makes them suitable equipment. Flash memory versions, µPD78F0034A 78F0034AY, that operate same power supply voltage range mask version, various development tools, available. Detailed function descriptions provided following user's manuals. sure read them before designing.
µPD780024A, 780034A, 780024AY, 780034AY
Subseries User's Manual: 78K/0 Series User's Manual Instructions: U14046E U12326E
FEATURES
Internal
Item Part Number Program Memory (Internal ROM) 1024 bytes Data Memory (Internal High-Speed RAM) bytes Package
µPD780031A(A), 780031AY(A) µPD780032A(A), 780032AY(A) µPD780033A(A), 780033AY(A) µPD780034A(A), 780034AY(A)
64-pin plastic SDIP 64-pin plastic
(19.05 (750))
64-pin plastic TQFP
External memory expansion space: Minimum instruction execution time: 0.24 8.38 operation) ports: V-tolerant N-ch open-drain: 10-bit resolution converter: channels (AVDD Serial interfaces: channels µPD780031A(A), 780032A(A), 780033A(A), 780034A(A): UART mode, 3-wire serial mode channels) µPD780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A): UART mode, 3-wire serial mode, mode Timer: channels Power supply voltage:
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Document U15132EJ1V0DS00 (1st edition) Date Published November 2000 CP(K) Printed Japan
2000
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
APPLICATIONS
Telephones, household electrical appliances, pagers, equipment, audios, office automation equipment, etc.
ORDERING INFORMATION
Part Number Package 64-pin plastic SDIP (19.05 (750)) 64-pin plastic 64-pin plastic TQFP 64-pin plastic SDIP (19.05 (750)) 64-pin plastic 64-pin plastic TQFP 64-pin plastic SDIP (19.05 (750)) 64-pin plastic 64-pin plastic TQFP 64-pin plastic SDIP (19.05 (750)) 64-pin plastic 64-pin plastic TQFP 64-pin plastic SDIP (19.05 (750)) 64-pin plastic 64-pin plastic TQFP 64-pin plastic SDIP (19.05 (750)) 64-pin plastic 64-pin plastic TQFP 64-pin plastic SDIP (19.05 (750)) 64-pin plastic 64-pin plastic TQFP 64-pin plastic SDIP (19.05 (750)) 64-pin plastic 64-pin plastic TQFP
Remark indicates code suffix.
QUALITY GRADE
Special
Please refer "Quality Grades Semiconductor Devices" (Document C11531E) published Corporation know specification quality grade devices recommended applications.
DIFFERENCES BETWEEN µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A) 780034AY(A), µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY 780034AY
Product name Item Quality grade
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Special
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
Standard
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
78K/0 SERIES LINEUP
products 78K/0 Series listed below. names enclosed boxes subseries names.
Products mass production Products under development subseries products compatible with bus. Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42-/44-pin
PD78075B µPD78078 PD78070A PD780058 PD78058F µPD78054 µPD780065 PD780078 PD780034A PD780024A µPD78014H µPD78018F PD78083
Inverter control
EMI-noise reduced version µPD78078
µPD78078Y PD78070AY PD780018AY PD780058Y PD78058FY
µPD78054 with added timer enhanced external interface
ROM-less version µPD78078 µPD78078Y with enhanced serial limited function
µPD78054 with enhanced serial
EMI-noise reduced version PD78054
µPD78018F with added UART converter enhanced PD78054Y capacity PD780024A increased µPD780034A with added timer enhanced serial PD780078Y PD780034AY µPD780024A with enhanced converter PD780024AY µPD78018F with enhanced serial EMI-noise reduced version µPD78018F PD78018FY
Basic subseries control On-chip UART, capable operating voltage (1.8
64-pin
µPD780988
drive
On-chip inverter controller UART. EMI-noise reduced.
100-pin 78K/0 Series 80-pin 80-pin 80-pin
PD780208 PD780232 µPD78044H µPD78044F
drive
µPD78044F with enhanced C/D. Display output total:
panel control. On-chip C/D. Display output total:
µPD78044F with added N-ch open-drain I/O. Display output total:
Basic subseries drive. Display output total:
120-pin 120-pin 120-pin 100-pin 100-pin 100-pin
PD780338 PD780328 µPD780318 PD780308 µPD78064B µPD78064 µPD780308Y PD78064Y
PD780308 with enhanced display function timer. Segment signal output: pins max. PD780308 with enhanced display function timer. Segment signal output: pins max. PD780308 with enhanced display function timer. Segment signal output: pins max.
PD78064 with enhanced SIO, increased ROM, capacity EMI-noise reduced version PD78064
Basic subseries drive, on-chip UART
interface supported 100-pin 80-pin 80-pin 80-pin Meter control 100-pin 80-pin 80-pin
PD780948 PD78098B PD780701Y PD780833Y
On-chip D-CAN controller µPD78054 with added IEBuscontroller. EMI-noise reduced. On-chip D-CAN/IEBus controller On-chip controller compliant with J1850 (Class
µPD780958 µPD780852 µPD780824
industrial meter control On-chip automobile meter controller/driver automobile meter driver. On-chip D-CAN controller
Remark (Vacuum Fluorescent Display) referred FIP(Fluorescent Indicator Panel) some documents, functions same.
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
major functional differences among subseries shown below. subseries
Function Subseries Name Control Capacity Timer 8-Bit 16-Bit Watch 8-Bit 10-Bit 8-Bit Serial Interface External MIN. Expansion Value
µPD78075B µPD78078 µPD78070A
(UART:
(Time-division UART: (UART: 1ch)
µPD780058 µPD78058F µPD78054
µPD780065 µPD780078
µPD780034A µPD780024A
(UART: (UART: (UART: time-division 3-wire:
µPD78014H µPD78018F µPD78083
Inverter control drive
(UART: (UART:
µPD780988 Note µPD780208 µPD780232 µPD78044H µPD78044F
drive
µPD780338 µPD780328 µPD780318 µPD780308 µPD78064B µPD78064
(UART:
(Time-division UART: (UART:
µPD780948 interface supported µPD78098B Meter control Dash board control
(UART:
µPD780958 µPD780852 µPD780824
(UART:
(UART: (UART:
Note
16-bit timer: channels 10-bit timer: channel
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
subseries
Function Capacity Timer 8-Bit 16-Bit Watch (UART: I2C: (I2C: 8-Bit 10-Bit 8-Bit Serial Interface External MIN. Expansion Value
Subseries Name Control
µPD78078Y µPD78070AY
µPD780018AY µPD780058Y µPD78058FY µPD78054Y µPD780078Y
(Time division UART: I2C: (UART: I2C: (UART: I2C: (UART: I2C:
µPD780034AY µPD780024AY µPD78018FY
drive
(I2C:
µPD780308Y µPD78064Y
(Time division UART: I2C: (UART: I2C:
µPD780701Y interface µPD780833Y
(UART: I2C:
Remark functions subseries subseries products same, except serial interface.
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
OVERVIEW FUNCTIONS
Part Number Item Internal memory Memory space General-purpose registers Minimum instruction execution time High-speed
µPD780031A(A) µPD780031AY(A)
bytes
µPD780032A(A) µPD780032AY(A)
µPD780033A(A) µPD780033AY(A)
1024 bytes
µPD780034A(A) µPD780034AY(A)
bits registers bits registers banks) On-chip minimum instruction execution time cycle variable function
When main system 0.24 µs/0.48 µs/0.95 µs/1.91 µs/3.81 8.38 operation) clock selected When subsystem clock selected 32.768 operation) 16-bit operation Multiply/divide bits bits, bits bits) manipulation (set, reset, test, Boolean operation) adjust, etc.
Instruction
ports
Total: CMOS input: CMOS I/O: V-tolerant N-ch open-drain
converter
10-bit resolution channels Low-voltage operation available: AVDD µPD780031A(A), 780032A(A), 780033A(A), 780034A(A) UART mode: channel 3-wire serial mode: channels µPD780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A) UART mode: channel 3-wire serial mode: channel mode (multimaster supporing): channel 16-bit timer/event counter: 8-bit timer/event counter: Watch timer: Watchdog timer: channel channels channel channel
Serial interfaces
Timers
Timer outputs Clock output
(8-bit output capable: 65.5 kHz, kHz, kHz, kHz, 1.05 MHz, 2.10 MHz, 4.19 MHz, 8.38 8.38 operation with main system clock 32.768 32.768 operation with subsystem clock) 1.02 kHz, 2.05 kHz, 4.10 kHz, 8.19 8.38 operation with main system clock) Maskable Non-maskable Software Internal: external: Internal: +85°C 64-pin plastic SDIP (19.05 (750)) 64-pin plastic 64-pin plastic TQFP
Buzzer output Vectored interrupt sources
Power supply voltage Operating ambient temperature Package
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
CONTENTS
CONFIGURATION (TOP VIEW) BLOCK DIAGRAM FUNCTIONS
Port Pins Non-Port Pins Circuits Recommended Connection Unused Pins
MEMORY SPACE PERIPHERAL HARDWARE FUNCTION FEATURES
Ports Clock Generator Timer/Counter Clock Output/Buzzer Output Controller Converter Serial Interface
INTERRUPT FUNCTIONS EXTERNAL DEVICE EXPANSION FUNCTION STANDBY FUNCTION RESET FUNCTION MASK OPTION.32 INSTRUCTION ELECTRICAL SPECIFICATIONS PACKAGE DRAWINGS RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTS
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
CONFIGURATION (TOP VIEW)
64-pin plastic SDIP (19.05 (750))
P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 P56/A14 P57/A15 VSS0 VDD0 P32/SDA0Note P33/SCL0Note P34/SI31Note P35/SO31Note P36/SCK31Note P20/SI30 P21/SO30 P22/SCK30 P23/RxD0 P24/TxD0 P25/ASCK0 VDD1
P67/ASTB P66/WAIT P65/WR P64/RD P75/BUZ P74/PCL P73/TI51/TO51 P72/TI50/TO50 P71/TI01 P70/TI00/TO0 P03/INTP3/ADTRG P02/INTP2 P01/INTP1 P00/INTP0 VSS1 RESET AVDD AVREF P10/ANI0 P11/ANI1 P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 AVSS
Notes SDA0 SCL0 incorporated only µPD780034AY Subseries. SI31, SO31, SCK31 incorporated only µPD780034A Subseries. Cautions Connect (Internally Connected) directly VSS0 VSS1. Connect AVSS VSS0. Remark When µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A) used applications where noise generated inside microcontroller needs reduced, implementation noise reduction measures, such supplying voltage VDD0 VDD1 individually connecting VSS0 VSS1 different ground lines, recommended.
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
64-pin plastic
64-pin plastic TQFP
P73/TI51/TO51 P72/TI50/TO50
P67/ASTB
P66/WAIT
P75/BUZ
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P42/AD2
P41/AD1
P40/AD0
P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 P56/A14 P57/A15 VSS0 VDD0 P32/SDA0
Note
P74/PCL
P65/WR
P64/RD
P71/TI01 P70/TI00/TO0 P03/INTP3/ADTRG P02/INTP2 P01/INTP1 P00/INTP0 VSS1 RESET AVDD AVREF P10/ANI0
P33/SCL0Note P34/SI31Note P35/SO31
Note
P20/SI30
P21/SO30
P22/SCK30
P23/RxD0
P24/TxD0
P25/ASCK0
AVSS
VDD1
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P12/ANI2
P36/SCK31Note
P11/ANI1
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Notes SDA0 SCL0 incorporated only µPD780034AY Subseries. SI31, SO31, SCK31 incorporated only µPD780034A Subseries. Cautions Connect (Internally Connected) directly VSS0 VSS1. Connect AVSS VSS0. Remark When µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A) used applications where noise generated inside microcontroller needs reduced, implementation noise reduction measures, such supplying voltage VDD0 VDD1 individually connecting VSS0 VSS1 different ground lines, recommended.
A15: AD7: ADTRG: ANI0 ANI7: ASCK0: ASTB: AVDD: AVREF: AVSS: BUZ: INTP0 INTP3: P03: P17: P25: P36: P47: P57: P67:
Address Address/Data Trigger Input Analog Input Asynchronous Serial Clock Address Strobe Analog Power Supply Analog Reference Voltage Analog Ground Buzzer Clock Internally Connected External Interrupt Input Port Port Port Port Port Port Port
P75: PCL: RESET: RxD0: SCK30, SCK31, SCL0: SDA0: SI30, SI31: SO30, SO31: TI00, TI01, TI50, TI51: TO0, TO50, TO51: TxD0: VDD0, VDD1: VSS0, VSS1: WAIT: XT1, XT2:
Port Programmable Clock Read Strobe Reset Receive Data Serial Clock Serial Data Serial Input Serial Output Timer Input Timer Output Transmit Data Power Supply Ground Wait Write Strobe Crystal (Main System Clock) Crystal (Subsystem Clock)
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
BLOCK DIAGRAM
TI00/TO0/P70 TI01/P71 TI50/TO50/P72 TI51/TO51/P73
16-bit timer/ event counter 8-bit timer/ event counter 8-bit timer/ event counter Watchdog timer Watch timer
Port
Port
Port
Port
78K/0 core
Port
SI30/P20 SO30/P21 SCK30/P22 SI31/P34 SO31/P35 SCK31/P36 RxD0/P23 TxD0/P24 ASCK0/P25 SDA0/P32 SCL0/P33 ANI0/P10 ANI7/P17 AVDD AVSS AVREF INTP0/P00 INTP3/P03 BUZ/P75 PCL/P74
Serial interface
Port
Port Serial interface 31Note UART0
Port
AD0/P40 AD7/P47 A8/P50 A15/P57 External access RD/P64 WR/P65 WAIT/P66 ASTB/P67
busNote
converter RESET
Interrupt control Buzzer output Clock output control VDD0 VDD1 VSS0 VSS1
System control
Notes Incorporated only µPD780034A Subseries. Incorporated only µPD780034AY Subseries. Remark internal capacities vary depending product.
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
FUNCTIONS
Port Pins (1/2)
Name Function After Reset Input Alternate Function INTP0 INTP1 INTP2 INTP3/ADTRG Input Port 8-bit input-only port Port 6-bit port Input/output specified 1-bit units. on-chip pull-up resistor specified means software. Port 8-bit port Input/output specified 1-bit units. on-chip pull-up resistor specified means software. interrupt request flag (KRIF) falling edge detection. Port 8-bit port LEDs driven directly. Input/output specified 1-bit units. on-chip pull-up resistor specified means software. Port 4-bit port Input/output specified 1-bit units. on-chip pull-up resistor specified means software. ASTB Input on-chip pull-up resistor specified means software. Port 7-bit port Input/output specified 1-bit units. N-ch open-drain port on-chip pull-up resistor specified mask option. LEDs driven directly. SCL0Note SI31Note SO31Note SCK31Note SDA0Note Input RxD0 TxD0 ASCK0 Input ANI0 ANI7
Port 4-bit port Input/output specified 1-bit units. on-chip pull-up resistor specified means software.
Input
SI30 SO30 SCK30
Input
Input
WAIT
Notes SDA0 SCL0 incorporated only µPD780034AY Subseries. SI31, SO31, SCK31 incorporated only µPD780034A Subseries.
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Port Pins (2/2)
Name Function After Reset Input Alternate Function TI00/TO0 TI01 TI50/TO50 TI51/TO51
Port 6-bit port Input/output specified 1-bit units. on-chip pull-up resistor specified means software.
Non-Port Pins (1/2)
Name Function After Reset Input Alternate Function P03/ADTRG Input Serial interface serial data input Input Output Serial interface serial data output Input Input Serial interface serial data input/output Serial interface serial clock input/output Input Input Output Input Serial data input asynchronous serial interface Serial data output asynchronous serial interface Serial clock input asynchronous serial interface Input Input
INTP0 INTP1 INTP2 INTP3 SI30 SI31Note SO30 SO31Note SDA0Note SCK30 SCK31Note SCL0Note RxD0 TxD0 ASCK0
Input
External interrupt request input which valid edge (rising edge, falling edge, both rising falling edges) specified
Notes SI31, SO31, SCK31 incorporated only µPD780034A Subseries. SDA0 SCL0 incorporated only µPD780034AY Subseries.
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Non-Port Pins (2/2)
Name Function After Reset Input Alternate Function P70/TO0
TI00
Input
External count clock input 16-bit timer/event counter Capture trigger input capture register (CR01) 16-bit timer/event counter
TI01
Capture trigger input capture register (CR00) 16-bit timer/event counter External count clock input 8-bit timer/event counter External count clock input 8-bit timer/event counter Output 16-bit timer/event counter output 8-bit timer/event counter output (also used 8-bit output) 8-bit timer/event counter output (also used 8-bit output) Output Output Output Output Clock output (for trimming main system clock subsystem clock) Buzzer output Lower address/data expanding memory externally Higher address expanding memory externally Strobe signal output reading from external memory Strobe signal output writing external memory Input Output Input Input Input Input Input Input Positive power supply ports Ground potential ports Positive power supply (except ports) Ground potential (except ports) Internally connected. Connect directly VSS0 VSS1. Connecting crystal resonator subsystem clock oscillation Wait insertion external memory access Strobe output that externally latches address information output ports access external memory converter analog input converter trigger signal input converter reference voltage input converter analog power supply. potential that VDD0 VDD1 converter ground potential. potential that VSS0 VSS1 System reset input Connecting crystal resonator main system clock oscillation Input Input Input Input Input Input Input Input Input Input Input
TI50 TI51 TO50 TO51 WAIT ASTB ANI0 ANI7 ADTRG AVREF AVDD AVSS RESET VDD0 VSS0 VDD1 VSS1
P72/TO50 P73/TO51 P70/TI00 P72/TI50 P73/TI51 P03/INTP3
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Circuits Recommended Connection Unused Pins input/output circuit type each recommended connection unused pins shown Table 3-1. input/output circuit configuration each type, Figure 3-1. Table 3-1. Types Circuits
Name P00/INTP0 P01/INTP1 P02/INTP2 P03/INTP3/ADTRG P10/ANI0 P17/ANI7 P20/SI30 P21/SO30 P22/SCK30 P23/RxD0 P24/TxD0 P25/ASCK0 P30, P32, (µPD780034A Subseries only) P32/SDA0 (µPD780034AY Subseries only) P33/SCL0 (µPD780034AY Subseries only) P34/SI31Note P35/SO31Note P36/SCK31Note P40/AD0 P47/AD7 Input: Independently connect VDD0 VSS0 resistor. Output: Leave open. Input: Independently connect VDD0 resistor. Output: Leave open. P50/A8 P57/A15 P64/RD P65/WR P66/WAIT P67/ASTB P70/TI00/TO0 P71/TI01 P72/TI50/TO50 P73/TI51/TO51 P74/PCL P75/BUZ RESET AVDD AVREF AVSS Connect directly VSS0 VSS1. Input Connect VDD0. Leave open. Connect VDD0 VDD1. Connect VSS0 VSS1. Input: Independently connect VDD0 VSS0 resistor. Output: Leave open. 13-R 13-Q 13-S Input: Independently connect VDD0 resistor. Output: Leave open. Input Connect VDD0 VSS0. Input: Independently connect VDD0 VSS0 resistor. Output: Leave open. Input/Output Circuit Type Input Recommended Connection Unused Pins Input: Independently connect VSS0 resistor. Output: Leave open.
Note
SI31, SO31, SCK31 incorporated only µPD780034A Subseries.
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Figure 3-1. Circuits
TYPE TYPE 13-R
IN/OUT Data Output disable N-ch
VSS0
Schmitt-triggered input with hysteresis characteristics
TYPE
VDD0
TYPE 13-S
Mask option
VDD0
Pullup enable Data
IN/OUT
P-ch VDD0 P-ch
Data Output disable
N-ch
VSS0 IN/OUT Output disable Input enable TYPE VDD0 Feedback cut-off P-ch VDD0 P-ch IN/OUT Output disable N-ch VSS0 P-ch TYPE N-ch VSS0
Pullup enable Data
TYPE 13-Q
Mask option
VDD0
TYPE
IN/OUT Data Output disable Comparator N-ch VSS0
P-ch
N-ch VSS0 VREF (threshold voltage) Input enable
Input enable
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
MEMORY SPACE
Figure shows memory µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A). Figure 4-1. Memory
FFFFH Special function registers (SFRs) bits FF00H FEFFH FEE0H FEDFH
General-purpose registers bits
Internal high-speed RAMNote mmmmH mmmmH
Data memory space
nnnnH Reserved 1000H 0FFFH F800H F7FFH CALLF entry area 0800H 07FFH External memory Program area 0080H 007FH CALLT table area 0040H 003FH Vector table area 0000H 0000H Program area
Program memory space nnnnH nnnnH
Internal
Note
Note
internal internal high-speed capacities vary depending product (see following table).
Part Number Last Address Internal nnnnH 1FFFH 3FFFH 5FFFH 7FFFH FB00H Start Address Internal High-Speed mmmmH FD00H
µPD780031A(A), 780031AY(A) µPD780032A(A), 780032AY(A) µPD780033A(A), 780033AY(A) µPD780034A(A), 780034AY(A)
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
PERIPHERAL HARDWARE FUNCTION FEATURES
Ports following types ports available. CMOS input (Port CMOS (Ports P36): N-ch open-drain (P30 P33): Total: Table 5-1. Port Functions
Name Port Name Function port. Input/output specified 1-bit units. on-chip pull-up resistor specified means software. Input-only port. port. Input/output specified 1-bit units. on-chip pull-up resistor specified means software. N-ch open-drain port. Input/output specified 1-bit units. on-chip pull-up resistor specified mask option. LEDs driven directly. port. Input/output specified 1-bit units. on-chip pull-up resistor specified means software. port. Input/output specified 1-bit units. on-chip pull-up resistor specified means software. interrupt request flag (KRIF) falling edge detection. port. Input/output specified 1-bit units. on-chip pull-up resistor specified means software. LEDs driven directly. Port port. Input/output specified 1-bit units. on-chip pull-up resistor specified means software. port. Input/output specified 1-bit units. on-chip pull-up resistor specified means software.
Port Port
Port
Port
Port
Port
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Clock Generator system clock generator incorporated. minimum instruction execution time changed. 0.24 µs/0.48 µs/0.95 µs/1.91 µs/3.81 8.38 operation with main system clock) 32.768 operation with subsystem clock) Figure 5-1. Clock Generator Block Diagram
Subsystem clock oscillator
Watch timer, clock output function Prescaler
Main system clock oscillator
Prescaler
Clock peripheral hardware
STOP
Selector
Standby controller
Wait controller
clock (fCPU)
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Timer/Counter Five timer/counter channels incorporated. 16-bit timer/event counter: channel 8-bit timer/event counter: Watch timer: Watchdog timer: channels channel channel Table 5-2. Operations Timer/Event Counter
16-Bit Timer/ Event Counter Operation mode Interval timer External event counter Function Timer output output output Pulse width measurement Square wave output Interrupt source inputs channel channel channels channels channelNote channelNote 8-Bit Timer/ Event Counters Watch Timer Watchdog Timer
Notes watch timer perform both watch timer interval timer functions same time. watchdog timer watchdog timer interval timer functions. However, watchdog timer selecting either watchdog timer function interval timer function. Figure 5-2. Block Diagram 16-Bit Timer/Event Counter
Internal
Selector
INTTM00
Selector
TI01/P71
Noise eliminator
16-bit capture/compare register (CR00) Match
Selector
fX/22 fX/26
16-bit timer counter (TM0) Match
Clear Output controller TO0/TI00/P70
fX/23
Noise eliminator Noise eliminator
TI00/TO0/P70
16-bit capture/compare register (CR01)
Selector
INTTM01
Internal
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Figure 5-3. Block Diagram 8-Bit Timer/Event Counter
Internal
Mask circuit
8-bit compare register (CR50) TI50/TO50/P72 fX/22 fX/24 fX/26 fX/28 fX/210 Match
Selector
Selector
INTTM50
8-bit timer counter (TM50) Clear
Selector
TO50/TI50/P72
Selector
Level inversion
TCL502 TCL501 TCL500 Timer clock select register (TCL50)
TCE50 TMC506 TMC504 LVS50 LVR50 TMC501 TOE50 8-bit timer mode control register (TMC50) Internal
Figure 5-4. Block Diagram 8-Bit Timer/Event Counter
Internal
Mask circuit
8-bit compare register (CR51) TI51/TO51/P73 fX/2 fX/23 fX/25 fX/27 fX/29 fX/211 Match Selector
Selector
INTTM51
8-bit timer counter (TM51) Clear
Selector
TO51/TI51/P73
Selector
Level inversion
TCL512 TCL511 TCL510 Timer clock select register (TCL51)
TCE51 TMC516 TMC514 LVS51 LVR51 TMC511 TOE51 8-bit timer mode control register (TMC51) Internal
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Figure 5-5. Watch Timer Block Diagram
Clear
Selector
fX/2
9-bit prescaler
Selector
5-bit counter Clear
INTWT
INTWTI
WTM7 WTM6 WTM5 WTM4 WTM1 WTM0 Watch timer operation mode register (WTM) Internal
Figure 5-6. Watchdog Timer Block Diagram
Clock input controller Divided clock selector
fX/28
Divider
Output controller
INTWDT RESET
Division mode selector
mode signal
OSTS2 OSTS1 OSTS0
Oscillation stabilization time select register (OSTS)
WDCS2 WDCS1 WDCS0
WDTM4 WDTM3
Watchdog timer clock select register (WDCS)
Watchdog timer mode register (WDTM)
Internal
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Clock Output/Buzzer Output Controller clock output/buzzer output controller (CKU) incorporated. Clocks with following frequencies output clock output. 65.5 kHz/131 kHz/262 kHz/524 kHz/1.05 MHz/2.10 MHz/4.19 MHz/8.38 8.38 operation with main system clock) 32.768 32.768 operation with subsystem clock) Clocks with following frequencies output buzzer output. 1.02 kHz/2.05 kHz/4.10 kHz/8.19 8.38 operation with main system clock) Figure 5-7. Block Diagram Clock Output/Buzzer Output Controller
Prescaler fX/210 fX/213
Selector
BUZ/P75
BZOE fX/27
Selector
BCS0, BCS1
Clock controller CLOE
PCL/P74
BZOE
BCS1
BCS0
CLOE
CCS3
CCS2
CCS1
CCS0
Clock output select register (CKS) Internal
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Converter converter consisting eight 10-bit resolution channels incorporated. following conversion operation startup methods available. Hardware start Software start Figure 5-8. Converter Block Diagram
Series resistor string ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 Succesive approximation register (SAR) AVSS Selector selector Sample hold circuit Voltage comparator AVDD AVREF
ADTRG/INTP3/P03
Edge detector
Controller
INTAD
Edge detector
conversion result register (ADCR0) INTP3 Internal
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Serial Interface Three serial interface channels incorporated. µPD780034A Subseries Serial interface UART0: Serial interface µPD780034AY Subseries Serial interface UART0: Serial interface Serial interface IIC0: Serial interface UART0 Serial interface UART0 modes: asynchronous serial interface (UART) mode infrared data transfer mode. Asynchronous serial interface (UART) mode This mode enables full-duplex operation wherein byte data starting from start transmitted received. on-chip UART-dedicated baud-rate generator enables communication using wide range selectable baud rates. addition, baud rate also defined dividing clock input ASCK0 pin. UART-dedicated baud-rate generator also used generate MIDI-standard baud rate (31.25 kbps). Infrared data transfer mode This mode enables pulse output pulse reception data format. This mode used office equipment applications such personal computers. Figure 5-9. Block Diagram Serial Interface UART0 channel channel channel channel channels
Internal Asynchronous serial interface mode register (ASIM TXE0 RXE0 PS01 PS00 ISRM0 IRDAM0
Receive RXB0 buffer register
Asynchronous serial interface status register (ASIS TXS0 Transmit shift OVE0 register
RxD0/P23
Receive shift register
TxD0/P24
Receive controller (parity check)
INTSER0 controller INTSR0
(parity addition)
Transmit
INTST0
Baud rate generator
ASCK0/P25 fX/2 fX/27
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Serial interface 3nNote Serial interface mode: 3-wire serial mode. 3-wire serial mode (fixed first) This 8-bit data transfer mode using three lines: serial clock line (SCK3n), serial output line (SO3n), serial input line (SI3n). Since simultaneous transmit receive operations enabled 3-wire serial mode, processing time data transfer reduced. first 8-bit data serial transfer fixed MSB. 3-wire serial mode useful connection peripheral devices, display controllers, etc., that include clocked serial interface. Figure 5-10. Block Diagram Serial Interface
Internal SI3n Serial shift register (SIO3n)
SO3n SCK3n Serial clock counter Serial clock controller Interrupt request signal generator INTCSI3n fX/23 fX/24 fX/25
Selector
Remark µPD780034A Subseries:
µPD780034AY Subseries:
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Serial interface IIC0 (µPD780034AY Subseries only) serial interface IIC0 (Inter mode (multimaster supported). mode (multimaster supported) This 8-bit data transfer mode using lines: serial clock line (SCL0) serial data line (SDA0). This mode complies with format, output "start condition", "data", "stop condition" during transmission serial data bus. This data automatically detected hardware during reception. Since SCL0 SDA0 open-drain outputs IIC0, pull-up resistors serial clock line serial data line required. Figure 5-11. Block Diagram Serial Interface IIC0
Internal status register (IICS0)
MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0
control register (IICC0) SDA0/P32 Noise eliminator Slave address register (SVA0) Matched signal
IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0
CLEAR latch CL00
shift register (IIC0)
N-ch opendrain output
Data hold time corrector
Acknowledge detector
Wake-up controller Acknowledge detector Start condition detector
SCL0/P33 Noise eliminator
Stop condition detector Interrupt request signal generator
Serial clock counter
INTIIC0
Serial clock controller N-ch open-drain output Prescaler
Serial clock wait controller
CLD0 DAD0 SMC0 DFC0 CL00
transfer clock select register (IICCL0)
Internal
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
INTERRUPT FUNCTIONS
total interrupt sources provided, divided into following three types. Non-maskable: Maskable: Software: Table 6-1. Interrupt Source List
Interrupt Type Nonmaskable Maskable Default PriorityNote Interrupt Source Name INTWDT Trigger Watchdog timer overflow (with watchdog timer mode selected) Watchdog timer overflow (with interval timer mode selected) input edge detection External 0006H 0008H 000AH 000CH Serial interface UART0 reception error generation serial interface UART0 reception serial interface UART0 transmission serial interface SIO3 (SIO30) transfer serial interface SIO3 (SIO31) transfer [Only µPD780034A Subseries] serial interface IIC0 transfer [Only µPD780034AY Subseries] Reference time interval signal from watch timer Match between CR00 (when CR00 specified compare register) Detection TI01 valid edge (when CR00 specified capture register) Match between CR01 (when CR01 specified compare register) Detection TI00 valid edge (when CR01 specified capture register) Match between TM50 CR50 Match between TM51 CR51 conversion Watch timer overflow Port falling edge detection instruction execution External Internal 000EH Internal/ External Internal Vector Table Address 0004H Basic Configuration TypeNote
INTWDT
INTP0 INTP1 INTP2 INTP3 INTSER0
INTSR0 INTST0 INTCSI30 INTCSI31
0010H 0012H 0014H 0016H
INTIIC0
0018H
INTWTI INTTM00
001AH 001CH
INTTM01
001EH
Software
INTTM50 INTTM51 INTAD0 INTWT INTKR
0020H 0022H 0024H 0026H 0028H 003EH
Notes default priority priority order when several maskable interrupt requests generated same time. highest, lowest. Basic configuration types correspond Figure 6-1. Remark watchdog timer interrupt sources (INTWDT): non-maskable interrupt mask interrupt (internal), available, either which selected.
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Figure 6-1. Basic Configuration Interrupt Function (1/2) Internal non-maskable interrupt
Internal
Interrupt request
Priority controller
Vector table address generator Standby release signal
Internal maskable interrupt
Internal
Interrupt request
Priority controller
Vector table address generator Standby release signal
External maskable interrupt (INTP0 INTP3)
Internal
External interrupt edge enable register (EGP, EGN)
Interrupt request
Edge detector
Priority controller
Vector table address generator Standby release signal
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Figure 6-1. Basic Configuration Interrupt Function (2/2) External maskable interrupt (INTKR)
Internal
Interrupt request when
Falling edge detector
Priority controller
Vector table address generator Standby release signal
Software interrupt
Internal
Interrupt request
Priority controller
Vector table address generator
ISP:
Interrupt request flag Interrupt enable flag In-service priority flag Interrupt mask flag Priority specification flag
MEM: Memory expansion mode register
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
EXTERNAL DEVICE EXPANSION FUNCTION
external device expansion function connecting external devices areas other than internal ROM, RAM, SFR. Ports used external device connection.
STANDBY FUNCTION
following standby modes available further reduction system current consumption. HALT mode: this mode, operation clock stopped. average current consumption reduced intermittent operation combining this mode with normal operation mode. STOP mode: this mode, oscillation main system clock stopped. operations performed main system clock suspended, only subsystem clock used, resulting extremely small power consumption. This used only when main system clock operating (the subsystem clock oscillation cannot stopped).
Figure 8-1. Standby Function
Main system clock operation Interrupt request STOP instruction Interrupt request
HALT instruction
Subsystem clock operationNote HALT instruction
Interrupt request
STOP mode (Main system clock oscillation stopped)
HALT mode (Clock supply halted, oscillation maintained)
HALT modeNote (Clock supply halted, oscillation maintained)
Note
current consumption reduced stopping main system clock. When operating subsystem clock, (MCC) processor clock control register (PCC) stop main system clock. STOP instruction cannot used.
Caution When main system clock stopped device operating subsystem clock, wait until oscillation stabilization time been secured program before switching back main system clock.
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
RESET FUNCTION
following reset methods available. External reset RESET signal input Internal reset watchdog timer runaway time detection
MASK OPTION
Table 10.1 Mask Option Selection
Subseries Name Pins P30, Mask Option on-chip pull-up resistor specified 1-bit units.
µPD780034A Subseries µPD780034AY Subseries
mask option used specify connection on-chip pull-up resistor P33Note, 1-bit units. Note µPD780034AY Subseries only.
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
INSTRUCTION
8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Operand Operand #byte
byte]
Note
saddr
!addr16
[DE]
[HL]
$addr16
None
ADDC SUBC
ADDC SUBC
ADDC SUBC
ADDC SUBC
ADDC SUBC
ADDC SUBC
RORC ROLC
ADDC SUBC
saddr ADDC SUBC !addr16
DBNZ
DBNZ
PUSH
[DE] [HL]
ROR4 ROL4
byte]
MULU DIVUW
Note
Except
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Operand Operand #word ADDW SUBW CMPW MOVW MOVW MOVW MOVW MOVWNote MOVW MOVW MOVW MOVW rpNote MOVW XCHW sfrp MOVW saddrp MOVW !addr16 MOVW MOVW None
sfrp saddrp !addr16
INCW, DECW PUSH,
Note
Only when
manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BTCLR
Operand Operand A.bit A.bit sfr.bit saddr.bit PSW.bit [HL].bit MOV1 $addr16 BTCLR BTCLR BTCLR BTCLR BTCLR None SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1
sfr.bit
MOV1
saddr.bit
MOV1
PSW.bit
MOV1
[HL].bit
MOV1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
SET1 CLR1 NOT1
Call instructions/branch instructions CALL, CALLF, CALLT, BNC, BNZ, BTCLR, DBNZ
Operand Operand Basic instruction Compound instruction !addr16 CALL !addr11 CALLF [addr5] CALLT $addr16 BTCLR DBNZ
Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, HALT, STOP
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings 25°C)
Parameter Supply voltage Symbol AVDD AVREF AVSS Input voltage P03, P17, P25, P36, P47, P57, P67, P75, XT1, XT2, RESET N-ch open-drain Without pull-up resistor With pull-up resistor Output voltage Analog input voltage Output current, high Total P03, P47, P57, P67, Total P25, Output current, P03, P25, P36, P47, P67, P33, Total P03, P47, P67, Total Total Total Operating ambient temperature Storage temperature Tstg Analog input Conditions Ratings -0.3 +6.5 -0.3 -0.3 0.3Note 0.3Note Unit
-0.3 +0.3 -0.3 0.3Note
-0.3 +6.5 -0.3 0.3Note
-0.3 0.3Note AVSS AVREF -0.3 0.3Note +150 0.3Note
Note
below Product quality suffer absolute maximum rating exceeded even momentarily parameter. That absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions that ensure that absolute maximum ratings exceeded.
Caution
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Capacitance 25°C,
Parameter Input capacitance capacitance Symbol Conditions Unmeasured pins returned Unmeasured pins returned P03, P25, P36, P47, P57, P67, MIN. TYP. MAX. Unit
Remark
Unless otherwise specified, characteristics alternate-function pins same those port pins.
Main System Clock Oscillator Characteristics +85°C,
Resonator Ceramic resonator Recommended Circuit
Parameter Oscillation frequency (fX)Note Oscillation stabilization timeNote Oscillation frequency (fX)Note Oscillation stabilization timeNote input frequency (fX)Note input high-/low-level width (tXH, tXL)
Conditions
MIN.
TYP.
MAX. 8.38
Unit
After reaches oscillation voltage range MIN.
Crystal resonator
8.38
External clock
8.38
PD74HCU04
Notes Indicates only oscillator characteristics. Refer Characteristics instruction execution time. Time required stabilize oscillation after reset STOP mode release. Cautions When using main system clock oscillator, wire follows area enclosed broken lines above figures avoid adverse effect from wiring capacitance. Keep wiring length short possible. cross wiring with other signal lines. route wiring near signal line through which high fluctuating current flows. Always make ground point oscillator capacitor same potential VSS1. ground capacitor ground pattern through which high current flows. fetch signals from oscillator. When main system clock stopped system operating subsystem clock, wait until oscillation stabilization time been secured program before switching back main system clock.
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Subsystem Clock Oscillator Characteristics +85°C,
Resonator Crystal resonator Recommended Circuit
Parameter Oscillation frequency (fXT)Note Oscillation stabilization timeNote input frequency (fXT)Note input high-/low-level width (tXTH tXTL)
Conditions
MIN.
TYP. 32.768
MAX.
Unit
External clock
38.5
µPD74HCU04
Notes Indicates only oscillator characteristics. Refer Characteristics instruction execution time. Time required stabilize oscillation after reaches oscillation voltage range MIN. Cautions When using subsystem clock oscillator, wire follows area enclosed broken lines above figures avoid adverse effect from wiring capacitance. Keep wiring length short possible. cross wiring with other signal lines. route wiring near signal line through which high fluctuating current flows. Always make ground point oscillator capacitor same potential VSS1. ground capacitor ground pattern through which high current flows. fetch signals from oscillator. subsystem clock oscillator designed low-amplitude circuit reducing current consumption, more prone malfunction noise than main system clock oscillator. Particular care therefore required with wiring method when subsystem clock used.
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Recommended Oscillator Constant Main system clock: Ceramic resonator +85°C)
Manufacturer Part Number Frequency (MHz) Murata Mfg. Co., Ltd. CSB1000J CSA2.00MG040 CST2.00MG040 CSA3.58MG CST3.58MGW CSA4.19MG CST4.19MGW CSA5.00MG CST5.00MGW CSA8.00MTZ CST8.00MTW CSA8.00MTZ093 CST8.00MTW093 CSA8.38MTZ CST8.38MTW CSA8.38MTZ093 CST8.38MTW093 CCR3.58MC3 CCR4.19MC3 CCR5.0MC3 CCR8.0MC5 CCR8.38MC5 1.00 2.00 2.00 3.58 3.58 4.19 4.19 5.00 5.00 8.00 8.00 8.00 8.00 8.38 8.38 8.38 8.38 3.58 4.19 5.00 8.00 8.38 Recommended Circuit Constant (pF) On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip (pF) Oscillation Voltage Range MIN. MAX.
Caution oscillator constant oscillation voltage range indicate conditions stable oscillation. Oscillation frequency precision guaranteed. applications requiring oscillation frequency precision, oscillation frequency must adjusted implementation circuit. details, contact directly manufacturer resonator used.
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Characteristics +85°C,
Parameter Output current, high Output current, Symbol pins P03, P25, P36, P47, P67, P33, Total P03, P47, P67, Total Total Total Input voltage, high VIH1 P17, P21, P24, P35, P47, P57, P67, P74, P03, P20, P22, P23, P25, P34, P36, P73, RESET (N-ch open-drain) 0.7VDD 0.8VDD 0.8VDD 0.85VDD 0.7VDD 0.8VDD VIH5 XT1, 0.8VDD 0.9VDD Input voltage, VIL1 P17, P21, P24, P35, P47, P57, P67, P74, P03, P20, P22, P23, P25, P34, P36, P73, RESET VIL4 VIL5 XT1, Output voltage, high Output voltage, VOH1 -100 VOL1 Conditions MIN. TYP. MAX. 0.3VDD 0.2VDD 0.2VDD 0.15VDD 0.3VDD 0.2VDD 0.1VDD 0.2VDD 0.1VDD Unit
VIH2 VIH3
VIH4
VIL2
VIL3
P03, P25, P36, P47, P67, VOL2
Remark
Unless otherwise specified, characteristics alternate-function pins same those port pins.
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Characteristics +85°C,
Parameter Input leakage current, high Symbol ILIH1 Conditions P03, P17, P25, P36, P47, P57, P67, P75, RESET XT1, P33Note P03, P17, P25, P36, P47, P57, P67, P75, RESET XT1, VOUT VOUT P30, P31, P32Note P33Note P03, P25, P36, P47, P57, P67,
Note
MIN.
TYP.
MAX.
Unit
ILIH2 ILIH3 Input leakage current, ILIL1
ILIL2 ILIL3 Output leakage current, high Output leakage current, Mask option pull-up resistance Software pullup resistance ILOH ILOL
Notes µPD780031A(A), 780032A(A),: 780033A(A), 780034A(A) 780033AY(A), 780034AY(A)
When pull-up resistors connected (specified mask option). (specified mask option).
µPD780031AY(A), 780032AY(A),: When pull-up resistors connected
Only µPD780031A(A), 780032A(A), 780033A(A), 780034A(A) Remark Unless otherwise specified, characteristics alternate-function pins same those port pins.
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Characteristics +85°C,
Parameter Power supply currentNote Symbol IDD1 Conditions 8.38 ±10%Note crystal oscillation operating mode 5.00 ±10%Note crystal oscillation operating mode ±10%Note When converter stopped When converter operating When converter stopped When converter operating When converter stopped When converter operating IDD2 8.38 ±10%Note crystal oscillation HALT mode ±10%Note 5.00 crystal oscillation HALT mode ±10%Note When peripheral functions stopped When peripheral functions operating When peripheral functions stopped When peripheral functions operating When peripheral functions stopped When peripheral functions operating
IDD3
MIN.
TYP.
MAX.
Unit
0.35
0.15
32.768 crystal oscillation operating modeNote
±10% ±10% ±10% ±10% ±10% ±10% ±10% ±10% ±10%
0.05 0.05
IDD4
32.768 crystal oscillation HALT modeNote
IDD5
STOP mode When feedback resistor used
Notes Total current through internal power supply (VDD0, VDD1), including peripheral operation current (except current through pull-up resistors ports AVREF pin). When processor clock control register (PCC) 00H. When 02H. When main system clock operation stopped.
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Characteristics Basic Operation +85°C,
Parameter Cycle time (Min. instruction execution time) Symbol Operating with main system clock Conditions MIN. 0.24 Operating with subsystem clock TI00, TI01 input high-/low-level width TI50, TI51 input frequency TI50, TI51 input high-/low-level width Interrupt request input high-/low -level width RESET low-level width tRSL tINTH, tINTL INTP0 INTP3, tTIH0, tTIL0 103.9Note 2/fsam 0.1Note 2/fsam 0.2Note 2/fsam 0.5Note fTI5 tTIH5, tTIL5 TYP. MAX. Unit
Notes Value when external clock used. When crystal resonator used, (MIN.). Selection fsam fX/4, fX/64 possible using bits (PRM00, PRM01) prescaler mode register (PRM0). However, TI00 valid edge selected count clock, value becomes fsam fX/8.
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
(Main system clock operation)
16.0 10.0
Cycle time
Operation guaranteed range
0.24
Supply voltage
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Read/Write Operation +85°C,
Parameter ASTB high-level width Address setup time Address hold time Input time from address data Symbol tASTH tADS tADH tADD1 tADD2 Output time from address Input time from data tRDAD tRDD1 tRDD2 Read data hold time low-level width tRDH tRDL1 tRDL2 Input time from WAIT tRDWT1 tRDWT2 Input time from WAIT WAIT low-level width Write data setup time Write data hold time low-level width Delay time from ASTB Delay time from ASTB Delay time from ASTB external fetch Hold time from address external fetch Write data output time from Write data output time from Hold time from address Delay time from WAIT Delay time from WAIT tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR tRDAST (0.5 n)tCY (1.5 2n)tCY 2tCY 0.8tCY 1.2tCY (1.5 2n)tCY (2.5 2n)tCY 2n)tCY Conditions MIN. 0.3tCY 2n)tCY 2n)tCY 2n)tCY 2n)tCY MAX.
(1/3)
Unit
tRDADH
0.8tCY
1.2tCY
tRDWD tWRWD tWRADH tWTRD tWTWR
0.8tCY 0.8tCY 0.8tCY 1.2tCY 2.5tCY 2.5tCY
Remarks
TCY/4 indicates number waits. indicates load capacitance AD7, A15, WAIT, ASTB pins.)
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Read/Write Operation +85°C, (2/3)
Parameter ASTB high-level width Address setup time Address hold time Input time from address data Symbol tASTH tADS tADH tADD1 tADD2 Output time from address Input time from data tRDAD tRDD1 tRDD2 Read data hold time low-level width tRDH tRDL1 tRDL2 Input time from WAIT tRDWT1 tRDWT2 Input time from WAIT WAIT low-level width Write data setup time Write data hold time low-level width Delay time from ASTB Delay time from ASTB Delay time from ASTB external fetch Hold time from address external fetch Write data output time from Write data output time from Hold time from address Delay time from WAIT Delay time from WAIT tRDADH 0.8tCY 1.2tCY tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR tRDAST (0.5 2n)tCY (1.5 2n)tCY 2tCY 0.8tCY 1.2t (1.5 2n)tCY (2.5 2n)tCY 2n)tCY Conditions MIN. 0.3tCY 2n)tCY 2n)tCY 2n)tCY 2n)tCY MAX. Unit
tRDWD tWRWD tWRADH tWTRD tWTWR
0.8tCY 0.5tCY 0.5tCY 1.2tCY 2.5tCY 2.5tCY
Remarks
TCY/4 indicates number waits. indicates load capacitance AD7, AD15, WAIT, ASTB pins.)
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Read/Write Operation +85°C, (3/3)
Parameter ASTB high-level width Address setup time Address hold time Input time from address data Symbol tASTH tADS tADH tADD1 tADD2 Output time from address Input time from data tRDAD tRDD1 tRDD2 Read data hold time low-level width tRDH tRDL1 tRDL2 Input time from WAIT tRDWT1 tRDWT2 Input time from WAIT WAIT low-level width Write data setup time Write data hold time low-level width Delay time from ASTB Delay time from ASTB Delay time from ASTB external fetch Hold time from address external fetch Write data output time from Write data output time from Hold time from address Delay time from WAIT Delay time from WAIT tRDADH 0.8tCY 1.2tCY tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR tRDAST (0.5 2n)tCY (1.5 2n)tCY 2tCY 0.8tCY 1.2tCY (1.5 2n)tCY (2.5 2n)tCY 2n)tCY Conditions MIN. 0.3tCY 2n)tCY 2n)tCY 2n)tCY 2n)tCY MAX. Unit
tRDWD tWRWD tWRADH tWTRD tWTWR
0.8tCY 0.5tCY 0.5tCY 1.2tCY 2.5tCY 2.5tCY
Remarks
TCY/4 indicates number waits. 100pF indicates load capacitance AD7, AD15, WAIT, ASTB pins.)
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Serial Interface +85°C,
3-wire serial mode (SCK3n. Internal clock output)
Parameter SCK3n cycle time Symbol tKCY1 Conditions MIN. 1600 3200 SCK3n high-/ low-level width SI3n setup time SCK3n) tSIK1 5.5V 4.0V tKH1, tKL1 tKCY1/2 tKCY1/2 SI3n hold time (from SCK3n) Delay time from SCK3n SO3n output tKSI1 pFNote TYP. MAX. Unit
tKSO1
Note load capacitance SCK3n, SO3n output lines. 3-wire serial mode (SCK3n. External clock input)
Parameter SCK3n cycle time Symbol tKCY2 Conditions MIN. 1600 3200 SCK3n high-/ low-level width tKH2, tKL2 1600 SI3n setup time SCK3n) SI3n hold time (from SCK3n) Delay time from SCK3n SO3n output tSIK2 TYP. MAX. Unit
tKSI2 pFNote
tKSO2
Note load capacitance SO3n output line. Remark
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A):
µPD780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A):
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
UART mode (dedicated baud-rate generator output)
Parameter Transfer rate Symbol Conditions MIN. TYP. MAX. 131031 78125 39063 Unit
UART mode (external clock input)
Parameter ASCK0 cycle time Symbol tKCY3 Conditions MIN. 1600 3200 ASCK0 high-/low-level width tKH3, tKL3 1600 Transfer rate 39063 19531 9766 TYP. MAX. Unit
UART mode (infrared data transfer mode)
Parameter Transfer rate rate allowable error Output pulse width Input pulse width Symbol Conditions 4/fX MIN. MAX. 131031 ±0.87 0.24/fbrNote Unit
Note
fbr: Specified baud rate
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
mode (µPD780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A) only)
Standard Mode Parameter SCL0 clock frequency Bus-free time (between stop start conditions) Hold timeNote SCL0 clock low-level width SCL0 clock high-level width Start/restart condition setup time Data hold time CBUS-compatible master Data setup time SDA0 SCL0 signal rise time SDA0 SCL0 signal fall time Stop condition setup time Spike pulse width controlled input filter Capacitive load line tSU:DAT tSU:STO Symbol fCLK tBUF MIN. MAX. High-Speed Mode MIN. MAX. Unit
tHD:STA tLOW tHIGH tSU:STA tHD:DAT
0Note
1000
0Note 100Note 0.1CbNote 0.1CbNote
0.9Note
Notes start condition, first clock pulse generated after this hold time. fill undefined area SCL0 falling edge, necessary device internally provide least hold time SDA0 signal (which VIHmin. SCL0 signal). device does extend SCL0 signal hold time (tLOW), only maximum data hold time tHD:DAT needs fulfilled. high-speed mode available standard mode system. this time, conditions described below must satisfied. device does extend SCL0 signal state hold time tSU:DAT device extends SCL0 signal state hold time sure transmit next data SDA0 line before SCL0 line released (tRmax. tSU:DAT 1000 1250 standard mode specification). Total capacitance line (unit:
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Timing Measurement Points (Excluding inputs)
0.8VDD 0.2VDD
Point measurement
0.8VDD 0.2VDD
Clock Timing
1/fX
VIH4 (MIN.) VIL4 (MAX.)
Input
1/fXT
tXTL Input
tXTH VIH5 (MIN.) VIL5 (MAX.)
Timing
tTIL0 tTIH0
TI00, TI01
1/fTI5 tTIL5 tTIH5
TI50, TI51
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Interrupt Request Input Timing
tINTL
tINTH
INTP0 INTP3
RESET Input Timing
tRSL
RESET
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Read/Write Operation External fetch wait):
Higher 8-bit address tADD1
Lower 8-bit address tADS tASTH tADH
Hi-Z tRDAD tRDD1
Instruction code tRDADH tRDAST
ASTB
tASTRD tRDL1 tRDH
External fetch (wait insertion):
Higher 8-bit address tADD1
Lower 8-bit address tADS tASTH tADH tRDAD
Hi-Z tRDD1
Instruction code tRDADH tRDAST
ASTB
tASTRD WAIT tRDWT1 tWTL tWTRD tRDL1 tRDH
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
External data access wait):
tADD2 Lower 8-bit address tADS tASTH ASTB tADH Hi-Z tRDAD tRDD2
Higher 8-bit address
Read data
Write data
Hi-Z
tRDH
tASTRD tASTWR tWRL1 tRDL2 tRDWD tWRWD tWDS tWDH tWRADH
External data access (wait insertion):
tADD2
Lower 8-bit address
Higher 8-bit address Hi-Z tRDAD tRDH tRDD2 tASTRD Hi-Z
Read data
Write data
tADS tADH tASTH ASTB
tRDL2 tASTWR WAIT tRDWT2 tWTL tWTRD
tRDWD tWRWD
tWDS
tWDH
tWRL1
tWRADH
tWTL tWRWT tWTWR
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Serial Transfer Timing 3-wire serial mode:
tKCYm tKLm tKHm
SCK3n tSIKm tKSIm
SI3n tKSOm
Input data
SO3n
Output data
Remarks µPD780031A(A), 780032A(A), 780033A(A), 780034A(A):
µPD780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A):
UART mode (external clock input):
KCY3
ASCK0
mode (µPD780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A) only):
tLOW SCL0 tHD:DAT tHD:STA
tHIGH tSU:DAT
tSU:STA
tHD:STA
tSU:STO
SDA0 tBUF Stop condition Start condition Restart condition Stop condition
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Converter Characteristics +85°C, AVDD AVREF AVSS
Parameter Resolution Overall errorNotes AVREF AVREF AVREF Conversion time tCONV AVREF AVREF AVREF Zero-scale errorNotes AVREF AVREF AVREF Full-scale errorNotes AVREF AVREF AVREF Integral linearity errorNote AVREF AVREF AVREF Differential linearity error AVREF AVREF AVREF Analog input voltage Reference voltage Resistance between AVREF AVSS VIAN AVREF RREF When conversion performed. Symbol Conditions MIN. TYP. ±0.2 ±0.3 ±0.6 MAX. ±0.4 ±0.6 ±1.2 ±0.4 ±0.6 ±1.2 ±0.4 ±0.6 ±1.2 ±2.5 ±4.5 ±8.5 ±1.5 ±2.0 ±3.5 AVREF AVDD Unit %FSR %FSR %FSR
%FSR %FSR %FSR %FSR %FSR %FSR
Notes Excludes quantization error (±1/2 LSB). This value indicated ratio full-scale value. Data Memory STOP Mode Supply Voltage Data Retention Characteristics +85°C)
Parameter Data retention power supply voltage Data retention power supply current Release signal time Oscillation stabilization wait time Symbol VDDDR Conditions MIN. TYP. MAX. Unit
IDDDR
Subsystem clock stop (XT1 VDD) feed-back resistor disconnected Release RESET Release interrupt request
tSREL tWAIT
217/fX Note
Note
Selection 212/fX 214/fX 217/fX possible using bits (OSTS0 OSTS2) oscillation stabilization time select register (OSTS).
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Data Retention Timing (STOP Mode Release RESET)
Internal reset operation HALT mode STOP mode Operating mode
Data retention mode
STOP instruction execution RESET
VDDDR tSREL
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release Interrupt Request Signal)
HALT mode STOP mode Operating mode
Data retention mode
STOP instruction execution Standby release signal (interrupt request)
VDDDR tSREL
tWAIT
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
PACKAGE DRAWINGS
64-PIN PLASTIC SDIP (19.05mm(750))
NOTES Each lead centerline located within 0.17 true position (T.P.) maximum material condition. Item center leads when formed parallel.
ITEM
MILLIMETERS 58.0 +0.68 -0.20 1.78 MAX. 1.778 (T.P.) 0.50±0.10 MIN. 3.2±0.3 0.51 MIN. 4.05 +0.26 -0.20 5.08 MAX. 19.05 (T.P.) 17.0±0.2 0.25 +0.10 -0.05 0.17 P64C-70-750A,C-4
Remark external dimensions materials version same those mass-produced version.
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
64-PIN PLASTIC (14x14)
detail lead
NOTE Each lead centerline located within 0.15 true position (T.P.) maximum material condition.
ITEM
MILLIMETERS 17.6±0.4 14.0±0.2 14.0±0.2 17.6±0.4 0.37 +0.08 -0.07 0.15 (T.P.) 1.8±0.2 0.8±0.2 0.17 +0.08 -0.07 0.10 2.55±0.1 0.1±0.1 5°±5° 2.85 MAX. P64GC-80-AB8-5
Remark external dimensions materials version same those mass-produced version.
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
64-PIN PLASTIC TQFP (12x12)
detail lead
ITEM MILLIMETERS 14.0±0.2 12.0±0.2 12.0±0.2 14.0±0.2 1.125 1.125 0.32 +0.06 -0.10 0.13 0.65 (T.P.) 1.0±0.2 0.17 +0.03 -0.07 0.10 0.1±0.05 1.1±0.1 0.25 0.6±0.15 P64GK-65-9ET-3
NOTE Each lead centerline located within 0.13 true position (T.P.) maximum material condition.
Remark external dimensions materials version same those mass-produced version.
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
RECOMMENDED SOLDERING CONDITIONS
This product should soldered mounted under following recommended conditions. details recommended soldering conditions, refer document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended below, contact your sales representative. Table 14-1. Surface Mounting Type Soldering Conditions (1/2) 64-pin plastic 64-pin plastic 64-pin plastic 64-pin plastic
64-pin plastic 64-pin plastic 64-pin plastic 64-pin plastic
Recommended Condition Symbol IR35-00-3 VP15-00-3 WS60-00-1
Soldering Method Infrared reflow Wave soldering
Soldering Conditions Package peak temperature: 235°C, Time: seconds max. 210°C higher), Count: Three times less Package peak temperature: 215°C, Time: seconds max. 200°C higher), Count: Three times less Solder bath temperature: 260°C max., Time: seconds max., Count: Once, Preheating temperature: 120°C max. (package surface temperature) temperature: 300°C max., Time: seconds max. (per row)
Partial heating
Caution different soldering methods together (except partial heating).
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Table 14-1. Surface Mounting Type Soldering Conditions (2/2) 64-pin plastic TQFP 64-pin plastic TQFP 64-pin plastic TQFP 64-pin plastic TQFP
64-pin plastic TQFP 64-pin plastic TQFP 64-pin plastic TQFP 64-pin plastic TQFP
Recommended Condition Symbol IR35-107-2
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 235°C, Time: seconds max. 210°C higher), Count: times less, Exposure limit: daysNote (after that, prebake 125°C hours) Package peak temperature: 215°C, Time: seconds max. 200°C higher), Count: times less, Exposure limit: daysNote (after that, prebake 125°C hours) temperature: 300°C max., Time: seconds max. (per row)
VP15-107-2
Partial heating
Note After opening pack, store 25°C less 65%RH less allowable storage period. Caution different soldering methods together (except partial heating).
Table 14-2. Insertion Type Soldering Conditions
64-pin plastic SDIP (19.05 (750)) 64-pin plastic SDIP (19.05 (750)) 64-pin plastic SDIP (19.05 (750)) 64-pin plastic SDIP (19.05 (750))
64-pin plastic SDIP (19.05 (750)) 64-pin plastic SDIP (19.05 (750)) 64-pin plastic SDIP (19.05 (750)) 64-pin plastic SDIP (19.05 (750))
Soldering Method Wave soldering (only pins) Partial heating Soldering Condition Solder bath temperature: 260°C max., Time: seconds max. temperature: 300°C max., Time: seconds max. (per row)
Caution Apply wave soldering only pins careful bring solder into direct contact with package.
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
APPENDIX DEVELOPMENT TOOLS
following development tools available system development using µPD780034A, 780034AY Subseries. Also refer Cautions Using Development Tools. Language Processing Software
RA78K0 CC78K0 DF780034 CC78K0-L Assembler package common 78K/0 Series compiler package common 78K/0 Series Device file µPD780034A, 780034AY Subseries compiler library source file common 78K/0 Series
Flash Memory Writing Tools
Flashpro (FL-PR2) Flashpro (FL-PR3, PG-FP3) FA-64CW FA-64GC FA-64GK-9ET Flash programmer dedicated microcontrollers with on-chip flash memory
Adapter flash memory writing
Debugging Tools When using in-circuit emulator IE-78K0-NS
IE-78K0-NS IE-70000-MC-PS-B IE-78K0-NS-PA IE-70000-98-IF-C IE-70000-CD-IF-A IE-70000-PC-IF-C IE-70000-PCI-IF-A IE-780034-NS-EM1 NP-64CW NP-64GC NP-64GC-TQ NP-64GK EV-9200GC-64 TGC-064SAP TGK-064SBP ID78K0-NS SM78K0 DF780034 In-circuit emulator common 78K/0 Series Power supply unit IE-78K0-NS Performance board enhance expand functions IE-78K0-NS Adapter required when using PC-9800 series host machine (excluding notebook PCs) supported) card interface cable when using notebook host machine (PCMCIA socket supported) Adapter required when using PC/ATor compatible host machine (ISA supported) Adapter required when using which incorporated host machine Emulation board emulate µPD780034A, 780034AY Subseries Emulation probe 64-pin plastic SDIP type) Emulation probe 64-pin plastic (GC-AB8 type) Emulation probe 64-pin plastic TQFP (GK-9ET type) Conversion socket connect NP-64GC target system board which 64-pin plastic (GC-AB8 type) mounted Conversion adapter connect NP-64GC-TQ target system board which 64-pin plastic (GC-AB8 type) mounted Conversion adapter connect NP-64GK target system board which 64-pin plastic TQFP (GK-9ET type) mounted Integrated debugger IE-78K0-NS System simulator common 78K/0 Series Device file µPD780034A, 780034AY Subseries
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
When using in-circuit emulator IE-78001-R-A
IE-78001-R-A IE-70000-98-IF-C IE-70000-PC-IF-C IE-70000-PCI-IF-A IE-78000-R-SV3 IE-780034-NS-EM1 IE-78K0-R-EX1 EP-78240CW-R EP-78240GC-R EP-78012GK-R EV-9200GC-64 TGK-064SBP ID78K0 SM78K0 DF780034 In-circuit emulator common 78K/0 Series Adapter required when using PC-9800 series host machine (excluding notebook PCs) supported) Adapter required when using PC/AT compatible host machine (ISA supported) Adapter required when using which incorporated host machine Interface adapter cable when using host machine Emulation board emulate µPD780034A, 780034AY Subseries Emulation probe conversion board necessary when using IE-780034-NS-EM1 IE-78001-R-A Emulation probe 64-pin plastic SDIP type) Emulation probe 64-pin plastic (GC-AB8 type) Emulation probe 64-pin plastic TQFP (GK-9ET type) Conversion socket connect EP-78240GC-R target system board which 64-pin plastic (GC-AB8 type) mounted Conversion adapter connect EP-78012GK-R target system board which 64-pin plastic TQFP (GK-9ET type) mounted Integrated debugger IE-78001-R-A System simulator common 78K/0 Series Device file µPD780034A, 780034AY Subseries
Real-Time
RX78K0 MX78K0 Real-time 78K/0 Series 78K/0 Series
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Cautions Using Development Tools ID78K0-NS, ID78K0, SM78K0 used combination with DF780034. CC78K0 RX78K0 used combination with RA78K0 DF780034. FL-PR2, FL-PR3, FA-64CW, FA-64GC, FA-64GK-9ET, NP-64CW, NP-64GC, NP-64GC-TQ, NP-64GK products made Naito Densei Machida Mfg. Co., Ltd. (+81-44-822-3813). TGC-064SAP, TGK-064SBP products made TOKYO ELETECH CORPORATION. Refer Daimaru Kogyo, Ltd. Tokyo Electronic Division (+81-3-3820-7112) Osaka Electronic Division (+81-6-6244-6672) third-party development tools, Single-chip Microcontroller Development Tool Selection Guide (U11069E). host machines supporting each software follows.
Host Machine [OS] Software RA78K0 CC78K0 ID78K0-NS ID78K0 SM78K0 RX78K0 MX78K0
PC-9800 series [Japanese WindowsTM] PC/AT compatibles [Japanese/English Windows] Note
Note
HP9000 series 700[HP-UXTM] SPARCstation[SunOSTM, SolarisTM] NEWS(RISC) [NEWS-OSTM]
Note
Note
Note
DOS-based software
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
APPENDIX RELATED DOCUMENTS
related documents indicated this publication include preliminary versions. However, preliminary versions marked such. Documents Related Devices
Document Name Document U14046E This document
µPD780024A, 780034A, 780024AY, 780034AY Subseries User's Manual µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A) Data Sheet µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY Data Sheet µPD78F0034A, 78F0034AY Data Sheet
78K/0 Series User's Manual Instructions
U14044E U14040E U12326E
Documents Related Development Tools (User's Manuals)
Document Name RA78K0 Assembler Package Operation Assembly Language Structured Assembly Language CC78K0 Compiler Operation Language IE-78K0-NS In-circuit Emulator IE-78001-R-A In-circuit Emulator IE-780034-NS-EM1 Emulation Board EP-78240 Emulation Probe EP-78012GK-R Emulation Probe SM78K0S, SM78K0 System Simulator Ver. 2.10 Later Windows based SM78K Series System Simulator Ver. 2.10 Later Windows based Operation External Part User Open Interface Specifications ID78K0-NS Integrated Debugger Ver. 2.00 Later Windows based ID78K0-NS, ID78K0S-NS Integrated Debugger Ver. 2.20 Later Windows based ID78K0 Integrated Debugger based ID78K0 Integrated Debugger Windows based Reference Reference Guide U11539E U11649E Operation Operation U14379E prepared Document U11802E U11801E U11789E U11517E U11518E prepared U10332E U14611E prepared
Caution related documents listed above subject change without notice. sure latest version each document designing.
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Documents Related Embedded Software (User's Manuals)
Document Name 78K/0 Series Real-time Fundamentals Installation 78K/0 Series MX78K0 Fundamental Document U11537E U11536E U12257E
Other Related Documents
Document Name SEMICONDUCTOR SELECTION GUIDE Products Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades Semiconductor Devices Semiconductor Device Reliability/Quality Control System Guide Prevent Damage Semiconductor Devices Electrostatic Discharge (ESD) Guide Microcomputer-Related Products Third Party Document X13769X C10535E C11531E C10983E C11892E
Caution related documents listed above subject change without notice. sure latest version each document designing.
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
[MEMO]
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
[MEMO]
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
[MEMO]
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Note: Purchase components conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips.
IEBus trademarks Corporation. Windows either registered trademark trademark Microsoft Corporation United States and/ other countries. PC/AT trademark International Business Machines Corporation. HP9000 series HP-UX trademarks Hewlett-Packard Company. SPARCstation trademark SPARC International, Inc. Solaris SunOS trademarks Microsystems, Inc. NEWS NEWS-OS trademarks Sony Corporation.
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Regional Information
Some information contained this document vary from country country. Before using product your application, pIease contact office your country obtain list authorized representatives distributors. They will verify:
Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements
addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 Fax: 01-30-67 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics (France) S.A. Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
Electronics Singapore Pte. Ltd.
United Square, Singapore Tel: 65-253-8311 Fax: 65-250-3583
Electronics Taiwan Ltd. Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
Brasil S.A.
Electron Devices Division Guarulhos-SP Brasil Tel: 55-11-6462-6810 Fax: 55-11-6462-6829
J00.7
Data Sheet U15132EJ1V0DS00
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
export this product from Japan regulated Japanese government. export this product prohibited without governmental license, need which must judged customer. export re-export this product from country other than Japan also prohibited without license from that country. Please call sales representative.
information this document current September, 2000. information subject change without notice. actual design-in, refer latest publications NEC's data sheets data books, etc., most up-to-date specifications semiconductor products. products and/or types available every country. Please check with sales representative availability additional information. part this document copied reproduced form means without prior written consent NEC. assumes responsibility errors that appear this document. does assume liability infringement patents, copyrights other intellectual property rights third parties arising from semiconductor products listed this document other liability arising from such products. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. assumes responsibility losses incurred customers third parties arising from these circuits, software information. While endeavours enhance quality, reliability safety semiconductor products, customers agree acknowledge that possibility defects thereof cannot eliminated entirely. minimize risks damage property injury (including death) persons arising from defects semiconductor products, customers must incorporate sufficient safety measures their design, such redundancy, fire-containment, anti-failure features. semiconductor products classified into following three quality grades: "Standard", "Special" "Specific". "Specific" quality grade applies only semiconductor products developed based customer-designated "quality assurance program" specific application. recommended applications semiconductor product depend quality grade, indicated below. Customers must check quality grade each semiconductor product before using particular application. "Standard": Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade semiconductor products "Standard" unless otherwise expressly specified NEC's data sheets data books, etc. customers wish semiconductor products applications intended NEC, they must contact sales representative advance determine NEC's willingness support given application. (Note) "NEC" used this statement means Corporation also includes majority-owned subsidiaries. "NEC semiconductor products" means semiconductor product developed manufactured defined above).

µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), µPD780031AY(A), 780

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