Ultra Power 10/100 Ethernet Transceiver with Auto-MDIX DESCRIPTIO

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Ultra Power 10/100 Ethernet Transceiver with Auto-MDIX DESCRIPTIO

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AC101L
Ultra Power 10/100 Ethernet Transceiver with Auto-MDIX
DESCRIPTION AC101L single channel, power, transceiver integrated voltage regulator allow operation from single supply source. device contains full-duplex 10BASE-T/100BASE-TX/ 100BASE-FX Fast Ethernet transceiver, which performs physical layer interface functions. AC101L highly integrated solution combining encoder/decoder, link monitor, auto-negotiation selection, parallel detection, adaptive equalization, clock/ data recovery, baseline wander correction, multimode transmitter, scrambler/descrambler, far-end fault (FEF), auto-MDI/MDIX circuitry. fully compliant with IEEE802.3 802.3u standards.
tolerant capable Integrated voltage regulator allow operation from single supply source 10/100 TX/FX Full-duplex half-duplex FEFI 100FX 48-pin TQFP Industrial temperature (-40°C +85°C) 0.25 CMOS Fully compliant with IEEE 802.3/802.3u MII/RMII interface Baseline wander correction Multifunction outputs Cable length indicator auto-MDI/MDIX Eight programmable interrupts Diagnostic registers
100RX
RXN/RXP
Data Interface Interface
Framer Carrier 4B/5B
Clock Recov. Link Monitor Signal Detect 25Mhz
TP_PMD MLT3 Stream Cipher
100TX
TXN/TXP
10RX
10BASE-T
10TX
Serial Interface Serial Management Interface Register
Control Status
Gen. Test/LED Control
25Mhz
Auto Negotiation
PHYAD[4:0]
XTLI/CLKIN
Drivers
Figure
AC101L functional block diagram
16215 Alton Parkway P.O. 57013 Irvine, California 92619-7013 Phone: 949-450-8700 Fax: 949-450-8710
AC101L-DS02-R 06/06/02
REVISION HISTORY
Revision
AC101L-DS02-R
Date
06/06/02
Change Description
Added table showing current requirements operation with disabled. Added table showing current requirements operation with disabled. Added output voltage high values output voltage values (all digital pins). Added input voltage high values (all digital input pins).
AC101L-DS01-R AC101L-DS00-R
02/20/02 01/02/02
Updated application figure Power ground filtering figure. Initial release.
Broadcom Corporation P.O. 57013 16215 Alton Parkway Irvine, California 92619-7013 Copyright 2001 Broadcom Corporation rights reserved Printed U.S.A.
Broadcom® pulse logo® trademarks Broadcom Corporation and/or subsidiaries United States certain other countries. other trademarks property their respective owners.
Preliminary Data Sheet
06/06/02
AC101L
CONTENTS
Section Functional Description.
Encoder/Decoder Link monitor Carrier sense (CRS)/RXDV Collision detection Auto-Negotiation Parallel detection Analog adaptive equalizer Clock recovery Baseline wander correction Multimode transmitter Stream cipher scrambler/descrambler (far-end fault) Transmit driver auto-MDI/MDIX interface
RMII SMI.
Physical layer interfaces
Section Descriptions Section Pinout Diagram Section Operational Description
Reset Power source Power saving mode Clock source Isolate mode Loopback mode Interrupt mode operation
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AC101L
Preliminary Data Sheet
06/06/02
interface.14 configuration [3:0] event table
Section Register Description
register summary.17
Register Control register.18 Register Status register Register Identifier register Register Identifier register Register Auto-Negotiation Advertisement register Register Auto-Negotiation Link Partner Ability register/Link Partner Next Page message.21 Register Auto-Negotiation Expansion register.21 Register Auto-Negotiation Next Page Transmit register.22 Register Interrupt Level Control register Register Interrupt Control/Status register Register Diagnostic register Register Power/Loopback register Register Cable Measurement Capability register Register Receive Error Counter Register Power Management register Register Operation Mode register Register Recent Received Packet.26
Common registers
Common Register (Map Reg. Mode Control register Common Register (Map Reg. Page a28.[15:12]=0000) Test Mode register Common Register (Map Reg. Page a28.[15:12]=0001) Blink Rate.27 Common Register (Map Reg. Page a.28.[15:12]=0001) LED0 Setting1 register Common Register (Map Reg. Page a.28.[15:12]=0001) LED0 Setting2 register Common Register (Map Reg. Page a.28.[15:12]=0010) LED1 Setting1 register Common Register (Map Reg. Page a.28.[15:12]=0010) LED1 Setting2 register Common Register (Map Reg. Page a.28.[15:12]=0010) LED2 Setting1 register Common Register (Map Reg. Page a.28.[15:12]=0011) LED2 Setting2 register Common Register (Map Reg. Page a.28[.15:12]=0011) LED3 Setting1 register Common Register (Map Reg. Page a.28.[15:12]=0011) LED3 Setting2 register
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Preliminary Data Sheet
06/06/02
AC101L
Section 4B/5B Code Group. Section Read/Write Sequence. Section Timing Characteristics
Clock timing Reset timing Management Data Interface timing 100BASE-TX/FX transmit system timing 100BASE-TX/FX receive system timing 10BASE-T transmit system timing 10BASE-T receive system timing RMII transmit timing RMII receive timing Copper application termination
Section Electrical Characteristics.
Absolute maximum ratings Recommended operating conditions
Section Fiber Application Termination. Section Power Ground Filtering Section Mechanical Information. Section Thermal Parameters Section Ordering Information.
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AC101L
Preliminary Data Sheet
06/06/02
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Preliminary Data Sheet
06/06/02
AC101L
FIGURES
Figure AC101L functional block diagram.i Figure AC101L pinout diagram. Figure Reset timing Figure Management interface timing Figure 100BASE-TX/FX transmit timing Figure 100BASE-T receive timing Figure 10BASE-T transmit timing Figure 10BASE-T Receive Timing. Figure RMII transmit timing Figure RMII receive timing. Figure application. Figure application. Figure Power ground filtering Figure Quad Flat Pack outline mm).
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AC101L
Preliminary Data Sheet
06/06/02
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Preliminary Data Sheet
06/06/02
AC101L
TABLES
Table Pinout signal definitions. Table [3:0] event table Table register summary Table Register Control register. Table Register Status register Table Register Identifier register Table Register Identifier register Table Register Auto-Negotiation Advertisement register Table Register Auto-Negotiation Link Partner Ability register/Link partner Next Page message Table Register Auto-Negotiation Expansion register. Table Register Auto-Negotiation Next Page Transmit register. Table Register Interrupt Level Control register Table Register Interrupt Control/Status register Table Register Diagnostic register Table Register Power/Loopback register Table Register Cable Measurement Capability register Table Register Receive Error Counter Table Register Power Management register Table Register Operation Mode register Table Register Recent Received Packet. Table Common Register (Map Reg. Mode Control register Table Common Register (Map Reg. Page a28.[15:12]=0000) Test Mode register Table Common Register (Map Reg. Page a28.[15:12]=0001) Blink Rate. Table Common Register (Map Reg. Page a.28.[15:12]=0001) LED0 Setting1 Register. Table Common Register (Map Reg. Page a.28.[15:12]=0001) LED0 Setting2 register Table Common Register (Map Reg. Page a.28.[15:12]=0010) LED1 Setting1 register Table Common Register (Map Reg. Page a.28.[15:12]=0010) LED1 Setting2 register Table Common Register (Map Reg. Page a.28.[15:12]=0010) LED2 Setting1 register Table Common Register (Map Reg. Page a.28.[15:12]=0011) LED2 Setting2 register Table Common Register (Map Reg. Page a.28[.15:12]=0011) LED3 Setting1 register Table Common Register (Map Reg. Page a.28.[15:12]=0011) LED3 Setting2 register Table 4B/5B code group.
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AC101L
Preliminary Data Sheet
06/06/02
Table read/write sequence Table Clock timing Table Reset Timing Table Management Interface Timing Table 100BASE-X transmit system timing Table 100BASE-TX/FX receive system timing.38 Table 10BASE-T transmit system timing Table 10BASE-T receive system timing Table RMII transmit timing Table RMII receive timing Table Absolute maximum ratings.45 Table Current requirement operation with disabled.45 Table Current requirement operation with disabled.45 Table Recommended operating conditions Table Thermal parameters.53
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Preliminary Data Sheet
06/06/02
AC101L
Functional Description
AC101L single-chip, Fast Ethernet transceiver. performs physical layer interface functions 100BASE-TX full-duplex half-duplex Category twisted-pair cable, 10BASE-T full-duplex half-duplex Category cable. configure 100BASE-FX full- half-duplex transmission over fiber optic cable when pair with external fiber optic line driver receiver. chip performs 4B5B, MLT3, NRZI, encoder/decoder, link monitor, auto-negotiation selection, adaptive equalization, clock/data recovery, baseline wander correction, multimode transmitter, scrambler/descrambler, far-end fault (FEF), auto-MDI/MDIX. connected switch controller through side, connects directly media other side through transformer twisted-pair (TP) mode, fiber-optic module mode. fully compliant with IEEE 802.3 803.3u standards.
ENCODER/DECODER
100BASE-TX 100BASE-FX modes, AC101L transmits receives data stream twisted-pair fiber-optic cable. When transmit enable asserted, nibble wide bit) data from transmit data pins encoded into 5-bit code groups inserted into transmit data stream. 4B5B encoding shown Section "4B/5B Code Group" page transmit packet encapsulated replacing first nibbles preamble with start stream delimiter (J/K codes) appending stream delimiter (T/R codes) packet. When transmit error input asserted during packet, error code group sent place corresponding data code group. transmitter sends repeatedly idle code group between packets. 100BASE-TX mode, encode data stream scrambled stream cipher block then serialized encoded into MLT3 signal level. multi mode transmit (digital analog converter) used drive MLT3 data onto twistedpair cable. Following baseline wander correction, adaptive equalization clock/data recovery 100BASE-TX mode, receive data stream converted from MLT3 serial data. data descrambled stream cipher block then deserialized aligned into 5-bit code groups. 100BASE-FX mode, scrambling function bypassed data NRZII encoded. multi mode transmit drives differential Positive (PECL) levels external fiber optic transmitter. Baseline wander correction, adaptive equalization, stream cipher descrambling functions bypass NRZI decoding used instead MLT3. 5-bit code groups decoded into data nibbles. start stream delimiter replaced with preamble nibbles stream delimiter idle codes replaced with zeros. decoded data driven onto receive data pins. When invalid code group detected data stream, AC101L asserts RXER signal. 10BASE-T mode, Manchester encoding decoding performed data stream. multi mode transmit performs pre-equalization meters Category cable.
LINK MONITOR
100BASE-TX mode, receive signal energy detected monitoring receive pair transitions signal level. signal levels qualified using squelch detect circuits. When signal certain valid signal detected receive pair minimum period time, link monitor enter link pass state transmit receive functions enabled. 100BASE-FX mode, external fiber-optic receiver performs signal energy detection function communicates this information directly signal (PIN 28).
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AC101L
Carrier sense (CRS)/RXDV
Preliminary Data Sheet
06/06/02
10BASE-T mode, link pulse detection circuit constantly monitors RXP/RXN pins present valid link pulses.
CARRIER SENSE (CRS)/RXDV
Carrier sense asserted asynchronously pins soon activity detected receive data stream. RXDV asserted soon valid (Start-of-Stream Delimiter) detected. Carrier sense RXDV de-asserted synchronously upon detection valid stream delimiter consecutive idle code groups receive data stream. However, carrier sense asserted valid detected immediately, RXER asserted instead RXDV. 10BASE-T mode, asserted asynchronously when valid preamble data activity detected RXIP RXIN pins. half-duplex mode, activated during data transmit. full-duplex mode, activated during data receiving only.
COLLISION DETECTION
half-duplex mode, collision detect asserted whenever carrier sense asserted transmission progress.
AUTO-NEGOTIATION
Auto-negotiation selection 100BASE twisted-pair only; operating 100BASE fiber PHY. 100BASE-TX mode, auto-negotiation enabled disabled hardware software control. When auto-negotiation function enable, 100BASE-TX automatically chooses mode operation advertising abilities comparing them with those received from it's link partner. 100BASE-TX configured advertise 100BASE-TX full-duplex 100BASE-TX half-duplex. default auto-negotiation mode configured reset read value ANEN/LED3 signal (pin SPD100/LED1.
Table
0.13 0.12 4.8/1.14 4.7/1.13 4.6/1.12 4.5/1.11 Speed Select ANEN Enable Duplex 100BASE-TX Full-Duplex 100BASE-TX 10BASE-T Full-Duplex 10BASE-T default value SPD100 Enable Auto-negotiation. Disable Auto-negotiation. default value !ANEN DUPLEX default value this SPD100 DUPLEX default value SPD100 (ANEN !DUPLEX) default value this DUPLEX (ANEN !SPD100) default value ANEN (!SPD100 !DUPLEX)
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Preliminary Data Sheet
06/06/02
AC101L
Functional Description
PARALLEL DETECTION
Because there many devices field that support ANEN process, must still communicated with, necessary detect link through parallel detection process. parallel detection circuit enabled absence FLPs. circuit able detect following: Normal link pulse (NLP) 10BASE-T receive data 100BASE-TX idle
mode operation gets configured based technology incoming signal. above detected, device automatically configures match detected operating speed half-duplex mode. This ability allows device communicate with legacy 10BASE-T 100BASE-TX systems, while maintaining flexibility auto-negotiation.
ANALOG ADAPTIVE EQUALIZER
analog adaptive equalizer removes Inter Symbol Interference (ISI) created transmission channel media. designed accommodate maximum meters Category cable. AT&T 1061 Category cable this length typically attenuation MHz. typical attenuation 100-meter cable worst case cable attenuation around 24-26 defined TP-PMD specification. amplitude phase distortion from cable causes which makes clock data recovery difficult. adaptive equalizer designed closely match inverse transfer function twisted-pair cable. equalizer ability changes equalizer frequency response according cable length. equalizer will tune itself automatically cable, compensating amplitude phase distortion introduced cable.
CLOCK RECOVERY
equalized MLT3 signal passes through slicer circuit, gets converted NRZI format. uses proprietary mixed-signal Phase Locked Loop (PLL) extract clock information from incoming NRZI data. extracted clock used re-time data stream data boundaries. transmit clock locked clock input while receive clock locked incoming data streams. When initial lock achieved, switches data stream, extracts clock, uses framing recovered data. recovered clock also used generate RX_CLK signal. requires external components operation high noise immunity jitter. provides fast phase alignment locks data transition. data/clock acquisition time, after power-on, less than transitions. maintain lock run-lengths data bits absence signal transitions. When valid data present (that when deasserted), switches locks TX_CLK. This provides continuously running RX_CLK. interface, 5-bit data RXD[4:0] synchronized RX_CLK.
BASELINE WANDER CORRECTION
100BASE-TX data stream always balanced. Because receive signal must pass through transformer, offset differential receive input wander. This effect, known baseline wander, greatly reduce noise immunity receiver. 100BASE-TX automatically compensates baseline wander removing offset from input signal, thereby significantly reduces chance receive symbol error. baseline wander circuit required 100BASE-FX operation.
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AC101L
Multimode transmitter
Preliminary Data Sheet
06/06/02
MULTIMODE TRANSMITTER
multimode transmitter transmits MLT3 coded symbols 100BASE-TX mode, NRZI coded symbols 100BASE-FX mode. utilizes current drive output, which well balanced produces very noise transmit signals. PECL voltage levels produced with resistive terminations 100BASE-FX mode. serialized data bypasses scrambler 4B/5B encoder mode. output data NRZI PECL signals. PECL level signals used drive fiber-optic transmitter.
STREAM CIPHER SCRAMBLER/DESCRAMBLER
100BASE-TX mode, transmit data stream scrambled reduce radiated emissions twisted-pair cable. data scrambled exclusive ORing signal with output 11-bit wide Linear Feedback Shift register (LFSR), which produces 2047 nonrepeating sequence. scrambler reduces peak emission randomly spreading signal energy over transmit frequency range eliminating peaks certain frequencies. receiver descrambles incoming data stream exclusive ORing with same sequence generated transmitter. descrambler detects state transmit LFSR looking sequence representing consecutive idle codes. descrambler locks scrambler state after detecting sufficient number consecutive idle code group. receiver does attempt decode data stream unless descrambler locked. When locked, descrambler continuously monitors data stream make sure that lost synchronization. receive data stream expected contain inter-packet idle periods. descrambler does detect enough idle code within becomes unlocked receive decoder disabled. descrambler always forced into unlock state when link failure condition detected. Stream cipher descrambler used 100BASE-FX mode.
(FAR-END FAULT)
Auto-negotiation provides mechanism inform link partner that remote fault occurred. Auto-negotiation disabled, however, 100BASE-FX applications. alternative in-band signaling function (FEFI) used signal remote fault condition. FEFI stream consecutive ones followed logic zero. This pattern repeated three times. FEFI signal given under three conditions: When activity received from link partner, When clock recovery circuit detects signal error lock error, When management entity sets Transmit Far-End Fault bit.
FEFI mechanism enabled default 100BASE-FX mode, disabled 100BASE-TX 10BASE-T modes. register setting changed software after reset.
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Preliminary Data Sheet
06/06/02
AC101L
Functional Description
TRANSMIT DRIVER
100BASE-TX mode, transmit function converts synchronous 4-bit data nibbles from pair Mbps differential serial data streams. serial data transmitted over network twisted-pair cables isolation transformer. Data conversion includes 4B/5B encoding, scrambling, parallel-to-serial, NRZI, MLT3 encoding. entire operation synchronous clocks. Both clocks generated on-chip clock synthesizer that locked external clock source. 100BASE-FX, transmit driver does perform filtering; utilizes current drive output that well balanced produces noise PECL signal. PECL voltage levels produced with resistive terminations. 10BASE-T mode, interface used, parallel-to-serial logic used convert 4-bit data into serial stream through output wave shaping driver. wave shaper reduces emission filtering harmonics, therefore eliminating need external filter.
AUTO-MDI/MDIX
This feature able detect required cable connection type (straight through crossed over) make correction automatically.
INTERFACE
Media Independent Interface (MII) 18-wire MAC/PHY interface described IEEE 802.3u. purpose interface allow layer devices attach variety physical layer devices through common interface. operates either Mbps Mbps, depending speed physical layer. With clocks running either MHz, 4-bit data clocked between PHY, synchronously with Enable Error signals. time lock incoming signal from wire interface, generates RX_CLK either Mbps Mbps. receipt valid data from wire interface, RXDV goes active signaling that valid data will presented RXD[3:0] pins speed RX_CLK. transmission data from MAC, TXEN presented PHY, indicating presence valid data TXD[3:0]. TXD[3:0] sampled PHY( synchronous TX_CLK) during time that TXEN valid.
RMII
Reduced Media Independent Interface (RMII) used connect with MAC. obtain their clock timing from common source, such clock oscillator. This clock shared ports within transmitting receiving data individual 2-bit data buses. RXDV multiplexed indicate when there valid data receive bus. Mbps mode, RXD[1:0] sampled every cycle REFCLK. Mbps mode, RXD[1:0] sampled every 10th cycle REFCLK. RXER generated indicate receive error MAC. TXEN generated indicate when there valid data transmit bus. Mbps mode reads bits from TXD[1:0] each cycle REFCLK. Mbps mode, reads bits data from TXD[1:0] every 10th cycle REFCLK.
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AC101L
Physical layer interfaces
Preliminary Data Sheet
06/06/02
PHYs internal registers accessible only through 2-wire Serial Management Interface (SMI). clock input PHY, which used latch data instructions PHY. clock speed from MHz. MDIO bidirectional connection used write instructions write data read data from PHY. Each data latched either rising edge MDC. required maintain speed duty cycle, provided half cycle less than that data presented synchronous MDC. MDC/MDIO common signal pair PHYs design. Therefore, each needs have unique physical address. physical address using pins defined PHYAD[4:0]. These input signals strapped externally, sampled reset negated. idle, responsible pull MDIO line high state. Therefore, resistor required connect MDIO line VCC.
PHYSICAL LAYER INTERFACES
supported interfaces twisted-pair (TP) interface with auto-MDI/MDIX selection, fiber-optic Interface with PECL signaling. selection these interfaces performed reset time SD/FXEN signal (pin 28). Pull enable interface, connect fiber module enable interface.
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Preliminary Data Sheet
06/06/02
AC101L
Descriptions
Section iptions
Many have multiple functions. multifunction pins designated bold style number. separate descriptions these pins listed proper sections. Designers must assure that they have identified modes operation prior final design. Signal types: Bidirection Power Ground Analog Input Analog output Digital pull-down Digital pull-up Active
digital pins bidirectional pins.
Table Pinout signal definitions
name
RXDV/CRSDV
Type
Description
+2.5 power supply. Ground Ground RXDV (active HIGH output): Receive Data Valid output signal mode. RXDV active HIGH indicate that receive frame progress, that data stream present output pins valid. CRSDV (active HIGH output): Carrier Sense/Data Valid output signal RMII mode. CRSDV asserted high when media non-idle. RMII_mode (resets read input): Pull HIGH configure chip into RMII mode. Default mode. RX_CLK (Out put): Receive clock mode. RX_CLK 100BASE output 10BASE. This clock recovered from incoming data cable inputs. ISOLATE (resets read Input): Pull HIGH isolate from MII. output pins high impedance. input pins still respond data. This allows multiple attached same interface. RXER (active HIGH output): asserted indicate that invalid symbol detected both RMII modes. Ground +2.5 power supply. TXER (active HIGH input): Transmits error interface. When TXER asserted more TX_CLK periods while TXEN also asserted, emits more symbols that part valid data delimiter somewhere frame being transmitted. relative position error within frame need preserved. TX_CLK (output): Transmits clock signal mode. TX_CLK output 100BASE operation 10BASE operation. This clock continuously-driven output, generated from (crystal input) pin. TXEN (active HIGH input): Transmits Enable signal RMII interfaces. TXEN asserted indicate that valid data present TXD[3:0]. TXD0: Transmits data input RMII interfaces.
RMII_mode/ RX_CLK
ISOLATE/RXER
TXER
TX_CLK
TXEN TXD0
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AC101L
Physical layer interfaces
Preliminary Data Sheet
06/06/02
Table Pinout signal definitions (Cont.)
name
TXD1 TXD2 TXD3
Type
Description
TXD1: Transmits data input RMII interfaces. TXD2: Transmits data input interface. TXD3: Transmits data input interface. (active HIGH output): collision detect signal interface. halfduplex mode, active high output indicates that collision occurred. fullduplex mode, remains low. REPEATER: Resets read input. Active high puts chip repeater mode. (active HIGH output): Carrier sense signal interface. asserted when twisted-pair media non-idle deasserted when idle valid end-ofstream delimiter detected. Ground +2.5 power supply. PHYAD0: Resets read Input. Pull high Address MII/ RMII management function. INTR (output): interrupt output enable. active value inverse reset read value. BURNIN#: Resets read input. Active chip burn-in test mode. LED0 (output): active, default behavior when chip link-up condition BLINK when chip detects transmits receive activity. SPD100: Resets read input. ANEN Low, SPD100 sets port speed register ANEN High, SPD100 used Mbps half-duplex Mbps fullduplex bits register LED1 (output): active. default behavior when chip operating Mbps, when chip operating Mbps. DUPLEX: Resets read input. ANEN Low, DUPLEX sets port full-duplex mode register ANEN High, DUPLEX used Mbps Mbps bits register LED2 (output): active. default behavior when chip operating full-duplex mode when chip operating half-duplex mode. ANEN (resets read input): Auto-negotiation enable twisted-pair port. Pull high enable auto-negotiation. Pull disable auto-negotiation. LED3 (output): active. default behavior BLINK when chip detect collision half-duplex mode. PDOWN# (input): Power-down input. Pulling this puts both fiber port into power-down mode. This regular input, reset read signal. +2.5 power supply. Receive. port mode. Transmit. port MDIX mode. Receive port mode. Transmit port MDIX mode. SD/FXEN (analog input): Pull enable mode. Connect fiber module enable mode; also serves signal detect input. Ground Ground Bias resistor connection. Connect resistor GND. +2.5 supply analog bias, modules. Ground Transmit. mode. Receive. MDIX mode.
REPEATER/
PHYAD0/INTR
BURNIN#/ LED0
SPD100/LED1
DUPLEX/LED2
ANEN/LED3
PDOWN# SD/FXEN RBIAD VCCPLL
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Preliminary Data Sheet
06/06/02
AC101L
Descriptions
Table Pinout signal definitions (Cont.)
name
VCC25OUT
Type
Description
Transmit mode. Receive MDIX mode. +2.5 from chip regulator. Ground Ground XTAL output. XTAL input. RMII mode, defined CLK_REF clock input. Mode: designed connect MHz., XTAL OSC. Power supply input. Reset input. active. MDIO (input/ output): Management data I/O. This serial input/output used read from write register. data value MDIO valid latched rising edge MDC. This requires resistor pull-up. (input): Management data clock. clock input must provided allow management function. This Schmitt trigger input. PHYAD1: Resets read input. Pull high Address MII/RMII management function. RXD3: Receives data output signal interface. PHYAD2: Resets read input. Pull high Address MII/RMII management function. RXD2: Receives data output signal interface. PHYAD3 (Reset Read Input): Pull High Address MII/ RMII management function. RXD1: Receive data output signal MII/RMII interface. PHYAD4: Resets read input. Pull high Address MII/RMII management function. RXD0: Receives data output signal MII/RMII interface.
VCC33IN RST# MDIO
PHYAD1/ RXD3
PHYAD2/ RXD2
PHYAD3/ RXD1
PHYAD4/ RXD0
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AC101L
Physical layer interfaces
Preliminary Data Sheet
06/06/02
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Preliminary Data Sheet
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AC101L
Pinout Diagram
PHYAD4/RXD0 PHYAD3/RXD1 PHYAD2/RXD2 PHYAD1/RXD3
RST#
VCC33IN
MDIO
RXDV/CRSDV RMII_mode/RX_CLK ISOLATE/RXER TXER TXEN TXD0 TXD1
VCC25OUT VCCPLL RBIAD SD/FXEN
AC101L
48TQFP_7x7mm
BURNIN#_L/LED0
SPD100/LED1
REPEATER/CRS
PHYAD0/INTR
DUPLEX/LED2
ANEN/LED3
TXD2
TXD3
Figure AC101L pinout diagram
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PDOWN#
AC101L
Physical layer interfaces
Preliminary Data Sheet
06/06/02
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Preliminary Data Sheet
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AC101L
Operational Description
RESET
reset three ways: During initial power Hardware reset: (See "Pin Descriptions" page Software reset: (See "Register Description" page 17).
POWER SOURCE
AC101L chip provides onboard input output regulator with capability drive current. output supplies operation, including LEDs. recommended limit current below LED. power should decoupled provide digital analog pins chip.
POWER SAVING MODE
power consumption AC101L device significantly reduced built-in power management features. Separate power supply lines used power 10BASE-T circuitry 100BASE-TX circuitry. Therefore, circuits turned turned independently. When operate 100BASE-TX mode, 10BASET circuitry powered down. following power management features supported: Power-down mode: (see register descriptions). During power down mode, device still able interface through management interface. Energy detect/power saving mode: Energy detect mode turns power select internal circuitry when there live network connected. energy detect (ED) circuit always turned monitor there signal energy present media. management circuitry also powered ready respond management transaction. transmit circuit still sends link pulses with minimum power consumption. valid signal received from media, device powers resumes normal transmit/receive operations. Valid data detection mode: This achieved writing Receive Clock Register control bit. During this mode, there data other than incoming idles, receive clock (RX_CLK) turns itself off. This could save power attached media access controller. RX_CLK resumes operation clock period prior assertion RXDV. receive clock again shuts clock cycles after RXDV deasserted.
CLOCK SOURCE
clock source this chip from pin. mode, connect (parts million) XTAL (crystal). When operating RMII mode, this shall connected MHz, clock reference. internal circuit determines operating mode upon reset read RX_CLK/RMII_SEL signal, decides whether divide done this clock provide internal clock reference.
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AC101L
Isolate mode
Preliminary Data Sheet
06/06/02
ISOLATE MODE
When AC101L device into isolate mode, inputs (TXD[3:0}, TXEN, TXER) ignored, outputs (TX_CLK, COL, CRS, RX_CLK, RXDV, RXER, RXD[3:0] high impedance. Only management pins (MDC, MDIO) operate normally. Pull HIGH reset write register chip into isolate mode.
LOOPBACK MODE
Local loopback provided testing purpose. enabled writing register local loopback routes transmitted data through transmit path back clock data recovery module receiving path. loopback data presented symbol format. This loopback used check operation 5-bit symbol decoder phase lock loop circuitry. local loopback, output forced logical TXOP/N outputs tri-stated.
INTERRUPT MODE
INTR asserted whenever selectable interrupt events occurs. assertion state high programmable through INTR_LEVL register bit. selection made setting appropriate upper half Interrupt Control/Status register. When INTR goes active, interface required read Interrupt Control/Status register determine which event caused interrupt. Status bits read-only clear-on-read. When INTR asserted, held high impedance state.
OPERATION
INTERFACE
interface fully configurable through register setting. connection (source/sink current) depends default setting. default modes shown below:
LED0 Link/Act LED1 Speed LED2 Duplex LED3
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Preliminary Data Sheet
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AC101L
Operational Description
CONFIGURATION
LEDs fully configurable other operational modes. Each 16-bit registers define operation. "Common registers" page Table configure LEDs work with operational modes other than default mode.
[3:0] EVENT TABLE
[3:0] configurable. following events defined AC101L operation:
Table [3:0] event table
Bit#
Description
Duplex Collision Speed Speed Transmit activity Transmit/Receive activity Receive activity Link
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AC101L
operation
Preliminary Data Sheet
06/06/02
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Preliminary Data Sheet
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AC101L
Register Description
first registers register defined specification. addition these required registers several registers that specific Altima Communications Inc. There reserved registers and/or bits that Altima internal only. following standard registers supported (register numbers decimal notation; values hexadecimal notation): NOTE-When writing registers, recommended that read/modify/write operation performed, unintended bits unwanted states. This applies registers, including those with reserved bits. Legend: Read write access Self-clearing Latch until cleared reading Read-only Cleared read Latch high until cleared reading
REGISTER SUMMARY
Table register summary
Register Description Default value
Registers
Control register Status register Identifier register Identifier register Auto-Negotiation Advertisement register Auto-Negotiation Link Partner Ability register Auto-Negotiation Expansion register Next Page Advertisement register 3000 7849 0022 5521 01E1 0001 0004 2001
Registers 8-31
8-15 18,19 22-31 Reserved Interrupt Level Control register Interrupt Control/Status register Reserved Cable measurement capability register Receive Error Counter register Reserved XXXX 03C0 0000 XXXX XXXX 0304 XXXX
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REGISTER CONTROL REGISTER
Table Register Control register
0.15 0.14
Name
Reset Loopback
Description
reset. This self-clearing. Enable loopback mode. This loops back ignores activity cable media. Normal operation. Mbps Mbps Default value: SPD100 Enable auto-negotiate process (overrides 0.13 0.8) Disable auto-negotiate process. Mode selection controlled 0.8, 0.13 Default value: ANEN Power down. blocks except will turned off. Setting PDOWN# (24) will achieve same result. Normal operation. Electrically isolate from MII. still able respond SMI. Normal operation. Restart auto-negotiation process. Normal operation. Full-duplex operation. Half-duplex operation. Default value: !ANEN DUPLEX Enable collision test, which issues signal response assertion TXEN signal. Collision test disabled PCSBP high. Collision test enabled regardless duplex mode. Disable test.
Mode
RW/SC
Default
0.13
Speed Select
SPD100
0.12
ANEN Enable
ANEN
0.11
Power Down
0.10
Isolate
Restart ANEN Duplex Mode
RW/SC
description
Collision Test
0.[6:0]
Reserved
0000000
REGISTER STATUS REGISTER
Table Register Status register
1.15 1.14
Name
100BASE-T4 100BASE-TX Full-Duplex
Description
Permanently tied zero; indicates 100BASE-T4 capability. 100BASE-TX full-duplex capable. 100BASE-TX full-duplex capable. Default value: SPD100 DUPLEX
Mode
Default
description
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AC101L
Register Description
Table Register Status register
1.13
Name
100BASE-TX Half-Duplex
Description
100BASE-TX half-duplex capable. half-duplex capable. Default value: SPD100 (ANEN !DUPLEX). 10BASE-T full-duplex capable. 10BASE-T full-duplex capable. Default value: DUPLEX (ANEN !SPD100) 10BASE-T half-duplex capable. 10BASE-T half-duplex capable. Default value: ANEN (!SPD100 !DUPLEX) able perform management transaction without MDIO preamble. management interface needs minimum bits preamble after reset. Auto-negotiation process completed. Registers valid after this set. Auto-negotiation process completed. Remote fault condition detected. remote fault. This will remain until cleared reading register Able perform auto-negotiation function; default value determined ANEN pin. Unable perform Auto-Negotiation function. Link established. link fails, this clears remains until register read again. Link down. Jabber condition detected. Jabber condition detected. Extended register capable. This tied permanently value
Mode
Default
description
1.12
10BASE-T Full-Duplex
description
1.11
10BASE-T Half-Duplex
description
1.[10:7]
Reserved Preamble Suppression ANEN Complete
0000
Remote Fault
RO/LH
ANEN Ability
ANEN
Link Status
RO/LL
Jabber Detect Extended Capability
RO/LH
REGISTER IDENTIFIER REGISTER
Table Register Identifier register
2.[15:0]
Name
OUIa
Description
Composed through 18th bits Organizationally Unique Identifier (OUI), respectively.
Mode
Default
0022(H)
Based 0010A9 (hexadecimal)
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REGISTER IDENTIFIER REGISTER
Table Register Identifier register
3.[15:10] 3.[9:4] 3.[3:0]
Name
OUIa Model Number Revision Number
Description
Assigned 19th through 24th bits OUI. manufacturer's model number. Four-bit manufacturer's revision number.
Mode
Default
010101 010010 0001
Based 0010A9 (hexadecimal)
REGISTER AUTO-NEGOTIATION ADVERTISEMENT REGISTER
Table Register Auto-Negotiation Advertisement register
4.15 4.14 4.[13:11] 4.10
Name
Next Page Acknowledge Reserved FDFC
Description
Next Page enabled. Next Page disabled. This internally after receiving consecutive consistent bursts. Full-duplex flow control. Advertise that (MAC) implemented both optional control sublayer pause function specified Clause Annex IEEE 802.3u. does support flow control. Technology supported. This always 100BASE-TX full-duplex capable. 100BASE-TX full-duplex capable. Default value: SPD100 DUPLEX 100BASE-TX half-duplex capable. half-duplex capable. Default value: SPD100 (ANEN !DUPLEX) 10BASE-T full-duplex capable. 10BASE-T full-duplex capable. Default value: DUPLEX (ANEN !SPD100) 10BASE-T half-duplex capable. 10BASE-T half-duplex capable. Default value: ANEN (!SPD100 !DUPLEX) Protocol selection [00001] IEEE 802.3.
Mode
Default
100BASE-T4 100BASE-TX Full-Duplex
description
100BASE-TX
description
10BASE-T Full Duplex
description
10BASE-T
Description
4.[4:0]
Selector Field
00001
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AC101L
Register Description
REGISTER AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER/LINK PARTNER NEXT PAGE
MESSAGE
Table Register Auto-Negotiation Link Partner Ability register/Link partner Next Page message
5.15 5.14 5.[13:10] 5.[4:0]
Name
Next Page Acknowledge Reserved 100BASE-T4 100BASE-TX Full Duplex 100BASE-TX 10BASE-T Full Duplex 10BASE-T Selector Field
Description
Link partner desires Next Page transfer. Link partner does desire Next Page transfer. Link Partner acknowledges reception words. acknowledged link partner.
Mode
Default
100BASE-T4 operation supported link partner. 100BASE-T4 operation supported link partner. 100BASE-TX full-duplex operation supported link partner. 100BASE-TX full-duplex operation supported link partner. 100BASE-TX half-duplex operation supported link partner. 100BASE-TX half-duplex operation supported link partner. Mbps full-duplex operation supported link partner. Mbps full-duplex operation supported link partner. Mbps half-duplex operation supported link partner. Mbps half-duplex operation supported link partner. Protocol Selection [00001] IEEE 802.3.
00001
NOTE-When this register used Next Page message, definition same that register
REGISTER AUTO-NEGOTIATION EXPANSION REGISTER
Table Register Auto-Negotiation Expansion register
6.[15:5]
Name
Reserved Parallel Detection Fault
Description
Fault detected parallel detection logic; this fault more than technology detecting concurrent link-up condition. This only cleared reading register using management interface. fault detected parallel detection logic. Link partner supports Next Page function. Link partner does support Next Page function. Next page supported. This when link code word been received into Auto-Negotiation Link Partner Ability register. This cleared upon read this register. Link partner auto-negotiation capable. Link partner auto-negotiation capable.
Mode
RO/LH
Default
Link Partner Next Page Able Next Page Able Page Received
Link Partner ANEN-Able
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REGISTER AUTO-NEGOTIATION NEXT PAGE TRANSMIT REGISTER
Table Register Auto-Negotiation Next Page Transmit register
7.15 7.14 7.13 7.12 7.11 17.[10:0]
Name
Reserved ACK2 TOG_TX CODE
Description
Another Next Page desired. other Next Page transmit desired. Message page. Unformatted page. Will comply with message. Cannot comply with message. Previous value transmitted link code word equals Previous value transmitted link code word equals Message/Unformatted Code field.
Mode
Default
REGISTER INTERRUPT LEVEL CONTROL REGISTER
Table Register Interrupt Level Control register
16.15 16.14 16.13 16.12 16.11
Name
Repeater INTR_LEVL TXJAM Disable Test Inhibit
Description
Repeater mode. Full-duplex inactive, only responds receive activity. test function disabled. INTR active high. INTR active low. Forces send pattern. Normal operation. Disables carrier integrity monitor. Enables carrier integrity monitor. Disable 10BASE-T testing. Enable 10BASE-T testing, which generates pulse following completion packet transmission. Disables autopolarity detection/correction. Enables autopolarity detection/correction. Reverses polarity when register 16.5 Normal polarity when register 16.5 register 16.5 writing this reverses polarity transmitter.
Mode
Default
Repeater
16.[10:6] 16.5 16.4
Reserved Autopolarity Disable Reverse Polarity
16.[3:0]
Reserved
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AC101L
Register Description
REGISTER INTERRUPT CONTROL/STATUS REGISTER
Table Register Interrupt Control/Status register
17.15 17.14 17.13 17.12 17.11 17.10 17.9 17.8 17.7 17.6 17.5 17.4 17.3 17.2 17.1 17.0
Name
Jabber_IE RXER_IE Page_Rx_IE PD_Fault_IE LP_Ack_IE Link_Status_Change_IE R_Fault_IE ANEN_Comp_IE Jabber_Int RXER_Int Page_Rx_Int PD_Fault_Int LP_Ack_Int Link_Not_OK R_Fault_Int ANEN _Comp
Description
Jabber interrupt enable. Receive error interrupt enable. Page received interrupt enable. Parallel detection fault interrupt enable. Link partner acknowledge interrupt enable. Link status change interrupt enable. Remote fault interrupt enable. Auto-negotiation complete interrupt enable. This when jabber event detected. This when RXER transitions high. This when page received during ANEN. This when parallel detect fault detected. This when with acknowledge received. This when link status switches from status NonOK status (fail ready). This when remote fault detected. This when ANEN complete.
Mode
Default
REGISTER DIAGNOSTIC REGISTER
Table Register Diagnostic register
18.[15] 18.[14] 18.[13] 18.[12] 18.11 18.10 18.9 18.8 18.[7:0]
Name
Reserved Reserved Force Link Pass 10BT Force Link Pass 100TX Reserved Reserved Reserved Reserved Reserved
Description
Reserved Reserved Enables force link pass 10BASE-T. Disables force link pass 10BASE-T. Force link pass 100BASE-TX. Disable Force link pass 100BASE-TX. Reserved Reserved Reserved Reserved Reserved
Mode
RO/RC
Default
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REGISTER POWER/LOOPBACK REGISTER
Table Register Power/Loopback register
19.[14:7] 19.6 19.5
Name
Reserved Reserved Disable Watchdog Timer Decipher Power Mode Disable Reserved Reserved Link Integrity Test Jabber Disable
Description
Reserved Reserved Disables watchdog timer. Enables advanced power saving mode. Enables advanced power saving mode. Disables advanced power saving mode. Reserved Reserved auto-negotiation test mode, sends instead test receive integrity. Sends auto-negotiation test mode. Disables jabber.
Mode
Default
19.4 19.3 19.1
19.0
REGISTER CABLE MEASUREMENT CAPABILITY REGISTER
Table Register Cable Measurement Capability register
20.15 20.14 20.[13:9]
Name
Reserved Reserved Reserved Adaptation Disable Cable Measurement Capability
Description
Reserved Reserved Disables adaptation. Enables adaptation. These bits used cable length indicator. bits incremented from 0000 1111, with increment approximately meters. equivalent with increment MHz. value read back from equalizer, measured value absolute. Reserved
Mode
Default
20.8
20.[7:4]
20.[3:0]
Reserved
value 20.[7:4], must turn 20.8 turn 20.14. Otherwise, this will reject receive packets.
REGISTER RECEIVE ERROR COUNTER
Table Register Receive Error Counter
21.[15:0]
Name
RXER Counter
Description
Counts Receive Error events.
Mode
Default
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AC101L
Register Description
REGISTER POWER MANAGEMENT REGISTER
Table Register Power Management register
22.[15:14] 22.13 22.12 22.11 22.10 22.9 22.8 22.[7:6] 22.5 22.4 22.3 22.2 22.1 22.0
Name
Reserved PD_PLL PD_EQUAL PD_BT_RCVR PD_LP PD_EN_DET PD_FX Reserved MSK_PLL MSK_EQUAL MSK_BT_RCVR MSK_LP MSK_EN_DET MSK_FX
Description
circuit powers down. Equalizer circuit powers down. 10BASE-T receiver powers down. Link pulse receiver powers down. Energy-detect circuit powers down. circuit powers down. Forces circuit power Forces equalizer circuit power Forces 10BASE-T receiver power Forces link pulse receiver power Forces energy-detect circuit power Forces circuit power
Mode
Default
REGISTER OPERATION MODE REGISTER
Table Register Operation Mode register
23.[15:14] 23.13 23.12 23.11 23.10 23.9 23:8 23.[7:6] 23.5 23.[4:0]
Name
Reserved Clk_rclk_save Reserved Scramble Disable Reserved Pcsbp Reserved Reserved Reserved Reserved
Description
Sets rclk save mode. Rclk shuts after cycles each packet. Disables scrambler. Enables scrambler. Enables bypass mode. Disables bypass mode.
Mode
Default
XXXXX
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Common registers
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REGISTER RECENT RECEIVED PACKET
Table Register Recent Received Packet
24.[15:0]
Name
CRC16
Description
Displays CRC16 value. system-level test purposes.
Mode
Default
0000H
COMMON REGISTERS
following registers mapped Reg28-31 PHY. Reg28.[15:12] used page select. There multiple pages Reg29-31, depends value Reg. 28[15:12]
COMMON REGISTER (MAP REG. MODE CONTROL REGISTER
Table Common Register (Map Reg. Mode Control register
a.28.[15:12] a.28.[11:7] a.28.6 a.28.5 a.28.4 a.28.3 a.28.2
Name
Page Selection Reserved MII_enable Reserved RMII_enable Reserved select
Description
Selects multiple common register pages. Reserved Enables interface. Reserved Puts chip reduce mode. Reserved Selects activity event. Receive activity. activity.
Mode
Default
0000 0000
a.28.1 a.28.0
Reserved Reserved
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Register Description
COMMON REGISTER (MAP REG. PAGE A28.[15:12]=0000) TEST MODE REGISTER
Table Common Register (Map Reg. Page a28.[15:12]=0000) Test Mode register
A0.29.15 A0.29.[14:10] A0.29.[9:8] A0.29.[7:4] A0.29.3 A0.29.2 A0.29.1 A0.29.0
Name
Reduce_mcount Reserved Reserved Test Mode Burn Output Disable Reserved Reduce Timer
Description
Reduces millisecond counter microseconds. 0000 Normal operation. Enables burn-in test mode. Normal operation. Disables digital output. Normal operation. Normal operation. Reduces timer auto-negotiation testing. Normal operation.
Mode
Default
00100 0000
COMMON REGISTER (MAP REG. PAGE A28.[15:12]=0001) BLINK RATE
Table Common Register (Map Reg. Page a28.[15:12]=0001) Blink Rate
A1.29.[15:8] A1.29.[7:0]
Name
Reserved Blink Rate
Description
blink rate. blink rate this number Default value
Mode
Default
00000000 00010000
COMMON REGISTER (MAP REG. PAGE A.28.[15:12]=0001) LED0 SETTING1
REGISTER
Default operation LED0 when Link; BLINK when Activity.
Table Common Register (MAP REG. PAGE A.28.[15:12]=0001) LED0 SETTING1 REGISTER
A1.30.[15:13] A1.30.12 A1.30.[11:9] A1.30.8 A1.30.[7:0]
Name
Reserved Force Reserved Force Blink
Description
Forces LED0 Forces LED0 off. Blink mask. When bits corresponding event causes blink.
Mode
Default
0000 00000100
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Common registers
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COMMON REGISTER (MAP REG. PAGE A.28.[15:12]=0001) LED0 SETTING2
REGISTER
Table Common Register (Map Reg. Page a.28.[15:12]=0001) LED0 Setting2 register
A1.31. [15:8] A1.31. [7:0]
Name
Description
mask. When bits corresponding event causes turn mask. When bits corresponding event causes turn off.
Mode
Default
00000001 00000000
COMMON REGISTER (MAP REG. PAGE A.28.[15:12]=0010) LED1 SETTING1
REGISTER
Table Common Register (Map Reg. Page a.28.[15:12]=0010) LED1 Setting1 register
A2.29.[15:13] A2.29.12 A2.29.[11:9] A2.29.8 A2.29.[7:0]
Name
Reserved Force Reserved Force Blink
Description
Forces LED1 Forces LED1 off. Blink mask. When bits corresponding event causes blink.
Mode
Default
00000000
COMMON REGISTER (MAP REG. PAGE A.28.[15:12]=0010) LED1 SETTING2
REGISTER
Default Operation LED1 when Mbps operation.
Table Common Register (Map Reg. Page a.28.[15:12]=0010) LED1 Setting2 register
A2.30.[15:8] A2.30.[7:0]
Name
Description
mask. When bits corresponding event causes turn mask. When bits one, corresponding event causes turn off.
Mode
Default
00100000 00000000
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AC101L
Register Description
COMMON REGISTER (MAP REG. PAGE A.28.[15:12]=0010) LED2 SETTING1
REGISTER
Table Common Register (Map Reg. Page a.28.[15:12]=0010) LED2 Setting1 register
A2.31.[15:13] A2.31.12 A2.31.[11:9] A2.31.8 A2.31.[7:0]
Name
Reserved Force Reserved Force Blink
Description
Forces LED2 Forces LED2 off. Blink mask. When bits corresponding event causes blink.
Mode
Default
00000000
COMMON REGISTER (MAP REG. PAGE A.28.[15:12]=0011) LED2 SETTING2
REGISTER
Default operation LED2 when operating duplex mode.
Table Common Register (Map Reg. Page a.28.[15:12]=0011) LED2 Setting2 register
A3.29.[15:8] A3.29.[7:0]
Name
Description
mask. When bits corresponding event causes turn mask. When bits corresponding event causes turn off.
Mode
Default
10000000 00000000
COMMON REGISTER (MAP REG. PAGE A.28[.15:12]=0011) LED3 SETTING1
REGISTER
Default operation LED3 BLINK when COL.
Table Common Register (Map Reg. Page a.28[.15:12]=0011) LED3 Setting1 register
Reg.bit
A3.30.[15:13] A3.30.12 A3.30.[11:9] A3.30.8 A3.30.[7:0]
Name
Reserved Force Reserved Force Blink
Description
Forces LED3 Forces LED3 off. Blink mask. When bits corresponding event causes blink.
Mode
Default
0100000
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Common registers
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COMMON REGISTER (MAP REG. PAGE A.28.[15:12]=0011) LED3 SETTING2
REGISTER
Table Common Register (Map Reg. Page a.28.[15:12]=0011) LED3 Setting2 register
A3.31.[15:8] A3.31.[7:0]
Name
Description
mask. When bits corresponding event causes turn mask. When bits corresponding event causes turn off.
Mode
Default
00000000 00000000
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AC101L
4B/5B Code Group
ction 4B/5B Code Group
Table 4B/5B code group
Symbol name
code
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
code
11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101
Description
Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data
Idle control codes
0000 0101 0101 Undefined Undefined 11111 11000 10001 01101 00111 Idle Start-of-stream delimiter, part always pair with symbol. Start-of-stream delimiter, part always pair with symbol. End-of-stream delimiter, part always pair with symbol. End-of-stream delimiter, part always pair with symbol.
Invalid code
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001 Transmit error; used send HALT code group Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code
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Common registers
Preliminary Data Sheet
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AC101L
Read/Write Sequence
Section Read/Write Sequence
Table read/write sequence
read/write sequence
Read Write Pream bits) Start bits) OpCode bits) PHYAD bits) AAAAA AAAAA REGAD bits) RRRRR RRRRR TurnAround bits) Data bits) Idle
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Common registers
Preliminary Data Sheet
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AC101L
Timing Characteristics
ction Timing Char acte ristics
CLOCK TIMING
Table Clock timing
Parameter
XTAL input cycle time XTAL input high/low time XTAL input rise/fall time REF_CLK cycle time (RMII) REF_CLK high/low time (RMII) REF_CLK rise/fall time (RMII)
Symbol
CK_CYCLE CK_HI CK_LO CK_EDGE
Units
RESET TIMING
Table Reset Timing
Parameter
Reset pulse length period with stable XTAL input Activity after hardware reset Reset rise/fall time
Symbol
RESET_LEN RESET_WAIT RESET_WAIT
Units
CK_EDGE
CK_EDGE
XTAL Input
CK_HI CK_LO
Normal activity begins here
CK_CYCLE RESET_EDGE
RESET#
RESET_LEN RESET_EDGE Figure Reset timing RESET_WAIT
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Management Data Interface timing
Preliminary Data Sheet
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MANAGEMENT DATA INTERFACE TIMING
Table Management Interface Timing
Parameter
cycle time high/low rise/fall time MDIO input setup time rising MDIO input hold time from rising MDIO output delay from rising
Symbol
MDC_CYCLE MDC_RISE MDC_FALL MDIO_SETUP MDIO_HOLD MDIO_DELAY
Units
MDC_CYCLE MDC_FALL MDIO_SETUP MDIO (Into AC101L) MDIO_HOLD MDIO_SETUP
MDC_RISE
MDIO_HOLD
MDIO (From AC101L) MDIO_DELAY Figure Management interface timing
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AC101L
Timing Characteristics
100BASE-TX/FX TRANSMIT SYSTEM TIMING
Table 100BASE-X transmit system timing
Parameter
TX_CLK period TX_CLK high period TX_CLK period TXEN TXEN sampled TXEN sampled !TXEN !TXEN sampled !CRS !TXEN sampled !COL propagation delay TXD[3:0], TXEN, TXER setup TXD[3:0], TXEN, TXER hold
Symbol
tCKH tCKL tCSA tCLA tCSD tCLD tTXS tTXH
Conditions
RPTR logic RPTR logic RPTR logic RPTR logic From TXD[3:0] TXOP/N(FXTP/N) From rising edge TX_CLK From rising edge TX_CLK
39.998 18.000 18.000
40.000 20.000 20.000
40.002 22.000 22.000
Units
tCKH TX_CLK tTXS TXEN TXD[3:0] TX_ER TXOP/N
Start Packet tCKL
Packet
tTX_T tTXH
FXTP/N tTCS tTCLA
tTCS tTCLD
Figure 100BASE-TX/FX transmit timing
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100BASE-TX/FX receive system timing
Preliminary Data Sheet
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100BASE-TX/FX RECEIVE SYSTEM TIMING
Table 100BASE-TX/FX receive system timing
Parameter
RX_CLK period RX_CLK high period RX_CLK period /J/K RXDV assert /J/K assert /J/K assert /T/R !RXDV /T/R !CRS /T/R !COL propagation delay RXD[3:0], RXDV, RXER setup RXD[3:0], RXDV, RXER hold
Symbol
tCKH tCKL tRDVA tRCSA tRCLA tRDVD tRCSD tRCLD tRDVA tRXS tRXH
Conditions
RPTR logic RPTR logic RPTR logic RPTR logic From RXIP/N(FXRP/N) RXD[3:0] From rising edge RX_CLK From rising edge RX_CLK
39.998 18.000 18.000
40.000 20.000 20.000
40.002 22.000 22.000
Units
Start tCKH RX_CLK tRDV RXDV tRXS RXD[3:0] RXER RXDV /J/K RXIP/N tRXH Packet tCKL
Packet
tRDV
/T/R
FXRP/N
tRCSA
tRCSD
tRCLA
tRCLD
Figure 100BASE-T receive timing
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Timing Characteristics
10BASE-T TRANSMIT SYSTEM TIMING
Table 10BASE-T transmit system timing
Parameter
TX_CLK period TX_CLK high period TX_CLK period TXEN TXEN sampled TXEN sampled !TXEN !TXEN sampled !CRS !TXEN sampled !COL propagation delay TXD[3:0], TXEN, TXER setup TXD[3:0], TXEN, TXER hold
tCKH tCKL tTCSA tTCLA tTCSD tTCLD tTXS tTXH
Conditions
RPTR logic RPTR logic RPTR logic RPTR logic From TXD[3:0] TXOP/N From rising edge TX_CLK From rising edge TX_CLK
399.98 180.00 180.00
400.00 200.00 200.00
400.02 220.00 220.00
Units
tCKH TX_CLK tTXS TXEN TXD[3:0] TX_ER TXOP/N
Start Packet tCKL
Packet
tTX_T tTXH
tTCS tTCLA
tTCS tTCLD
Figure 10BASE-T transmit timing
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10BASE-T receive system timing
Preliminary Data Sheet
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10BASE-T RECEIVE SYSTEM TIMING
Table 10BASE-T receive system timing
Parameter
RX_CLK period RX_CLK high period RX_CLK period RXDV !RXDV !CRS !COL propagation delay RXD[3:0], RXDV, RXER setup RXD[3:0], RXDV, RXER hold
Symbol
tCKH tCKL tRDVA tRCSA tRCLA tRDVD tRCSD tRCLD tRDVA tRXS tRXH
Conditions
RPTR logic RPTR logic RPTR logic RPTR logic From RXIP/N RXD[3:0] From rising edge RX_CLK From rising edge RX_CLK
399.98 180.00 180.00
400.00 200.00 200.00
400.02 220.00 220.00
Units
tCKH RX_CLK tRDV RXDV tRXS RXD[3:0] RXER RXDV RXIP/N tRCSA tRCLA
Start Packet tCKL
Packet
tRDV tRXH
tRCSD
tRCLD
Figure 10BASE-T Receive Timing
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Timing Characteristics
RMII TRANSMIT TIMING
Table RMII transmit timing
Parameter
REFCLK period REFCLK high period REFCLK period propagation delay TXD[1:0], TXEN setup TXD[1:0], TXEN hold
Symbol
tCKH tCKL tTXS tTXH
Conditions
From TXD[1:0] TXOP/N(FXTP/N) From rising edge REFCLK From rising edge REFCLK
19.999 9.000 9.000
20.000 10.000 10.000
20.001 11.000 11.000
Units
tCKH REFCLK tTXS TXEN TXD[1:0] TXOP/N
Start Packet tCKL
Packet
tTX_T tTXH
FXTP/N
TXOP/N
Figure RMII transmit timing
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AC101L
RMII receive timing
Preliminary Data Sheet
06/06/02
RMII RECEIVE TIMING
Table RMII receive timing
Parameter
REFCLK period REFCLK high period REFCLK period propagation delay RXD[1:0], CRS_DV, RXER setup RXD[1:0], CRS_DV, RXER hold
Symbol
tCKH tCKL tRDVA tRXS tRXH
Conditions
From RXIP/N(FXRP/N) RXD[1:0] From rising edge REFCLK From rising edge REFCLK
19.999 9.000 9.000
20.000 10.000 10.000
20.001 11.000 11.000
Units
tCKH REFCLK tRDV CRS_DV tRXS RXD[1:0] RXER /J/K RXIP/N
Start Packet tCKL
Packet
tRDV tRXH
/T/R
FXRP/N RXIP/N
Figure RMII receive timing
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Preliminary Data Sheet
06/06/02
AC101L
Timing Characteristics
COPPER APPLICATION TERMINATION
49.9_1/16W_1% 49.9_1/16W_1% 49.9_1/16W_1% 49.9_1/16W_1%
Auto MDI/MDIX
RJ45
AC101L
4578
Auto MDI/MDIX Magnetics: BEL: S558-5999-W2; PULSE: H1102; HALO: TG110-S050N2
75_1/16W_5% 75_1/16W_5%
75_1/16W_5% 75_1/16W_5%
1000PF_2KV
Figure application
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AC101L
Copper application termination
Preliminary Data Sheet
06/06/02
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Preliminary Data Sheet
06/06/02
AC101L
Electrical Characteristics
ction ctrica Char acte ristics
NOTE-The following electrical characteristics design goals rather than characterized numbers.
ABSOLUTE MAXIMUM RATINGS
Table Absolute maximum ratings
Parameter
Supply voltage Input voltage Storage temperature Electrostatic discharge
Symbol
VESD
GND-0.3 GND-0.3
+125 1000
Units
Table Current requirement operation with disabled
Current (mA) Operational mode
Traffic Mbps Power-down Standby
@VCC
@VCC 2.625
Table Current requirement operation with disabled
Current (mA) Operational mode
Traffic Mbps Power-down Standby
@VCC
@VCC 2.625
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AC101L
Recommended operating conditions
Preliminary Data Sheet
06/06/02
RECOMMENDED OPERATING CONDITIONS
Table Recommended operating conditions
Parameter
Ambient operating temperature AC101L Bias voltage Common mode input voltage Common mode input voltage Differential input voltage Differential output voltage Input current Input voltage high Input voltage high Input voltage
Symbol
VBIAS VICM VICM VIDIFF VODIFF
Pins
RBIAD Digital inputs with pull-up resistor digital input digital inputs
Operating mode
100BASE-TX 100BASE-FX 100BASE-FX 100BASE-FX mode 100BASE-FX 100BASE-FX Driving load magnetic module Driving load magnetic module
1.18
1.30
Units
Input voltage Input voltage Output voltage high Output voltage high Output voltage high Output voltage Output voltage Output voltage Supply voltage AC101L Supply voltage AC101L
digital input digital output digital output digital output digital output VCC33IN VCC, VCCPLL, VCC25OUT
VCC-1.5 3.135 2.375
VCC+1.5 3.465 2.625
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Preliminary Data Sheet
06/06/02
AC101L
Fiber Application Termination
cati
BLM11A601S
Z=50 Z=50 Z=50
Z=50 Z=50 Z=50 Z=50 RDSD
SD/FXEN
Z=50 Z=50
RxVcc RxVee TxVcc TxVee
AC101L
BLM11A601S
0.01
0.01
HFBR-5903
Figure application
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AC101L
Recommended operating conditions
Preliminary Data Sheet
06/06/02
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Preliminary Data Sheet
06/06/02
AC101L
Power Ground Filtering
Grou
RXD0/PHYAD4 RXD1/PHYAD3 RXD2/PHYAD2 RXD3/PHYAD1 MDIO RST_L VCC33IN GND8 GND7
Place CAPs close possible each power AC101L
0.01
0.01
TXD2 TXD3 CRS/REPEATER GND3 INTR/PHYAD0 LED0/BURNIN_L LED1/SPD100 LED2/DUPLEX LED3/ANEN PDOWN
0.01
GND1 RXDV/CRSDV RXC/RMII_mode AC101L RXER/ISOLATE GND2 TQFP_7x7mm TXER TXEN TXD0 TXD1
VCC25OUT GND6 VCCPLL RBIAD GND5 GND4 SD/FXEN
VCCPLL
0.01
0.1µ
0.01
Figure Power ground filtering
Document
AC101L-DS02-R
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AC101L
Recommended operating conditions
Preliminary Data Sheet
06/06/02
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Preliminary Data Sheet
06/06/02
AC101L
Mechanical Information
echa
Figure Quad Flat Pack outline
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AC101L
Recommended operating conditions
Preliminary Data Sheet
06/06/02
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Preliminary Data Sheet
06/06/02
AC101L
Thermal Parameters
Section Para mete
Table Thermal parameters
Airflow (feet minute)
ThetaJA (°C/W)
53.9
51.2
24.7
48.6
47.5
ThetaJC (°C/W) maximum junction temperature
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AC101L
Recommended operating conditions
Preliminary Data Sheet
06/06/02
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Preliminary Data Sheet
06/06/02
AC101L
Ordering Information
Part number
AC101LKQT AC101LIQT
Package
48TQFP 48TQFP
Ambient temperature
+70°C -40°C +85°C
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AC101L
Preliminary Data Sheet
06/06/02
Altima Communications, Inc.
Wholly Owned Subsidiary Broadcom Corporation
16215 Alton Parkway P.O. 57013 Irvine, California 92619-7013 Phone: 949-450-8700 Fax: 949-450-8710
Broadcom® Corporation reserves right make changes without further notice products data herein improve reliability, function, design. Information furnished Broadcom Corporation believed accurate reliable. However, Broadcom Corporation does assume liability arising application this information, application product circuit described herein, neither does convey license under patent rights rights others.
ment 101L S02-

Ultra Power 10/100 Ethernet Transceiver with Auto-MDIX DESCRIPTIO

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