268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM DESCRIPTION

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM DESCRIPTION

Datasheet Thumbnail

Top Searches for this datasheet

268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
DESCRIPTION
MH4S64CBMD 4194304-word 64-bit Synchronous DRAM module. This consists sixteen industry standard 2Mx8 Synchronous DRAMs TSOP industory standard EEPROM TSSOP. mounting TSOP card edge Dual Inline package provides application where high densities large quantities memory required. This socket type memory modules, suitable easy interchange addition modules.
85pin
1pin
94pin 95pin
10pin 11pin
FEATURES
Frequency -10,-10B -12,-12B -15,-15B 100MHz 83MHz 67MHz Access Time
(Component SDRAM)
8ns(CL=3) 8ns(CL=3)
Back side
9ns(CL=3)
Front side
Utilizes industry standard Synchronous DRAMs TSOP industry standard EEPROM TSSOP 168-pin (84-pin dual in-line package)
124pin 125pin
40pin 41pin
single 3.3V±0.3V power supply Clock frequency 100MHz/83MHz/67MHz Fully synchronous operation referenced clock rising edge Dual bank operation controlled BA(Bank Address) /CAS latency- 1/2/3(programmable) Burst length- 1/2/4/8(programmable) Burst type- sequential interleave(programmable) Column access random Auto precharge bank precharge controlled Auto refresh Self refresh 4096 refresh cycle /64ms LVTTL Interface
168pin 84pin
APPLICATION
main memory graphic memory computer systems
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
NAME DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 /WE0 DQMB0 DQMB1
NAME DQMB2 DQMB3 DQ16 DQ17 DQ18 DQ19 DQ20 CKE1 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
NAME DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 /CAS DQMB4 DQMB5 /RAS
NAME CKE0 DQMB6 DQMB7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
Connection
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM Block Diagram
DQMB0
DQMB4
DQMB1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
D4,D12,D13 4SDRAMs D0,D1,D5,D8,D9 4SDRAMs 4SDRAMs D2,D3,D10,D11 4SDRAMs D6,D7,D14,D15
DQMB2
DQMB6
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 /RAS /CAS BA,A<10:0>
CK,DQ=10
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB7
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
CKE1 CKE0
SERIAL
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
Serial Presence Detect Table
Byte Function described Defines bytes written into serial memory module mfgr Total bytes memory device Fundamental memory type Addresses this assembly Column Addresses this assembly Module Banks this assembly Data Width this assembly. Data Width continuation Voltage interface standard this assembly SDRAM Cycletime Max. Supported Latency (CL). Cycle time CL=3 SDRAM Access from Clock CL=3 DIMM Configuration type (Non-parity,Parity,ECC) Refresh Rate/Type SDRAM width,Primary DRAM Error Checking SDRAM data width
Minimum Clock Delay,Back Back Random Column Addresses
enrty data Bytes SDRAM A0-A10 A0-A8 2BANK LVTTL 10ns 12ns 15ns
Non-PARITY
DATA(hex)
self refresh(15.625uS) 1/2/4/8 2bank CL=1/2/3 non-buffered,non-registered Precharge All,Auto precharge 15ns 15ns 20ns 9.5ns 12ns 30ns 30ns 30ns 27ns 27ns 30ns 30ns 30ns 40ns 20ns 24ns 30ns
Burst Lengths Supported Banks Each SDRAM device CAS# Latency Latency Write Latency SDRAM Module Attributes SDRAM Device Attributes:General SDRAM Cycle time(2nd highest latency) Cycle time CL=2
SDRAM Access form Clock(2nd highest latency) CL=2
SDRAM Cycle time(3rd highest latency) Cycle time CL=1
SDRAM Access form Clock(3rd highest latency) CL=1
Precharge Active Minimum
Active Active Min.
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
Serial Presence Detect Table
Delay Active Precharge 32-61 Density each bank module Superset Information (may used future) Revision Checksum bytes 0-62 30ns 30ns 30ns 60ns 70ns 80ns 16MByte option Check Check Check 64-71 Manufactures Jedec code JEP-108E Manufacturing location MITSUBISHI Miyoshi,Japan Tajima,Japan NC,USA Germany 73-90 Manufactures Part Number MH4S64CBMD-10 MH4S64CBMD-12 MH4S64CBMD-15 MH4S64CBMD-10B MH4S64CBMD-12B MH4S64CBMD-15B 91-92 93-94 95-98 99-125 128+ Revision Code Manufacturing date Assembly Serial Number Manufacture Specific Data Intetl specification frequency Intel specification CAS# Latency support Unused storage locations revision year/week code serial number option 66MHz CL=3: 04H, CL=2/3: open 1CFFFFFFFFFFFFFF rrrr yyww ssssssss
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
FUNCTION
(CK0 CK3) Input Master Clock:All other inputs referenced rising edge Clock Enable:CKE controls internal clock.When low,internal clock following cycle ceased. also used select auto self refresh. After self refresh mode started, becomes asynchronous input.Self refresh maintained long low. Chip Select: When high,any command means Operation. Combination /RAS,/CAS,/WE defines basic commands. A0-10 specify Row/Column Address conjunction with BA.The Address specified A0-10.The Column Address specified A0-8.A10 also used indicate precharge option.When high read write command, auto precharge performed. When high precharge command, both banks precharged. Bank Address:BA simply BA.BA specifies bank which command applied.BA must with ACT,PRE,READ,WRITE commands
CKE0,1
Input
(/S0 /S3) /RAS,/CAS,/WE
Input Input
A0-10
Input
Input
DQ0-63
Input/Output Data Data referenced rising edge Input Mask/Output Disable:When DQMB high burst write.Din current cycle masked.When DQMB high burst read,Dout disabled next cycle.
DQMB0-7
Vdd,Vss SA0-3
Power Supply Power Supply memory mounted module. Input Output Input Serial clock serial Serial data serial Address input serial
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
BASIC FUNCTIONS
MH4S64CBMD provides basic read write, bank(row)precharge,and auto self refresh. Each command defined control signals /RAS,/CAS rising edge. addition signals,/S,CKE used chip select,refresh option,and precharge option,respectively. know detailed definition commands please command truth table.
/RAS /CAS
Chip Select L=select, H=deselect Command Command Command Refresh Option @refresh command Precharge Option @precharge read/write command define basic commands
Activate(ACT) [/RAS /CAS command activates idle bank indicated Read(READ) [/RAS =H,/CAS READ command starts burst read from active bank indicated BA.First output data appears after /CAS latency. When this command,the bank deactivated after burst read(auto-precharge,READA). Write(WRITE) [/RAS /CAS WRITE command starts burst write active bank indicated Total data length written burst length. When this command, bank deactivated after burst write(auto-precharge,WRITEA). Precharge(PRE) [/RAS /CAS =H,/WE command deactivates active bank indicated This command also terminates burst read write operation. When this command, both banks deactivated(precharge all, PREA). Auto-Refresh(REFA) [/RAS =/CAS =CKE PEFA command starts auto-refresh cycle. Refresh address including bank address generated internally. After this command, banks precharged automatically.
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
COMMAND TRUTH TABLE
COMMAND Deselect Operation Adress Entry Bank Activate Single Bank Precharge Precharge Bank Column Address Entry Write Column Address Entry Write with AutoPrecharge Column Address Entry Read Column Address Entry Read with Auto Precharge Auto-Refresh Self-Refresh Entry Self-Refresh Exit Burst Terminate Mode Register MNEMONIC DESEL PREA WRITE /RAS /CAS A0-9
WRITEA
READ
READA REFA REFS REFSX TERM
=High Level, Level, Valid, Don't Care, cycle number NOTE: 1.A7-9 A0-6 Mode Address
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE
Current State IDLE ACTIVE READ /RAS /CAS BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 Address Command DESEL TBST PRE/PREA REFA DESEL TBST READ/READA WRITE/ WRITEA PRE/PREA REFA DESEL TBST ILLEGAL*2 Bank Active,Latch NOP*4 Auto-Refresh*5 Mode Register Set*5 Begin Read,Latch Determine Auto-Precharge Begin Write,Latch Determine Auto-Precharge Bank Active/ILLEGAL*2 Precharge/Precharge ILLEGAL ILLEGAL NOP(Continue Burst END) NOP(Continue Burst END) Terminate Burst Terminate Burst,Latch READ/READA Begin Read,Determine Auto-Precharge*3 Terminate Burst,Latch BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add WRITE/WRITEA Begin Write,Determine AutoPrecharge*3 PRE/PREA REFA Bank Active/ILLEGAL*2 Terminate Burst,Precharge ILLEGAL ILLEGAL Action
READ/WRITE ILLEGAL*2
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State WRITE /RAS /CAS Address BA,CA,A10 Command DESEL TBST Action NOP(Continue Burst END) NOP(Continue Burst END) Terminate Burst
Terminate Burst,Latch READ/READA Begin Read,Determine AutoPrecharge*3 Terminate Burst,Latch Begin Write,Determine AutoPrecharge*3 Bank Active/ILLEGAL*2 Terminate Burst,Precharge ILLEGAL ILLEGAL NOP(Continue Burst END) NOP(Continue Burst END) ILLEGAL ILLEGAL ILLEGAL Bank Active/ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP(Continue Burst END) NOP(Continue Burst END) ILLEGAL ILLEGAL ILLEGAL Bank Active/ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
READ with AUTO PRECHARGE WRITE with AUTO PRECHARGE
BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add
WRITE/ WRITEA PRE/PREA REFA DESEL TBST READ/READA WRITE/ WRITEA PRE/PREA REFA DESEL TBST READ/READA WRITE/ WRITEA PRE/PREA REFA
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State CHARGING ACTIVATING WRITE RECOVERING /RAS /CAS BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add Address Command DESEL TBST PRE/PREA REFA DESEL TBST PRE/PREA REFA DESEL TBST PRE/PREA REFA Action NOP(Idle after tRP) NOP(Idle after tRP) ILLEGAL*2 ILLEGAL*2 NOP*4(Idle after tRP) ILLEGAL ILLEGAL NOP(Row Active after tRCD NOP(Row Active after tRCD ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
READ/WRITE ILLEGAL*2
READ/WRITE ILLEGAL*2
READ/WRITE ILLEGAL*2
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State REFRESHING MODE REGISTER SETTING /RAS /CAS BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add Address Command DESEL TBST Action NOP(Idle after tRC) NOP(Idle after tRC) ILLEGAL
READ/WRITE ILLEGAL PRE/PREA REFA DESEL TBST ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP(Idle after tRSC) NOP(Idle after tRSC) ILLEGAL
READ/WRITE ILLEGAL PRE/PREA REFA ILLEGAL ILLEGAL ILLEGAL ILLEGAL
ABBREVIATIONS: Hige Level, Level, Don't Care Bank Address, Address, Column Address, Operation NOTES: entries assume that High during preceding clock cycle current clock cycle. ILLEGAL bank specified state; function legal bank indicated depending state that bank. Must satisfy contention, turn around, write recovery requirements. bank precharging idle state.May precharge bank indicated ILLEGAL bank idle. ILLEGAL Device operation date-integrity guaranteed.
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE
Current State SELF REFRESH*1 POWER DOWN BANKS IDLE*2 STATE other than listed above /RAS /CAS INVALID Exit Self-Refresh(Idle after tRC) Exit Self-Refresh(Idle after tRC) ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Self-Refresh) INVALID Exit Power Down Idle NOP(Maintain Self-Refresh) Refer Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer Current State Power Down Refer Function Truth Table Begin Suspend Next Cycle*3 Exit Suspend Next Cycle*3 Maintain Suspend Action
ABBREVIATIONS: High Level, Level, Don't Care NOTES: High transition will re-enable other inputs asynchronously. minimum setup time must satisfied before command other than EXIT. Power-Down Self-Refresh entered only form banks idle State. Must legal command.
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
SIMPLIFIED STATE DIAGRAM
SELF REFRESH
REFS REFSX
MODE REGISTER
REFA
IDLE
AUTO REFRESH
CKEL
SUSPEND
CKEL CKEH
CKEH
POWER DOWN
ACTIVE
WRITE WRITEA READA READ WRITE READ
CKEL
CKEL
WRITE SUSPEND
WRITE
CKEH
READ
CKEH
READ SUSPEND
WRITEA WRITEA CKEL READA
READA
CKEL
WRITEA SUSPEND
WRITEA
CKEH
READA
CKEH
READA SUSPEND
POWER APPLIED
POWER
CHARGE Automatic Sequence Command Sequence
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
POWER SEQUENCE
Before starting normal operation, following power sequence necessary prevent SDRAM from damaged malfunctioning. Apply power start clock. Attempt maintain high, DQMB0-7 high condition inputs. Maintain stable power, stable cock, input conditions minimum Issue precharge commands banks. (PRE PREA) After banks become idle state (after tRP), issue more auto-refresh commands. Issue mode register command initialize mode register. After these sequence, SDRAM idle state ready normal operation.
MODE REGISTER
Burst Length, Burst Type /CAS Latency programmed setting mode register(MRS). mode register stores these date until next command, which issue when both banks idle state. After tRSC from command, SDRAM ready command.
/RAS /CAS LTMODE SEQUENTIAL INTERLEAVED
LATENCY MODE
/CAS LATENCY
BURST LENGTH
BURST TYPE
R:Reserved Future
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
Command Address /CAS Latency
Read Write
Burst Length Burst Type
Burst Length
Initial Address Sequential
Column Addressing Interleaved
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
OPERATION DESCRIPTION
BANK ACTIVATE SDRAM independent banks. Each bank activated command with bank address(BA). indicated address A10-0. minimum activation interval between bank other bank tRRD. PRECHARGE command deactivates indicated When both banks active, precharge command(PREA,PRE A10=H) available deactivate them same time. After from precharge, command issued.
Bank Activation Precharge (BL=4, CL=3)
Command A0-9
tRRD tRCD READ tRAS
Precharge
READ After tRCD from bank activation, READ command issued. output date available after /CAS Latency from READ, followed (BL-1) consecutive date when Burst Length start address specified A8-0, address sequence burst data defined Burst Type. READ command applied active bank, precharge time(tRP) hidden behind continuous output data(in case BL=8) interleaving dual banks. When high READ command, auto-precharge(READA) performed. command (READ, WRITE, PRE, ACT) same bank inhibited till internal precharge complete. internal precharge start timing depends /CAD Latency. next command issued after from internal precharge timing.
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
Dual Bank Interleaving READ (BL=4, CL=3)
Command A0-9
/CAS latency tRCD READ READ
Burst Length
READ with Auto-Precharge (BL=4, CL=3)
Command A0-9
tRCD READ
Internal precharge begins
READ Auto-Precharge Timing (BL=4)
Command CL=4 CL=3 CL=2
READ
Internal Precharge Start Timing MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
WRITE After tRCD from bank activation, WRITE command issued. input data same cycle WRITE. Following(BL-1) data written into RAM, when Burst Length start address specified A8-0, address sequence burst data defined Burst Type. WRITE command applied active bank, precharge time(tRP) hidden behind continuous input data case BL=8) interleaving dual banks. From last input data command, write recovery time (tWR) required. When high WRITE command, auto-precharge(WRITEA) performed. command(READ, WRITE, PRE, ACT) same bank inhibited till internal precharge complete. internal precharge begins after last input data cycle. next command issued after from internal precharge timing.
Dual Bank Interleaving WRITE (BL=4)
Command A0-9
tRCD Write tRCD Write
Burst Length
WRITE with Auto-Precharge (BL=4)
Command A0-9
tRCD Write
Internal precharge begins
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
BURST INTERRUPTION Read Interrupted Read Burst read option interrupted read same other bank. MH4S64CTJ allows random column access. READ READ interval minimum Read Interrupted Read (BL=4, CL=3)
Command A0-9
READ READ READ Qai0 Qaj0 READ Qaj1 Qbk0 Qbk1 Qbk2 Qal0 Qal1 Qal2 Qal3
Read Interrupted Write Burst read operation interrupted write same other bank. Random column access allowed. this case, should controlled adequately using DQMB0-7 prevent contention. output disabled automatically cycle after WRITE assertion. Read Interrupted Write (BL=4, CL=3)
Command A0-9 DQMB0-7
Qai0 Daj0 Daj1 Daj2 Daj3 READ Write
control
Write control
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
Read Interrupted Precharge Burst read operation interrupted precharge same other bank. Read interval minimum command disables data output, depending /CAS Latency. figure below shows examples, when dataout terminated. Read Interrupted Precharge (BL=4)
Command
READ
CL=4
Command
READ
Command
READ
CL=3
Command
READ
Command
READ
CL=2
Command
READ
Comman
Comman
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
Read Interrupted Burst Terminate Similarly precharge, burst terminate command interrupt burst read operation disable data output. READ TERM interval minimum figure below shows examples, when dataout terminated. Read Interrupted Burst Terminate (BL=4)
Command Command
READ
TERM
READ
TERM
CL=3
Command
READ TERM
Command Command
READ
TERM
READ
TERM
CL=2
Command
READ TERM
Comman
TERM
TERM
Comman
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
Write Interrupted Write Burst write operation interrupted write same other bank. Random column access allowed. WRITE WRITE interval minimum Write Interrupted Write (BL=4)
Command A0-9
Write Write Dai0 Daj0 Daj1 Write Write Dal1 Dal2 Dal3
Dbk0 Dbk1 Dbk2 Dal0
Write Interrupted Read Burst write operation interrupted read same other bank. Random column access allowed. WRITE READ interval minimum input data interrupting READ cycle "don't care". Write Interrupted Read (BL=4, CL=3)
Command A0-9 DQMB0-7
Dai0 Qaj0 Qaj1 Dak0 Dak1 Qbl0 Write READ Write READ
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
Write Interrupted Precharge Burst write operation interrupted precharge same bank. Random column access allowed. Because write recovery time(tWR) required between last input data next PRE, data should masked with DQMB0-7 shown below. Write Interrupted Precharge (BL=4)
Command A0-9 DQMB0-7
Dai0 Dai1 Write
This data should masked satisfy requirement.
Write Interrupted Burst Terminate Burst terminate command terminate burst write operation. this case, write recovery time required bank remains active. figure below shows case words data written. Random column access allowed. WRITE TERM interval minimum Write Interrupted Burst Terminate (BL=4)
Command A0-9 DQMB0-7
Dai0 Dai1 Dai2 Write TERM
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
AUTO REFRESH Single cycle auto-refresh initiated with REFA(/CS=/RAS=/CAS=L, /WE=/CKE=H) command. refresh address generated internally. 4096 REFA cycle within 64ms refresh 16Mbit memory cells. auto-refresh performed each bank alternately(ping-pong refresh). Before performing auto-refresh, both banks must idle state. Additional commands must supplied device before from REFA command.
Auto-Refresh
DESLECT /RAS /CAS A0-10
minimum
Auto Refresh Bank
Auto Refresh Bank
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
SELF REFRESH Self-refresh mode entered issuing REFS command (/CS=/RAS=/CAS=L, /WE=H, CKE=L). Once self-refresh initiated, maintained kept low.During self-refresh mode, asynchronous only enabled input (but asynchronous), other inputs including disabled ignored, power consumption synchronous inputs saved. exit self-refresh, supplying stable inputs, asserting DESEL command then asserting CKE(REFSX). After from REFSX both banks idle state command issued after tRC, DESEL commands must asserted till then. Self-Refresh
Stable
/RAS /CAS
command
A0-10
Self Refresh Entry
Self Refresh Exit
minimum recovery
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
SUSPEND controls internal following cycle. Figure below shows works. negating CKE, next internal suspended. purpose suspend power down, output suspend input suspend. synchronous input except during self-refresh mode. suspend performed either when banks active idle, command following cycle ignored.
(ext.CLK)
int.CLK
Power Down
Command
Standby Power Down
Command
Active Power Down
Suspend
Command
Write READ
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
CONTROL DQMB0-7 dual function signal defined data mask writes output disable reads. During writes, DQMB0-7 masks input data word word. DQMB0-7 write mask latency During reads, DQMB0-7 forces output Hi-Z word word. DQMB0-7 output Hi-Z latency Function
Command DQMB0-7
Write READ
masked DQM=H
disabled DQM=H
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
ABSOLUTE MAXIMUM RATINGS
Symbol Topr Tstg Parameter Supply Voltage Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature Ta=25°C Condition with respect with respect with respect Ratings -0.5 -0.5 -0.5 Unit
RECOMMENDED OPERATING CONDITION
(Ta=0 70°C, unless otherwise noted) Symbol Parameter Min. Supply Voltage Supply Voltage High-Level Input Voltage inputs Low-Level Input Voltage inputs -0.3 Limits Typ. Max. Vdd+0.3 Unit
CAPACITANCE
(Ta=0 70°C, 0.3V, unless otherwise noted) Symbol CI(A) CI(C) CI(K) CI/O Parameter Input Capacitance, address Input Capacitance, control Input Capacitance, Input Capacitance, Test Condition f=1MHz Vi=25mVrms Limits(max.) Unit
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
AVERAGE SUPPLY CURRENT from
(Ta=0 ~70°C, 0.3V, unless otherwise noted)
Symbol Parameter Test Condition tRC=min.tCLK=min, BL=1, CL=3 tRC=min.tCLK=min, BL=1, CL=3 both banks idle, tCLK=min, CKE=H both banks idle, tCLK=min, CKE=L Limits(max)
-10(B) -12(B) -15(B)
Unit
bank Icc1s* operating current, single(discrete) operating current, dual bank Icc1d* (discrete) Icc2h standby current, CKE=H Icc2l standby current, CKE=L Icc3 active standby current Icc4* burst current Icc5 auto-refresh current Icc6 self-refresh current
1120 both banks active, tCLK=min, CKE=H tCLK=min, BL=4, CL=3, both banks active(discerte) tRC=min, tCLK=min 1040 <0.2V
*One bank module operating,the other bank module standby,CKE=H.
OPERATING CONDITIONS CHARACTERISTICS
(Ta=0 70°C, 0.3V, unless otherwise noted)
Symbol VOH(DC) VOL(DC) VOH(AC VOL(AC) Parameter High-Level Output Voltage(DC) Low-Level Output Voltage(DC) Off-stare Output Current High-Level Output Voltage(AC) Input Current Low-Level Output Voltage(AC) Off-stare Output Current Input Current Limits Min. Max. IOH=-2mA IOL=2mA floating CL=50pF, VO=0 IOH=-2mAIOL=2mA -160 VIH=0 Vdd+0.3V CL=50pF, floating VO=0 VIH=0 Vdd+0.3V Test Condition Unit
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
TIMING REQUIREMENTS (SDRAM Component)
(Ta=0 70°C, 0.3V, unless otherwise noted) Input Pulse Levels: 0.8V 2.0V Input Timing Measurement Level: 1.4V Limits Unit -10,-10B -12,-12B -15,-15B Min. Max. Min. Max. Min. Max. 10000 10000 10000 65.6 65.6 65.6
Symbol Parameter tCLK tRCD tRAS tRRD tRSC tPDE tREF cycle time CL=1 CL=2 CL=3
High pulse width pilse width Transition time Input Setup time(all inputs) Input Hold time(all inputs) cycle time Column Delay Active time Precharge time Write Recovery time Deley time Mode Register Cycle time Power Down Exit time Refresh Interval time
1.4V
timing referenced input
Signal
1.4V
signal crossing through 1.4V.
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
SWITCHING CHARACTERISTICS (SDRAM Component)
(Ta=0 70°C, 0.3V, unless otherwise noted) Symbol Parameter CL=1 CL=2 CL=3 Limits -12,-12B Min. Max.
tOLZ tOHZ
Access time from Output Hold time from Delay time, output impedance from Delay time, output high impedance from
-10,-10B Min. Max.
-15,-15B Unit Min. Max.
Output Load Condition
VTT=1.4V
1.4V
VOUT 50pF Output Timing Measurement Reference Point
1.4V
1.4V
tOHZ
1.4V
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
WRITE CYCLE (single bank)
BL=4
tRAS
/RAS
tRCD
/CAS
DQMB A0-9
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
WRITE CYCLE (dual bank)
BL=4
tRAS tRRD tRAS
/RAS
tRCD tRCD
/CAS
DQMB A0-9
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
READ CYCLE (single bank)
BL=4, CL=3
tRAS
/RAS
tRCD
/CAS
DQMB A0-9
tRAC
tCAC
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
READ CYCLE (dual bank)
BL=4, CL=3
tRAS tRRD tRAS
/RAS
tRCD tRCD
/CAS
DQMB A0-9
tCAC tRAC tRAC
tCAC
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
WRITE READ (single bank)
BL=4, CL=3
tRAS
/RAS
tRCD
/CAS
DQMB A0-9
tCAC
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
WRITE READ (dual bank)
BL=4, CL=3
tRAS tRRD tRAS
/RAS
tRCD tRCD
/CAS
DQMB A0-9
tCAC
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
READ WRITE (single bank)
BL=4, CL=3
tRAS
/RAS
tRCD
/CAS
output diable
DQMB A0-9
tCAC tRAC
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
READ WRITE (dual bank)
BL=4, CL=3
tRAS tRRD tRAS
/RAS
tRCD tRCD
/CAS
output disable
DQMB A0-9
tCAC tRAC
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
WRITE with AUTO-PRECHARGE
BL=4
/RAS
tRCD
/CAS
DQMB A0-9
internal precharge starts this timing depends
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
READ with AUTO-PRECHARGE
BL=4, CL=3
/RAS
tRCD
/CAS
DQMB A0-9
tCAC tRAC internal precharge starts @CL=3, BL=4 this timing depends
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
AUTO-REFRESH
/RAS
/CAS
DQMB A0-9
bank active, must precharged
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
SELF-REFRESH ENTRY
/RAS
/CAS
DQMB A0-9
bank active, must precharged
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
SELF-REFRESH EXIT
DESEL
/RAS
/CAS
DQMB A0-9
internal re-start
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
MODE REGISTER
BL=4, CL=3
tRSC tRCD
/RAS
/CAS
DQMB A0-9
mode
tCAC tRAC bank active, must precharged
MIT-DS-0113-1.1
MITSUBISHI ELECTRIC
25.Mar.1997
268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM
OUTLINE
3.9MAX
2-R2±0.13
1±0.13
1.27±0.1 17.78±0.13 17.78±0.13 3±0.13 2±0.13 29.21±0.13
1.27±0.1 133.35±0.13 127.35±0.13 6.35±0.13 24.495±0.13 9x1.27=11.43±0.2 29x1.27=36.83±0.2 42.18±0.13 6.35±0.1 43x1.27=54.61±0.2
3±0.13 1±0.13
MIT-DS-0113-1.1
8.89±0.13
MITSUBISHI ELECTRIC
25.Mar.1997

268435456-BIT (4194304-WORD 64-BIT)SynchronousDRAM DESCRIPTION

Top Searches for this datasheet

Other recent searches