HYPER PAGE MODE 75497472-BIT 2097152-WORD 36-BIT DYNAMIC CONFIGUR
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MH2M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 75497472-BIT 2097152-WORD 36-BIT DYNAMIC
CONFIGURATION (TOP VIEW)
DESCRIPTION
MH2M365CXJ/CNXJ 2097152-word 36-bits dynamic RAM. This consists four industry standard dynamic RAMs industry dyanmic RAMs SOJ. mounting single in-line package provides application where high densities large quantities memory required. This socket-type memory module,suitable easy interchange addition modules.
[Double side]
1.Vss 2.DQ0 3.DQ16 4.DQ1 5.DQ17 6.DQ2
37.MP1 38.MP3 39.Vss 40.CAS0 41.CAS2 42.CAS3 43.CAS1 44.RAS0 45.RAS1 46.NC 47.W 48.NC 49.DQ8 50.DQ24 51.DQ9 52.DQ25 53.DQ10 54.DQ26 55.DQ11
FEATURES
Type name MH2M365CXJ/CNXJ-5 MH2M365CXJ/CNXJ-6 MH2M365CXJ/CNXJ-7 access access time time (max.ns) (max.ns) Address Cycle Power access dissipatime time tion (max.ns) (min.ns) (typ.mW)
7.DQ18 8.DQ3 11.NC 10.Vcc 11.NC 12.A0 13.A1 14.A2 15.A3
2137 1767 1537
72pin single in-line package Single 5.0V supply stand-by power dissipation 33mW (Max) operating power dissipation MH2M365CXJ/CNXJ- MH2M365CXJ/CNXJ- MH2M365CXJ/CNXJ-
16.A4 17.A5
CMOS lnput level 2.69W (Max) 2.22W (Max) 1.92W (Max)
18.A6 19.NC 20.DQ4 21.DQ20 22.DQ5
Hyper-page mode RAS-only refresh before refresh, Hidden refresh capabilities inputs output directly compatible 1024 refresh cycles every 16.4ms
23.DQ21 24.DQ6 25.DQ22 26.DQ7 27.DQ23 28.A7 29.NC
APPLICATION
Main memory unit computers, Microcomputer memory, Refresh memory
30.Vcc 31.A8 32.A9 33.RAS3 34.RAS2 35.MP2 36.MP0
56.DQ27 57.DQ12 58.DQ28 59.Vcc 60.DQ29 61.DQ13 62.DQ30 63.DQ14 64.DQ31 65.DQ15 66.NC 67.PD1 68.PD2 69.PD3 70.PD4 71.NC 72.Vss
Outline 72N9J-C
CONNECTION
MIT-DS-0083-1.2
MITSUBISHI ELECTRIC
21/Feb./1997
MH2M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 75497472-BIT 2097152-WORD 36-BIT DYNAMIC FUNCTION
addition normal read, write, number other functions, e.g., hyper page mode, only refresh, input conditions each shown Table
Table Input conditions each mode
Inputs Operation Read Early write RAS-only refresh Hidden refresh before refresh Standby address Column address Input/Output Input Output
Note active, nonactive, don' care, valid, Invalid,APD applied, open
BLOCK DIAGRAM
RAS1 RAS3
LCAS
UCAS
LCAS
UCAS
M5M418165CJ
LDATA UDATA
M5M44505CJ
M5M418165CJ
LDATA UDATA
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
LDATA UDATA LDATA UDATA
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
M5M418165CJ
LCAS UCAS
M5M44505CJ
M5M418165CJ
LCAS UCAS
RAS0
CAS0
CAS1
RAS2
CAS2
CAS3
MIT-DS-0083-1.2
MITSUBISHI ELECTRIC
21/Feb./1997
MH2M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 75497472-BIT 2097152-WORD 36-BIT DYNAMIC ABSOLUTE MAXIMUM RATINGS
Symbol Topr Tstg Supply voltage Input voltage Output voltage Output current Power dissipation Operating temperature Storage temperature Ta=25 With respect Parameter Conditions Ratings 6000 Unit
RECOMMENDED OPERATING CONDITIONS
Symbol Supply voltage Supply voltage High-level input voltage, inputs Low-level input voltage, inputs Parameter
(Ta=0 unless otherwise noted) (Note Limits Unit
Note voltage values with respect
ELECTRICAL CHARACTERISTICS
Symbol Parameter High-level output voltage Low-level output voltage Off-state output current Input current Average supply current from operating (Note 3,4,5) ICC2
(Ta=0 70°C, Vcc=5.0V 10%, Vss=0V, unless otherwise noted) (Note Test conditions IOH=-5.0mA IOL=4.2mA floating VOUT 5.5V Other inputs pins=0V Limits RAS= =VIH, output open RAS= cycling, CAS= tRC=min. output open Unit
MH2M365C MH2M365C MH2M365C
ICC1 (AV)
RAS, cycling tRC=tWC=min. output open
Supply current from stand-by (Note Average supply current from refreshing (Note 3,5) Average supply current from Hyper-Page-Mode (Note 3,4,5) Average supply current from before refresh mode (Note MH2M365C MH2M365C MH2M365C MH2M365C MH2M365C MH2M365C MH2M365C MH2M365C MH2M365C
ICC3 (AV)
ICC4(AV)
RAS=VIL, cycling tPC=min. output open
ICC6(AV)
before refresh cycling tRC=min. output open
Note Current flowing into positive, negative. Icc1 (AV), Icc3 (AV) Icc4 (AV) dependent cycle rate. Maximum current measured fastest cycle rate. Icc1 (AV) Icc4 (AV) dependent output loading. Specified values obtained with output open. Column Address changed once less while RAS=VIL CAS=VIH
MIT-DS-0083-1.2
MITSUBISHI ELECTRIC
21/Feb./1997
MH2M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 75497472-BIT 2097152-WORD 36-BIT DYNAMIC
CAPACITANCE (Ta=0 Vcc=5.0V 10%, Vss=0V, unless
Symbol (RAS) (CAS) Parameter Input capacitance,address inputs Input capacitance, write control input Input capacitance, input Input capacitance, input Input/Output capacitance, data ports VI=Vss
otherwise noted) Test conditions Limits Unit
f=1MHZ Vi=25mVrms
SWITCHING CHARACTERISTICS
Symbol
(Ta=0 10%, Vss=0V, unless otherwise noted notes 6,14,15) Limits
Parameter Access time from Access time from Column address access time Access time from precharge Output hold time from (Note Output hold time from Output impedance time from (Note (Note Output disable time after high Output disable time after high Output disable time after high (Note 12,13) (Note 12,13) (Note 7,8) (Note 7,9) (Note 7,10) (Note 7,11)
MH2M365C
MH2M365C
MH2M365C
Unit
tCAC tRAC tCPA tOHC tOHR tCLZ tWEZ tOFF tREZ
Note initial pause 500µs required after power-up followed minimum eight initialization cycles (any combination cycles containing clock such RAS-Only refresh). Note cycled during initial pause RAS/CAS cycles required after prolonged periods (greater than 16.4 inactivity before proper device operation achieved. Measured with load circuit equivalent VOH=2.4V(IOH=-5mA) VOL=0.4V(IOL=-4.2mA) load 100pF. reference levels measuring output signal 2.0V(VOH) 0.8V(VOL). Assumes that tRCD tRCD(max) tASC tASC(max) CP(max). Assumes that tRCD tRCD(max) tRAD tRAD(max). tRCD tRAD greater than maximum recommended value shown this table, tRAC will increase amount that tRCD exceeds value shown. Assumes that tRAD tRAD(max) tASC tASC(max). Assumes that tCP(max) tASC tASC(max). tWEZ(max) ,tOFF(max) tREZ(max)defines time which output achieves high impedance state reference VOH(min) VOL(max). Output disabled after both high. IOUT
MIT-DS-0083-1.2
MITSUBISHI ELECTRIC
21/Feb./1997
MH2M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 75497472-BIT 2097152-WORD 36-BIT DYNAMIC TIMING REQUIREMENTS (For Read, Write, Refresh, Hyper-Page Mode Cycles)
(Ta=0 70°C, 10%, Vss=0V, unless otherwise noted notes 14,15) Limits MH2M365C 16.4
Symbol
Parameter Refresh cycle time high pulse width Delay time, Delay time, high Delay time, high high pulse width
Column address delay time from
MH2M365C 16.4 (Note16) (Note17) (Note18) (Note19) (Note20) (Note20) (Note21)
MH2M365C 16.4
Unit
tREF tRCD tCRP tRPC tCPN tRAD tASR tASC tRAH tCAH tDZC tRDD tCDD
address setup time before
Column address setup time before
address hold time after Column address hold time after Delay time, data Delay time, high data Delay time, high data Transition time
Note timing requirements assumed =3ns. VIH(min) VIL(max) reference levels measuring timing input signals. tRCD(max) specified reference point only. tRCD less than tRCD(max), access time tRAC. tRCD greater than tRCD(max), access time controlled exclusively tCAC tAA. tRAD(max) specified reference point only. tRAD tRAD(max) tASC tASC(max), access time controlled exclusively tAA. tASC(max) specified reference point only. tRCD tRCD(max) tASC tASC(max), access time controlled exclusively tCAC. tDZC must satisfied. Either tRDD tCDD tODD must satisfied. measured between VIH(min) VIL(max).
Read Refresh Cycles
Symbol Parameter Read cycle time pulse width pulse width hold time after hold time after Read Setup time before Read hold time after high Read hold time after high Column address hold time Column address hold time (Note (Note MH2M365C 10000 10000 Limits MH2M365C 10000 10000 MH2M365C 10000 10000 Unit
tRAS tCAS tCSH tRSH tRCS tRCH tRRH tRAL tCAL
Note Either tRCH tRRH must satisfied read cycle.
MIT-DS-0083-1.2
MITSUBISHI ELECTRIC
21/Feb./1997
MH2M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 75497472-BIT 2097152-WORD 36-BIT DYNAMIC Write Cycle (Early Write)
MH2M365C Limits MH2M365C 10000 10000 10000 10000 MH2M365C
Symbol
Parameter Write cycle time pulse width pulse width hold time after hold time after Write setup time before Write hold time after Write pulse width Data setup time before Data hold time after
Unit
10000 10000
tRAS tCAS tCSH tRSH tWCS tWCH
Hyper page Mode Cycle (Read, Early Write, Hi-Z control
(Note
Symbol
Parameter Hyper page mode read/write cycle time Output hold time from pulse width read write cycle high pulse width hold time after precharge Hold time maintain data Hi-Z until access Pulse Width (Hi-Z control) (Note24) (Note25)
MH2M365C
Limits MH2M365C
MH2M365C
Unit
Note previously specified timing requirements switching characteristics applicable their respective Hyper page mode cycle. tRAS(min) specified cycles input performed. tCP(max) specified reference point only.
tHPC tDOH tRAS tCPRH tCHOL tWPE
100000
100000
100000
before Refresh Cycle
Symbol tCSR tCHR Parameter
(Note Limits MH2M365C
MH2M365C
MH2M365C
Unit
setup time before hold time after
Note Eight more before cycles instead eight cycles necessary proper operation before refresh mode.
MIT-DS-0083-1.2
MITSUBISHI ELECTRIC
21/Feb./1997
MH2M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 75497472-BIT 2097152-WORD 36-BIT DYNAMIC
Timing Diagrams Read Cycle
(Note
tRAS tCSH tCRP tRAD tASR A0~A9 tRAH tASC tCAH
ADDRESS
tRCD
tRSH tCAS
tCRP
tRAL tCAL
tASR
ADDRESS
COLUMN ADDRESS
tRCS tDZC
DQ(INPUTS)
tRRH tRCH
tCDD tRDD Hi-Z
tCAC tCLZ
DQ(OUTPUTS)
tREZ tOHR
DATA VALID
tWEZ tOFF tOHC
Hi-Z tRAC
Hi-Z
Note
Indicates don't care input. VIH(min) VIH(max) VIL(min) VIL(max) Indicates invalid output.
MIT-DS-0083-1.2
MITSUBISHI ELECTRIC
21/Feb./1997
MH2M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 75497472-BIT 2097152-WORD 36-BIT DYNAMIC
Early Write Cycle
tRAS tCSH tCRP tASR A0~A9 tASR tRAH tASC tCAH
COLUMN ADDRESS ADDRESS
tRCD
tRSH tCAS
tCRP
ADDRESS
tWCS
DQ(INPUTS)
tWCH
DATA VALID
DQ(OUTPUTS)
Hi-Z
MIT-DS-0083-1.2
MITSUBISHI ELECTRIC
21/Feb./1997
MH2M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 75497472-BIT 2097152-WORD 36-BIT DYNAMIC
Hyper Page Mode Read Cycle
tRAS tCSH tCRP tRAD tASR A0~A9 tRAH tASC tCAH tASC tCAH tASC tCPRH tCAH tRCD tCAS tHPC tCAS tRSH tCAS
tASR
ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
ADDRESS
tRCS tCAL tDZC tCAL tCAL
tRRH tRCH
tWEZ tRDD tCDD tCAC tCLZ Hi-Z tCAC tDOH
DATA VALID-1 DATA VALID-2
DQ(INPUTS)
tCAC tDOH
tREZ tOHR tOFF tOHC
DATA VALID-3
DQ(OUTPUTS)
Hi-Z tRAC
tCPA
tCPA
MIT-DS-0083-1.2
MITSUBISHI ELECTRIC
21/Feb./1997
MH2M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 75497472-BIT 2097152-WORD 36-BIT DYNAMIC
Hyper Page Mode Early Write Cycle
tRAS tCSH tCRP tCAL tASR A0~A9 tRAH tASC tCAH tASC tCAH tASC tCAL tCAH tRCD tCAS tHPC tCAS tRSH tCAS
tCRP
tASR
ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
ADDRESS
tWCS
tWCH
tWCS
tWCH
tWCS
tWCH
DQ(INPUTS)
DATA VALID-1
DATA VALID-2
DATA VALID-3
DQ(OUTPUTS)
Hi-Z
MIT-DS-0083-1.2
MITSUBISHI ELECTRIC
21/Feb./1997
MH2M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 75497472-BIT 2097152-WORD 36-BIT DYNAMIC
Hyper Page Mode Read Cycle Hi-Z control
tRAS tCSH tCRP tRAD tASR A0~A9 tRAH tASC tCAH tASC tCAH tASC tCPRH tCAH tRCD tCAS tHPC tCAS tRSH tCAS
tCRP
tASR
ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
ADDRESS
tRAL tRCS tDZC tWPE tRCH tRCS
tRRH tRCH
tRDD tCDD tCAC
DQ(INPUTS)
tCAC tCLZ
tCAC tDOH
DATA VALID-1
Hi-Z
tWEZ
DATA VALID-2
tCLZ Hi-Z
tREZ tOHR tOFF tOHC
DATA VALID-3
DQ(OUTPUTS)
Hi-Z tRAC
tCPA
tCPA
MIT-DS-0083-1.2
MITSUBISHI ELECTRIC
21/Feb./1997
MH2M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 75497472-BIT 2097152-WORD 36-BIT DYNAMIC
RAS-only Refresh Cycle
tRAS tRPC tCRP tASR tRAH tASR tCRP
A0~A9
ADDRESS
ADDRESS
DQ(INPUT)
DQ(OUTPUT)
Hi-Z
MIT-DS-0083-1.2
MITSUBISHI ELECTRIC
21/Feb./1997
MH2M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 75497472-BIT 2097152-WORD 36-BIT DYNAMIC
before Refresh Cycle
tRPC tCSR tCPN tCHR tRAS tRAS
tRPC
tCSR
tCHR
tRPC
tCRP
tASR A0~A9 tRRH tRCH tRCS
ADDRESS COLUMN ADDRESS
DQ(INPOUT)
DQ(OUTPUT)
tREZ tOHR tOFF tOHC Hi-Z
MIT-DS-0083-1.2
MITSUBISHI ELECTRIC
21/Feb./1997
MH2M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 75497472-BIT 2097152-WORD 36-BIT DYNAMIC
Hidden Refresh Cycle (Read)
(Note
tRAS tCRP tRAD tASR A0~A9 tRAH
ADDRESS
tRAS
tRCD
tRSH
tCHR
tASC
tCAH
COLUMN ADDRESS
tASR
ADDRESS
tRCS
tRAL
tRRH tRCH
tDZC tCDD tRDD
DQ(INOUT)
Hi-Z tCAC tCLZ
tREZ tOHR tOFF tOHC
DQ(OUTPUT)
Hi-Z tRAC
DATA VALID
Hi-Z
Note Early write cycle applicable instead read cycle. Timing requirements output state same that each cycle shown above.
MIT-DS-0083-1.2
MITSUBISHI ELECTRIC
21/Feb./1997
MH2M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 75497472-BIT 2097152-WORD 36-BIT DYNAMIC
72pin DRAM Module Outline
107.95 8.6MAX 3.38 101.19
20.2
R1.57
5.96MIN.
2.03
R1.57
1.27
1.27
6.35
35x1.27=44.45
6.35
35x1.27=44.45
MIT-DS-0083-1.2
MITSUBISHI ELECTRIC
21/Feb./1997
5.96MIN.
10.16
6.35
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