M5M5V208FP,VP,RV,KV,KR -70L-W -85L -10L-W -12L-W -70LL-W, -85LL-W

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M5M5V208FP,VP,RV,KV,KR -70L-W -85L -10L-W -12L-W -70LL-W, -85LL-W

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'97.3.21
M5M5V208FP,VP,RV,KV,KR
-70L-W -85L -10L-W -12L-W -70LL-W, -85LL-W, -10LL-W, -12LL-W
2097152-BIT (262144-WORD 8-BIT) CMOS STATIC
DESCRIPTION
M5M5V208 2,097,152-bit CMOS static organized 262,144-words 8-bit which fabricated using high-performance quadruple-polysilicon double metal CMOS technology. thin film transistor(TFT) load cells CMOS periphery results high density power static RAM. M5M5V208 designed memory applications where high reliability, large storage, simple interfacing battery back-up important design objectives. M5M5V208VP,RV,KV,KR packaged 32-pin thin small outline package which high reliability high density surface mount device(SMD).Two types devices available. VP,KV(normal lead bend type package),RV,KR(reverse lead bend type package). Using both types devices, becomes very easy design printed circuit board.
CONFIGURATION (TOP VIEW) (0V)GND
FEATURE
Type M5M5V208FP,VP,RV,KV,KR-70L M5M5V208FP,VP,RV,KV,KR-85L M5M5V208FP,VP,RV,KV,KR-10L M5M5V208FP,VP,RV,KV,KR-12L M5M5V208FP,VP,RV,KV,KR-70LL M5M5V208FP,VP,RV,KV,KR-85LL M5M5V208FP,VP,RV,KV,KR-10LL M5M5V208FP,VP,RV,KV,KR-12LL Access Power supply current time Active Stand-by (max) (max) (max) 70ns 85ns 100ns 120ns 70ns 85ns 100ns 120ns 27mA
(Vcc=3.6V)
VCC(3V)
Outline 32P2M-A(FP) 60µA
(Vcc=3.6V)
(Vcc=3.6V)
Single 3.6V power supply W-version: operating temperature +70°C clocks, refresh inputs outputs compatible. Easy memory expansion power down Data retention supply voltage=2.0V Three-state outputs: OR-tie capability prevents data contention Common Data Battery backup capability Small stand-by current 0.3µA(typ.)
M5M5V208VP,KV
Outline 32P3H-E(VP), 32P3K-B(KV)
PACKAGE
M5M5V208FP M5M5V208VP,RV 32pin TSOP M5M5V208KV,KR 32pin 13.4 TSOP
M5M5V208RV,KR
APPLICATION
Small capacity memory units Battery operating system Handheld communiation tools
Outline 32P3H-F(RV), 32P3K-C(KR)
MITSUBISHI ELECTRIC
'97.3.21
M5M5V208FP,VP,RV,KV,KR
-70L-W -85L -10L-W -12L-W -70LL-W, -85LL-W, -10LL-W, -12LL-W
2097152-BIT (262144-WORD 8-BIT) CMOS STATIC
FUNCTION
operation mode M5M5V208 determined combination device control inputs Each mode summarized function table. write cycle executed whenever level overlaps with level high level address must before write cycle must stable during entire cycle. data latched into cell trailing edge whichever occurs first, requiring set-up hold time relative these edge maintained. output enable directly controls output stage. Setting high level,the output stage high-impedance state, data contention problem write cycle eliminated. read cycle executed setting high level level while active state When setting high level level, chips non-selectable mode which both reading writing disabled. this mode, output stage high-impedance state, allowing OR-tie with other chips memory expansion power supply current reduced stand-by current which specified Icc3 Icc4, memory data held power supply, enabling battery back-up operation during power failure power-down operation nonselected mode.
FUNCTION TABLE
Mode selection selection Write Read High-impedance High-impedance High-impedance Standby Standby Active Active Active
BLOCK DIAGRAM
262144 WORDS BITS ROWS COLUMNS BLOCKS
CLOCK GENERATOR
(3V)
(0V)
*Pin numbers inside dotted line show those TSOP.
MITSUBISHI ELECTRIC
'97.3.21
M5M5V208FP,VP,RV,KV,KR
-70L-W -85L -10L-W -12L-W -70LL-W, -85LL-W, -10LL-W, -12LL-W
2097152-BIT (262144-WORD 8-BIT) CMOS STATIC
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Supply voltage Topr Tstr
Input voltage Output voltage Power dissipation Operating temperature Storage temperature
Conditions
With respect Ta=25°C
Ratings 0.5*~4.6 0.5*
(Max 4.6)
Unit
~150
-3.0V case Pulse width 30ns
ELECTRICAL CHARACTERISTICS
Symbol VOH1 VOH2 Parameter High-level input voltage Low-level input voltage High-level output voltage High-level output voltage Low-level output voltage Input current Output current off-state Active supply current
(CMOS-level Input)
(Ta=- 20~70°C, Vcc= 3.6V, unless otherwise noted)
Test conditions
Limits +0.3V
Unit
IOH= -0.5mA IOH= -0.05mA IOL=2mA VI=0 S1=VIH S2=VIL OE=VIH VI/O=0 0.2V, Vcc-0.2V, other inputs 0.2V Vcc-0.2V,output-open S1=VIL,S2=VIH, other inputs=VIH output-open 0.2V
-0.3* -0.5V
10MHz 5MHz 10MHz 5MHz
Icc1
Icc2
Active supply current
(TTL-level Input)
+70°C
Icc3
Stand-by current
+70°C Vcc-0.2V, Vcc-0.2V +40°C other inputs=0 +25°C
0.33
Icc4
Stand-by current
S1=VIH S2=VIL,other inputs=0
-3.0V case Pulse width 30ns
CAPACITANCE
Symbol Parameter
Input capacitance Output capacitance
(Ta=- 70°C, Vcc= 3.6V, unless otherwise noted) Limits Test conditions Unit VI=GND, VI=25mVrms, f=1MHz VO=GND,VO=25mVrms, f=1MHz
Note Direction current flowing into positive mark). Typical value 25°C
MITSUBISHI ELECTRIC
'97.3.21
M5M5V208FP,VP,RV,KV,KR
-70L-W -85L -10L-W -12L-W -70LL-W, -85LL-W, -10LL-W, -12LL-W
2097152-BIT (262144-WORD 8-BIT) CMOS STATIC
ELECTRICAL CHARACTERISTICS MEASUREMENT CONDITIONS
Input pulse level Input rise fall time Reference level Output loads
70°C, Vcc= 3.6V, unless otherwise noted 1TTL including scope Fig.1 Output load
3.6V VIH=2.2V,VIL=0.4V VOH=VOL=1.5V Fig.1,CL=30pF CL=5pF (for ten,tdis) Transition measured ±500mV from steady state voltage. (for ten,tdis)
READ CYCLE
Symbol ta(A) ta(S1) ta(S2) ta(OE) tdis(S1) tdis(S2) tdis(OE) ten(S1) ten(S2) ten(OE) tV(A) Parameter Read cycle time Address access time Chip select access time Chip select access time Output enable access time Output disable time after high Output disable time after Output disable time after high Output enable time after Output enable time after high Output enable time after Data valid time after address -70L,LL Limits -85L,LL -10L,LL -12L,LL Unit
WRITE CYCLE
-70L,LL Write cycle time tw(W) Write pulse width tsu(A) Address setup time tsu(A-WH) Address setup time with respect tsu(S1) Chip select setup time tsu(S2) Chip select setup time tsu(D) Data setup time th(D) Data hold time trec(W) Write recovery time tdis(W) Output disable time from tdis(OE) Output disable time from high ten(W) Output enable time from high ten(OE) Output enable time from Symbol Parameter Limits -85L,LL -10L,LL -12L,LL Unit
MITSUBISHI ELECTRIC
'97.3.21
M5M5V208FP,VP,RV,KV,KR
-70L-W -85L -10L-W -12L-W -70LL-W, -85LL-W, -10LL-W, -12LL-W
2097152-BIT (262144-WORD 8-BIT) CMOS STATIC
TIMING DIAGRAMS Read cycle
A0~17 ta(A) (S1)
(Note
tdis (S1)
(Note
(Note
(S2) (OE) (OE) tdis (S2)
(Note
(Note
tdis (OE) (S1) (S2)
(Note
DQ1~8
level
DATA VALID
Write cycle control mode)
A0~17
(S1)
(Note (Note
(Note
(S2)
(Note
(A-WH) tdis tdis (OE) DQ1~8 ten(OE) trec
DATA STABLE
MITSUBISHI ELECTRIC
'97.3.21
M5M5V208FP,VP,RV,KV,KR
-70L-W -85L -10L-W -12L-W -70LL-W, -85LL-W, -10LL-W, -12LL-W
2097152-BIT (262144-WORD 8-BIT) CMOS STATIC
Write cycle control mode)
A0~17 (S1) trec
(Note (Note (Note
(Note
(Note
(Note
DQ1~8
DATA STABLE
Write cycle control mode)
A0~17
(Note (Note
(S2)
trec
(Note
(Note
(Note
(Note
DQ1~8
DATA STABLE
Note Hatching indicates state "don't care". Writing executed while high overlaps low. When falling edge simultaneously prior falling edge rising edge outputs maintained high impedance state. Don't apply inverted phase signal externally when output mode.
MITSUBISHI ELECTRIC
'97.3.21
M5M5V208FP,VP,RV,KV,KR
-70L-W -85L -10L-W -12L-W -70LL-W, -85LL-W, -10LL-W, -12LL-W
2097152-BIT (262144-WORD 8-BIT) CMOS STATIC
POWER DOWN CHARACTERISTICS ELECTRICAL CHARACTERISTICS
Symbol
(PD) (S1) (S2) (PD)
70°C, unless otherwise noted)
Parameter
Power down supply voltage Chip select input Chip select input Power down supply current
Test conditions
Limits
Unit
3.0V 0.2V 0.2V,S2 0.2V
(Note
Note7: (PD) 0.5µA (Max.) case +25°C
TIMING REQUIREMENTS
Symbol Parameter (PD) Power down time trec (PD) Power down recovery time Test conditions
70°C, unless otherwise noted
Limits
Unit
POWER DOWN CHARACTERISTICS control mode
(PD)
2.2V 2.7V
2.7V
(PD)
2.2V
0.2V
control mode
0.2V 0.2V
(PD)
2.7V
2.7V
(PD)
0.2V
MITSUBISHI ELECTRIC

M5M5V208FP,VP,RV,KV,KR -70L-W -85L -10L-W -12L-W -70LL-W, -85LL-W

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