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M5M44260CJ,TP-5,-6,-7, -5S,-6S,-7S FAST PAGE MODE 4194304-BIT (26


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MITSUBISHI LSIs MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7, -5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC
This family 262144-word 16-bit dynamic RAMs, fabricated with high performance CMOS process, ideal memory systems where high speed, power dissipation, costs essential. double-layer metalization process technology single-transistor dynamic storage stacked capacitor cell provide high circuit density reduced costs. Multiplexed address inputs permit both reduction pins increase system densities. Self extended refresh current small enough battery back-up application. This device 2CAS terminals with refresh cycle cycles every 8.2ms.
CONFIGURATION (TOP VIEW)
(5V)VCC (5V)VCC VSS(0V) DQ16 DQ15 DQ14 DQ13 VSS(0V) DQ12 DQ11 DQ10 LCAS UCAS VSS(0V)
FEATURES
Type name
M5M44260CXX-5,-5S M5M44260CXX-6,-6S M5M44260CXX-7,-7S access access time time (max.ns) (max.ns) Address access access time time (max.ns) (max.ns) Power Cycle dissipatime tion (min.ns) (typ.mW)
XX=J,TP
Standard 40pin SOJ, TSOP (II) Single 5V±10% supply stand-by power dissipation CMOS Input level 5.5mW (Max) CMOS Input level 550µW (Max) Operating power dissipation M5M44260Cxx-5,-5S 688mW (Max) M5M44260Cxx-6,-6S 605mW (Max) M5M44260Cxx-7,-7S 523mW (Max) Self refresh capability Self refresh current 150µA (Max) Extended refresh capability Extended refresh current 150µA (Max) Fast-page mode (512-column random access), Read-modify-write, RAS-only refresh, before refresh, Hidden refresh capabilities. Early-write mode, LCAS UCAS control output buffer impedance refresh cycles every 8.2ms (A0~A8) refresh cycles every 128ms (A0~A8) Byte word control Read/Write operation (2CAS, type) Applicable self refresh version (M5M44260CJ,TP-5S,-6S,-7S option) only
(5V)VCC
Outline 40P0K (400mil SOJ)
(5V)VCC (5V)VCC
VSS(0V) DQ16 DQ15 DQ14 DQ13 VSS(0V) DQ12 DQ11 DQ10
APPLICATION
Microcomputer memory, Refresh memory
LCAS UCAS VSS(0V)
name A0~A8 DQ1~DQ16 LCAS UCAS Function Address inputs Data inputs outputs address strobe input Lower byte control column address strobe input Upper byte control column address strobe input Write control input Output enable input Power supply (+5V) Ground (0V)
(5V)VCC
Outline 44P3W-R (400mil TSOP Nomal Bend)
CONNECTION
M5M44260CJ,TP-5,-5S Under development
MITSUBISHI LSIs
FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC
FUNCTION
addition normal read,write read-modify-write operations M5M44260CJ, provides number other functions, e.g., fast page mode, RAS-only refresh delayed-write. input conditions each shown Table
Table Input conditions each mode
Inputs Operation Lower byte read Upper byte read Word read Lower byte write Upper byte write Word write only refresh Hidden refresh
before (Extended refresh
Input/Output
address Column address DQ1~
LCAS
UCAS
Self refresh Stand-by
Refresh Remark DQ9~ DQ16 DOUT DOUT DOUT Fast page mode identical
DOUT DOUT DOUT
Note active, nonactive, don' care, open
BLOCK DIAGRAM
ADDRESS STROBE INPUT LOWER BYTE CONTROL COLUMN ADDRESS LCAS STROBE INPUT UPPER BYTE CONTROL UCAS COLUMN ADDRESS STROBE INPUT WRITE CONTROL INPUT
(5V)
CLOCK GENERATOR CIRCUIT
(0V) LOWER UPPER
(8)LOWER DATA BUFFER
(8)LOWER DATA BUFFER
LOWER DATA INPUTS OUTPUTS
(5V) (0V)
A0~A8 COLUMN DECODER
(8)UPPER DATA BUFFER
SENSE REFRESH AMPLIFIER CONTROL
DQ10 DQ16
ADDRESS INPUTS
COLUMN ADDRESS BUFFER
UPPER DATA INPUTS OUTPUTS
DECODER
MEMORY CELL (4194304 BITS)
(8)UPPER DATA BUFFER
(5V) (0V)
OUTPUT ENABLE INPUT
M5M44260CJ,TP-5,-5S Under development
MITSUBISHI LSIs
FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC
ABSOLUTE MAXIMUM RATINGS
Symbol Topr Tstg Parameter Supply voltage Input voltage Output voltage Output current Power dissipation Operating temperature Storage temperature Conditions With respect Ratings -1~7 -1~7 -1~7 1000 0~70 -65~150
(Note
Ta=25°C
Unit
RECOMMENDED OPERATING CONDITIONS (Ta=0~70°C, unless otherwise noted)
Symbol Parameter Supply voltage Supply voltage High-level input voltage, inputs Low-level input voltage, inputs -0.5 Limits
Unit
Note voltage values with respect VSS. VIL(min) -2.0V when pulse width less than 25ns. (Pulse width with respect Vss.)
ELECTRICAL CHARACTERISTICS (Ta=0~70°C VCC=5V±10%, VSS=0V, unless otherwise noted)
Symbol ICC1(AV) Parameter High-level output voltage Low-level output voltage Off-state output current Input current Average supply current from Vcc, operating M5M44260C-5,-5S M5M44260C-6,-6S Test conditions IOH=-5mA IOL=4.2mA floating VOUT 5.5V +6.0V, Other inputs pins=0V RAS, cycling tRC=tWC=min. output open RAS= =VIH, output open ICC2 Supply current from VCC, stand-by (Note RAS= -0.5V output open cycling, CAS=VIH tRC=min. output open RAS=VIL, cycling tPC=min. output open before refresh cycling tRC=min. output open cycling 0.2V before refresh cycling 0.2V VCC-0.2V 0.2V VCC-0.2V 0.2V VCC-0.2V 0.2V VCC-0.2V A0~A8 0.2V VCC-0.2V, DQ=open tRC=250µs, tRAS=tRAS min~1µs RAS=CAS 0.2V output open
(Note
Limits
Unit
(Note 3,4,5) M5M44260C-7,-7S
ICC3(AV)
Average supply current M5M44260C-5,-5S from Vcc, only M5M44260C-6,-6S refresh mode (Note 3,5) M5M44260C-7,-7S Average supply current M5M44260C-5,-5S from M5M44260C-6,-6S Fast page mode (Note 3,4,5) M5M44260C-7,-7S Average supply current M5M44260C-5,-5S from before refresh M5M44260C-6,-6S (Note 3,5) M5M44260C-7,-7S mode
ICC4(AV)
ICC6(AV)
ICC8(AV)
Average supply current from Extended-refresh mode
(Note
ICC9(AV)
Average supply current from Self-refresh mode
(Note
Note Current flowing into positive, negative. ICC1 (AV), ICC3 (AV), ICC4 (AV), ICC6 (AV) dependent cycle rate. Maximum current measured fastest cycle rate. ICC1 (AV) ICC4 (AV) dependent output loading. Specified values obtained with output open. Column Address changed once less while RAS=VIL CAS=VIH. M5M44260CJ,TP-5,-5S Under development
MITSUBISHI LSIs
FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC
CAPACITANCE (Ta=0~70°C VCC=5V±10%, VSS=0V, unless otherwise noted)
Symbol (CLK) Parameter Input capacitance, address inputs Input capacitance, clock inputs Input/Output capacitance, data ports Test conditions VI=VSS f=1MHz VI=25mVrms Limits Unit
SWITCHING CHARACTERISTICS (Ta=0~70°C, VCC=5V±10%, Vss=0V, unless otherwise noted, notes 6,13,14)
Limits Symbol tCAC tRAC tCPA tOEA tCLZ tOFF tOEZ Parameter Access time from Access time from Columu address access time Access time from precharge Access time from Output impedance time from Output disable time after high Output disable time after high (Note 7,8) (Note 7,9) (Note 7,10) (Note 7,11) (Note (Note (Note (Note
M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S
Unit
Note initial pause required after power-up followed minimum eight initialization cycles (RAS-only refresh before refresh cycles). Note cycled during initial pause. initialization cycles required after prolonged periods (greater than 8.2ms) inactivity before proper device operation achieved. Measured with load circuit equivalent 2TTL loads 100pF. Assumes that tRCD tRCD(max) tASC tASC(max). Assumes that tRCD tRCD(max) tRAD tRAD(max). tRCD tRAD greater than maximum recommended value shown this table, tRAC will increase amount that tRCD exceeds value shown. Assumes that tRAD tRAD(max) tASC tASC(max). Assumes that tCP(max) tASC tASC(max). tOFF(max) tOEZ (max) defines time which output achieves high impedance state (IOUT reference VOH(min) VOL(max).
M5M44260CJ,TP-5,-5S Under development
MITSUBISHI LSIs
FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh Fast-Page Mode Cycles)
(Ta=0~70°C, VCC=5V±10%, VSS=0V, unless otherwise noted, notes 6,13,14) Limits Symbol tREF tREF tRCD tCRP tRPC tCPN tRAD tASR tASC tRAH tCAH tDZC tDZO tCDD tODD Parameter Refresh cycle time Refresh cycle time high pulse width Delay time, Delay time, high Delay time, high high pulse width Column address delay time from address setup time before Column address setup time before address hold time after Column address hold time after Delay time, data Delay time, data Delay time, high data Delay time, high data Transition time
M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S
Unit
(Note
(Note (Note
(Note (Note (Note (Note (Note
Note timing requirements assumed =5ns. VIH(min) VIL(max) reference levels measuring timing input signals. tRCD(max) specified reference point only. tRCD less than tRCD(max), access time tRAC. tRCD greater than tRCD(max), access time controlled exclusively tCAC tAA. tRAD(max) specified reference point only. tRAD tRAD(max) tASC tASC(max), access time controlled exclusively tAA. tASC(max) specified reference point only. tRCD tRCD(max) tASC tASC(max), access time controlled exclusively tCAC. Either tDZC tDZO must satisfied. Either tCDD tODD must satisfied. measured between VIH(min) VIL(max).
Read Refresh Cycles
Limits Symbol tRAS tCAS tCSH tRSH tRCS tRCH tRRH tRAL tOCH tORH Parameter
M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S
Unit
Read cycle time pulse width pulse width hold time after hold time after Read setup time before Read hold time after high Read hold time after high Column address hold time hold time after hold time after Note Either tRCH tRRH must satisfied read cycle.
(Note (Note
10000 10000
10000 10000
10000 10000
M5M44260CJ,TP-5,-5S Under development
MITSUBISHI LSIs
FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC
Write Cycle (Early Write Delayed Write)
Limits Symbol tRAS tCAS tCSH tRSH tWCS tWCH tCWL tRWL tOEH Parameter Write cycle time pulse width pulse width hold time after hold time after Write setup time before Write hold time after hold time after hold time after Write pulse width Data setup time before Data hold time after hold time after
M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S
Unit
(Note
10000 10000
10000 10000
10000 10000
Read-Write Read-Modify-Write Cycles
Limits Symbol tRWC tRAS tCAS tCSH tRSH tRCS tCWD tRWD tAWD tCWL tRWL tOEH Parameter Read write/read modify write cycle time pulse width pulse width hold time after hold time after Read setup time before Delay time, Delay time, Delay time, address hold time after hold time after Write pulse width Data setup time before Data hold time after hold time after (Note
M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S
Unit
(Note (Note (Note
10000 10000
10000 10000
10000 10000
Note tRWC specified tWCS, tCWD, tRWD tAWD tCPWD specified reference points only. tWCS tWCS(min) cycle early write cycle pins will remain high impedance throughout entire cycle. tCWD tCWD(min), tRWD tRWD(min), tAWD tAWD(min) tCPWD tCPWD(min) (for fast page mode cycle only), cycle read-modify-write cycle will contain data read from selected address. neither above condition (delayed write) access time until goes back VIH) indeterminate.
M5M44260CJ,TP-5,-5S Under development
MITSUBISHI LSIs
FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC
Fast-Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle)
Symbol tPRWC tRAS tCPRH tCPWD Parameter Fast page mode read/write cycle time Fast page mode read write/read modify write cycle time pulse width read write cycle (Note (Note high pulse width hold time after precharge Delay time, precharge (Note
(Note
Limits
M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S
Unit
100000
100000
100000
Note previously specified timing requirements switching characteristics applicable their respective fast page mode cycle. tRAS(min) specified cycles input performed. tCP(max) specified reference point only.
before Refresh Cycle, Extended Refresh Cycle
Symbol tCSR tCHR tCAS Parameter setup time before hold time after pulse width
(Note
Limits
M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S
Unit
Note Eight more before cycles instead eight cycles necessary proper operation before refresh mode.
Self Refresh Cycle
Symbol tRASS tRPS tCHS
(Note
Limits Parameter self refresh pulse width self refresh high precharge time self refresh hold time
M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S
Unit
M5M44260CJ,TP-5,-5S Under development
MITSUBISHI LSIs
FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC
Timing Diagrams Read Cycle
(Note
tRAS tCSH tCRP LCAS/UCAS tRAD tASR A0~A8 tRAH tASC tCAH
COLUMN ADDRESS
tRCD
tRSH tCAS
tRPC
tCRP
tRAL tASR
ADDRESS
ADDRESS
tRRH tRCS tDZC DQ1~DQ16 (INPUTS) tCAC tCLZ DQ1~DQ16 (OUTPUTS)
Hi-Z Hi-Z DATA VALID Hi-Z
tRCH
tCDD
tOFF
tRAC tDZO tOEA tOCH
tOEZ tODD
tORH
Note
Indicates don't care input. VIH(min) VIH(max) VIL(min) VIL(max) Indicates invalid output.
M5M44260CJ,TP-5,-5S Under development
MITSUBISHI LSIs
FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC
Byte Read Cycle
tRAS tCRP tCPN tRCD tCAS UCAS LCAS) tCSH tRSH tRPC tCRP
LCAS UCAS)
tASR tRAH tRAD tASC tCAH tRAL tASR
A0~A8
ADDRESS
COLUMN ADDRESS
ADDRESS
tRRH tRCS tRCH
DQ1~DQ8 DQ9~DQ16) (INPUTS)
DQ1~DQ8 DQ9~DQ16) (OUTPUTS) tDZC DQ9~DQ16 DQ1~DQ8) (INPUTS) tCAC tCLZ DQ9~DQ16 DQ1~DQ8) (OUTPUTS)
Hi-Z
Hi-Z
tCDD
Hi-Z
tOFF
Hi-Z
DATA VALID
tRAC tDZO tOEA tOCH
tOEZ tODD
tORH
M5M44260CJ,TP-5,-5S Under development
MITSUBISHI LSIs
FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC
Write Cycle (Early write)
tRAS tCSH tCRP LCAS/UCAS tASR tRAH tASC tCAH tASR tRCD tCAS tRSH tCPN tCRP tRPC
A0~A8
ADDRESS
COLUMN ADDRESS
ADDRESS
tWCS
tWCH
DQ1~DQ16 (INPUTS)
DATA VALID
DQ1~DQ16 (OUTPUTS)
Hi-Z
M5M44260CJ,TP-5,-5S Under development
MITSUBISHI LSIs
FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC
Byte Write Cycle (Early write)
tRAS tCSH tCRP tCPN tRCD tCAS UCAS LCAS) tRSH tRPC tCRP
LCAS UCAS)
tASR tRAH tASC tCAH
COLUMN ADDRESS
tASR
A0~A8
ADDRESS
ADDRESS
tWCS
tWCH
DQ1~DQ8 DQ9~DQ16) (INPUTS)
DQ1~DQ8 DQ9~DQ16) (OUTPUTS) DQ9~DQ16 DQ1~DQ8) (INPUTS)
Hi-Z
DATA VALID
DQ9~DQ16 DQ1~DQ8) (OUTPUTS)
Hi-Z
M5M44260CJ,TP-5,-5S Under development
MITSUBISHI LSIs
FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC
Write Cycle (Delayed write)
tRAS tCSH tCRP LCAS/UCAS tASR tRAH tASC tCAH tASR
COLUMN ADDRESS ADDRESS
tRPC tRSH tCAS tCPN tCRP
tRCD
A0~A8
ADDRESS
tCWL tRCS tWCH tDZC DQ1~DQ16 (INPUTS) tCLZ
Hi-Z
tRWL
DATA VALID
DQ1~DQ16 (OUTPUTS)
Hi-Z
Hi-Z
tDZO
tOEZ tODD
tOEH
M5M44260CJ,TP-5,-5S Under development
MITSUBISHI LSIs
FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC
Byte Write Cycle (Delayed write)
tRAS tCSH tCRP tCPN tASR tRAH tASC tCAH tASR
ADDRESS
tRPC tRSH tCAS tCRP
tRCD
UCAS LCAS)
LCAS UCAS)
A0~A8
ADDRESS
COLUMN ADDRESS
tRCS
tCWL tRWL
DQ1~DQ8 DQ9~DQ16) (INPUTS)
DQ1~DQ8 DQ9~DQ16) (OUTPUTS) tDZC DQ9~DQ16 DQ1~DQ8) (INPUTS)
Hi-Z
tWCH
Hi-Z
DATA VALID
tCLZ
DQ9~DQ16 DQ1~DQ8) (OUTPUTS)
Hi-Z
Hi-Z
tDZO
tOEZ tODD
tOEH
M5M44260CJ,TP-5,-5S Under development
MITSUBISHI LSIs
FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC
Read-Write, Read-Modify-Write Cycle
tRWC tRAS tCSH tCRP LCAS/UCAS tASR tRAH tRAD tASC tCAH tASR tRCD tRSH tCAS tRPC tCRP
A0~A8
ADDRESS
COLUMN ADDRESS
ADDRESS
tRCS tDZC DQ1~DQ16 (INPUTS)
Hi-Z
tAWD tCWD tRWD
tCWL tRWL
DATA VALID
tCAC tCLZ
DQ1~DQ16 (OUTPUTS)
Hi-Z
DATA VALID
Hi-Z
tRAC tDZO tOEA
tODD tOEZ
tOEH
M5M44260CJ,TP-5,-5S Under development
MITSUBISHI LSIs
FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC
Byte Read-Write, Read-Modify-Write Cycle
tRWC tRAS tCSH tRCD tCRP UCAS LCAS) tCPN tASR tRAH tRAD tASC tCAH tASR tRSH tCAS tRPC tCRP
LCAS UCAS)
A0~A8
ADDRESS
COLUMN ADDRESS
ADDRESS
tRCS
tAWD tCWD tRWD
tCWL tRWL
DQ1~DQ8 DQ9~DQ16) (INPUTS)
DQ1~DQ8 DQ9~DQ16) (OUTPUTS)
Hi-Z
tDZC DQ9~DQ16 DQ1~DQ8) (INPUTS)
Hi-Z
DATA VALID
tCAC tCLZ
DQ9~DQ16 DQ1~DQ8) (OUTPUTS)
Hi-Z
DATA VALID
Hi-Z
tRAC tDZO tOEA
tODD tOEZ tOEH
M5M44260CJ,TP-5,-5S Under development
MITSUBISHI LSIs
FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC
RAS-only Refresh Cycle
tRAS tRPC tCRP LCAS/UCAS tASR tRAH tASR tCRP
A0~A8
ADDRESS
ADDRESS
DQ1~DQ16 (INPUTS)
DQ1~DQ16 (OUTPUTS)
Hi-Z
M5M44260CJ,TP-5,-5S Under development
MITSUBISHI LSIs
FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC
before Refresh Cycle, Extended Refresh Cycle
tRPC tCSR tCHR tRAS tRAS
tRPC LCAS/UCAS
tCSR
tCHR
tRPC
tCRP
tCPN tASR A0~A8 tRCH tCDD DQ1~DQ16 (INPUTS) tOFF DQ1~DQ16 (OUTPUTS) tOEZ tODD
Hi-Z Hi-Z ADDRESS COLUMN ADDRESS
tRCS
M5M44260CJ,TP-5,-5S Under development
MITSUBISHI LSIs
FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC
Hidden Refresh Cycle (Read)
(Note
tRAS tCRP LCAS/UCAS tRAD tASR tRAH
ADDRESS
tRAS
tRCD
tRSH
tCHR
tASC
tCAH
COLUMN ADDRESS
tASR
A0~A8
ADDRESS
tRCS tRAL tDZC DQ1~DQ16 (INPUTS) tCAC tCLZ DQ1~DQ16 (OUTPUTS)
Hi-Z DATA VALID Hi-Z Hi-Z
tRRH
tCDD
tOFF
tRAC tDZO
tOEA tORH
tOEZ
tODD
Note Early write, delayed write, read write read modify write cycle applicable instead read cycle. Timing requirements output state same that each cycle described above.
M5M44260CJ,TP-5,-5S Under development
MITSUBISHI LSIs
FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC
Fast Page Mode Read Cycle
tRAS tCSH tCRP LCAS/UCAS tRAD tASR tRAH tASC tCAH
COLUMN ADDRESS1
tCAS tCAS
tRSH tCAS
tRCD
tCPRH tASC tCAH tASC tCAH tASR
ADDRESS
A0~A8
ADDRESS
COLUMN ADDRESS2
COLUMN ADDRESS3
tRAL tRCS tDZC tCLZ DQ1~DQ16 (OUTPUTS)
Hi-Z DATA VALID-1 Hi-Z Hi-Z
tRCH tRCS
tRCH tRRH
tRCH
tRCS
tDZC
tDZC
tCDD
DQ1~DQ16 (INPUTS)
Hi-Z
Hi-Z
tCAC tOFF
tCAC tCLZ tOFF
DATA VALID-2 Hi-Z
tCAC tCLZ tOFF
DATA VALID-3
tRAC tDZO
tCPA tOEA tOCH tOEZ tOEA tOCH
tCPA tOEZ tOEA tOCH tOEZ
tODD tDZO
tODD tDZO
tORH
tODD
M5M44260CJ,TP-5,-5S Under development
MITSUBISHI LSIs
FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC
Fast Page Mode Byte Read Cycle
tRAS tCSH tCRP UCAS LCAS) tRCD tCAS tCAS tRSH tCAS
LCAS UCAS)
tRAD tASR tRAH tASC tCAH tASC tCAH tCPRH tASC tCAH tASR
ADDRESS
A0~A8
ADDRESS
COLUMN ADDRESS1
COLUMN ADDRESS2
COLUMN ADDRESS3
tRAL tRCS tRCH tRCS tRRH tRCH tRCS
tRCH
DQ1~DQ8 DQ9~DQ16) (INPUTS)
DQ1~DQ8 DQ9~DQ16) (OUTPUTS) tDZC DQ9~DQ16 DQ1~DQ8) (INPUTS) tCLZ DQ9~DQ16 DQ1~DQ8) (OUTPUTS)
Hi-Z Hi-Z
Hi-Z
tDZC
Hi-Z
tDZC
tCDD
tCAC tOFF
tCAC tCLZ tOFF
DATA VALID-2
tCAC tCLZ tOFF
DATA VALID-3
DATA VALID-1
tRAC tDZO tOEA tOCH
tCPA tOEA tOEZ tOCH
tCPA tOEA tOEZ tOCH tOEZ
tODD tDZO tODD tDZO tORH tODD
M5M44260CJ,TP-5,-5S Under development
MITSUBISHI LSIs
FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC
Fast Page Mode Write Cycle (Early Write)
tRAS tCSH tCRP LCAS/UCAS tASR tRAH tASC tCAH tASC tCAH tASC tCAH tRCD tCAS tCAS tRSH tCAS
tASR
A0~A8
ADDRESS
COLUMN ADDRESS1
COLUMN ADDRESS2
COLUMN ADDRESS3
ADDRESS
tWCS DQ1~DQ16 (INPUTS)
tWCH
tWCS
tWCH
tWCS
tWCH
DATA VALID-2
DATA VALID-1
DATA VALID-3
DQ1~DQ16 (OUTPUTS)
Hi-Z
M5M44260CJ,TP-5,-5S Under development
MITSUBISHI LSIs
FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC
Fast Page Mode Byte Write Cycle (Early Write)
tRAS tCSH tCRP UCAS LCAS) tRCD tCAS tCAS tRSH tCAS
LCAS UCAS)
tASR tRAH tASC tCAH tASC tCAH tASC tCAH tASR
A0~A8
ADDRESS
COLUMN ADDRESS1
COLUMN ADDRESS2
COLUMN ADDRESS3
ADDRESS
tWCS
tWCH
tWCS
tWCH
tWCS
tWCH
DQ1~DQ8 DQ9~DQ16) (INPUTS)
DQ1~DQ8 DQ9~DQ16) (OUTPUTS) DQ9~DQ16 DQ1~DQ8) (INPUTS)
Hi-Z
DATA VALID-1
DATA VALID-2
DATA VALID-3
DQ9~DQ16 DQ1~DQ8) (OUTPUTS)
Hi-Z
M5M44260CJ,TP-5,-5S Under development
MITSUBISHI LSIs
FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC
Fast-Page Mode Write Cycle (Delayed Write)
tRAS tCSH tCRP LCAS/UCAS tASR tRAH tASC tCAH tASC tRWL tCAH tCWL tRCD tCAS tCAS tRSH
tASR
ADDRESS
A0~A8
ADDRESS
COLUMN ADDRESS1
COLUMN ADDRESS2
tRCS tWCH tDZC DQ1~DQ16 (INPUTS)
Hi-Z
tCWL
tRCS
tWCH
DATA VALID-1
tDZC
Hi-Z
DATA VALID-2
tCLZ DQ1~DQ16 (OUTPUTS)
Hi-Z Hi-Z
tCLZ
Hi-Z
tDZO
tOEZ tODD tDZO
tOEZ tODD
tOEH
M5M44260CJ,TP-5,-5S Under development
MITSUBISHI LSIs
FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC
Fast-Page Mode Byte Write Cycle (Delayed Write)
tRAS tCRP tRCD tCSH tCAS UCAS LCAS) tRSH tCAS
LCAS UCAS)
tASR tRAH tASC tCAH tASC tCAH tRWL tCWL tASR
ADDRESS
A0~A8
ADDRESS
COLUMN ADDRESS1
COLUMN ADDRESS2
tCWL tRCS tWCH
tRCS
tWCH
DQ1~DQ8 DQ9~DQ16) (INPUTS)
DQ1~DQ8 DQ9~DQ16) (OUTPUTS) tDZC DQ9~DQ16 DQ1~DQ8) (INPUTS)
Hi-Z
Hi-Z
DATA VALID-1
tDZC
Hi-Z
DATA VALID-2
tCLZ DQ9~DQ16 DQ1~DQ8) (OUTPUTS)
Hi-Z Hi-Z
tCLZ
Hi-Z
tOEZ tDZO tODD tDZO
tOEZ tODD tOEH
M5M44260CJ,TP-5,-5S Under development
MITSUBISHI LSIs
FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC
Fast Page Mode Read-Write, Read-Modify-Write Cycle
tRAS tCSH tCRP LCAS/UCAS tASR tRAH tRAD tASC tCAH
COLUMN ADDRESS1
tRWL tCAS tPRWC tCAS
tRCD
tASC
tCAH
tCWL
tASR
ADDRESS
A0~A8
ADDRESS
COLUMN ADDRESS2
tAWD tRCS tRWD tDZC DQ1~DQ16 (INPUTS) tCLZ DQ1~DQ16 (OUTPUTS)
Hi-Z
DATA VALID-1
tCWD
tCWL
tAWD tRCS tCWD
tCPWD
DATA VALID-1
tDZC
Hi-Z
DATA VALID-2
Hi-Z
tCAC
tCAC tCLZ
Hi-Z
DATA VALID-2
Hi-Z
tRAC tDZO tOEA
tODD tOEZ tDZO
tCPA tOEA
tODD tOEZ tOEH
M5M44260CJ,TP-5,-5S Under development
MITSUBISHI LSIs
FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC
Fast Page Mode Byte Read-Write, Read-Modify-Write Cycle
tRAS tCSH tCRP UCAS LCAS) tRCD tCAS tPRWC tCAS
tRWL
LCAS UCAS)
tASR tRAD tRAH tASC tCAH
COLUMN ADDRESS1
tASC
tCAH
tCWL
tASR
ADDRESS
A0~A8
ADDRESS
COLUMN ADDRESS2
tRCS
tAWD tCWD
tCWL tRCS
tAWD tCWD
tRWD
tCPWD
DQ1~DQ8 DQ9~DQ16) (INPUTS)
DQ1~DQ8 DQ9~DQ16) (OUTPUTS) tDZC DQ9~DQ16 DQ1~DQ8) (INPUTS)
Hi-Z
Hi-Z
DATA VALID-1
tDZC
Hi-Z
DATA VALID-2
tCAC tCLZ
tCAC tCLZ
DATA VALID-1
DQ9~DQ16 DQ1~DQ8) (OUTPUTS)
Hi-Z
Hi-Z
DATA VALID-2
Hi-Z
tRAC tDZO tOEA
tODD tOEZ tDZO
tCPA tOEA
tODD tOEZ
tOEH
M5M44260CJ,TP-5,-5S Under development
MITSUBISHI LSIs
FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC
Self Refresh Cycle
(Note28)
tRASS
tRPS
tRPC tRPC tCSR LCAS/UCAS tCPN tASR A0~A8 tRCH tCDD DQ1~DQ16 (INPUTS) tOFF DQ1~DQ16 (OUTPUTS) tOEZ tODD
Hi-Z Hi-Z ADDRESS COLUMN ADDRESS
tCHS
tCRP
tRCS
M5M44260CJ,TP-5,-5S Under development
MITSUBISHI LSIs
FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC
Note Self refresh sequence refreshing methods should used properly depending pulse width (tRASS) signal during self refresh period. Distributed refresh during Read/Write operation Timing Diagram
Read Write Cycle Self Refresh Cycle Read Write Cycle
tNSD
tRASS100µs
tSND
last refresh cycle
first refresh cycle
Table
Read Write Cycle distributed refresh only distributed refresh Read Write Self Refresh tNSD250µs tNSD16µs Self Refresh Read Write tSND250µs tSND16µs
Definition distributed refresh tREF tREF tREF
refresh cycle read/write cycles refresh cycle refresh cycle read/write cycles
Definition distributed refresh (Including extended refresh) distributed refresh performs more than constant period (250µs max.) cycles within Definition only distributed refresh combinations nine address signals (A0~A8) selected during constant period (16µs max.) only refresh cycles within Note: Hidden refresh used instead refresh. RAS/CAS refresh used instead only refresh. distributed refresh Switching from read/write operation self refresh operation. time interval from falling edge signal last refresh cycle during read/write operation period falling edge signal start self refresh operation should within tNSD (shown table
Switching from self refresh operation read/write operation. time interval from rising edge signal self refresh operation falling edge signal first refresh cycle during read/write operation period should within tSND (shown table only distributed refresh Switching from read/write operation self refresh operation. time interval tNSD from falling edge signal last only refresh cycle during read/write operation period falling edge signal start self refresh operation should within 16µs. Switching from self refresh operation read/write operation. time interval tSND from rising edge signal self refresh operation falling edge signal first refresh cycle during read/write operation period should within 16µs.
M5M44260CJ,TP-5,-5S Under development
MITSUBISHI LSIs
FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC
Burst refresh during Read/Write operation Timing diagram
Read Write Self Refresh Read Write
tNSB
tRASS100µs
tSNB
refresh cycles cycles last refresh Cycles
first refresh cycles
refresh cycles cycles
Table
Read Write Cycle burst refresh only burst refresh Read Write Self Refresh tNSB8.2ms Self Refresh Read Write tSNB8.2ms
tNSB+tSNB8.2ms
Definition burst refresh
8.2ms
refresh cycles cycles
read/write cycles
Definition burst refresh burst refresh performs more than continuous cycles within Definition only burst refresh combination nine address signals (A0~A8) selected during continuous only refresh cycles within burst refresh Switching from read/write operation self refresh operation. time interval tNSB from falling edge signal first refresh cycle during read/write operation period falling edge signal start self refresh operation should within Switching from self refresh operation read/write operation. time interval tSNB from rising edge signal self refresh operation falling edge signal last refresh cycle during read/write operation period should within only burst refresh Switching from read/write operation self refresh operation. time interval from falling edge signal first only refresh cycle during read/write operation period falling edge signal start self refresh operation should within tNSB (shown table Switching from self refresh operation read/write operation. time interval from rising edge signal self refresh operation falling edge signal last only refresh cycle during read/write operation period should within tSNB (shown table
M5M44260CJ,TP-5,-5S Under development

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