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HYPER PAGE MODE 4194304-BIT 1048576-WORD 4-BIT DYNAMIC HYPER PAGE MODE


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MITSUBISHI LSIs MITSUBISHI LSIs
HYPER PAGE MODE 4194304-BIT 1048576-WORD 4-BIT DYNAMIC HYPER PAGE MODE 4194304-BIT 1048576-WORD 4-BIT DYNAMIC
This family 1048576-word 4-bit dynamic RAMs, fabricated with high performance CMOS process,and ideal largecapacity memory systems where high speed, power dissipation, costs essential. quadruple-layer polysilicon process combined with silicide technology single-transistor dynamic storage stacked capacitor cell provide high circuit density reduced costs. Multiplexed address inputs permit both reduction pins increase system densities. Self extended refresh current enough battery back-up application.
CONFIGURATION (TOP VIEW)
FEATURES
Type name
M5M44405CXX-5,-5S M5M44405CXX-6,-6S M5M44405CXX-7,-7S
access access time time (max.ns) (max.ns)
Address Cycle Power access access time dissipatime time tion (max.ns) (max.ns) (min.ns) (typ.mW)
XX=J,TP
Outline 26P0J (300mil SOJ)
Standard SOJ, TSOP(II) Single 5V±10%supply stand-by power dissipation CMOS lnput level 5.5mW (Max) CMOS lnput level 550µW (Max) operating power dissipation M5M44405Cxx-5,-5S 687.5mW (Max) M5M44405Cxx-6,-6S 550.0mW (Max) M5M44405Cxx-7,-7S 467.5mW (Max) Self refresh capabiility Self refresh current 120µA(max) Extended refresh capability Extended refresh current 120µA(max) Hyper-page mode (1024-bit random access), Read-modify- write, RAS-only refresh before refresh, Hidden refresh, self refresh(-5S,-6S,-7S) capabilities Early-write mode control output buffer impedance inputs, output compatible capacitance 1024 refresh cycles every 16.4ms (A0~A9) 1024refresh cycle every 128ms (A0~A9) 4-bit parallel test mode capability Applicable self refresh version (M5M44405CJ,TP-5S,-6S,-7S option) only
Outline 26P3Z-E (300mil TSOP)
APPLICATION
Main memory unit computers, Microcomputer memory, Refresh memory CRT, Frame Buffer memory
name A0~A9 DQ1~DQ4 Function Address Inputs Data Inputs Outputs Address Strobe Input Column Address Strobe Input Write Control Input Output Enable Input Power Supply (+5V) Ground (0V)
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
HYPER PAGE MODE 4194304-BIT 1048576-WORD 4-BIT DYNAMIC
FUNCTION
M5M44405CJ, provide, addition normal read, write, read-modify-write operations,a number other functions, e.g., hyper page mode, RAS-only refresh, delayed-write. input conditions each shown Table
Table Input conditions each mode
Operation Read Write (Early write) Write (Delayed write) Read-modify-write RAS-only refresh Hidden refresh before refresh Self refresh Stand-by Inputs
address Column address
Input/Output Output Input
Refresh Remark
HyperPage mode identical
Note active, nonactive, don' care, valid, invalid, applied, open
BLOCK DIAGRAM
COLUMN ADDRESS STROBE INPUT ADDRESS STROBE INPUT WRITE CONTROL INPUT A0~A9
(5V) CLOCK GENERATOR CIRCUIT (0V)
COLUMN DECODER
DATA BUFFERS
SENSE REFRESH AMPLIFER CONTROL
DATA BUFFERS
DATA INPUTS OUTPUTS
ADDRESS INPUTS
COLUMN ADDRESS BUFFER
DECODER
MEMORY CELL (4,194,304 BITS)
OUTPUT ENABLE INPUT
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
HYPER PAGE MODE 4194304-BIT 1048576-WORD 4-BIT DYNAMIC
ABSOLUTE MAXIMUM RATINGS
Symbol Topr Tstg Parameter Supply voltage Input voltage Output voltage Output current Power dissipation Operating temperature Storage temperature Conditions With respect Ratings -1~7 -1~7 -1~7 1000 0~70 -65~150 Unit
Ta=25°C
RECOMMENDED OPERATING CONDITIONS (Ta=0~70°C, unless otherwise noted) (Note
Symbol Supply voltage Supply voltage High-level input voltage, inputs DQ1~4 Low-level input voltage others Parameter Limits -1.0 -2.0 Unit
Note voltage values with respect Vss.
ELECTRICAL CHARACTERISTICS (Ta=0~70°C, VCC= 5V±10%, VSS=0V, unless otherwise noted)
Symbol ICC1 (AV) Parameter High-level output voltage Low-level output voltage Off-state output current Input current Test conditions =-5mA 4.2mA floating VOUT 5.5V +6.5V, Other inputs pins=0V
(Note
Limits
ICC2 (AV)
M5M44405C-5,-5S RAS, cycling Average supply current from Vcc, operating M5M44405C-6,-6S tRC=tWC=min. (Note 3,4,5) M5M44405C-7,-7S output open RAS= =VIH, output open Supply current from M5M44405C RAS= VCC-0.5V stand-by (Note output open M5M44405C(S) Average supply current M5M44405C-5,-5S from Vcc, refreshing M5M44405C-6,-6S (Note 3,5) M5M44405C-7,-7S M5M44405C-5,-5S Average supply current from Vcc, Hyper-PageM5M44405C-6,-6S Mode (Note 3,4,5) M5M44405C-7,-7S M5M44405C-5,-5S Average supply current from Vcc, before M5M44405C-6,-6S refresh mode (Mote M5M44405C-7,-7S cycling, CAS= tRC=min. output open RAS=VIL, cycling tPC=min. output open before refresh cycling tRC=min. output open
cycling 0.2V before refresh cycling 0.2V VCC-0.2V 0.2V VCC-0.2V 0.2V(Except falling edge) VCC-0.2V 0.2V VCC-0.2V A0~A9 0.2V VCC-0.2V, DQ=open tRC=125µs, tRAS=tRAS min~1µs
ICC3 (AV)
ICC4(AV)
Unit
ICC6(AV)
ICC8(AV)
Average supply current from Vcc, Extended-Refresh cycle
(Note
ICC9(AV)
Average supply current from Vcc, Self-Refresh cycle (Note
M5M44405C(S)
RAS=CAS 0.2V output open
Note Current flowing into positive, negative. Note ICC1(AV), ICC3 (AV), ICC4(AV) ICC6(AV) dependent cycle rate. Maximum current measured fastest cycle rate. Note ICC1(AV) ICC4(AV) dependent output loading. Specified values obtained with output open. Note Column Address changed once less while RAS=VIL CAS=VIH.
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
HYPER PAGE MODE 4194304-BIT 1048576-WORD 4-BIT DYNAMIC
CAPACITANCE (Ta=0~70°C, VCC= 5V±10%, VSS=0V, unless otherwise noted)
Symbol (CLK) Parameter Input capacitance, address inputs Input capacitance, clock inputs Input/Output capacitance, data ports Test conditions VI=VSS f=1MHz VI=25mVrms Limits Unit
SWITCHING CHARACTERISTICS (Ta=0~70°C, VCC= 5V±10%, VSS=0V, unless otherwise noted, notes 6,14,15)
Limits Symbol tCAC tRAC tCPA tOEA tOHC tOHR tCLZ tOEZ tWEZ tOFF tREZ Parameter Access time from Access time from Column address access time Access time from precharge Access time from Output hold time from Output hold time from Output impedance time from Output disable time after high Output disable time after high Output disable time after high Output disable time after high (Note 7,8) (Note 7,9) (Note 7,10) (Note 7,11) (Note (Note (Note (Note (Note (Note 12,13) (Note 12,13)
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S
Unit
Note initial pause 200µs required after power-up followed minimum eight initialization cycles (RAS only refresh before refresh cycles). Note cycled during initial pause eight initialization cycles required after prolonged periods (greater than tREF(max)) inactivity before proper device operation achieved. Note Measured with load circuit equivalent 2TTL 100pF. reference levels measuring output signals 2.0V(VOH) 0.8V(VOL). Note Assumes that tRCD tRCD(max) tASC tASC(max) tCP(max). Note Assumes that tRCD tRCD(max) tRAD tRAD(max). tRCD tRAD greater than maximum recommended value shown this table, tRAC will increase amount that tRCD exceeds value shown. Assumes that tRAD tRAD(max) tASC tASC(max). Assumes that tCP(max) tASC tASC(max). tOEZ(max), tWEZ(max), tOFF(max) tREZ(max) defines time which output achieves high impedance state (IOUT ±10µA reference VOH(min) VOL(max). Output disabled after both high.
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
HYPER PAGE MODE 4194304-BIT 1048576-WORD 4-BIT DYNAMIC
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, Hyper-Page Mode Cycles)
(Ta=0~70°C, VCC= 5V±10%, VSS=0V, unless otherwise noted, notes 14,15) Limits Symbol tREF tREF tRCD tCRP tRPC tCPN tRAD tASR tASC tRAH tCAH tDZC tDZO tRDD tCDD tODD Refresh cycle time Refresh cycle time (Note Parameter
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S
Unit
16.4
16.4
16.4
high pulse width Delay time, Delay time, high Delay time, high high pulse width Column address delay time from address setup time before Column address setup time before address hold time after Column address hold time after Delay time, data Delay time, data Delay time, high data Delay time, high data Delay time, high data Transition time Note timing requirements assumed tT=2ns.
(Note (Note
(Note (Note (Note (Note (Note (Note
Note VIH(min) VIL(max) reference levels measuring timing input signals. Note tRCD(max) specified reference point only. tRCD less than tRCD(max), access time tRAC. tRCD greater than tRCD(max), access time controlled exclusively tCAC tAA. Note tRAD(max) specified reference point only. tRAD tRAD(max) tASC tASC(max), access time controlled exclusively tAA. Note tASC(max) specified reference point only. tRCD tRCD(max) tASC tASC(max), access time controlled exclusively tCAC. Note Either tDZC tDZO must satisfied. Note Either tRDD tCDD tODD must satisfied. Note measured between VIH(min) VIL(max).
Read Refresh Cycles
Limits Symbol tRAS tCAS tCSH tRSH tRCS tRCH tRRH tRAL tCAL tORH tOCH Read cycle time Parameter
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S
Unit
pulse width pulse width hold time after hold time after Read Setup time before Read hold time after high Read hold time after high Column address hold time Column address hold time hold time after hold time after Note Either tRCH tRRH must satisfied read cycle.
(Note (Note
10000 10000
10000 10000
10000 10000
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
HYPER PAGE MODE 4194304-BIT 1048576-WORD 4-BIT DYNAMIC
Write Cycle (Early Write Delayed Write)
Limits Symbol tRAS tCAS tCSH tRSH tWCS tWCH tCWL tRWL Parameter Write cycle time pulse width pulse width hold time after hold time after Write setup time before Write hold time after hold time after hold time after Write pulse width Data setup time before Data hold time after
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S
Unit
(Note
10000 10000
10000 10000
10000 10000
Read-Write Read-Modify-Write Cycles
Limits Symbol tRWC tRAS tCAS tCSH tRSH tRCS tCWD tRWD tAWD tOEH Parameter
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S
Unit
(Note Read write/read modify write cycle time 10000 10000 10000 pulse width pulse width 10000 10000 10000 hold time after hold time after Read setup time before (Note Delay time, (Note Delay time, (Note Delay time, address hold time after Note tRWC specified Note tWCS, tCWD, tRWD tAWD and, tCPWD specified reference points only. tWCS tWCS(min) cycle early write cycle pins will remain high impedance throughout entire cycle. tCWD tCWD(min), tRWD tRWD(min), tAWD tAWD(min) tCPWD tCPWD(min) (for fast page
mode cycle only), cycle read-modify-write cycle will contain data read from selected address. neither above condition (delayed write) access time until goes back VIH) indeterminate.
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
HYPER PAGE MODE 4194304-BIT 1048576-WORD 4-BIT DYNAMIC
Hyper page Mode Cycle (Read, Early Write, Read-Write, Read-Modify-Write Cycle, Read Write Cycle, Hi-Z control (Note
Limits Symbol tHPC tHPRWC tDOH tRAS tCPRH tCPWD tCHOL tOEPE tWPE tHCWD tHAWD tHPWD tHCOD tHAOD tHPOD Parameter (Note Hyper page mode read/write cycle time Hyper Page Mode read write/read modify write cycle time Output hold time from (Note pulse width read write cycle (Note high pulse width hold time after precharge (Note Delay time, precharge Hold time maintain data Hi-Z until access Pulse Width (Hi-Z control) Pulse Width (Hi-Z control) Delay time, after read Delay time, Address after read Delay time, precharge after read Delay time, high after read Delay time, Address high after read Delay time, precharge high after read
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S
Unit
100000
100000
100000
Note previously specified timing requirements switching characteristics applicable their respective Hyper page mode cycle. Note tHPC(min) specified case read-only early write-only Hyper Page Mode. Note tRAS(min) specified cycles input performed. Note tCP(max) specified reference point only.
before Refresh Cycle
Symbol tCSR tCHR tRSR tRHR tCAS
(Note
Limits Parameter setup time before hold time after Read setup time before Read hold time after pulse width
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S
Unit
Note Eight more before cycles instead eight cycles necessary proper operation before refresh mode.
Self Refresh Cycle
Symbol tRASS tRPS tCHS tRSR tRHR
(Note
Limits Parameter self refresh pulse width self refresh high precharge time self refresh hold time Read setup time before Read hold time after
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S
Unit
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
HYPER PAGE MODE 4194304-BIT 1048576-WORD 4-BIT DYNAMIC
Test Mode Specification (Note ELECTRICAL CHARACTERISTICS (Ta=0~70°C, VCC= 5V±10%, VSS=0V, unless otherwise noted) (Note
Symbol Parameter Test conditions Limits Unit
ICC1(AV)
ICC3(AV)
Average supply current M5M44405C-5,-5S RAS, cycling from VCC, M5M44405C-6,-6S tRC=tWC=min. operating (Note 3,4,5) M5M44405C-7,-7S output open Average supply current M5M44405C-5,-5S cycling, CAS=VIH from VCC, M5M44405C-6,-6S tRC=min. refreshing (Note 3,5) M5M44405C-7,-7S output open Average supply current M5M44405C-5,-5S from Vcc, Hyper-PageM5M44405C-6,-6S Mode (Note 3,4,5) M5M44405C-7,-7S Average supply current M5M44405C-5,-5S from VCC, before M5M44405C-6,-6S refresh mode (Note M5M44405C-7,-7S RAS=VIL, cycling tPC=min. output open before refresh cycling tRC=min. output open
ICC4(AV)
ICC6(AV)
Note previously specified electrical characteristics, switing characteristics, timing requirements applicable that test mode.
SWITCHING CHARACTERISTICS (Ta=0~70°C, VCC= 5V±10%, VSS=0V, unless otherwise noted, notes 6,14,15)
Limits Symbol tCAC tRAC tCPA tOEA Parameter Access time from Access time from Column address access time Access time from precharge Access time from (Note 7,8) (Note 7,9) (Note 7,10) (Note 7,11) (Note
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S
Unit
TIMING REQUIREMENTS (Ta=0~70°C, VCC= 5V±10%, VSS=0V, unless otherwise noted, notes 14,15) Read Refresh Cycles
Limits Symbol tRAS tCAS tCSH tRSH tRAL tCAL tORH tOCH Parameter Read cycle time pulse width pulse width hold time after hold time after Column address hold time Column address hold time hold time after hold time after
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S
Unit
10000 10000
10000 10000
10000 10000
Read-Write Read-Modify-Write Cycles
Limits Symbol tRWC tRAS tCAS tCSH tRSH tCWD tRWD tAWD Parameter Read write/read modify write cycle time pulse width pulse width hold time after hold time after Delay time, Delay time, Delay time, address (Note
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S
Unit
(Note (Note (Note
10000 10000
10000 10000
10000 10000
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
HYPER PAGE MODE 4194304-BIT 1048576-WORD 4-BIT DYNAMIC
Hyper page Mode Cycle (Read, Early Write, Read-Write, Read-Modify-Write Cycle, Read Write Cycle, Hi-Z control (Note
Limits Symbol tHPC tHPRWC tRAS tCPRH tCPWD tHCWD tHAWD tHPWD tHCOD tHAOD tHPOD Parameter (Note Hyper page mode read/write cycle time Hyper Page Mode read write/read modify write cycle time pulse width read write cycle (Note hold time after precharge (Note Delay time, precharge Delay time, after read Delay time, Address after read Delay time, precharge after read Delay time, high after read Delay time, Address high after read Delay time, precharge high after read
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S
Unit
100000
100000
100000
Test Mode Cycle
Limits Symbol tWSR tWHR Parameter Write setup time before Write hold time after
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S
Unit
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
HYPER PAGE MODE 4194304-BIT 1048576-WORD 4-BIT DYNAMIC
Timing Diagram Read Cycle
(Note
tRAS VIH- VIL- tCSH tCRP VIH- VIL- tRAD tASR A0~A9 VIH- VIL- tRAH
ADDRESS
tRCD
tRSH tCAS
tCRP
tRAL tCAL tASC tCAH
COLUMN ADDRESS
tASR
ADDRESS
tRCS VIH- VIL- tDZC DQ1~DQ4 (INPUTS) VIH- VIL- tCAC tCLZ
Hi-Z Hi-Z
tRRH tRCH
tCDD
tREZ tOHR
DATA VALID
tWEZ tOFF tOHC
Hi-Z
VOH- DQ1~DQ4 (OUTPUTS) VOL-
tRAC tDZO
tOHO tOEA tOCH tOEZ tODD
VIH- VIL- tORH
Note
Indicates don't care input. VIH(min) VIH(max) VIL(min) VIL(max) Indicates invalid output.
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
HYPER PAGE MODE 4194304-BIT 1048576-WORD 4-BIT DYNAMIC
Early Write Cycle
tRAS VIH- VIL- tCSH tCRP VIH- VIL- tASR VIH- VIL- tRAH tASC tCAH tASR
ADDRESS
tRCD
tRSH tCAS
tCRP
A0~A9
ADDRESS
COLUMN ADDRESS
tWCS VIH- VIL- DQ1~DQ4 (INPUTS) VIH- VIL-
tWCH
DATA VALID
VOH- DQ1~DQ4 (OUTPUTS) VOL-
Hi-Z
VIH- VIL-
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
HYPER PAGE MODE 4194304-BIT 1048576-WORD 4-BIT DYNAMIC
Delayed Write Cycle
tRAS VIH- VIL- tCSH tCRP VIH- VIL- tASR VIH- VIL- tRAH tASC tCAH tASR
ADDRESS
tCRP tRSH tCAS
tRCD
A0~A9
ADDRESS
COLUMN ADDRESS
tRCS VIH- VIL- tDZC tWCH DQ1~DQ4 (INPUTS) VIH- VIL- tCLZ VOH- DQ1~DQ4 (OUTPUTS) VOL-
Hi-Z Hi-Z
tCWL tRWL
DATA VALID
Hi-Z
tOHO tDZO VIH- VIL- tOEZ tODD
tOEH
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
HYPER PAGE MODE 4194304-BIT 1048576-WORD 4-BIT DYNAMIC
Read-Write, Read-Modify-Write Cycle
tRWC tRAS VIH- VIL- tCSH tCRP VIH- VIL- tRAD tASR A0~A9 VIH- VIL- tRAH
ADDRESS
tRCD
tRSH tCAS
tCRP
tASC
tCAH
COLUMN ADDRESS
tASR
ADDRESS
tRCS VIH- VIL-
tAWD tCWD tRWD
tCWL tRWL
tDZC DQ1~DQ4 (INPUTS) VIH- VIL-
Hi-Z
DATA VALID
tCAC tCLZ
Hi-Z Hi-Z
VOH- DQ1~DQ4 (OUTPUTS) VOL-
DATA VALID
tRAC tDZO tOEA
tODD tOHO tOEZ
tOEH
VIH- VIL-
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
HYPER PAGE MODE 4194304-BIT 1048576-WORD 4-BIT DYNAMIC
Hyper Page Mode Read Cycle
tRAS VIH- VIL- tCSH tCRP VIH- VIL- tRAD tASR A0~A9 VIH- VIL- tRAH
ADDRESS
tHPC tCAS tCAS
tRCD
tRSH tCAS
tCPRH tASC tCAH
COLUMN-1
tASC
tCAH
tASC
tCAH
tASR
ADDRESS
COLUMN-2
COLUMN-3
tRCS tCAL VIH- VIL- tDZC tCAL
tRAL tCAL
tRRH tRCH
tRDD tCDD DQ1~DQ4 (INPUTS) VIH- VIL- tCAC tCLZ VOH- DQ1~DQ4 (OUTPUTS) VOL-
Hi-Z DATA VALID-1 DATA VALID-2 Hi-Z
tWEZ
tCAC tDOH
tCAC tDOH
tREZ tOHR tOFF tOHC
DATA VALID-3
tRAC tDZO VIH- VIL-
tCPA tOEA tOCH
tCPA
tOHO tOEZ
tODD
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
HYPER PAGE MODE 4194304-BIT 1048576-WORD 4-BIT DYNAMIC
Hyper Page Mode Early Write Cycle
tRAS VIH- VIL- tCSH tCRP VIH- VIL- tRAH
ADDRESS
tRCD
tCAS
tHPC tCAS
tRSH tCAS tCRP
tASR A0~A9 VIH- VIL-
tASC
tCAH
tASC
tCAL tCAH
COLUMN-2
tASC
tCAL tCAH
COLUMN-3
tASR
ADDRESS
COLUMN-1
tWCS VIH- VIL- DQ1~DQ4 (INPUTS) VIH- VIL-
tWCH
tWCS
tWCH
tWCS
tWCH
DATA VALID-1
DATA VALID-2
DATA VALID-3
VOH- DQ1~DQ4 (OUTPUTS) VOL-
Hi-Z
VIH- VIL-
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
HYPER PAGE MODE 4194304-BIT 1048576-WORD 4-BIT DYNAMIC
Hyper Page Mode Read-Write, Read-Modify-Write Cycle
tRAS VIH- VIL- tCSH tCRP VIH- VIL- tASR A0~A9 VIH- VIL- tRAD tRAH tASC tCAH
COLUMN-1
tHPRWC tCAS tCAS
tRWL
tRCD
tCRP
tASC
tCAH
tCWL
tASR
ADDRESS
ADDRESS
COLUMN-2
tAWD tRCS VIH- VIL- tRWD tDZC DQ1~DQ4 (INPUTS) VIH- VIL-
Hi-Z
tCWL tRCS
tAWD tCWD
tCWD
tCPWD
DATA VALID-1
tDZC
Hi-Z
DATA VALID-2
tCAC tCLZ
tCAC tCLZ
DATA VALID
VOH- DQ1~DQ4 (OUTPUTS) VOL-
Hi-Z
Hi-Z
tRAC tDZO tOEA
DATA VALID
Hi-Z
tODD tOHO tOEZ tDZO
tCPA tOEA
tODD tOHO tOEZ
tOEH
VIH- VIL-
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
HYPER PAGE MODE 4194304-BIT 1048576-WORD 4-BIT DYNAMIC
Hyper Page Mode Cycle
tRAS tRWL VIH- VIL- tCSH tCRP VIH- VIL- tRAD tASR A0~A9 VIH- VIL- tRAH tASC tCAH tASC tCAH tASC tCAH tRCD tCAS tHPC tCAS tHPRWC tCAS tCWL
tCRP
tASR
ADDRESS
ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
tRCS tCAL VIH- VIL- tDZC
tWCS
tWCH tCAL
tCPWD tAWD tCWD
tDZC
DQ1~DQ4 (INPUTS)
VIH- VIL- tCLZ tCAC
DATA VALID-2
DATA VALID-3
tWEZ
DATA VALID
tCAC tCLZ
DATA VALID
VOH- DQ1~DQ4 (OUTPUTS) VOL-
Hi-Z
tRAC tDZO
tOEA tOCH
tOHO tOEZ tDZO
tCPA tOEA
tOHO tOEZ tOEH
VIH- VIL- tODD tODD
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
HYPER PAGE MODE 4194304-BIT 1048576-WORD 4-BIT DYNAMIC
Hyper Page Mode Cycle
VIH- VIL-
VIH- VIL- tASC A0~A9 VIH- VIL- tCAL VIH- VIL- tHCWD tHAWD tHPWD DQ1~DQ4 (INPUTS) VIH- VIL- tCPA VOH- DQ1~DQ4 (OUTPUTS) VOL- tHCOD tHAOD tHPOD VIH- VIL- tWEZ
DATA VALID-1 Hi-Z Hi-Z
tCAS tCAH
COLUMN-1
tCAS tASC tCAH
COLUMN-2
tASC
tCAH
COLUMN-3
tRCH tWCS
tCAL tWCH
DATA VALID-2
tDZC
Hi-Z
tCAC
tCAC tCPA tCLZ
DATA VALID-3
tOHO tOEZ tODD
tDZC
tOEA
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
HYPER PAGE MODE 4194304-BIT 1048576-WORD 4-BIT DYNAMIC
Hyper Page Mode Read Cycle Hi-Z control
tRAS VIH- VIL- tCSH tCRP VIH- VIL- tRAD tASR A0~A9 VIH- VIL- tRAH
ADDRESS
tRCD
tCAS
tHPC tCAS
tRSH tCAS tCRP
tCPRH tASC tCAH
COLUMN-1
tASC
tCAH
tASC
tCAH
tASR
ADDRESS
COLUMN-2
COLUMN-3
tRCS VIH- VIL-
tRAL
tRRH tRCH
tWEZ tDZC DQ1~DQ4 (INPUTS) VIH- VIL- tCAC tCLZ VOH- DQ1~DQ4 (OUTPUTS) VOL-
Hi-Z DATA VALID-1 HI-Z
tRDD tCDD
tCAC tDOH
DATA VALID-1 DATA VALID-2
tCAC tCLZ
Hi-Z
tREZ tOHR tOFF tOHC
DATA VALID-3
tRAC tDZO VIH- VIL- tOEA
tOEZ tOHO tOCH tOEA
tCPA tOHO
tCPA tCHOL tOEZ
tOHO tOEZ
tOEPE
tOEPE
tODD
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
HYPER PAGE MODE 4194304-BIT 1048576-WORD 4-BIT DYNAMIC
Hyper Page Mode Read Cycle Hi-Z control
tRAS VIH- VIL- tCSH tCRP VIH- VIL- tRAD tASR A0~A9 VIH- VIL- tRAH
ADDRESS
tHPC tCAS tCAS
tRSH tCAS tCRP
tRCD
tCPRH tASC tCAH
COLUMN-1
tASC
tCAH
tASC
tCAH
COLUMN-3
tASR
ADDRESS
COLUMN-2
tRCS VIH- VIL- tDZC DQ1~DQ4 (INPUTS) VIH- VIL- tCAC tCLZ VOH- DQ1~DQ4 (OUTPUTS) VOL-
Hi-Z DATA VALID-1
tRAL tRCH tRCS
tRRH tRCH
tWPE
Hi-Z
tRDD tCDD
tWEZ
tCAC tWEZ tDOH
DATA VALID-2
tCAC tCLZ
Hi-Z
tREZ tOHR tOFF tOHC
DATA VALID-3
tRAC tDZO
tOEA tOCH
tCPA
tCPA
tOHO tOEZ
VIH- VIL- tODD
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
HYPER PAGE MODE 4194304-BIT 1048576-WORD 4-BIT DYNAMIC
RAS-only Refresh Cycle
tRAS VIH- VIL- tCRP VIH- VIL- tASR A0~A9 VIH- VIL- tRAH tASR
ADDRESS ADDRESS
tRPC
tCRP
VIH- VIL-
DQ1~DQ4 (INPUTS)
VIH- VIL-
VOH- DQ1~DQ4 (OUTPUTS) VOL-
Hi-Z
VIH- VIL-
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
HYPER PAGE MODE 4194304-BIT 1048576-WORD 4-BIT DYNAMIC
before Refresh Cycle, Extended Refresh Cycle
VIH- VIL- tRPC tCSR VIH- VIL- tCPN tASR A0~A9 VIH- VIL- tRCH VIH- VIL- tRRH tRSR tRHR tRSR tRHR
ADDRESS COLUMN ADDRESS
tRAS
tRAS
tCHR
tRPC
tCSR
tCHR
tRPC
tCRP
tRCS
DQ1~DQ4 (INPUTS)
VIH- VIL- tREZ tOHR tOFF tOHC
VOH- DQ1~DQ4 (OUTPUTS) VOL- tOHO tOEZ VIH- VIL-
Hi-Z
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
HYPER PAGE MODE 4194304-BIT 1048576-WORD 4-BIT DYNAMIC
Hidden Refresh Cycle (Read) (Note
tRAS VIH- VIL- tRCD tRSH tCHR tRAS
tCRP VIH- VIL-
tASR A0~A9 VIH- VIL-
tRAD tRAH tASC
ADDRESS
tASR tCAH
COLUMN ADDRESS ADDRESS
tRCS tRAL tRCH VIH- VIL- tDZC DQ1~DQ4 (INPUTS) VIH- VIL- tCAC tCLZ VOH- DQ1~DQ4 (OUTPUTS) VOL-
Hi-Z DATA VALID Hi-Z
tRRH
tCDD tRDD
tOFF tOHC
tREZ tOHR
Hi-Z
tRAC tDZO VIH- VIL-
tOEA tORH
tOHO tOEZ tODD
Note Early write, delayed write, read write read modify write cycle applicable instead read cycle. Timing requirements output state same that each cycle shown above.
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
HYPER PAGE MODE 4194304-BIT 1048576-WORD 4-BIT DYNAMIC
Self Refresh Cycle *(Note
VIH- VIL- tRPC tCSR VIH- VIL- tCPN
tRASS
tRPS
tRPC tCHS tCRP
tASR A0~A9 VIH- VIL- tRRH tRCH VIH- VIL- tRDD tCDD DQ1~DQ4 (INPUTS) VIH- VIL-
Hi-Z ADDRESS COLUMN ADDRESS
tRSR
tRHR
tRCS
tREZ tOHR tOFF tOHC
Hi-Z
VOH- DQ1~DQ4 (OUTPUTS) VOL- tOHO tOEZ VIH- VIL- tODD
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
HYPER PAGE MODE 4194304-BIT 1048576-WORD 4-BIT DYNAMIC
Test Mode Cycle (Note
VIH- VIL- tRPC VIH- VIL- tCPN VIH- VIL- tWSR tRCH VIH- VIL- tWHR tASR
ADDRESS COLUMN ADDRESS
tRAS
tCSR
tCHR
tRPC
tCRP
A0~A9
tRCS
DQ1~DQ4 (INPUTS)
VIH- VIL- tOFF
VOH- DQ1~DQ4 (OUTPUTS) VOL- tOEZ VIH- VIL-
Hi-Z
Note cycle also avaiilable initialization cycle, this case device enters test mode. test mode function initiated with before cycle(WCBR cycle) specified above timing diagram. test mode function terminated either before RAS(CBR) refresh only refresh cycle. During test mode, device internally organized 4-bits wide (256-kilobytes deep) each (input/output) port. addressing A0,A1(column only) required. During write cycle, data each (input) written parallel into 4-bits each port written independently each port. During read cycle, each (output) indicates independently HIGH state 4-bits equal, state bits differ. During test mode operation, WCBR cycle used perform refresh.
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
HYPER PAGE MODE 4194304-BIT 1048576-WORD 4-BIT DYNAMIC
Note Self refresh sequence refreshing methods should used properly depending pulse width(tRASS) signal during self refresh period. Distributed refresh during Read/Write operation Timing Diagram
Read /Write Cycle Self Refresh Cycle Read /Write Cycle
tNSD
tRASS100µs
tSND
last refresh cycle first refresh cycle
Table
Read/Write Cycle distributed refresh only distributed refresh Read/Write Self Refresh tNSD125µs tNSD16µs Self Refresh Read/Write tSND125µs tSND16µs
Definition distributed refresh tREF tREF/1024 tREF/1024
refresh cycle read/write cycles refresh cycle refresh cycle read/write cycles
Definition distributed refresh (Including extended refresh) distributed refresh performs more than 1024 constant period (125µs max.) cycles within 128ms. Definition only distributed refresh combinations nine address signals (A0~A9) selected during 1024 constant period (16µs max.) only refresh cycles within 16.4ms. Note: Hidden refresh used instead refresh. RAS/CAS refresh used instead only refresh. distributed refresh Switching from read/write operation self refresh operation. time interval from falling edge signal last refresh cycle during read/write operation period falling edge signal start self refresh operation should within tNSD (shown table Switching from self refresh operation read/write operation. time interval from rising edge signal self refresh operation falling edge signal first refresh cycle during read/write operation period should within tSND(shown table only distributed refresh Switching from read/write operation self refresh operation. time interval tNSD from falling edge signal last only refresh cycle during read/write operation period falling edge signal start self refresh operation should within 16µs. Switching from self refresh operation read/write operation. time interval tSND from rising edge signal self refresh operation falling edge signal first refresh cycle during read/write operation period should within 16µs.
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
HYPER PAGE MODE 4194304-BIT 1048576-WORD 4-BIT DYNAMIC
Burst refresh during Read/Write operation Timing diagram
Read /Write Self Refresh Read /Write
tNSB
tRASS100µs
tSNB
first refresh cycles refresh cycles 1024 cycles refresh cycles 1024 cycles last refresh Cycles
Table
Read/Write Cycle burst refresh only burst refresh Read/Write Self Refresh tNSB16.4ms Self Refresh Read/Write tSNB16.4ms
tNSB+tSNB16.4ms
Definition burst refresh
16.4ms
refresh cycles 1024cycles read/write cycles
Definition burst refresh burst refresh performs more than 1024 continuous cycles within 16.4ms. Definition only burst refresh combination nine address signals (A0~A9) selected during 1024 continuous only refresh cycles within 16.4ms. burst refresh Switching from read/write operation self refresh operation. time interval from falling edge signal first refresh cycle during read/write operation period falling edge signal start self refresh operation should within 16.4ms. Switching from self refresh operation read/write operation. time interval snob from rising edge signal self refresh operation falling edge signal last refresh cycle during read/write operatio period should within 16.4ms. only burst refresh Switching from read/write operation self refresh operation. time interval from falling edge signal first only refresh cycle during read/write operation period falling edge signal start self refresh operation should within tNSB (Shown table Switching from self refresh operation read/write operation. time interval from rising edge signal self refresh operation falling edge signal last only refresh cycle during read/write operation period should within tSNB (shown table
M5M44405CJ,TP-5,-5S:Under development

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