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16,777,216-BIT (1048,576-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERA


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M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY DESCRIPTION
MITSUBISHI Mobile FLASH M5M29GB/T161BWG 3.3V-only high speed 16,777,216-bit CMOS boot block Flash Memories with alternating (Back Ground Operation) feature. feature device allows Program Erase operations performed bank while device simultaneously allows Read operations performed other bank. This feature suitable mobile personal computing, communication products. M5M29GB/T161BWG fabricated CMOS technology peripheral circuits DINOR(Divided line NOR) architecture memory cells, available 6x8-balls (0.75mm ball pitch)
FEATURES
Organization
1048,576 word 16bit
(M5M29GB/T161BWG)
Boot Block Bottom Boot M5M29GB161BWG Boot M5M29GT161BWG Other Functions Soft Ware Command Control Selective Block Lock Erase Suspend/Resume Program Suspend/Resume Status Register Read Alternating Back Ground Program/Erase Operation Between Bank(I) Bank(II) Package 8.5mm (Chip Scale Package) balls, 0.75mm ball pitch
2.7~3.6V Supply voltage
Access time
90ns (Max.)
Power Dissipation (Max. 5MHz) Read (After Automatic Power saving) 0.33µW (typ.) (Max.) Program/Erase 0.33µW (typ.) Standby Deep power down mode 0.33µW (typ.) Auto program Bank(I) (typ.) Program Time Program Unit (Byte Program) 1word (Page Program) 128word Auto program Bank(II) (typ.) Program Time 128word Program Unit Auto Erase (typ.) Erase time Erase Unit Bank(I) Boot Block 16Kword Parameter Block 16Kword Bank(II) Main Block 32Kword Program/Erase cycles 100Kcycles
APPLICATION
Digital Cellular Phone Telecommunication Mobile Computing Machine (Personal Digital Assistance) Navigation System Video Game Machine
CONFIGURATION (TOP VIEW)
8.5mm
WP2#
WP1#
7.0mm
INDEX
M5M29GB/T161BWG CSP(0.75mm ball pitch):48FJA 16-bit version CONNECTION
Mar.1999. Rev2.1
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
BLOCK DIAGRAM
ADDRESS INPUTS
WP1# WP2#
WORD PAGE BUFFER Main Block 32KW
(3.3V)
Bank(II)
(0V)
Main Block
Parameter Block7 Parameter Block6 Parameter Block5 Parameter Block4 Parameter Block3 Parameter Block2 Parameter Block1 Boot Block
X-DECODER Bank(I)
32KW
16KW 16KW 16KW 16KW 16KW 16KW 16KW 16KW
Y-DECODER
Y-GATE SENSE AMP.
STATUS REGISTER
CHIP ENABLE INPUT OUTPUT ENABLE INPUT WRITE ENABLE INPUT WRITE PROTECT INPUT WRITE PROTECT INPUT RESET/POWER DOWN INPUT
MULTIPLEXER
INPUT/OUTPUT BUFFERS
DQ15 DQ14DQ13 DQ12
DQ3DQ2 DQ1DQ0
DATA INPUTS/OUTPUTS
M5M29GB/T161BWG version)
Mar.1999. Rev2.1
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY FUNCTION
M5M29GB/T161BWG includes on-chip program/erase control circuitry. Write State Machine (WSM) controls block erase byte/page program operations. Operational modes selected commands written Command User Interface (CUI). Status Register indicates status when successfully completes desired program block erase operation. Deep Powerdown mode enabled when GND, minimizing power consumption. Read M5M29GB/T161BWG three read modes, which accesses memory array, Device Identifier Status Register. appropriate read command required written CUI. Upon initial device powerup after exit from deep powerdown, M5M29GB/T161BWG automatically resets read array mode. read array mode, level input OE#, high level input RP#, address signals address inputs (A19-A0:M5M29GB/T161BWG) output data addressed location data input/output (D15-D0:M5M29 GB/T161BWG). Write Writes enables reading memory array data, device identifiers reading clearing Status Register. They also enable block erase program. written bringing level, while level high level. Address data latched earlier rising edge CE#. Standard micro-processor write timings used. Deep Power-Down When VIL, device deep powerdown mode power consumption substantially low. During read modes, memory deselected data input/ output high-impedance(High-Z) state. After return from powerdown, reset Read Array Status Register cleared value 80H. During block erase program modes, will abort either operation. Memory array data block being altered become invalid. Automatic Power-Saving (APS) Automatic Power-Saving minimizes power consumption during read mode. device automatically turns this mode when addresses isn't changed more than 200ns after last alternation. power consumption becomes same stand-by mode. While this mode, output data latched read out. data read correctly when addresses changed.
Alternating Background Operation (BGO) M5M29GB/T161BWG allows read array from bank while other bank operates software command write cycling erasing programming operation background. Read array operation with other bank performed changing bank address without additional command. When bank address points bank software command write cycling erasing programming operation, data read from status register. access time with same normal read operation. Output Disable When VIH, output from devices disabled. Data input/output high-impedance(High-Z) state. Standby When VIH, device standby mode power consumption reduced. Data input/output highimpedance(High-Z) state. memory deselected during block erase program, internal control circuits remain active device consume normal active power until operation completes.
Mar.1999. Rev2.1
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
SOFTWARE COMMAND DEFINITIONS device operations selected writing specific software command into Command User Interface. Read Array Command (FFH) device Read Array mode initial device power after exit from deep powerdown, writing Command User Interface. After starting internal operation device read status register mode automatically. Read Device Identifier Command (90H) normally read device identifier codes when Read Device Identifier Code Command(90H) written command latch. Following command write, manufacturer code device code read from address 0000H 0001H, respectively. Read Status Register Command (70H) Status Register read after writing Read Status Register command Command User Interface. Also, after starting internal operation device Read Status Register mode automatically. contents Status Register latched later falling edge CE#. must toggled every status read. Clear Status Register Command (50H) Erase Status, Program Status Block Status bits "1"s Write State Machine only reset Clear Status Register command 50H. These bits indicates various failure conditions. C)Single Data Load Page Buffer (74H) Page Buffer Flash (0EH/D0H) Single data load page buffer performed writing followed second write specifying column address data. Distinct data 128word loaded page buffer this two-command sequence. other hand, loaded data page buffer programed simultaneously writing Page Buffer Flash command followed confirm command D0H. After completion programing data page buffer cleared automatically. This command valid only Bank(I) alike Word Program. Clear Page Buffer Command (55H) Loaded data page buffer cleared writing Clear Page Buffer command followed Confirm command D0H. This command valid clearing data loaded Single Data Load Page Buffer command. Suspend/Resume Command (B0H/D0H) Writing Suspend command during block erase operation interrupts block erase operation allows read from another block memory. Writing Suspend command during program operation interrupts program operation allows read from another block memory. Bank address required when writing Suspend/Resume Command. device continues output Status Register data when read, after Suspend command written Polling Status Suspend Status bits will determine when erase operation program operation been suspended. this point, writing Read Array command enables reading data from blocks other than that which suspended. When Resume command written CUI, will continue with erase program processes.
DATA PROTECTION Block Erase Confirm Command (20H/D0H) Automated block erase initiated writing Block Erase command followed Confirm command D0H. address within block erased required. executes iterative erase pulse application erase verify operation. Program Commands A)Word Program (40H) Word program executed two-command sequence. Word Program Setup command written Command Interface, followed second write specifying address data written. controls program pulse application verify operation. Word Program Command Valid only Bank(I). M5M29GB/T161BWG provides selectable block locking memory blocks. Each block associated nonvolatile lock-bit which determines lock status block. addition, M29GB/T161BWG have master Write Protect (WP1# which prevents modifications memory blocks whose lockbits "0", when WP1# WP2# low. When WP1# WP2# high blocks programmed erased regardless state lock-bits, lock-bits cleared erase. BLOCK LOCKING table details. Power Supply Voltage When power supply voltage (Vcc) less than LKO, Lock-Out voltage, device Read-only mode. Regarding electrical characteristics LKO, delay time required before device operation initiated. delay time measured from time reaches Vccmin (2.7V). During power RP#=GND recommended. Falling Busy status recommended possibility damaging device. MEMORY ORGANIZATION M5M29GB/T161BWG 16Kword boot block, seven Kword parameter blocks, Bank(I) twenty-eight 32Kword main blocks Bank(II). block erased independently other blocks array.
B)Page Program Data Blocks (41H) Page Program Bank(I) Bank(II) allows fast programming 128words data. Writing initiates page program operation Data area. From cycle 129th cycle write data must serially inputted. Address A6-A0 have incremented from 7FH. After completion data loading, controls program pulse application verify operation.
Mar.1999. Rev2.1
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Mitsubishi Flash Memory Type name
160B
Operating Voltage 3.6V Standard Type 1.65 2.2V Standard Type Boot Block Boot Bottom Boot Density/Write Protect/ Word Organizetion: 160B WP1#, x8/x16 161B WP1# WP2#,
Package 48pin TSOP(I) 12mm 20mm (Nomal Pinout) Ball Pitch 0.75mm,6x8 array, 8.5mm
Mar.1999. Rev2.1
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
MEMORY ORGANIZATION
Wordmode) F8000H-FFFFFH F0000H-F7FFFH E8000H-EFFFFH E0000H-E7FFFH D8000H-DFFFFH D0000H-D7FFFH C8000H-CFFFFH C0000H-C7FFFH B8000H-BFFFFH B0000H-B7FFFH A8000H-AFFFFH A0000H-A7FFFH 98000H-9FFFFH 90000H-97FFFH 88000H-8FFFFH 80000H-87FFFH 78000H-7FFFFH 70000H-77FFFH 68000H-6FFFFH 60000H-67FFFH 58000H-5FFFFH 50000H-57FFFH 48000H-4FFFFH 40000H-47FFFH 38000H-3FFFFH 30000H-37FFFH 28000H-2FFFFH 20000H-27FFFH 1C000H-1FFFFH 18000H-1BFFFH 14000H-17FFFH 10000H-13FFFH 0C000H-0FFFFH 08000H-0BFFFH 04000H-07FFFH 00000H-03FFFH A19-A0 (M5M29GB161BWG) Wordmode)
32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK BANK(II) BANK(I) 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK
16Kword PARAMETER BLOCK 16Kword PARAMETER BLOCK 16Kword PARAMETER BLOCK 16Kword PARAMETER BLOCK 16Kword PARAMETER BLOCK 16Kword PARAMETER BLOCK 16Kword PARAMETER BLOCK
FC000H-FFFFFH
16Kword BOOT BLOCK
F8000H-FBFFFH 16Kword PARAMETER BLOCK F4000H-F7FFFH 16Kword PARAMETER BLOCK
BANK(I)
F0000H-F3FFFH 16Kword PARAMETER BLOCK EC000H-EFFFFH 16Kword PARAMETER BLOCK E8000H-EBFFFH 16Kword PARAMETER BLOCK E4000H-E7FFFH 16Kword PARAMETER BLOCK E0000H-E3FFFH 16Kword PARAMETER BLOCK D8000H-DFFFFH D0000H-D7FFFH C8000H-CFFFFH C0000H-C7FFFH B8000H-BFFFFH B0000H-B7FFFH A8000H-AFFFFH A0000H-A7FFFH 98000H-9FFFFH 90000H-97FFFH 88000H-8FFFFH 80000H-87FFFH 78000H-7FFFFH 70000H-77FFFH 68000H-6FFFFH 60000H-67FFFH 58000H-5FFFFH 50000H-57FFFH 48000H-4FFFFH 40000H-47FFFH 38000H-3FFFFH 30000H-37FFFH 28000H-2FFFFH 20000H-27FFFH 18000H-1FFFFH 10000H-17FFFH 08000H-0FFFFH 00000H-07FFFH (M5M29GT161BWG)
32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK BANK(II) 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK
16Kword BOOT BLOCK
M5M29GB161BWG Memory
M5M29GT161BWG Memory
Mar.1999. Rev2.1
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
OPERATIONS Operations Word-Wide Mode M5M29GB/T161BWG
Mode Read Pins DQ0-15 Data Status Register Data Lock Data Identifier Code Hi-Z Hi-Z Command/Data Command Command Hi-Z
Array Status Register Lock Status Identifier Code Output disable Stand Program Write Erase Others Deep Power Down
control pins.
Mar.1999. Rev2.1
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
SOFTWARE COMMAND DEFINITION Command List
cycle Command Mode Read Array Device Identifier Read Status Register Clear Status Register Clear Page Buffer Word Program Page Program Single Data Load Page Buffer Page Buffer Flash Block Erase Confirm Suspend Resume Read Lock Status Lock Program Confirm Erase Unlocked Blocks Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Address Bank Bank(I) Bank Bank(I) Bank(I) Bank Bank Bank Bank Data
(DQ15-0)1)
cycle Data Mode Address Bank
(DQ15-0)
~129th cycles M5M29GB/T161BWG
Mode
Address
Data
(DQ15-0)
Read Read Write Write Write Write Write Write
Write
Read Write Write
Upper byte data (DQ8-DQ15) ignored. IA=ID Code Address A0=VIL (Manufacturer's Code) A0=VIH (Device Code), ID=ID Code Bank Bank Address (Bank(I) Bank(II)). A19-A17. Status Register Data Word Program, Single Data Load Page Buffer Flash Command valid only Bank(I). Write Address,WD Write Data WA0,WAn=Write Address, WD0,WDn=Write Data. Write Address Write Data must provided sequentially from A6-A0. Page size 128word (128word 16bit). also A19-A7(Block Address, Page Address) must valid. Write Address Upper page address, A19-A7(Block Address, Page Address) must valid. Block Address Bank1: A19-A14 Bank2: A19-A15 provides Block Lock Status, Block Unlock, Block Locked.
Mar.1999. Rev2.1
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY BLOCK LOCKING
161BWG WP1# Lock WP2# (Internally) Write Protection Provided BANK(I) BANK(II) Lock Boot Parameter Data Locked Locked Locked Locked Locked Locked Locked Locked Unlocked Unlocked Locked Locked Blocks Unlocked Blocks Locked
Only Parameter Block Unlocked
Note Deep Power Down Mode
Unlocked Unlocked Unlocked Unlocked Locked Locked Locked Locked Locked Locked Locked Locked Locked Unlocked Locked Locked
provides Lock Status each block after writing Read Lock Status command (71H). WP1# WP2# pins must switched during performing Erase Write operations Busy (WSMS Erase/Write command locked blocks aborted. this time read mode array read mode status read mode 00B0 read. Please issue Clear Status Register command plus Read Array command change mode from status read mode array read mode.
STATUS REGISTER
Symbol SR.7 (DQ7) SR.6 (DQ6) SR.5 (DQ5) SR.4 (DQ4) SR.3 (DQ3) SR.2 (DQ2) SR.1 (DQ1) SR.0 (DQ0) Status Write State Machine Status Suspend Status Erase Status Program Status Block Status after Program Reserved Reserved Reserved Definition Ready Suspended Error Error Error Busy Operation Progress Completed Successful Successful Successful
*DQ3 indicates block status after page programming, byte/word programming page buffer flash. When "1", page overprogramed cell over-program occurs, device block fail. However "1", please block erase block. block revive.
Mar.1999. Rev2.1
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY DEVICE IDENTIFIER CODE
Code Manufacturer Code Device Code (-T161BWG) Device Code (-B161BWG)
upper data(D 15-8) "0".
Pins
Hex. Data
ABSOLUTE MAXIMUM RATINGS
Symbol Tstg Parameter voltage input output voltage except cc,A9,RP# Ambient temperature Temperature under bias Storage temperature Output short circuit current Conditions
With respect Ground
-0.2 -0.6
Unit
Minimum voltage -0.5V input/output pins. During transitions, this level undershoot -2.0V periods <20ns. Maximum voltage input/output pins +0.5V which, during transitions, overshoot +1.5V periods <20ns.
CAPACITANCE
Symbol COUT Parameter Input capacitance (Address, Control Pins) Output capacitance Test conditions 25°C, 1MHz, Vout Limits Unit
ELECTRICAL CHARACTERISTICS -40~ 85°C, 2.7V 3.6V, unless otherwise noted)
Symbol ISB1 ISB2 ISB3 ISB4 ICC1 ICC2 ICC3 ICC4 ICC5 VOH1 VOH2 VLKO Parameter Input leakage current Output leakage current standby current Test conditions 0VVINVCC 0VVOUTVCC 3.6V, IN=VIL/VIH, =WP# 3.6V, IN=GND CC±0.3V 3.6V, IN=VIL/VIH, 3.6V, IN=GND =GND±0.3V 3.6V, IN=VIL/VIH, VIL, 5MHz RP#=OE#=V IOUT 1MHz 3.6V,V IN=VIL/VIH, =WE#= RP#=OE#=V 3.6V, IN=VIL/VIH, =WP# 3.6V, IN=VIL/VIH, =WP# 3.6V, IN=VIL/VIH, =WP# 4.0mA -2.0mA -100µA 0.85Vcc
Vcc-0.4
Limits Typ1)
±1.0
Vcc+0.5
Unit
deep powerdown current read current Word Byte Write current Word Byte program current erase current suspend current Input voltage Input high voltage Output voltage Output high voltage Lock-Out voltage
0.45
currents unless otherwise noted. Typical values Vcc=3.3V, Ta=25°C protect against initiation write cycle during power-up/ down, write cycle locked less than LKO. less than LKO, Write State Machine reset read mode. When Write State Machine Busy state, less than VLKO alteration memory contents
occur.
Mar.1999. Rev2.1
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
ELECTRICAL CHARACTERISTICS ~85°C, 2.7V ~3.6V) Read-Only Mode
Limits
Symbol
Parameter
Vcc=2.7-3.6V 90ns
Unit
(AD) (CE) (OE) tCLZ tDF(CE) tOLZ tDF(OE) tPHZ
tAVAV tAVQV tELQV tGLQV tELQX tEHQZ tGLQX tGHQZ tPLQZ tPHEL
Read cycle time Address access time Chip enable access time Output enable access time Chip enable output low-Z Chip enable high output high Output enable output low-Z Output enable high output high output high-Z Output hold from CE#, OE#, addresses recovery
Timing measurements made under waveforms read operations.
ELECTRICAL CHARACTERISTICS ~85°C, 2.7V ~3.6V) Write Mode (WE# control)
Limits Vcc=2.7-3.6V tOEH tAVAV tAVWH tWHAX tDVWH tWHDX tWHGL tELWL tWHEH tWLWH Write cycle time Address set-up time Address hold time Data set-up time Data hold time hold from high Latency between Read Write Chip enable set-up time Chip enable hold time Write pulse width Write pulse width high hold Block Lock set-up write enable high 90ns
Symbol
Parameter
Unit
tWPH tWHWL tGHWL tGHWL tBLS tBLH tDAP tDAE
tPHHWH tQVPH Block Lockhold from valid tWHRH1 Duration auto-program operation tWHRH2 Duration auto-block erase operation Write enable high F-RY/BY# high recovery write enable
tWHRL tWHRL tPHWL
Read timing parameters during command write operations mode same during read-only operations mode. Typical values Vcc=3.3V, Ta=25°C
Mar.1999. Rev2.1
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY ELECTRICAL CHARACTERISTICS 85°C, 2.7V 3.6V) Write Mode (F-CE# control)
Limits Vcc=2.7-3.6V 90ns
Symbol
Parameter
Unit
tOEH tCEP
tAVAV tAVWH tEHAX tDVWH tEHDX tEHGL tWLEL tEHWH tELEH
Write cycle time Address set-up time Address hold time Data set-up time Data hold time hold from high Latency between Read Write Write enable set-up time Write enable hold time pulse width pulse width high hold
tCEPH tEHEL tGHEL tGHEL tBLS tBLH tDAP tDAE tEHRL
tPHHEH Block Lock set-up chip enable high tQVPH Block Lockhold from valid tEHRH1 Duration auto-program operation tEHRH2 Duration auto-block erase operation tEHRL high F-RY/BY# tPHWL high recovery write enable
Read timing parameters during command write operation mode same during read-only operation mode. Typical values Vcc=3.3V, Ta=25°C
Erase Program Performance
Parameter Block Erase Time Main Block Write Time (Page Mode) Page Write Time Unit
Program Suspend Latency Erase Suspend Time
Parameter Program Suspend Latency Erase Suspend Time
Please page
Unit
Power Down Timing
Symbol tVCS
Please page
Parameter =VIH set-up time from Vccmin
Unit
During power up/down, noise pulses control pins, device possibility accidental erasure programming. device must protected against initiation write cycle memory contents during power up/down. delay time min.2µsec always required before read operation write operation initiated from time reaches Vccmin during power up/down. holding VIL, contents memory protected during power up/down. During power must held min.2µs from time reaches Vccmin. During power down, must held until reaches GND. doesn't have latch mode ,therefore must held during read operation erase/program operation.
Mar.1999. Rev2.1
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
POWER DOWN TIMING
Read /Write Inhibit Read /Write Inhibit Read /Write Inhibit
3.3V tVCS
WAVEFORMS READ OPERATION TEST CONDITIONS
ADDRESSES ADDRESS VALID
TEST CONDITIONS CHARACTERISTICS Input voltage 3.0V Input rise fall times Reference voltage timing measurement 1.5V Output load 1TTL gate +CL(30pF)
(AD) (CE) tDF(CE)
tOEH (OE) tOLZ HIGH-Z tCLZ tDF(OE) HIGH-Z
1.3V 1N914 3.3k
DATA
OUTPUT VALID
tPHZ
WAVEFORMS WRITE READ OPERATION
ADDRESSES
ADDRESS VALID
(AD) (CE) (OE)
tDF(CE)
tDF(OE)
HIGH-Z
tOLZ tCLZ
OUTPUT VALID
DATA
HIGH-Z
Valid
tPHZ
case fixed, allowed define timming specification from rising edge falling edge OE#, valid data read after spec tRE+ta(CE). (This only FFH,71H program read)
Mar.1999. Rev2.1
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY WAVEFORMS PAGE PROGRAM OPERATION (WE# control)
A19~A7 VALID other bank address VALID
PROGRAM READ STATUS WRITE READ REGISTER ARRAY COMMAND
ADDRESS VALID
BANK ADDRESS VALID
A6~A0
tWPH tOEH tGHWL ta(OE) tOEH tDAP
VALID 01H~7EH
ta(CE)
ta(CE) ta(OE)
DATA
DOUT
tBLS tBLH
WP1#, WP2#
WAVEFORMS PAGE PROGRAM OPERATION (CE# control)
other bank address VALID VALID ADDRESS VALID
READ STATUS WRITE READ REGISTER ARRAY COMMAND
PROGRAM
A19~A7
BANK ADDRESS VALID
A6~A0
tCEP
VALID
01H~7EH
tCEPH
ta(CE) ta(OE)
ta(CE) ta(OE) tOEH tDAP
tOEH
tGHEL
DOUT
DATA
WP1#, WP2#
tBLS tBLH
Mar.1999. Rev2.1
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY WAVEFORMS BYTE WORD PROGRAM OPERATION (WE# control) only BANK(I))
PROGRAM ADDRESS VALID READ STATUS REGISTER WRITE READ ARRAY COMMAND
ADDR DATA
BANK(I) ADDRESS VALID
ta(CE) ta(OE) tOEH
tWPH
RST#
tDAP tBLS tBLH
WP1#, WP2#
WAVEFORMS BYTE WORD PROGRAM OPERATION (CE# control)
only BANK(I))
WRITE READ ARRAY COMMAND
ADDR DATA
PROGRAM ADDRESS VALID
READ STATUS REGISTER
BANK(I) ADDRESS VALID
ta(CE) ta(OE)
tCEP
tOEH
WP1#, WP2#
tDAP tBLS tBLH
Mar.1999. Rev2.1
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
WAVEFORMS ERASE OPERATIONS (WE# control
ERASE
ADDRESSES
READ STATUS REGISTER
WRITE READ ARRAY COMMAND
ADDRESS VALID
BANK ADDRESS VALID
ta(CE)
tOEH tDAE
ta(OE)
tWPH
DATA
WP1#, WP2#
tBLS
tBLH
WAVEFORMS ERASE OPERATIONS (CE# control)
ERASE
ADDRESSES
READ STATUS REGISTER
WRITE READ ARRAY COMMAND
ADDRESS VALID
BANK ADDRESS VALID
ta(CE)
tCEP
tCEPH tOEH
ta(OE)
tDAE
DATA
WP1#, WP2#
tBLS
tBLH
Mar.1999. Rev2.1
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY WAVEFORMS PAGE PROGRAM OPERATION WITH (WE# control)
Change Bank Address PROGRAM DATA BANK ARRAY READ FROM OTHER BANK WITH
A19~A7 ADDRESS VALID
VALID
VALID
01H~7EH
A6~A0
VALID
VALID
tWPH
ta(CE) ta(OE) tOEH
DATA
DOUT
DOUT
WAVEFORMS PAGE PROGRAM OPERATION WITH (CE# control)
Change Bank Address PROGRAM DATA BANK ARRAY READ FROM OTHER BANK WITH
A19~A7 ADDRESS VALID
VALID
VALID
A6~A0 01H~7EH
VALID
VALID
tCEPH
ta(CE) ta(OE)
tCEP
tOEH
DATA
DOUT
DOUT
Mar.1999. Rev2.1
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
WAVEFORMS BYTE WORD PROGRAM OPERATION WITH (WE# control)
Change Bank Address PROGRAM DATA BANK(I) READ STATUS REGISTER ARRAY READ FROM BANK(II) WITH
A19~A7
ADDRESS VALID
VALID
VALID
A6~A0 VALID VALID VALID
ta(CE) ta(OE)
tWPH tOEH
DATA
DOUT DOUT
WAVEFORMS BYTE WORD PROGRAM OPERATION WITH (CE# control)
PROGRAM DATA READ STATUS BANK(I) REGISTER Change Bank Address ARRAY READ FROM BANK(II) WITH
A19~A7
ADDRESS VALID
VALID
VALID
VALID VALID VALID
A6~A0
DATA
tCEPH
ta(CE) ta(OE) tOEH
tCEP
DOUT DOUT
Mar.1999. Rev2.1
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY WAVEFORMS BLOCK ERASE OPERATION WITH (WE# control)
Change Bank Address BLOCK ERASE BANK READ STATUS REGISTER ARRAY READ FROM OTHER BANK WITH
ADDRESSES DATA
ADDRESS VALID
VALID
VALID
tWPH tOEH
ta(CE) ta(OE)
DOUT DOUT
WAVEFORMS BLOCK ERASE OPERATION WITH (CE# control)
Change Bank Address BLOCK ERASE BANK READ STATUS REGISTER READ DATA FROM OTHER BANK WITH
ADDRESSES
ADDRESS VALID
VALID
VALID
tCEPH
ta(CE) ta(OE)
tCEP
tOEH
DOUT DOUT
DATA
Mar.1999. Rev2.1
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY WAVEFORMS SUSPEND OPERATION (WE# control
ADDRESSES
READ STATUS REGISTER
BANK ADDRESS VALID
BANK ADDRESS VALID
ta(CE)
DATA WP1#, WP2# tBLS
tOEH Program Suspend Latency
ta(OE)
S.R.6,7=1
VALID
tBLH
WAVEFORMS SUSPEND OPERATION (CE# control
READ STATUS REGISTER
ADDRESSES
BANK ADDRESS VALID
BANK ADDRESS VALID
DATA WP1#, WP2# tBLS
tCEP
ta(CE)
ta(OE) tOEH Program Suspend Latency S.R.6,7=1
VALID
tBLH
Mar.1999. Rev2.1
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY FULL STATUS CHECK PROCEDURE
STATUS REGISTER READ
LOCK PROGRAM FLOW CHART
START
SR.4 SR.5
WRITE COMMAND SEQUENCE ERROR WRITE BLOCK ADDRESS
SR.5
BLOCK ERASE ERROR SR.7
SR.4
PROGRAM ERROR (PAGE, LOCK BIT) SR.4
LOCK PROGRAM FAILED
SR.3 SUCCESSFUL (BLOCK ERASE, PROGRAM)
PROGRAM ERROR (BLOCK)
LOCK PROGRAM SUCCESSFUL
BYTE PROGRAM FLOW CHART
START
PAGE PROGRAM FLOW CHART
START
WRITE WRITE
WRITE ADDRESS DATA
STATUS REGISTER READ
WRITE ADDRESS DATA
SR.7
WRITE
STATUS REGISTER READ
FULL STATUS CHECK DESIRED
SUSPEND LOOP WRITE
SR.7 WRITE
PAGE PROGRAM COMPLETED
Word program admitted only BANK(I).
FULL STATUS CHECK DESIRED
SUSPEND LOOP WRITE
PAGE PROGRAM COMPLETED
Mar.1999. Rev2.1
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY CLEAR PAGE BUFFER
START
SUSPEND RESUME FLOW CHART
START
WRITE WRITE STATUS REGISTER READ WRITE SR.7 PAGE BUFFER CLEAR COMPLETED
SUSPEND
SR.6
SINGLE DATA LOAD PAGE BUFFER
START WRITE
PROGRAM ERASE COMPLETED
WRITE
READ ARRAY DATA
WRITE ADDRESS DATA
DONE READING
DONE LOADING?
WRITE
RESUME
SINGLE DATA LOAD PAGE BUFFER COMPLETED
OPERATION RESUMED
bank address required when writing this command. Also, there need suspend erase program operation when reading data from other bank. Please function.
PAGE BUFFER FLASH
START
BLOCK ERASE FLOW CHART
START
WRITE WRITE WRITE BLOCK ADDRESS WRITE PAGE ADDRESS STATUS REGISTER READ
STATUS REGISTER READ
SR.7
WRITE
SR.7
WRITE
FULL STATUS CHECK DESIRED
SUSPEND LOOP WRITE
PAGE BUFFER FLASH COMPLETED
FULL STATUS CHECK DESIRED
SUSPEND LOOP WRITE
BLOCK ERASE COMPLETED
Mar.1999. Rev2.1
OPERATION STATUS EFFECTIVE COMMAND
Clear Status Register
Read/Standby State Read Status Register
Read Device Identifier
Read Lock Status
Read Array
Setup State Clear Page Buffer Setup
Single Data Load Page Buffer Setup
Page Buffer Flash Setup
Page Program Setup
Byte Program Setup
Lock Program Setup
Block Erase Setup
Erase Unlocked Blocks Setup
OTHER
OTHER OTHER
Internal State
i=0-127
OTHER
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Program Verify
Ready
Erase Verify Read Status Register
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
Read Status Register
Suspend State
Change Bank Address
Read Status Register
Change Bank Address
Read State with Mar.1999. Rev2.1 Read Array
(From Other Bank)
Read Array

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