FAST PAGE MODE 16777216-BIT (4194304-WORD 4-BIT) DYNAMIC DESCRIPTION
|
|
|
Top Searches for this datasheet
FAST PAGE MODE 16777216-BIT (4194304-WORD 4-BIT) DYNAMIC DESCRIPTION
This family 4194304-word 4-bit dynamic RAMS, fabricated with high performance CMOS process, ideal large-capacity memory systems where high speed, power dissipation, costs essential. double-layer metal process combined with twin-well CMOS technology single-transistor dynamic storage stacked capacitor cell provide high circuit density reduced costs. Multiplexed address inputs permit both reduction pins increase system densities.
DESCRIPTION
name Function Address inputs Data inputs outputs address strobe input Column address strobe input Write control input Output enable input Power supply (+5V) Ground (0V)
CONFIGURATION (TOP VIEW)
FEATURES
access time (max.ns) Address access time (max.ns) access time (max.ns) Cycle time (min.ns) Power dissipation (typ.mW)
Type Name
access time (max.ns)
M5M417400CXX-5,-5S M5M417400CXX-6,-6S M5M417400CXX-7,-7S
XX=J,
Standard SOJ, TSOP Single supply stand-by power dissipation 5.5mW(Max) .CMOS Input level 2.2mW (Max)* .CMOS Input level operating power dissipation M5M417400Cxx-5,-5S 800.0mW (Max) M5M417400Cxx-6,-6S 660.0mW (Max) M5M417400Cxx-7,-7S 580.0mW (Max) Self refresh capability self refresh current 200.0 A(Max) Outline 26P0D-B (300mil SOJ)
Fast-page mode, Read-modify-write, RAS-only refresh before refresh, Hidden refresh capabilities Early-write mode control output buffer impedance inputs, output compatible capacitance 2048 refresh cycles every 32ms A10) *Applicable self refresh version (M5M417400CJ,TP-5S,-6S, :option) only
APPLICATION
Main memory unit computers, Microcomputer memory, Refresh memory
Outline 26P3D-E (300mil TSOP) CONNECTION
FAST PAGE MODE 16777216-BIT (4194304-WORD 4-BIT) DYNAMIC
FUNCTION
M5M417400CJ,TP provide, addition normal read, write, read-modify-write operations, number other functions, e.g., fast page mode, RAS-only refresh, delayed-write. input conditions each shown Table
Table Input conditions each mode
Inputs Operation Read Write (Early write) Write (Delayed write) Read-modify-write RAS-only refresh Hidden refresh Self refresh before refresh Stand-by address Column address Input/Output Input Output Refresh Remark
Fast page mode identical
Note: ACT: active, NAC: nonactive, DNC: don't care, VLD: valid, IVD: invalid, APD: applied, OPN: open
BLOCK DIAGRAM
FAST PAGE MODE 16777216-BIT (4194304-WORD 4-BIT) DYNAMIC ABSOLUTE MAXIMUM RATINGS
Symbol Topr Tstg Supply voltage Input voltage Output voltage Output current Power dissipation Operating temperature Storage temperature 25°C With respect Parameter Conditions Ratings 1000 Unit
RECOMMENDED OPERATING CONDITIONS
70°C, unless otherwise noted) (Note Symbol Note Supply voltage Supply voltage High-level input voltage, inputs Low-level input voltage, inputs voltage values with respect VSS. Parameter Limits -1.0** Unit
VIL(min.) -2.0V when undershoot width less than 25ns. (Undershoot width with respect VSS.)
ELECTRICAL CHARACTERISTICS
70°C, 10%, unless otherwise noted) (Note Symbol ICC1(AV) High-level output voltage Low-level output voltage Off-state output current Input current Average supply current from VCC, operating (Note 3,4) ICC2 Supply current from VCC, stand-by Average supply current ICC3 (AV) from VCC, refreshing (Note Average supply current ICC4 (AV) from VCC, Fast-Page-Mode (Note 3,4) Average supply current from VCC, ICC6 (AV) before refresh mode (Note Note M5M417400C-5,-5S M5M417400C-6,-6S M5M417400C-7,-7S (Note M5M417400C-5,-5S M5M417400C-6,-6S M5M417400C-7,-7S M5M417400C-5,-5S M5M417400C-6,-6S M5M417400C-7,-7S M5M417400C-5,-5S M5M417400C-6,-6S M5M417400C-7,-7S Parameter -5.0mA 4.2mA floating VOUT 5.5V 5.5V, Other inputs pins RAS, cycling min. output open VIH, output open -0.2V cycling, min. output open VIL, cycling min. output open before refresh cycling min. output open Test conditions Limits Unit
Current flowing into positive, negative. ICC1 (AV), ICC3 (AV), ICC4 (AV) ICC6 (AV) dependent cycle rate. Maximum current measured fastest cycle rate. ICC1 (AV) ICC4 (AV) dependent output loading. Specified values obtained with output open.
FAST PAGE MODE 16777216-BIT (4194304-WORD 4-BIT) DYNAMIC
CAPACITANCE
70°C, 10%, unless otherwise noted) Symbol CI(A) CI(OE) CI(W) CI(RAS) CI(CAS) CI/O Parameter Input capacitance, address inputs Input capacitance, input Input capacitance, write control input Input capacitance, input Input capacitance, input Input/Output capacitance, data ports 1MHz 25mVrms Test conditions Limits Unit
SWITCHING CHARACTERISTICS
70°C, 10%, unless otherwise noted, notes Limits Symbol Parameter M5M417400C-5,-5S tCAC tRAC tCPA tOEA tCLZ tOFF tOEZ Note Access time from Access time from Column address access time Access time from precharge Access time from Output impedance time from Output disable time after high Output disable time after high (Note (Note (Note (Note (Note (Note (Note (Note M5M417400C-6,-6S M5M417400C-7,-7S Unit
initial pause required after power-up followed minimum eight initialization cycles. initialization cycles should done either RAS-only refresh cycles before refresh cycles only. Note cycled during initial pause. RAS/CAS cycles required after prolonged periods (greater than 32ms) inactivity before proper device operation achieved. After initialization cycles, should kept either higher than VIH(min) lower than VIL(max) except transition time. Measured with load circuit equivalent loads 100pF. Assumes that tRCD tRCD(max) tASC tASC(max). Assumes that tRCD tRCD(max) tRAD tRAD(max). tRCD tRAD greater than maximum recommended value shown this table, tRAC will increase amount that tRCD exceeds value shown. Assumes that tRAD tRAD(max) tASC tASC(max). Assumes that tCP(max) tASC tASC(max). tOFF(max) tOEZ(max) defines time which output achieves high impedance state (IOUT reference VOH(min) VOL(max).
FAST PAGE MODE 16777216-BIT (4194304-WORD 4-BIT) DYNAMIC TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, Fast-Page Mode Cycles)
70°C, 10%, unless otherwise noted. notes Limits Symbol Parameter M5M417400C-5,-5S tREF tRCD tCRP tRPC tCPN tRAD tASR tASC tRAH tCAH tDZC tDZO tCDD tODD Refresh cycle time high pulse width Delay time, Delay time, high Delay time, high high pulse width Column address delay time from address setup time before Column address setup time before address hold time after Column address hold time after Delay time, data Delay time, data Delay time, high data Delay time, high data Transition time (Note (Note (Note (Note (Note (Note (Note (Note M5M417400C-6,-6S M5M417400C-7,-7S Unit
Note timing requirements assumed 5ns. VIH(min) VIL(max) reference levels measuring timing input signals. tRCD(max) specified reference point only. tRCD less than tRCD(max), access time tRAC. tRCD greater than tRCD(max), access time controlled exclusively tCAC tAA. tRCD(min) specified tRCD(min) tRAH(min) tASC(min). tRAD(max) specified reference point only. tRAD tRAD(max) tASC tASC(max), access time controlled exclusively tAA. tASC(max) specified reference point only. tRCD tRCD(max) tASC tASC(max), access time controlled exclusively tCAC. Either tDZC tDZO must satisfied. Either tCDD tODD must satisfied. measured between VIH(min) VIL(max).
Read Refresh Cycles
Limits Symbol Parameter M5M417400C-5,-5S tRAS tCAS tCSH tRSH tRCS tRCH tRRH tRAL tOCH tORH Read cycle time pulse width pulse width hold time after hold time after Read setup time after high Read hold time after Read hold time after Column address hold time hold time after hold time after (Note (Note 10000 10000 M5M417400C-6,-6S 10000 10000 M5M417400C-7,-7S 10000 10000 Unit
Note Either tRCH tRRH must satisfied read cycle.
FAST PAGE MODE 16777216-BIT (4194304-WORD 4-BIT) DYNAMIC
Write Cycle (Early Write Delayed Write)
Limits Symbol Parameter M5M417400C-5,-5S tRAS tCAS tCSH tRSH tWCS tWCH tCWL tRWL tOEH Write cycle time pulse width pulse width hold time after hold time after Write setup time before Write hold time after hold time after hold time after Write pulse width Data setup time before Data hold time after hold time after (Note 10000 10000 M5M417400C-6,-6S 10000 10000 M5M417400C-7,-7S 10000 10000 Unit
Read-Write Read-Modify-Write Cycles
Limits Symbol Parameter M5M417400C-5,-5S tRWC tRAS tCAS tCSH tRSH tRCS tCWD tRWD tAWD tCWL tRWL tOEH Read write/read modify write cycle time pulse width pulse width hold time after hold time after Read setup time before Delay time, Delay time, Delay time, address hold time after hold time after Write pulse width Data setup time before Data hold time after hold time after (Note (Note (Note (Note 10000 10000 M5M417400C-6,-6S 10000 10000 M5M417400C-7,-7S 10000 10000 Unit
Note tRWC specified tRWC(min) tRAC(max) tODD(min) tRWL(min) tRP(min) 5tT. Note tWCS, tCWD, tRWD tAWD and, tCPWD specified reference points only. tWCS tWCS(min) cycle early write cycle pins will remain high impedance throughout entire cycle. tCWD tCWD(min), tRWD tRWD(min), tAWD tAWD(min) tCPWD tCPWD(min) (for fast page mode cycle only), cycle read-modify-write cycle will contain data read from selected address. neither above condition (delayed write) access time until goes back VIH) indeterminate.
FAST PAGE MODE 16777216-BIT (4194304-WORD 4-BIT) DYNAMIC Fast-Page Mode Cycle (Read, Early Write, Read-Write, Read-Modify-Write Cycle)
(Note Limits Symbol Parameter M5M417400C-5,-5S tPRWC tRAS tCPRH tCPWD Fast page mode read/write cycle time Fast page mode read write/read modify write cycle time pulse width read write cycle high pulse width hold time after precharge Delay time, precharge (Note (Note (Note 125000 M5M417400C-6,-6S 125000 M5M417400C-7,-7S 125000 Unit
Note previously specified timing requirements switching characteristics applicable their respective fast page mode cycle. tRAS(min) specified cycles input performed. tCP(max) specified reference point only.
before Refresh Cycle
(Note Limits Symbol Parameter M5M417400C-5,-5S tCSR tCHR tRSR tRHR setup time before hold time after Read setup time before Read hold time after M5M417400C-6,-6S M5M417400C-7,-7S Unit
Note Eight more before cycles instead eight cycles necessary proper operation before refresh mode.
SELF REFRESH SPECIFICATIONS
Self refresh devices denoted after speed item, like -5S/-6S/-7S. other characteristics requirements than below same normal devices.
ELECTRICAL CHARACTERISTICS
70°C, 10%, unless otherwise noted) (Note Symbol Parameter Test conditions before refresh cycling cycling 0.2V 0.2V 0.2V M5M417400C 0.2V 0.2V tREF 128ms (2048 cycles) output OPEN tRAS tRASmin. Average supply current from Slow-Refresh cycle (Note Limits Unit
ICC8(AV)
Average supply current from Slow-Refresh cycle (Note
ICC9(AV)
M5M417400C
0.2V output OPEN
FAST PAGE MODE 16777216-BIT (4194304-WORD 4-BIT) DYNAMIC
TIMING REQUIREMENTS
70°C, 10%, unless otherwise noted, notes Limits Symbol Parameter M5M417400C-5S tRASS tRPS tCHS tRSR tRHR Self Refresh pulse width Self Refresh high precharge time Self Refresh hold time Read setup time before Read hold time after M5M417400C-6S M5M417400C-7S Unit
SELF REFRESH ENTRY EXIT CONDITIONS
case distributed refresh last first full refresh cycles (2K) must made within before after self refresh, condition 32ms 32ms.
case burst refresh last first full refresh cycles (2K) must made within before after self refresh, condition 32ms.
FAST PAGE MODE 16777216-BIT (4194304-WORD 4-BIT) DYNAMIC TEST Mode Cycle
Limits Symbol Parameter M5M417400C-5,-5S tWSR tWHR setup time before hold time after M5M417400C-6,-6S M5M417400C-7,-7S Unit
Note test mode function initiated before cycle (WCBR cycle) specified timing diagram. test mode function terminated either before refresh cycle (CBR refresh cycle) only refresh cycle. During test mode, device internally organized 16-bits wide bytes depth). addressing required. During write cycle, data must applied (input) pins. data different between pins. data each written into 4-bits memory cells, respectively. During read cycle, each (output) shows test result 4-bits, respectively. High state indicates that they same. state indicates that they same. During test mode operation, only WCBR cycle used perform refresh.
FAST PAGE MODE 16777216-BIT (4194304-WORD 4-BIT) DYNAMIC
Timing Diagrams Read Cycle
(Note
FAST PAGE MODE 16777216-BIT (4194304-WORD 4-BIT) DYNAMIC Write Cycle (Early Write)
FAST PAGE MODE 16777216-BIT (4194304-WORD 4-BIT) DYNAMIC
Write Cycle (Delayed Write)
FAST PAGE MODE 16777216-BIT (4194304-WORD 4-BIT) DYNAMIC Read-Write, Read-Modify-Write Cycle
FAST PAGE MODE 16777216-BIT (4194304-WORD 4-BIT) DYNAMIC
RAS-only Refresh Cycle
FAST PAGE MODE 16777216-BIT (4194304-WORD 4-BIT) DYNAMIC before Refresh Cycle, Slow Refresh Cycle
FAST PAGE MODE 16777216-BIT (4194304-WORD 4-BIT) DYNAMIC
Hidden Refresh Cycle (Read)
(Note
Note Early write, delayed write, read write read modify write cycle applicable instead read cycle. Timing requirements output state same that each cycle shown above. cycle, tRSR tRHR should satisfied enter TEST MODE.
FAST PAGE MODE 16777216-BIT (4194304-WORD 4-BIT) DYNAMIC Fast Page Mode Read Cycle
FAST PAGE MODE 16777216-BIT (4194304-WORD 4-BIT) DYNAMIC
Fast Page Mode Write Cycle (Early Write)
FAST PAGE MODE 16777216-BIT (4194304-WORD 4-BIT) DYNAMIC Fast-Page Mode Write Cycle (Delayed Write)
FAST PAGE MODE 16777216-BIT (4194304-WORD 4-BIT) DYNAMIC
Fast Page Mode Read-Write, Read-Modify-Write Cycle
FAST PAGE MODE 16777216-BIT (4194304-WORD 4-BIT) DYNAMIC Self Refresh Cycle
FAST PAGE MODE 16777216-BIT (4194304-WORD 4-BIT) DYNAMIC
TEST Mode Cycle
Note
This cycle used initialized cycle after power-up, however entried into Test Mode.
Other recent searches
TMP91FW60FG - TMP91FW60FG TMP91FW60FG Datasheet
SN74ALVCH16901 - SN74ALVCH16901 SN74ALVCH16901 Datasheet
SMV1679L-LF - SMV1679L-LF SMV1679L-LF Datasheet
NII51009-7 - NII51009-7 NII51009-7 Datasheet
MPVZ12 - MPVZ12 MPVZ12 Datasheet
CR1216 - CR1216 CR1216 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
