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MH16S72BAMD-6

1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PRELIMINARY
Some of contents are subject to change without notice. DESCRIPTION
The MH16S72BAMD is 16777216 - word x 72-bit Synchronous DRAM module. This consist of eighteen industry standard 8M x 8 Synchronous DRAMs in TSOP. The TSOP on a card edge dual in-line package provides any application where high densities and large of quantities memory are required. This is a socket-type memory module , suitable for easy interchange or addition of module.
85pin
FEATURES
Type name Max. Frequency Access Time from CLK component level
94pin 95pin
10pin 11pin
MH16S72BAMD-6
133MHz
Utilizes industry standard 8M X 8 Synchronous DRAMs in TSOP package Single 3.3V + / - 0.3V supply Max.Clock frequency 133MHz Fully synchronous operation referenced to clock rising edge 4-bank operation controlled by BA0, BA1(Bank Address) / CAS latency -2 / 3(programmable, at buffer mode) LVTTL Interface Burst length 1 / 2 / 4 / 8 / Full Page(programmable) Burst type- Sequential and interleave burst (programmable) Random column access Burst Write / Single Write(programmable) Auto precharge / All bank precharge controlled by A10 Auto refresh and Self refresh 4096 refresh cycles every 64ms
124pin 125pin
40pin 41pin
APPLICATION
Main memory or graphic memory in computer systems
168pin
84pin
MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PIN NAME VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS NC NC VDD / WE DQMB0 DQMB1 / S0 NC VSS A0 A2 A4 A6 A8 A10 BA1 VDD VDD CK0
PIN NO. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
PIN NAME VSS NC / S2 DQMB2 DQMB3 NC VDD NC NC CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VDD DQ20 NC NC CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CK2 NC WP SDA SCL VDD
PIN NO. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126
PIN NAME VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 CB5 VSS NC NC VDD / CAS DQMB4 DQMB5 / S1 / RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD CK1 NC
PIN NO. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
PIN NAME VSS CKE0 / S3 DQMB6 DQMB7 NC VDD NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VDD DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CK3 NC SA0 SA1 SA2 VDD
MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
D2 D11 D1 D10
DQ32 DQ33
DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
SERIAL PD SCL WP 47K VDD VSS A0 A1 A2 SDA
SA0 SA1 SA2 D0-17 D0-17
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
Vcc CKE1 CKE0 A11-0, BA0-1 / RAS / CAS / WE 10K
D9-17 D0-8 D0-17 D0-17 D0-17 D0-17
DQM0 DQM 1 DQM 2 DQM 3 DQM 4 DQM 5 DQM 6 DQM 7
D0, 9 D1, 2, 10 D3, 12 D4, 13 D5, 14 D6, 11, 15 D7, 16 D8, 17
CK0 CK1 CK2 CK3
5DRAMs 5DRAMs 4DRAMs+3.3pF 4DRAMs+3.3pF
MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PIN FUNCTION
CK0-3 Input Master Clock:All other inputs are referenced to the rising edge of CK Clock Enable:CKE controls internal clock.When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE E becomes asynchronous input.Self refresh is maintained as long as CKE is low. Chip Select: When / S is high, any command means No Operation. Combination of / RAS, / CAS, / W defines basic commands. A0-11 specify the Row / Column Address in conjunction with BA.The Row Address is specified by A0-11.The Column Address is specified by A0-8.A10 is also used to indicate precharge option.When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, both banks are precharged. Bank Address:BA0, 1 is specifies the four bank to which a command is applied.BA must be set with ACT , PRE , READ , WRITE commands
CKE0, 1
Input
Input Input
A0-11
Input
BA0-1 DQ0-63 CB0-7 DQM0-7 Vdd, Vss
Input
Data In and Data out are referenced to the rising edge Input / Output of CK Din Mask / Output Disable:When DQMB is high in burst write.Din for the current cycle is masked.When DQMB is high Input in burst read, Dout is disabled at the next but one cycle. Power Supply for the memory mounted Power Supply module.
MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BASIC FUNCTIONS
The MH16S72BAMD provides basic functions, bank(row)activate, burst read / write, bank(row)precharge, and auto / self refresh. Each command is defined by control signals of / RAS, / CAS and / WE at CK rising edge. In addition to 3 signals, / S, CKE and A10 are used as chip select, refresh option, and precharge option, respectively. To know the detailed definition of commands please see the command truth table.
MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
COMMAND TRUTH TABLE
COMMAND Deselect No Operation Row Adress Entry & Bank Activate Single Bank Precharge Precharge All Bank Column Address Entry & Write Column Address Entry & Write with AutoPrecharge Column Address Entry & Read Column Address Entry & Read with Auto Precharge Auto-Refresh Self-Refresh Entry Self-Refresh Exit Burst Terminate Mode Register Set MNEMONIC DESEL NOP CKE CKE n-1 n H X H X / S H L / RAS / CAS X H X H / WE BA0, 1 X H X X A11 X X A10 X X A0-9 X X
ACT PRE PREA WRITE
WRITEA
READA REFA REFS REFSX TBST MRS
MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE
Current State IDLE / S H L L L L L L L ROW ACTIVE H L L L L L L L L READ H L L L / RAS / CAS X H H H L L L L X H H H H L L L L X H H H X H H L H H L L X H H L L H H L L X H H L / WE X H L X H L H L X H L H L H L H L X H L H X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 Address Command DESEL NOP TBST ACT PRE / PREA REFA MRS DESEL NOP TBST READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST NOP NOP ILLEGAL2 Bank Active, Latch RA NOP4 Auto-Refresh5 Mode Register Set5 NOP NOP NOP Begin Read, Latch CA, Determine Auto-Precharge Begin Write, Latch CA, Determine Auto-Precharge Bank Active / ILLEGAL2 Precharge / Precharge All ILLEGAL ILLEGAL NOP(Continue Burst to END) NOP(Continue Burst to END) Terminate Burst Terminate Burst, Latch CA, READ / READA Begin New Read, Determine Auto-Precharge3 Terminate Burst, Latch CA, L L L L L H L L L L L H H L L L H L H L BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add WRITE / WRITEA Begin Write, Determine AutoPrecharge3 ACT PRE / PREA REFA MRS Bank Active / ILLEGAL2 Terminate Burst, Precharge ILLEGAL ILLEGAL Action
READ / WRITE ILLEGAL2
MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State WRITE / S H L L L / RAS X H H H / CAS X H H L / WE X H L H X X BA BA, CA, A10 Address Command DESEL NOP TBST Action NOP(Continue Burst to END) NOP(Continue Burst to END) Terminate Burst Terminate Burst, Latch CA, READ / READA Begin Read, Determine AutoPrecharge3 L L L L L READ with AUTO PRECHARGE H L L L L L L L L WRITE with AUTO PRECHARGE H L L L L L L L L H L L L L X H H H H L L L L X H H H H L L L L L H H L L X H H L L H H L L X H H L L H H L L L H L H L X H L H L H L H L X H L H L H L H L BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST WRITE / WRITEA ACT PRE / PREA REFA MRS Terminate Burst, Latch CA, Begin Write, Determine AutoPrecharge3 Bank Active / ILLEGAL2 Terminate Burst, Precharge ILLEGAL ILLEGAL NOP(Continue Burst to END) NOP(Continue Burst to END) ILLEGAL
READ / READA ILLEGAL ILLEGAL Bank Active / ILLEGAL2 ILLEGAL2 ILLEGAL ILLEGAL NOP(Continue Burst to END) NOP(Continue Burst to END) ILLEGAL
READ / READA ILLEGAL ILLEGAL Bank Active / ILLEGAL2 ILLEGAL2 ILLEGAL ILLEGAL
MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State PRE CHARGING / S H L L L L L L L ROW ACTIVATING H L L L L L L L WRITE RECOVERING H L L L L L L L / RAS / CAS X H H H L L L L X H H H L L L L X H H H L L L L X H H L H H L L X H H L H H L L X H H L H H L L / WE X H L X H L H L X H L X H L H L X H L X H L H L X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add MRS ILLEGAL Address Command DESEL NOP TBST ACT PRE / PREA REFA MRS DESEL NOP TBST ACT PRE / PREA REFA MRS DESEL NOP TBST Action NOP(Idle after tRP) NOP(Idle after tRP) ILLEGAL2 ILLEGAL2 NOP4(Idle after tRP) ILLEGAL ILLEGAL NOP(Row Active after tRCD NOP(Row Active after tRCD ILLEGAL2 ILLEGAL2 ILLEGAL2 ILLEGAL ILLEGAL NOP NOP ILLEGAL2
READ / WRITE ILLEGAL2
READ / WRITE ILLEGAL2 ACT PRE / PREA REFA ILLEGAL2 ILLEGAL2 ILLEGAL
MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State REFRESHING / S H L L L L L L L MODE REGISTER SETTING H L L L L L L L / RAS / CAS X H H H L L L L X H H H L L L L X H H L H H L L X H H L H H L L / WE X H L X H L H L X H L X H L H L X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Address Command DESEL NOP TBST Action NOP(Idle after tRC) NOP(Idle after tRC) ILLEGAL
READ / WRITE ILLEGAL ACT PRE / PREA REFA MRS DESEL NOP TBST ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP(Idle after tRSC) NOP(Idle after tRSC) ILLEGAL
READ / WRITE ILLEGAL ACT PRE / PREA REFA MRS ILLEGAL ILLEGAL ILLEGAL ILLEGAL
MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE FOR CKE
10 / May. / 1999
MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning. 1. Clock will be applied at power up along with power. Attempt to maintain CKE high, DQMB high and NOP condition at the inputs along with power. 2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 200µs. 3. Issue precharge commands for all banks. (PRE or PREA) 4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and / CAS Latency can be programmed by setting the mode register(MRS). The mode register stores these date until the next MRS command, which may be issue when both banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command.
CL 000 001 LATENCY MODE 010 011 100 101 110 111 0 1
/ CAS LATENCY R R 2 3 R R R R BURST SINGLE BIT BURST LENGTH
WRITE MODE
R:Reserved for Future Use FP: Full Page
MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Y Q0 Q1 Q2 Q3 Write Y D0 D1 D2 D3
/ CAS Latency
Burst Length
Burst Type
Burst Length
MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITION
CAPACITANCE
MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
AVERAGE SUPPLY CURRENT from Vdd
Parameter
operating current single bank operation (discrete)
Symbol Icc1 Icc2N
Limits (max) 1575 450 360 36 18 990 720 36 18 1800 2700 18
precharge stanby current in Non power-down mode precharge stanby current in Power-down mode active stanby current in Non Power Down Mode active stanby current in Power Down Mode burst current auto-refresh current self-refresh current
Note) 1.Icc(max) is specified at the output open condition. 2.Input single are changed one time during 30ns.
AC OPERATING CONDITIONS AND CHARACTERISTICS
MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
AC TIMING REQUIREMENTS
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Signal
Any AC timing is referenced to the input signal crossing through 1.4V.
MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
SWITCHING CHARACTERISTICS
Symbol tAC tOH tOLZ tOHZ
NOTE) 1.If clock rising time is longer than 1ns, (tr / 2-0.5ns) should be added to the parameter. Output Load Condition
CK 1.4V
tAC tOH
MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
tRAS tRP
tRCD tRCD
CKE DQM
A10 A11 BA0, 1
ACT#0
WRITE#0
PRE#0
ACT#0
WRITE#0
Italic parameter indicates minimum case MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
tRRD tRRD
tRCD tRCD
tWR tWR
CKE DQM A0-9 A10 A11
BA0, 1
ACT#0
WRITE#0 ACT#1
PRE#0 WRITE#1
ACT#0
ACT#2 WRITE#0 PRE#1
Italic parameter indicates minimum case MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
tRAS tRP
tRCD tRCD
A0-9 A10 A11
BA0, 1
ACT#0
READ#0
PRE#0
ACT#0
READ#0
Italic parameter indicates minimum case MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
tRRD tRAS tRP tRRD
tRCD tRCD
A0-9 A10 A11 BA0, 1
ACT#0
READ#0 ACT#1
PRE#0 READ#1
ACT#0 PRE#1
READ#0 ACT#2
Italic parameter indicates minimum case MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
tRRD tRRD
tRCD tRCD tRCD
BL-1+ tWR + tRP BL-1+ tWR + tRP
/ WE CKE DQM A0-9 A10 A11
BA0, 1
ACT#0 ACT#1
WRITE#0 with AutoPrecharge
ACT#0 WRITE#1 with AutoPrecharge
WRITE#0 ACT#1 WRITE#1
Italic parameter indicates minimum case MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
tRRD tRRD
tRCD tRCD tRCD
BL+tRP BL+tRP
A0-9 A10 A11
BA0, 1
ACT#0 ACT#1
READ#0 with Auto-Precharge
ACT#0 READ#1 with Auto-Precharge
READ#0 ACT#1
Italic parameter indicates minimum case MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
/ CAS / WE CKE DQM A0-9 A10 A11
BA0, 1
ACT#0
WRITE#0 ACT#1
WRITE#0 WRITE#1
WRITE#0
Italic parameter indicates minimum case MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
A0-9 A10 A11
BA0, 1
ACT#0
READ#0 ACT#1
READ#0 READ#1
READ#0
Italic parameter indicates minimum case MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
tRCD tCCD
/ CAS / WE CKE DQM A0-9 A10 A11
BA0, 1
ACT#0
WRITE#0 WRITE#0 WRITE#0 READ#0 ACT#1 WRITE#1
Burst Write can be interrupted by Write or Read of any active bank. Italic parameter indicates minimum case MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
A0-9 A10 A11
BA0, 1
ACT#0
READ#0 READ#0 READ#0 READ#0 WRITE#0 ACT#1 READ#1 blank to prevent bus contention
Burst Read can be interrupted by Read or Write of any active bank. Italic parameter indicates minimum case MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
/ CAS / WE CKE DQM A0-9 A10 A11
BA0, 1
ACT#0
WRITE#0 ACT#1
PRE#0 WRITE#1 PRE#1
ACT#1
WRITE#1
Burst Write is not interrupted by Precharge of the other bank.
Burst Write is interrupted by Precharge of the same bank. Italic parameter indicates minimum case
MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
tRRD tRP
tRCD tRCD
A0-9 A10 A11
BA0, 1
ACT#0 READ#0 ACT#1
PRE#0 READ#1 PRE#1
ACT#1
READ#1
Burst Read is not interrupted by Precharge of the other bank.
Burst Read is interrupted by Precharge of the same bank. Italic parameter indicates minimum case
MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Mode Register Setting
tRC tRSC
/ CAS / WE CKE DQM A0-9 A10 A11
BA0, 1
Auto-Ref (last of 8 cycles)
Mode ACT#0 WRITE#0 Register Setting Italic parameter indicates minimum case
MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
/ CAS / WE CKE DQM A0-9 A10 A11
BA0, 1
Auto-Refresh Before Auto-Refresh, all banks must be idle state.
ACT#0
WRITE#0
After tRC from Auto-Refresh, all banks are idle state. Italic parameter indicates minimum case
MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Self-Refresh
CLK can be stopped tRC+1
CKE must be low to maintain Self-Refresh
DQM A0-9 A10 A11
BA0, 1
Self-Refresh Entry Before Self-Refresh Entry, all banks must be idle state.
Self-Refresh Exit After tRC from Self-Refresh Exit, all banks are idle state.
ACT#0
Italic parameter indicates minimum case MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DQM Write Mask
/ CAS / WE CKE DQM A0-9 A10 A11
BA0, 1
masked
ACT#0
WRITE#0
Italic parameter indicates minimum case MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DQM Read Mask
DQM A0-9 A10 A11
BA0, 1
masked
ACT#0
READ#0
Italic parameter indicates minimum case MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Power Down
CLK / CS / RAS / CAS / WE CKE DQM A0-9 A10 A11
BA0, 1
Precharge All
ACT#0
Italic parameter indicates minimum case MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CLK Suspend
DQM A0-9 A10 A11
BA0, 1
ACT#0
WRITE#0 READ#0 CLK suspended
CLK suspended
Italic parameter indicates minimum case MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Serial Presence Detect Table I
Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Function described # of Serial PD Bytes Written during Production Total # of Bytes in SPD device Fundamental memory type # Row Addresses on this assembly # Column Addresses on this assembly # Module Banks on this assembly Data Width of this assembly.. .. Data Width continuation Voltage interface standard of this assembly
SDRAM Cycletime at Max. Supported CAS Latency (CL).
SPD enrty data 128 256 Bytes SDRAM A0-A11 A0-A8 2BANK x72 0 LVTTL 7.5ns
SPD DATA(hex) 80 08 04 0C 09 02 48 00 01 75 54 02 80 08 08 01 8F 04 04 01 01 00 0E 00
Minimum Clock Delay, Back to Back Random Column Addresses ECC
5.4ns
self refresh(15.625uS) x8 x8 1 1 / 2 / 4 / 8 / Full page 4bank 3 0 0
unbuffered
Precharge All, Auto precharge Write1 / Read Burst
SDRAM Access form Clock(2nd highest CAS latency)
SDRAM Access form Clock(3rd highest CAS latency)
N / A N / A N / A 23ns(22.5ns) 15ns 23ns(22.5ns) 45ns
Precharge to Active Minimum Row Active to Row Active Min. RAS to CAS Delay Min Active to Precharge Min
MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Serial Presence Detect Table II
4D48313653373242414D442D362020202020
rrrr yyww ssssssss 00 64 FD 00
MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
3.9Max
MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999
MITSUBISHI LSIs
MH16S72BAMD-6
1, 207, 959, 552-BIT ( 16, 777, 216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
MIT-DS-0314-0.0
MITSUBISHI ELECTRIC
10 / May. / 1999