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536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC Some co


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MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
Some contents subject change without notice. DESCRIPTION
MH8S64BALD 8388608 word 64-bit Synchronous DRAM module. This consist eight industry standard Synchronous DRAMs TSOP. TSOP card edge dual in-line package provides application where high densities large quantities memory required. This socket-type memory module ,suitable easy interchange addition module.
85pin
1pin
FEATURES
Type name Max. Frequency Access Time from [component level]
94pin 95pin
10pin 11pin
MH8S64BALD-6
133MHz
5.4ns
Utilizes industry standard Synchronous DRAMs TSOP package Single 3.3V 0.3V supply Max.Clock frequency 133MHz Fully synchronous operation referenced clock rising edge 4-bank operation controlled BA0,BA1(Bank Address) /CAS latency -2/3(programmable,at buffer mode) LVTTL Interface Burst length 1/2/4/8/Full Page(programmable) Burst type- Sequential interleave burst (programmable) Random column access Burst Write Single Write(programmable) Auto precharge bank precharge controlled Auto refresh Self refresh 4096 refresh cycles every 64ms
124pin 125pin
40pin 41pin
APPLICATION
Main memory graphic memory computer systems
168pin
84pin
MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
NAME DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB0 DQMB1
NAME DQMB2 DQMB3 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
NAME DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 /CAS DQMB4 DQMB5 /RAS
NAME CKE0 DQMB6 DQMB7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
Connection
MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
SERIAL DQM0
D0-7 D0-7
4DRAMs+3.3pF TERMINATION 4DRAMs+3.3pF TERMINATION
CKE0 A11-0,BA0-1 /RAS /CAS
D0-7 D0-7 D0-7 D0-7 D0-7
MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
FUNCTION
CK0,2 Input Master Clock:All other inputs referenced rising edge Clock Enable:CKE controls internal clock.When low,internal clock following cycle ceased. also used select auto self refresh. After self refresh mode started, becomes asynchronous input.Self refresh maintained long low. Chip Select: When high,any command means Operation. Combination /RAS,/CAS,/W defines basic commands. A0-11 specify Row/Column Address conjunction with BA.The Address specified A0-11.The Column Address specified A0-8.A10 also used indicate precharge option.When high read write command, auto precharge performed. When high precharge command, both banks precharged. Bank Address:BA0,1 specifies four bank which command applied.BA must with ,PRE ,READ ,WRITE commands
CKE0
Input
/S0,2 /RAS,/CAS,/W
Input Input
A0-11
Input
BA0-1
Input
DQ0-63
Data Data referenced rising edge Input/Output Mask/Output Disable:When DQMB high burst write.Din current cycle masked.When DQMB high Input burst read,Dout disabled next cycle. Power Supply memory mounted Power Supply module.
DQM0-7 Vdd,Vss
MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
BASIC FUNCTIONS
MH8S64BALD provides basic read write, bank(row)precharge,and auto self refresh. Each command defined control signals /RAS,/CAS rising edge. addition signals,/S,CKE used chip select,refresh option,and precharge option,respectively. know detailed definition commands please command truth table.
/RAS /CAS
Chip Select L=select, H=deselect Command Command Command Refresh Option @refresh command Precharge Option @precharge read/write command define basic commands
Activate(ACT) [/RAS /CAS command activates idle bank indicated Read(READ) [/RAS =H,/CAS READ command starts burst read from active bank indicated BA.First output data appears after /CAS latency. When this command,the bank deactivated after burst read(auto-precharge,READA). Write(WRITE) [/RAS /CAS WRITE command starts burst write active bank indicated Total data length written burst length. When this command, bank deactivated after burst write(auto-precharge,WRITEA). Precharge(PRE) [/RAS /CAS =H,/WE command deactivates active bank indicated This command also terminates burst read write operation. When this command, both banks deactivated(precharge all, PREA). Auto-Refresh(REFA) [/RAS =/CAS =CKE PEFA command starts auto-refresh cycle. Refresh address including bank address generated internally. After this command, banks precharged automatically.
MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
COMMAND TRUTH TABLE
COMMAND Deselect Operation Adress Entry Bank Activate Single Bank Precharge Precharge Bank Column Address Entry Write Column Address Entry Write with AutoPrecharge Column Address Entry Read Column Address Entry Read with Auto Precharge Auto-Refresh Self-Refresh Entry Self-Refresh Exit Burst Terminate Mode Register MNEMONIC DESEL /RAS /CAS BA0,1 A0-9
PREA WRITE
WRITEA
READ
READA REFA REFS REFSX TBST
=High Level, Level, Valid, Don't Care, cycle number NOTE: 1.A7-9 A0-6 Mode Address
MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
FUNCTION TRUTH TABLE
Current State IDLE ACTIVE READ /RAS /CAS BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 Address Command DESEL TBST PRE/PREA REFA DESEL TBST READ/READA WRITE/ WRITEA PRE/PREA REFA DESEL TBST ILLEGAL*2 Bank Active,Latch NOP*4 Auto-Refresh*5 Mode Register Set*5 Begin Read,Latch Determine Auto-Precharge Begin Write,Latch Determine Auto-Precharge Bank Active/ILLEGAL*2 Precharge/Precharge ILLEGAL ILLEGAL NOP(Continue Burst END) NOP(Continue Burst END) Terminate Burst Terminate Burst,Latch READ/READA Begin Read,Determine Auto-Precharge*3 Terminate Burst,Latch BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add WRITE/WRITEA Begin Write,Determine AutoPrecharge*3 PRE/PREA REFA Bank Active/ILLEGAL*2 Terminate Burst,Precharge ILLEGAL ILLEGAL Action
READ/WRITE ILLEGAL*2
MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
FUNCTION TRUTH TABLE(continued)
Current State WRITE /RAS /CAS BA,CA,A10 Address Command DESEL TBST Action NOP(Continue Burst END) NOP(Continue Burst END) Terminate Burst Terminate Burst,Latch READ/READA Begin Read,Determine AutoPrecharge*3 READ with AUTO PRECHARGE WRITE with AUTO PRECHARGE BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add WRITE/ WRITEA PRE/PREA REFA DESEL TBST WRITE/ WRITEA PRE/PREA REFA DESEL TBST WRITE/ WRITEA PRE/PREA REFA Terminate Burst,Latch Begin Write,Determine AutoPrecharge*3 Bank Active/ILLEGAL*2 Terminate Burst,Precharge ILLEGAL ILLEGAL NOP(Continue Burst END) NOP(Continue Burst END) ILLEGAL
READ/READA ILLEGAL ILLEGAL Bank Active/ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP(Continue Burst END) NOP(Continue Burst END) ILLEGAL
READ/READA ILLEGAL ILLEGAL Bank Active/ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
FUNCTION TRUTH TABLE(continued)
Current State CHARGING ACTIVATING WRITE RECOVERING /RAS /CAS BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add ILLEGAL Address Command DESEL TBST PRE/PREA REFA DESEL TBST PRE/PREA REFA DESEL TBST Action NOP(Idle after tRP) NOP(Idle after tRP) ILLEGAL*2 ILLEGAL*2 NOP*4(Idle after tRP) ILLEGAL ILLEGAL NOP(Row Active after tRCD NOP(Row Active after tRCD ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL ILLEGAL*2
READ/WRITE ILLEGAL*2
READ/WRITE ILLEGAL*2
READ/WRITE ILLEGAL*2 PRE/PREA REFA ILLEGAL*2 ILLEGAL*2 ILLEGAL
MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
FUNCTION TRUTH TABLE(continued)
Current State REFRESHING MODE REGISTER SETTING /RAS /CAS BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add Address Command DESEL TBST Action NOP(Idle after tRC) NOP(Idle after tRC) ILLEGAL
READ/WRITE ILLEGAL PRE/PREA REFA DESEL TBST ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP(Idle after tRSC) NOP(Idle after tRSC) ILLEGAL
READ/WRITE ILLEGAL PRE/PREA REFA ILLEGAL ILLEGAL ILLEGAL ILLEGAL
ABBREVIATIONS: Hige Level, Level, Don't Care Bank Address, Address, Column Address, Operation NOTES: entries assume that High during preceding clock cycle current clock cycle. ILLEGAL bank specified state; function legal bank indicated depending state that bank. Must satisfy contention, turn around, write recovery requirements. bank precharging idle state.May precharge bank indicated ILLEGAL bank idle. ILLEGAL Device operation date-integrity guaranteed.
MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
FUNCTION TRUTH TABLE
Current State SELF REFRESH*1 POWER DOWN BANKS IDLE*2 STATE other than listed above /RAS /CAS INVALID Exit Self-Refresh(Idle after tRC) Exit Self-Refresh(Idle after tRC) ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Self-Refresh) INVALID Exit Power Down Idle NOP(Maintain Self-Refresh) Refer Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer Current State Power Down Refer Function Truth Table Begin Suspend Next Cycle*3 Exit Suspend Next Cycle*3 Maintain Suspend Action
ABBREVIATIONS: High Level, Level, Don't Care NOTES: High transition will re-enable other inputs asynchronously. minimum setup time must satisfied before command other than EXIT. Power-Down Self-Refresh entered only form banks idle State. Must legal command.
11/May. /1999
MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
POWER SEQUENCE
Before starting normal operation, following power sequence necessary prevent SDRAM from damaged malfunctioning. Clock will applied power along with power. Attempt maintain high, DQMB high condition inputs along with power. Maintain stable power, stable cock, input conditions minimum 200µs. Issue precharge commands banks. (PRE PREA) After banks become idle state (after tRP), issue more auto-refresh commands. Issue mode register command initialize mode register. After these sequence, SDRAM idle state ready normal operation.
MODE REGISTER
Burst Length, Burst Type /CAS Latency programmed setting mode register(MRS). mode register stores these date until next command, which issue when both banks idle state. After tRSC from command, SDRAM ready command.
/RAS /CAS LTMODE BA0,1 A11-0 BURST TYPE SEQUENTIAL INTERLEAVED
LATENCY MODE
/CAS LATENCY BURST SINGLE BURST LENGTH
WRITE MODE
R:Reserved Future Full Page
MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
Command Address
Read Write
/CAS Latency
Burst Length
Burst Type
Burst Length
Initial Address
Sequential
Column Addressing Interleaved
MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
ABSOLUTE MAXIMUM RATINGS
Symbol Topr Tstg Parameter Supply Voltage Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature Ta=25C Condition with respect with respect with respect Ratings -0.5 -0.5 -0.5 Unit
RECOMMENDED OPERATING CONDITION
(Ta=0 70C, unless otherwise noted) Limits Symbol VIH*1 Parameter Supply Voltage Supply Voltage High-Level Input Voltage inputs Min. Typ. Max. Vdd+0.3 Unit
-0.3 VIL*2 Low-Level Input Voltage inputs NOTES) VIH(max)=Vdd+2.0V pulse width less than acceptable. VIL(min)= -2.0V pulse width less than acceptable.
CAPACITANCE
(Ta=0 70C, 0.3V, unless otherwise noted) Symbol CI(A) CI(C) CI(K) CI/O Parameter Input Capacitance, address Input Capacitance, control Input Capacitance, Input Capacitance, 1Mhz 1.4V bias 200mV swing Test Condition Limits(max.) 45.5 45.5 32.3 16.5 Unit
MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
AVERAGE SUPPLY CURRENT from
(Ta=0 ~70C, 0.3V, unless otherwise noted)
Parameter
operating current single bank operation (discrete)
Symbol Icc1 Icc2N
Test Condition tRC=min.tCLK=min, BL=1, CL=3, IOL=0mA
CKE=VIHmin,tCLK=15ns
Limits (max) 1160 1200
Unit Note *1,2 *1,2 *1,2 *1,2
precharge stanby current power-down mode precharge stanby current Power-down mode active stanby current Power Down Mode active stanby current Power Down Mode burst current auto-refresh current self-refresh current
Icc2NS CLK=VILmax, CKE=VIHmin (fixed) Icc2P CKE=VILmax,tCLK=15ns
Icc2PS CKE=CLK=VILmax (fixed) Icc3N
CKE= /CS=VIHmin,tCLK=15ns
Icc3NS CKE= /CS=VIHmin,CLK=VILmax (fixed) Icc3P
CKE=VILmax,tCLK=15ns
Icc3PS CKE= CLK=VILmax (fixed) Icc4 Icc5 Icc6
tCLK=min, BL=4, CL=3,IOL=0mA banks active(discerte)
tRFC=min, tCLK=min <0.2V
Note) 1.Icc(max) specified output open condition. 2.Input single changed time during 30ns.
OPERATING CONDITIONS CHARACTERISTICS
(Ta=0 70C, 0.3V, unless otherwise noted)
Limits Symbol Parameter Test Condition IOH=-2mA IOL=2mA floating VO=0 VIH=0 Vdd+0.3V VOH(DC) High-Level Output Voltage(DC) VOL(DC) Low-Level Output Voltage(DC) Off-stare Output Current Input Current Min. Max. Unit
MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
TIMING REQUIREMENTS
(Ta=0 70C, 0.3V, unless otherwise noted) Input Pulse Levels: 0.8V 2.0V Input Timing Measurement Level: 1.4V
Limits Symbol Parameter tCLK tRFC tRCD tRAS tRRD tRSC tSRX tPDE tREF cycle time High pulse width pulse width Transition time Input Setup time(all inputs) Input Hold time(all inputs) Cycle time Refresh Cycle time Column Delay Active time Precharge time Write Recovery time Deley time Mode Register Cycle time Self Refresh Exit time Power Down Exit time Refresh Interval time CL=3 CL=2 Min.
67.5 22.5 22.5
Max.
Unit
100K
1.4V
Signal
1.4V
timing referenced input signal crossing through 1.4V.
MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
SWITCHING CHARACTERISTICS
(Ta=0 70C, 0.3V, unless otherwise noted)
Symbol tOLZ tOHZ
Limits Parameter Access time from Output Hold time from Delay time, output impedance from Delay time, output high impedance from CL=3 CL=2 Min. Max.
Unit
Note
NOTE) 1.If clock rising time longer than 1ns, /2-0.5ns) should added parameter. Output Load Condition
1.4V
VOUT Ext.CL=50pF Output Timing Measurement Reference Point
1.4V
1.4V
tOHZ
1.4V
MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
Burst WRITE (single bank) BL=4
tRAS
/RAS
tRCD tRCD
/CAS
A0-9
BA0,1
ACT#0
WRITE#0
PRE#0
ACT#0
WRITE#0
Italic parameter indicates minimum case MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
Burst WRITE (multi bank) BL=4
tRRD tRRD
tRAS
/RAS
tRCD tRCD
/CAS
A0-9
BA0,1
ACT#0
WRITE#0 ACT#1
PRE#0 WRITE#1
ACT#0
ACT#2 WRITE#0 PRE#1
Italic parameter indicates minimum case MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
Burst READ (single bank) BL=4,CL=3
tRAS
/RAS
tRCD tRCD
/CAS
read latency
A0-9
BA0,1
CL=3
ACT#0
READ#0
PRE#0
ACT#0
READ#0
READ allows full data
Italic parameter indicates minimum case MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
Burst READ (multi bank) BL=4,CL=3
tRRD tRAS tRRD
/RAS
tRCD tRCD
/CAS
read latency
A0-9 BA0,1
CL=3
CL=3
ACT#0
READ#0 ACT#1
PRE#0 READ#1
ACT#0 PRE#1
READ#0 ACT#2
Italic parameter indicates minimum case MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
Burst WRITE (multi bank) with AUTO-PRECHARGE BL=4
tRRD tRRD
/RAS
tRCD tRCD tRCD
/CAS
BL-1+ BL-1+
A0-9
BA0,1
ACT#0 ACT#1
WRITE#0 with AutoPrecharge
ACT#0 WRITE#1 with AutoPrecharge
WRITE#0 ACT#1 WRITE#1
Italic parameter indicates minimum case MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
Burst READ (multi bank) with AUTO-PRECHARGE BL=4,CL=3
tRRD tRRD
/RAS
tRCD tRCD tRCD
/CAS
BL+tRP BL+tRP
read latency
A0-9
BA0,1
CL=3
CL=3
CL=3
ACT#0 ACT#1
READ#0 with Auto-Precharge
ACT#0 READ#1 with Auto-Precharge
READ#0 ACT#1
Italic parameter indicates minimum case MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
Page Mode Burst Write (multi bank) BL=4
tRRD
/RAS
tRCD
/CAS A0-9
BA0,1
ACT#0
WRITE#0 ACT#1
WRITE#0 WRITE#1
WRITE#0
Italic parameter indicates minimum case MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
Page Mode Burst Read (multi bank) BL=4,CL=3
tRRD
/RAS
tRCD
/CAS
read latency=2
A0-9
BA0,1
CL=3
CL=3
CL=3
ACT#0
READ#0 ACT#1
READ#0 READ#1
READ#0
Italic parameter indicates minimum case MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
Write Interrupted Write Read BL=4
tRRD
/RAS
tRCD tCCD
/CAS A0-9
BA0,1
CL=3
ACT#0
WRITE#0 WRITE#0 WRITE#0 READ#0 ACT#1 WRITE#1
Burst Write interrupted Write Read active bank. Italic parameter indicates minimum case MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
Read Interrupted Read Write BL=4,CL=3
tRRD
/RAS
tRCD
/CAS
read latency=2
A0-9
BA0,1
ACT#0
READ#0 READ#0 READ#0 READ#0 WRITE#0 ACT#1 READ#1 blank prevent contention
Burst Read interrupted Read Write active bank. Italic parameter indicates minimum case MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
Write Interrupted Precharge BL=4
tRRD
/RAS
tRCD
/CAS A0-9
BA0,1
ACT#0
WRITE#0 ACT#1
PRE#0 WRITE#1 PRE#1
ACT#1
WRITE#1
Burst Write interrupted Precharge other bank.
Burst Write interrupted Precharge same bank. Italic parameter indicates minimum case
MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
Read Interrupted Precharge BL=4,CL=3
tRRD
/RAS
tRCD tRCD
/CAS
read latency=2
A0-9
BA0,1
ACT#0 READ#0 ACT#1
PRE#0 READ#1 PRE#1
ACT#1
READ#1
Burst Read interrupted Precharge other bank.
Burst Read interrupted Precharge same bank. Italic parameter indicates minimum case
MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
Mode Register Setting
tRSC
/RAS
tRCD
/CAS A0-9
BA0,1
Auto-Ref (last cycles)
Mode ACT#0 WRITE#0 Register Setting Italic parameter indicates minimum case
MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
Auto-Refresh BL=4
/RAS
tRCD
/CAS A0-9
BA0,1
Auto-Refresh Before Auto-Refresh, banks must idle state.
ACT#0
WRITE#0
After from Auto-Refresh, banks idle state. Italic parameter indicates minimum case
MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
Self-Refresh
stopped tRC+1
/RAS /CAS
tSRX
must maintain Self-Refresh
A0-9
BA0,1
Self-Refresh Entry Before Self-Refresh Entry, banks must idle state.
Self-Refresh Exit After from Self-Refresh Exit, banks idle state.
ACT#0
Italic parameter indicates minimum case MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
Write Mask
BL=4
/RAS
tRCD
/CAS A0-9
BA0,1
masked
masked
ACT#0
WRITE#0
WRITE#0
WRITE#0
Italic parameter indicates minimum case MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
Read Mask
BL=4, CL=3
/RAS
tRCD
/CAS
read latency=2
A0-9
BA0,1
masked
masked
ACT#0
READ#0
READ#0
READ#0
Italic parameter indicates minimum case MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
Power Down
/RAS /CAS A0-9
Standby Power Down latency=1 Active Power Down
BA0,1
Precharge
ACT#0
Italic parameter indicates minimum case MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
Suspend
BL=4,CL=3
/RAS
tRCD
/CAS
latency=1 latency=1
A0-9
BA0,1
ACT#0
WRITE#0 READ#0 suspended
suspended
Italic parameter indicates minimum case MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
Serial Presence Detect Table
Byte Function described Serial Bytes Written during Production Total Bytes device Fundamental memory type Addresses this assembly Column Addresses this assembly Module Banks this assembly Data Width this assembly. Data Width continuation Voltage interface standard this assembly
SDRAM Cycletime Max. Supported Latency (CL).
enrty data Bytes SDRAM A0-A11 A0-A8 1BANK LVTTL 7.5ns
DATA(hex)
Cycle time CL=3 SDRAM Access from Clock CL=3 DIMM Configuration type (Non-parity,Parity,ECC) Refresh Rate/Type SDRAM width,Primary DRAM Error Checking SDRAM data width
Minimum Clock Delay,Back Back Random Column Addresses non-parity
5.4ns
self refresh(15.625uS) 1/2/4/8/Full page 4bank
unbuffered
Precharge All,Auto precharge Write1/Read Burst
Burst Lengths Supported Banks Each SDRAM device CAS# Latency Latency Write Latency SDRAM Module Attributes SDRAM Device Attributes:General SDRAM Cycle time(2nd highest latency) Cycle time CL=2
SDRAM Access form Clock(2nd highest latency)
CL=2 SDRAM Cycle time(3rd highest latency)
SDRAM Access form Clock(3rd highest latency)
23ns(22.5ns) 15ns 23ns(22.5ns) 45ns
Precharge Active Minimum Active Active Min. Delay Active Precharge
MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
Serial Presence Detect Table
36-61 64-71 Density each bank module Command Address signal input setup time Command Address signal input hold time Data signal input setup time Data signal input hold time Superset Information (may used future) Revision Checksum bytes 0-62 Manufactures Jedec code JEP-108E Manufacturing location MITSUBISHI Miyoshi,Japan Tajima,Japan NC,USA Germany 73-90 91-92 93-94 95-98 99-125 128+ Manufactures Part Number Revision Code Manufacturing date Assembly Serial Number Manufacture Specific Data Intetl specification frequency Intel specification CAS# Latency support Unused storage locations MH8S64BALD-6 revision year/week code serial number option CL=3,AP,CK0,2 open 64MByte 1.5ns 0.8ns 1.5ns 0.8ns option JEDEC2 1CFFFFFFFFFFFFFF
rrrr yyww ssssssss
MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
133.35
8.89 11.43
6.35 36.83 24.495 42.18
6.35 54.61 127.35
1.27
34.925
3.9Max
1.27
MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999
MH8S64BALD-6
536,870,912-BIT 8,388,608-WORD 64-BIT Synchronous DYNAMIC
Keep safety first your circuit designs!
Mitsubishi Electric Corporation puts maximum effort into making semiconductor products better more reliable,but there always possibility that trouble occur with them. Trouble with semiconductors consideration safety when making your circuit designs,with appropriate measures such placement substitutive,auxiliary circuits,(ii) nonflammable material (iii) prevention against malfunction mishap.
Notes regarding these materials
1.These materials intended reference assist customers selection Mitsubishi semiconductor product best suited customer's application;they convey license under intellectual property rights,or other rights,belonging Mitsubishi Electric Corporation third party. 2.Mitsubishi Electric Corporation assumes responsibility damage, infringement thirdparty's rights,originating product data,diagrams,charts circuit application examples contained these materials. 3.All information contained these materials,including product data, diagrams charts,represent information products time publication these materials,and subject change Mitsubishi Electric Corporation without notice product improvements other reasons. therefore recommended that customers contact Mitsubishi Electric Corporation authorized Mitsubish Semiconductor product distributor latest product information before purchasing product listed herein. 4.Mitsubishi Electric Corporation semiconductors designed manufactured device system that used under circumstances which human life potentially stake. Please contact Mitsubishi Electric Corporation authorized Mitsubishi Semiconductor product distributor when considering product contained herein special applications,such apparatus systems transportation, undersea repeater use. 5.The prior written approval Mitsubishi Electric Corporation necessary reprint reproduce whole part these materials. 6.If these products technologies subject Japanese export control restrictions,they must exported under license from Japanese government cannot imported into country other than approved destination. diversion reexport contrary export control laws regulations Japan and/or country destination prohibited. 7.Please contact Mitsubishi Electric Corporation authorized Mitsubishi Semiconductor product distributor further details these materials products contained therein.
MIT-DS-0317-0.0
MITSUBISHI ELECTRIC
11/May. /1999

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