16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V

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16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V

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M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144WORD 16-BIT 524,288-WORD 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
FEATURES
MITSUBISHI M6MGB/T160S4BVP Stacked Multi Access time Chip Package (S-MCP) that contents 16M-bits flash memory Flash Memory 90ns (Max.) 4M-bits Static 48-pin TSOP (TYPE-I). SRAM 85ns (Max.) Supply voltage Vcc=2.7 3.6V 16M-bits Flash memory 2097152 bytes /1048576 words, Ambient temperature 3.3V-only, high performance non-volatile memory version Ta=-20 85°C fabricated CMOS technology peripheral circuit Package 48-pin TSOP (Type-I) 0.4mm lead pitch DINOR(DIvided bit-line NOR) architecture memory cell. 4M-bits SRAM 524288bytes 262144words unsynchronous SRAM fabricated silicon-gate CMOS APPLICATION technology. Mobile communication products M6MGB/T160S4BVP suitable application mobile-communication-system reduce both mount space weight
CONFIGURATION (TOP VIEW)
S-CE F-RP# F-WP# S-VCC F-RY/BY# BYTE# DQ15/A-1 DQ14 DQ13 DQ12 F-VCC DQ11 DQ10 F-CE#
10.0
14.0
F-VCC S-VCC A-1-A17 A18-A19 DQ0-DQ15 F-CE# S-CE F-WP# F-RP# F-RY/BY# BYTE# :Vcc Flash NC:Non Connection :Vcc SRAM :GND Flash/SRAM :Flash/SRAM common Address :Address Flash :Data :Flash Chip Enable :SRAM Chip Enable :Flash/SRAM Output Enable :Flash/SRAM Write Enable :Flash Write Protect :Flash Reset Power Down :Flash Ready /Busy :Flash/SRAM Byte Enable
Sep. 1999 Rev.2.0
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144WORD 16-BIT 524,288-WORD 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
BLOCK DIAGRAM
16Mb Flash Memory
WORD PAGE BUFFER Main Block 32KW
F-VCC (3.3V) (0V)
Main Block
Parameter Block7 Parameter Block6 Parameter Block5 Parameter Block4 Parameter Block3 Parameter Block2 Parameter Block1 Boot Block
Bank(II)
X-DECODER Bank(I)
32KW
16KW 16KW 16KW 16KW 16KW 16KW 16KW 16KW
ADDRESS INPUTS
Y-DECODER
Y-GATE SENSE AMP.
STATUS REGISTER
MULTIPLEXER
CHIP ENABLE INPUT OUTPUT ENABLE INPUT WRITE ENABLE INPUT WRITE PROTECT INPUT RESET/POWER DOWN INPUT BYTE ENABLE INPUT READY/BUSY OUTPUT
F-CE# F-WP# F-RP# BYTE#
INPUT/OUTPUT BUFFERS
F-RY/BY# DQ15/A-1 DQ14DQ13 DQ12 DQ3DQ2DQ1DQ0
SRAM
ADDRESS INPUT BUFFER SENSE AMP.
DATA INPUTS/OUTPUTS
DECODER
SENSE AMP.
524288WORD BITS 262144 WORD BITS
OUTPUT BUFFER
OUTPUT BUFFER
DQ15/A-1
S-CE
DATAINPUT BUFFER
CLOCK GENERATOR
S-VCC
DATAINPUT BUFFER
BYTE#
Sep. 1999 Rev.2.0
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144WORD 16-BIT 524,288-WORD 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
Flash Memory
Flash Memory M6MGB/T160S4BVP 3.3V-only high speed 16,777,216-bit CMOS boot block Flash Memories with alternating (Back Ground Operation) feature. feature device allows Program Erase operations performed bank while device simultaneously allows Read operations performed other bank. This feature suitable mobile personal computing, communication products. Flash Memory M6MGB/T160S4BVP fabricated CMOS technology peripheral circuits DINOR(Divided line NOR) architecture memory cells.
FEATURES
Organization
.1048,576 word 16bit .2,097,152 word
Boot Block M6MGB160S4BVP Bottom Boot M6MGT160S4BVP Boot Other Functions Soft Ware Command Control Selective Block Lock Erase Suspend/Resume Program Suspend/Resume Status Register Read Alternating Back Ground Program/Erase Operation Between Bank(I) Bank(II)
2.7~3.6V Supply voltage
Access time
90ns(Max.)
Power Dissipation (Max. 5MHz) Read (After Automatic Power saving) 0.33mW (typ.) Program/Erase .144 (Max.) 0.33mW (typ.) Standby Deep power down mode 0.33mW (typ.) Auto program Bank(I) (typ.) Program Time Program Unit .1word/1byte (Byte Program) (Page Program) 128word/256byte Auto program Bank(II) (typ.) Program Time 128word/256byte Program Unit Auto Erase (typ.) Erase time Erase Unit Bank(I) Boot Block 16Kword/32Kbyte Parameter Block 16Kword/32Kbyte 32Kword/64Kbyte Bank(II) Main Block Program/Erase cycles
100Kcycles
Sep. 1999 Rev.2.0
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144WORD 16-BIT 524,288-WORD 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package) FUNCTION
Flash Memory M6MGB/T160S4BVP includes on-chip program/erase control circuitry. Write State Machine (WSM) controls block erase byte/page program operations. Operational modes selected commands written Command User Interface (CUI). Status Register indicates status when successfully completes desired program block erase operation. Deep Powerdown mode enabled when GND, minimizing power consumption. Read Flash Memory M6MGB/T160S4BVP three read modes, which accesses memory array, Device Identifier Status Register. appropriate read command required written CUI. Upon initial device powerup after exit from deep powerdown, Flash Memory automatically resets read array mode. read array mode, level input F-CE# OE#, high level input RP#, address signals address inputs (A19-A-1:Byte Mode, A19-A0:Word Mode) output data addressed location data input/output (D7-D0:Byte Mode, D15-D0:Word Mode). Write Writes enables reading memory array data, device identifiers reading clearing Status Register. They also enable block erase program. written bringing level, while F-CE# level high level. Address data latched earlier rising edge F-CE#. Standard micro-processor write timings used. Alternating Background Operation (BGO) Flash Memory M6MGB/T160S4BVP allows read array from bank while other bank operates software command write cycling erasing programming operation background. Read array operation with other bank performed changing bank address without additional command. When bank address points bank software command write cycling erasing programming operation, data read from status register. access time with same normal read operation. Output Disable When VIH, output from devices disabled. Data input/output high-impedance(High-Z) state. Standby When F-CE# VIH, device standby mode power consumption reduced. Data input/output high-impedance(High-Z) state. memory deselected during block erase program, internal control circuits remain active device consume normal active power until operation completes. Deep Power-Down When VIL, device deep powerdown mode power consumption substantially low. During read modes, memory deselected data input/output high-impedance(High-Z) state. After return from powerdown, reset Read Array Status Register cleared value 80H. During block erase program modes, will abort either operation. Memory array data block being altered become invalid. Automatic Power-Saving (APS) Automatic Power-Saving minimizes power consumption during read mode. device automatically turns this mode when addresses F-CE# isn't changed more than 200ns after last alternation. power consumption becomes same stand-by mode. While this mode, output data latched read out. data read correctly when addresses changed.
Sep. 1999 Rev.2.0
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144WORD 16-BIT 524,288-WORD 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
SOFTWARE COMMAND DEFINITIONS device operations selected writing specific software command into Command User Interface. Read Array Command (FFH) device Read Array mode initial device power after exit from deep powerdown, writing Command User Interface. After starting internal operation device read status register mode automatically. Read Device Identifier Command (90H) normally read device identifier codes when Read Device Identifier Code Command(90H) written command latch. Following command write, manufacturer code device code read from address 0000H 0001H, respectively. Read Status Register Command (70H) Status Register read after writing Read Status Register command Command User Interface. Also, after starting internal operation device Read Status Register mode automatically. contents Status Register latched later falling edge F-CE#. F-CE# must toggled every status read. Clear Status Register Command (50H) Erase Status, Program Status Block Status bits "1"s Write State Machine only reset Clear Status Register command 50H. These bits indicates various failure conditions. C)Single Data Load Page Buffer (74H) Page Buffer Flash (0EH/D0H) Single data load page buffer performed writing followed second write specifying column address data. Distinct data 256byte/128word loaded page buffer this two-command sequence. other hand, loaded data page buffer programed simultaneously writing Page Buffer Flash command followed confirm command D0H. After completion programing data page buffer cleared automatically. This command valid only Bank(I) alike Word/Byte Program. Clear Page Buffer Command (55H) Loaded data page buffer cleared writing Clear Page Buffer command followed Confirm command D0H. This command valid clearing data loaded Single Data Load Page Buffer command. Suspend/Resume Command (B0H/D0H) Writing Suspend command during block erase operation interrupts block erase operation allows read from another block memory. Writing Suspend command during program operation interrupts program operation allows read from another block memory. Bank address required when writing Suspend/Resume Command. device continues output Status Register data when read, after Suspend command written Polling Status Suspend Status bits will determine when erase operation program operation been suspended. this point, writing Read Array command enables reading data from blocks other than that which suspended. When Resume command written CUI, will continue with erase program processes.
DATA PROTECTION Block Erase Confirm Command (20H/D0H) Automated block erase initiated writing Block Erase command followed Confirm command D0H. address within block erased required. executes iterative erase pulse application erase verify operation. Program Commands A)Word/Byte Program (40H) Word/Byte program executed two-command sequence. Word/Byte Program Setup command written Command Interface, followed second write specifying address data written. controls program pulse application verify operation. Word/Byte Program Command Valid only Bank(I). B)Page Program Data Blocks (41H) Page Program Bank(I) Bank(II) allows fast programming 128words/256bytes data. Writing initiates page program operation Data area. From cycle 257th cycle (Byte Mode)129th cycle (Word Mode), write data must serially inputted. Address A6-A0,A-1 (Byte Mode) A6-A0 (Word Mode) have incremented from 7FH/FFH. After completion data loading, controls program pulse application verify operation. Flash Memory M6MGB/T160S4BVP provides selectable block locking memory blocks. Each block associated nonvolatile lock-bit which determines lock status block. addition, Flash Memory master Write Protect (WP#) which prevents modifications memory blocks whose lock-bits "0", when low. When high, blocks programmed erased regardless state lock-bits, lock-bits cleared erase. BLOCK LOCKING table details. Power Supply Voltage When power supply voltage (F-Vcc) less than VLKO, Lock-Out voltage, device Read-only mode. Regarding electrical characteristics VLKO, P.10. delay time required before device operation initiated. delay time measured from time F-Vcc reaches F-Vccmin (2.7V). During power RP#=GND recommended. Falling Busy status recommended possibility damaging device. MEMORY ORGANIZATION Flash Memory M6MGB/T16S2BVP 32Kbyte boot block, seven 32Kbyte parameter blocks, Bank(I) twenty-eight 64Kbyte main blocks Bank(II). block erased independently other blocks array.
Sep. 1999 Rev.2.0
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144WORD 16-BIT 524,288-WORD 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
MEMORY ORGANIZATION
Bytemode) 1F0000H-1FFFFFH 1E0000H-1EFFFFH 1D0000H-1DFFFFH 1C0000H-1CFFFFH 1B0000H-1BFFFFH 1A0000H-1AFFFFH 190000H-19FFFFH 180000H-18FFFFH 170000H-17FFFFH 160000H-16FFFFH 150000H-15FFFFH 140000H-14FFFFH 130000H-13FFFFH 120000H-12FFFFH 110000H-1FFFFFH 100000H-10FFFFH F0000H-FFFFFH E0000H-EFFFFH D0000H-DFFFFH C0000H-CFFFFH B0000H-BFFFFH A0000H-AFFFFH 90000H-9FFFFH 80000H-8FFFFH 70000H-7FFFFH 60000H-6FFFFH 50000H-5FFFFH 40000H-4FFFFH 38000H-3FFFFH 30000H-37FFFH 28000H-2FFFFH 20000H-27FFFH 18000H-1FFFFH 10000H-17FFFH 08000H-0FFFFH 00000H-07FFFH A19-A-1 (Byte Mode) Wordmode) F8000H-FFFFFH F0000H-F7FFFH E8000H-EFFFFH E0000H-E7FFFH D8000H-DFFFFH D0000H-D7FFFH C8000H-CFFFFH C0000H-C7FFFH B8000H-BFFFFH B0000H-B7FFFH A8000H-AFFFFH A0000H-A7FFFH 98000H-9FFFFH 90000H-97FFFH 88000H-8FFFFH 80000H-87FFFH 78000H-7FFFFH 70000H-77FFFH 68000H-6FFFFH 60000H-67FFFH 58000H-5FFFFH 50000H-57FFFH 48000H-4FFFFH 40000H-47FFFH 38000H-3FFFFH 30000H-37FFFH 28000H-2FFFFH 20000H-27FFFH 1C000H-1FFFFH 18000H-1BFFFH 14000H-17FFFH 10000H-13FFFH 0C000H-0FFFFH 08000H-0BFFFH 04000H-07FFFH 00000H-03FFFH A19-A0 (Word Mode) Bytemode) Wordmode) FC000H-FFFFFH
32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK BANK(II) BANK(I) 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK
16Kword PARAMETER BLOCK 16Kword PARAMETER BLOCK 16Kword PARAMETER BLOCK 16Kword PARAMETER BLOCK 16Kword PARAMETER BLOCK 16Kword PARAMETER BLOCK 16Kword PARAMETER BLOCK
1F8000H-1FFFFFH 1F0000H-1F7FFFH 1E8000H-1EFFFFH 1E0000H-1E7FFFH 1D8000H-1DFFFFH 1D0000H-1D7FFFH 1C8000H-1CFFFFH 1C0000H-1C7FFFH 1B0000H-1BFFFFH 1A0000H-1AFFFFH 190000H-19FFFFH 180000H-18FFFFH 170000H-17FFFFH 160000H-16FFFFH 150000H-15FFFFH 140000H-14FFFFH 130000H-13FFFFH 120000H-12FFFFH 110000H-11FFFFH 100000H-10FFFFH F0000H-FFFFFH E0000H-EFFFFH D0000H-DFFFFH C0000H-CFFFFH B0000H-BFFFFH A0000H-AFFFFH 90000H-9FFFFH 80000H-8FFFFH 70000H-7FFFFH 60000H-6FFFFH 50000H-5FFFFH 40000H-4FFFFH 30000H-3FFFFH 20000H-2FFFFH 10000H-1FFFFH 00000H-0FFFFH A19-A-1 (Byte Mode)
16Kword BOOT BLOCK
F8000H-FBFFFH 16Kword PARAMETER BLOCK F4000H-F7FFFH 16Kword PARAMETER BLOCK
BANK(I)
F0000H-F3FFFH 16Kword PARAMETER BLOCK EC000H-EFFFFH 16Kword PARAMETER BLOCK E8000H-EBFFFH 16Kword PARAMETER BLOCK E4000H-E7FFFH 16Kword PARAMETER BLOCK E0000H-E3FFFH 16Kword PARAMETER BLOCK D8000H-DFFFFH D0000H-D7FFFH C8000H-CFFFFH C0000H-C7FFFH B8000H-BFFFFH B0000H-B7FFFH A8000H-AFFFFH A0000H-A7FFFH 98000H-9FFFFH 90000H-97FFFH 88000H-8FFFFH 80000H-87FFFH 78000H-7FFFFH 70000H-77FFFH 68000H-6FFFFH 60000H-67FFFH 58000H-5FFFFH 50000H-57FFFH 48000H-4FFFFH 40000H-47FFFH 38000H-3FFFFH 30000H-37FFFH 28000H-2FFFFH 20000H-27FFFH 18000H-1FFFFH 10000H-17FFFH 08000H-0FFFFH 00000H-07FFFH A19-A0 (Word Mode)
32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK BANK(II) 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK
16Kword BOOT BLOCK
Flash Memory M6MGB160S4BVP Memory
Flash Memory M6MGT160S4BVP Memory
Sep. 1999 Rev.2.0
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144WORD 16-BIT 524,288-WORD 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package) OPERATIONS Operations Word-Wide Mode
Pins
Mode Read
F-CE#
DQ0-15 Data Status Register Data Lock Data (DQ6) Identifier Code Hi-Z Hi-Z Command/Data Command Command Hi-Z
RY/BY# (Hi-Z) (Hi-Z) (Hi-Z)
Array Status Register Lock Status Identifier Code Output disable Stand Program Write Erase Others Deep Power Down
Operations Byte-Wide Mode
Mode Read Pins F-CE# DQ0-7 Data Status Register Data Lock Data (DQ6) Identifier Code Hi-Z Hi-Z Command/Data Command Command Hi-Z RY/BY# (Hi-Z) (Hi-Z) (Hi-Z)
Array Status Register Lock Status Identifier Code Output disable Stand Program Write Erase Others Deep Power Down
RY/BY# VOH(Hi-Z). *The RY/BY# open drain output indicates status internal WSM. When low,it indicates that Busy performing operation. pull-up resistor 10K-100K Ohms required allow RY/BY# signal transition high indicating Ready condition. control pins.
Sep. 1999 Rev.2.0
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144WORD 16-BIT 524,288-WORD 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
SOFTWARE COMMAND DEFINITION Command List
cycle Command Mode Read Array Device Identifier Read Status Register Clear Status Register Clear Page Buffer Byte/Word Program Page Program Single Data Load Page Buffer Page Buffer Flash Block Erase Confirm Suspend Resume Read Lock Status Lock Program Confirm Erase Unlocked Blocks Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Address Bank3) Bank(I) Bank Bank(I) Bank(I) Bank Bank Bank Bank Data
(DQ7-0) (DQ15-0)
cycle Data Mode Address Bank
(DQ7-0) (DQ15-0)
~257th cycles (Byte Mode) ~129th cycles (Word Mode)
Data Mode Address
(DQ7-0) (DQ15-0)
Read Read Write Write Write Write Write Write
SRD4)
Write
Read Write Write
word-wide version(Byte#=H), upper byte data (DQ8-DQ15) ignored. IA=ID Code Address A0=VIL (Manufacturer's Code) A0=VIH (Device Code), ID=ID Code Bank Bank Address (Bank(I) Bank(II)) A19-A17. Status Register Data Byte/Word Program, Single Data Load Page Buffer Flash Command valid only Bank(I). Write Address,WD Write Data WA0,WAn=Write Address, WD0,WDn=Write Data. Byte Mode Write Address Write Data must provided sequentially from A6-A0,A-1. Page size 256Byte (256byte 8bit), also A19-A7(Block Address, Page Address) must valid. Word Mode Write Address Write Data must provided sequentially from A6-A0. Page size 128word (128word 16bit). also A19-A7(Block Address, Page Address) must valid. Write Address Upper page address, A19-A7(Block Address, Page Address) must valid. Block Address Block Address A19-A14(Bank1) A19-A15(Bank2) provides Block Lock Status, Block Unlock, Block Locked.
Sep. 1999 Rev.2.0
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144WORD 16-BIT 524,288-WORD 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
BLOCK LOCKING
Lock (Internally) Write Protection Provided BANK(I) BANK(II) Note Lock Boot Parameter Data Locked Locked Locked Locked Deep Power Down Mode Locked Locked Locked Locked Locked Locked Unlocked Unlocked Unlocked Unlocked Unlocked Unlocked Blocks Unlocked
provides Lock Status each block after writing Read Lock Status command (71H). F-WP# pins must switched during performing Erase Write operations Busy (WSMS Erase/Write command locked blocks aborted. this time read mode array read mode status read mode 00B0H read. Please issue Clear Status Register command plus Read Array command change mode from status read mode array read mode.
STATUS REGISTER
Symbol SR.7 SR.6 SR.5 SR.4 SR.3 SR.2 SR.1 SR.0 (DQ7) (DQ6) (DQ5) (DQ4) (DQ3) (DQ2) (DQ1) (DQ0) Status Write State Machine Status Suspend Status Erase Status Program Status Block Status after Program Reserved Reserved Reserved Definition Ready Suspended Error Error Error Busy Operation Progress Completed Successful Successful Successful
*The F-RY/BY# open drain output indicates status internal WSM. When low,it indicates that Busy performing operation. pull-up resistor 10K-100K Ohms required allow F-RY/BY# signal transition high indicating Ready condition. *DQ3 indicates block status after page programming, byte/word programming page buffer flash. When "1", page over-programed cell over-program occurs, device block fail. However "1", please block erase block. block revive.
Sep. 1999 Rev.2.0
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144WORD 16-BIT 524,288-WORD 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package) DEVICE IDENTIFIER CODE
Code Manufacturer Code Device Code (-T160S4BVP) Device Code (-B160S4BVP) Pins Hex. Data
word-wide mode, upper data(D15-8) "0".
ABSOLUTE MAXIMUM RATINGS
Symbol F-Vcc Tstg Parameter Flash voltage input output voltage Ambient temperature Temperature under bias Storage temperature Output short circuit current Conditions
With respect Ground
-0.2 -0.6
Unit
Minimum voltage -0.5V input/output pins. During transitions, this level undershoot -2.0V periods <20ns. Maximum voltage input/output pins F-VCC+0.5V which, during transitions, overshoot F-VCC+1.5V periods <20ns.
CAPACITANCE
Symbol COUT Parameter Input capacitance (Address, Control Pins) Output capacitance Test conditions 25°C, 1MHz, Vout Limits Unit
Note: value common pins Flash Memory Flash Memory SRAM.
ELECTRICAL CHARACTERISTICS -20~ 85°C, F-Vcc 2.7V 3.6V, unless otherwise noted)
Symbol ISB1 ISB2 ISB3 ISB4 ICC1 ICC2 ICC3 ICC4 ICC5 VOH1 VOH2 VLKO Parameter Input leakage current Output leakage current F-VCC standby current Test conditions
F-VCC 3.6V, VIN=VIL/VIH, F-CE# F-RP# =F-WP#
Limits Typ1)
±2.0
F-Vcc+0.5
Unit
F-VCC 3.6V, VIN=GND F-VCC, F-CE# F-RP# F-WP# F-VCC±0.3V F-VCC 3.6V, VIN=VIL/VIH, F-RP#
F-VCC 3.6V, VIN=GND VCC, F-RP# =GND±0.3V
F-VCC deep powerdown current F-VCC read current Word Byte F-VCC Write current Word Byte F-VCC program current F-VCC erase current F-VCC suspend current Input voltage Input high voltage Output voltage Output high voltage Lock-Out voltage
F-VCC 3.6V, VIN=VIL/VIH, F-CE# VIL, F-RP#=OE#=VIH, IOUT
5MHz 1MHz F-VCC 3.6V,VIN=VIL/VIH, F-CE# =WE#= VIL, F-RP#=OE#=VIH
F-VCC 3.6V, VIN=VIL/VIH, F-CE# F-RP# =F-WP# F-VCC 3.6V, VIN=VIL/VIH, F-CE# F-RP# =F-WP# F-VCC 3.6V, VIN=VIL/VIH, F-CE# F-RP# =F-WP#
4.0mA -2.0mA -100mA
0.85(F-Vcc) F-Vcc-0.4
0.45
currents unless otherwise noted. Typical values F-Vcc=3.3V, Ta=25°C protect against initiation write cycle during power-up/ down, write cycle locked less than VLKO. less than VLKO, Write State Machine reset read mode. When Write State Machine Busy state, less than VLKO, alteration memory contents
occur.
Sep. 1999 Rev.2.0
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144WORD 16-BIT 524,288-WORD 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package) ELECTRICAL CHARACTERISTICS ~85°C) Read-Only Mode
Limits
Symbol
Parameter
Speed Item: F-Vcc=2.7~3.6V
Unit
(AD) (CE) (OE) tCLZ tDF(CE) tOLZ tDF(OE) tPHZ
tAVAV tAVQV tELQV tGLQV tELQX tEHQZ tGLQX tGHQZ tPLQZ
Read cycle time Address access time Chip enable access time Output enable access time Chip enable output low-Z Chip enable high output high Output enable output low-Z Output enable high output high F-RP# output high-Z
ta(BYTE) tFL/HQV BYTE# access time tBHZ tFLQZ BYTE# output high-Z tBCD tBAD tOEH Output hold from F-CE#, OE#, addresses tELFL/H F-CE# BYTE# high tAVFL/H Address BYTE# high tWHGL tPHEL hold from high F-RP# recovery F-CE#
Timing measurements made under waveforms read operations.
ELECTRICAL CHARACTERISTICS ~85°C) Write Mode (WE# control)
Symbol
Parameter
Limits Speed Item: F-Vcc=2.7~3.6V
Unit
tOEH tWPH
tAVAV tAVWH tWHAX tDVWH tWHDX tWHGL tELWL tWHEH tWLWH tWHWL tFL/HWH tWHFL/H
tGHWL tGHWL tBLS tPHHWH tBLH tQVPH tDAP tDAE tWHRL tWHRH1 tWHRH2 tWHRL tPHWL
Write cycle time Address set-up time Address hold time Data set-up time Data hold time hold from high Latency between Read Write Chip enable set-up time Chip enable hold time Write pulse width Write pulse width high Byte enable high set-up time Byte enable high hold time hold Block Lock set-up write enable high Block Lockhold from valid Duration auto-program operation Duration auto-block erase operation high RY/BY# F-RP# high recovery write enable
Read timing parameters during command write operations mode same during read-only operations mode. Typical values F-Vcc=3.3V, Ta=25°C
Sep. 1999 Rev.2.0
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144WORD 16-BIT 524,288-WORD 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package) ELECTRICAL CHARACTERISTICS 85°C) Write Mode (CE# control)
Symbol
Parameter
tOEH tCEP tCEPH tGHEL tBLS tBLH tDAP tDAE tEHRL
tAVAV tAVWH tEHAX tDVWH tEHDX tEHGL tWLEL tEHWH tELEH tEHEL tFL/HWH tWHFL/H tGHEL tPHHEH tQVPH
Write cycle time Address set-up time Address hold time Data set-up time Data hold time hold from F-CE# high Latency between Read Write Write enable set-up time Write enable hold time F-CE# pulse width F-CE# pulse width high Byte enable high set-up time Byte enable high hold time hold F-CE# Block Lock set-up write enable high Block Lockhold from valid
Limits Speed Item: F-Vcc=2.7~3.6V
Unit
tEHRH1 Duration auto-program operation tEHRH2 Duration auto-block erase operation tEHRL F-CE# high RY/BY# tPHWL F-RP# high recovery write enable
Read timing parameters during command write operation mode same during read-only operation mode. Typical values F-Vcc=3.3V, Ta=25°C
Erase Program Performance
Parameter Block Erase Time Main Block Write Time (Page Mode) Page Write Time Unit
Program Suspend Latency Erase Suspend Time
Parameter Program Suspend Latency Erase Suspend Time
Please page
Unit
Power Down Timing
Symbol tVCS
Please page During power up/down, noise pulses control pins, device possibility accidental erasure programming. device must protected against initiation write cycle memory contents during power up/down. delay time min.2msec always required before read operation write operation initiated from time F-Vcc reaches F-Vccmin during power up/down. holding F-RP# VIL, contents memory protected during F-Vcc power up/down. During power F-RP# must held min.2ms from time F-Vcc reaches F-Vccmin. During power down, F-RP# must held until reaches GND. F-RP# doesn't have latch mode ,therefore F-RP# must held during read operation erase/program operation.
Parameter =VIH set-up time from Vccmin
Unit
Sep. 1999 Rev.2.0
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144WORD 16-BIT 524,288-WORD 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
POWER DOWN TIMING
Read /Write Inhibit Read /Write Inhibit Read /Write Inhibit
3.3V F-VCC tVCS F-RP# F-CE#
WAVEFORMS READ OPERATION TEST CONDITIONS
ADDRESSES
ADDRESS VALID
TEST CONDITIONS CHARACTERISTICS Input voltage 3.0V Input rise fall times Reference voltage timing measurement 1.5V Output load 1TTL gate CL(30pF)
(AD) (CE) tDF(CE)
F-CE#
tOEH (OE) tOLZ HIGH-Z tCLZ tDF(OE) HIGH-Z
1.3V 1N914 3.3kW =30pF
DATA
OUTPUT VALID
F-RP#
tPHZ
Sep. 1999 Rev.2.0
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144WORD 16-BIT 524,288-WORD 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
WAVEFORMS WRITE READ OPERATION
ADDRESSES
ADDRESS VALID
(AD) (CE) (OE)
F-CE#
tDF(CE)
tDF(OE)
HIGH-Z
tOLZ tCLZ
OUTPUT VALID
DATA
HIGH-Z
Valid
F-RP#
tPHZ
case F-CE# fixed, allowed define timming specification from rising edge falling edge OE#, valid data read after spec tRE+ta(CE). (This only FFH,71H program read)
BYTE WAVEFORMS READ OPERATION
ADDRESSES A19,A-1*) ta(CE) ta(OE) ta(BYTE) tOLZ tCLZ tBCD HIGH-Z tBAD
OUTPUT VALID VALID VALID ADDRESS VALID ADDRESS VALID
ta(AD) F-CE#
tDF(CE)
tDF(OE) tBAD ta(BYTE)
BYTE#
DATA DATA D14)
tBHZ HIGH-Z
VALID
ta(AD)
When BYTE#=VIH, F-CE#=OE#=VIL D15/A-1 output status. this time, input signal must applied.
Sep. 1999 Rev.2.0
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144WORD 16-BIT 524,288-WORD 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package) WAVEFORMS PAGE PROGRAM OPERATION (WE# control)
A19~A7
BYTE#=VIL (A6~A-1) BYTE#=VIH ~A0) other bank address
BANK ADDRESS VALID
PROGRAM
READ STATUS WRITE READ REGISTER ARRAY COMMAND
VALID
VALID
ADDRESS VALID 01H~FEH
BANK ADDRESS VALID
VALID
01H~7EH
tWPH
ta(CE)
F-CE#
ta(CE) ta(OE)
tOEH tGHWL ta(OE) tOEH tDAP
DATA
DOUT
tWHRL
F-RY/BY# BYTE# F-RP#
tBLS tBLH
F-WP#
WAVEFORMS PAGE PROGRAM OPERATION (F-CE# control)
A19~A7
BYTE#=VIL (A6~A-1) BYTE#=VIH ~A0) other bank address
BANK ADDRESS VALID
PROGRAM
READ STATUS WRITE READ REGISTER ARRAY COMMAND
VALID
VALID
ADDRESS VALID 01H~FEH
BANK ADDRESS VALID
tCEP
VALID
01H~7EH
tCEPH
ta(CE) ta(OE) tOEH tGHEL tOEH tDAP
DOUT
F-CE#
ta(CE) ta(OE)
DATA
tEHRL
F-RY/BY#
BYTE#
F-RP#
tBLS
tBLH
F-WP#
Sep. 1999 Rev.2.0
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144WORD 16-BIT 524,288-WORD 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package) WAVEFORMS BYTE WORD PROGRAM OPERATION (WE# control) only BANK(I))
PROGRAM
BANK ADDRESS VALID
ADDR F-CE# DATA F-RY/BY#
READ STATUS REGISTER
WRITE READ ARRAY COMMAND
ADDRESS VALID
BANK(I) ADDRESS VALID
ta(CE) ta(OE) tOEH
tWPH
tWHRL
BYTE# F-RP#
tBLS
tDAP tBLH
F-WP#
WAVEFORMS BYTE WORD PROGRAM OPERATION (F-CE# control)
PROGRAM
BANK ADDRESS VALID
only BANK(I))
WRITE READ ARRAY COMMAND
ADDR F-CE# DATA F-RY/BY# BYTE# F-RP#
READ STATUS REGISTER
ADDRESS VALID
BANK(I) ADDRESS VALID
ta(CE) ta(OE)
tCEP
tOEH
tEHRL tBLS tDAP tBLH
F-WP#
Sep. 1999 Rev.2.0
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144WORD 16-BIT 524,288-WORD 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
WAVEFORMS ERASE OPERATIONS (WE# control)
ADDRESSES
ERASE READ STATUS REGISTER WRITE READ ARRAY COMMAND
F-CE#
BANK ADDRESS VALID
ADDRESS VALID
BANK ADDRESS VALID
ta(CE)
tOEH tDAE
ta(OE)
tWPH
DATA
tWHRL
F-RY/BY#
BYTE#
F-RP#
tBLS tBLH
F-WP#
WAVEFORMS ERASE OPERATIONS (F-CE# control)
ADDRESSES
ERASE READ STATUS REGISTER WRITE READ ARRAY COMMAND
F-CE#
BANK ADDRESS VALID
ADDRESS VALID
BANK ADDRESS VALID
ta(CE)
tCEP DATA
tCEPH tOEH
ta(OE)
tDAE
tEHRL
F-RY/BY#
BYTE#
F-RP#
tBLS tBLH
F-WP#
Sep. 1999 Rev.2.0
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144WORD 16-BIT 524,288-WORD 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
WAVEFORMS PAGE PROGRAM OPERATION WITH (WE# control)
Change Bank Address PROGRAM DATA BANK
A19~A7
ARRAY READ FROM OTHER BANK WITH
BANK ADDRESS VALID
ADDRESS VALID 01H~FEH 01H~7EH
VALID
VALID
BYTE#=VIL (A6~A-1) BYTE#=VIH ~A0)
VALID
VALID
tWPH
F-CE#
ta(CE) ta(OE) tOEH
DOUT DOUT
DATA F-RY/BY#
tWHRL
WAVEFORMS PAGE PROGRAM OPERATION WITH (F-CE# control)
Change Bank Address PROGRAM DATA BANK
A19~A7
ARRAY READ FROM OTHER BANK WITH
BANK ADDRESS VALID
ADDRESS VALID 01H~FEH 01H~7EH
VALID
VALID
BYTE#=VIL (A6~A-1) BYTE#=VIH ~A0)
VALID
VALID
tCEPH
F-CE#
ta(CE) ta(OE) tOEH
tCEP
DATA F-RY/BY#
DOUT
DOUT
tEHRL
Sep. 1999 Rev.2.0
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144WORD 16-BIT 524,288-WORD 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
WAVEFORMS BYTE WORD PROGRAM OPERATION WITH (WE# control)
Change Bank Address PROGRAM DATA BANK(I)
BANK ADDRESS VALID
A19~A7
BYTE#=VIL (A6~A-1) BYTE#=VIH ~A0)
READ STATUS REGISTER
ARRAY READ FROM BANK(II) WITH
ADDRESS VALID
VALID
VALID
VALID
VALID
VALID
tWPH
F-CE#
ta(CE) ta(OE)
tOEH
DOUT DOUT
DATA F-RY/BY#
tWHRL
WAVEFORMS BYTE WORD PROGRAM OPERATION WITH (F-CE# control)
PROGRAM DATA BANK(I)
BANK ADDRESS VALID
A19~A7
READ STATUS REGISTER
Change Bank Address ARRAY READ FROM BANK(II) WITH
ADDRESS VALID
VALID
VALID
BYTE#=VIL (A6~A-1) BYTE#=VIH ~A0)
VALID
VALID
VALID
tCEPH
F-CE#
ta(CE) ta(OE) tOEH
tCEP
DOUT DOUT
DATA F-RY/BY#
tEHRL
Sep. 1999 Rev.2.0
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144WORD 16-BIT 524,288-WORD 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package) WAVEFORMS BLOCK ERASE OPERATION WITH (WE# control)
Change Bank Address BLOCK ERASE BANK
BANK ADDRESS VALID
ADDRESSES F-CE# DATA F-RY/BY#
READ STATUS REGISTER
ARRAY READ FROM OTHER BANK WITH
ADDRESS VALID
VALID
VALID
tWPH tOEH
ta(CE) ta(OE)
DOUT DOUT
tWHRL
WAVEFORMS BLOCK ERASE OPERATION WITH (F-CE# control)
Change Bank Address BLOCK ERASE BANK
BANK ADDRESS VALID
ADDRESSES DATA
READ STATUS REGISTER
READ DATA FROM OTHER BANK WITH
ADDRESS VALID
VALID
VALID
F-CE#
tCEPH
ta(CE) ta(OE)
tCEP
tOEH
DOUT DOUT
F-RY/BY#
tEHRL
Sep. 1999 Rev.2.0
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144WORD 16-BIT 524,288-WORD 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package) WAVEFORMS SUSPEND OPERATION (WE# control)
ADDRESSES
READ STATUS REGISTER
F-CE#
BANK ADDRESS VALID
BANK ADDRESS VALID
ta(CE)
DATA
tOEH Program Suspend Latency
ta(OE)
S.R.6,7=1
VALID
tBLS tBLH
F-RY/BY#
F-RP#
F-WP#
WAVEFORMS SUSPEND OPERATION (F-CE# control)
ADDRESSES
READ STATUS REGISTER
F-CE# DATA
BANK ADDRESS VALID
BANK ADDRESS VALID
tCEP
ta(CE)
ta(OE) tOEH Program Suspend Latency S.R.6,7=1
VALID
tBLS tBLH
F-RY/BY#
F-RP#
F-WP#
Sep. 1999 Rev.2.0
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144WORD 16-BIT 524,288-WORD 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package) FULL STATUS CHECK PROCEDURE
STATUS REGISTER READ
LOCK PROGRAM FLOW CHART
START
SR.4 SR.5
WRITE COMMAND SEQUENCE ERROR WRITE BLOCK ADDRESS
SR.5
BLOCK ERASE ERROR SR.7
SR.4
PROGRAM ERROR (PAGE, LOCK BIT) SR.4
LOCK PROGRAM FAILED
SR.3 SUCCESSFUL (BLOCK ERASE, PROGRAM)
PROGRAM ERROR (BLOCK)
LOCK PROGRAM SUCCESSFUL
BYTE PROGRAM FLOW CHART
START
PAGE PROGRAM FLOW CHART
START
WRITE WRITE
WRITE ADDRESS DATA
STATUS REGISTER READ
WRITE ADDRESS DATA
SR.7
WRITE
STATUS REGISTER READ
FULL STATUS CHECK DESIRED
SUSPEND LOOP WRITE
SR.7 WRITE
PAGE PROGRAM COMPLETED
Byte/Word program admitted only BANK(I).
FULL STATUS CHECK DESIRED
SUSPEND LOOP WRITE
PAGE PROGRAM COMPLETED
Sep. 1999 Rev.2.0
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144WORD 16-BIT 524,288-WORD 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package) CLEAR PAGE BUFFER
START
SUSPEND RESUME FLOW CHART
START
WRITE WRITE STATUS REGISTER READ WRITE SR.7 PAGE BUFFER CLEAR COMPLETED
SUSPEND
SR.6
SINGLE DATA LOAD PAGE BUFFER
START WRITE
PROGRAM ERASE COMPLETED
WRITE
READ ARRAY DATA
WRITE ADDRESS DATA
DONE READING
DONE LOADING?
WRITE
RESUME
SINGLE DATA LOAD PAGE BUFFER COMPLETED
OPERATION RESUMED
bank address required when writing this command. Also, there need suspend erase program operation when reading data from other bank. Please function.
PAGE BUFFER FLASH
START
BLOCK ERASE FLOW CHART
START
WRITE WRITE WRITE BLOCK ADDRESS WRITE PAGE ADDRESS STATUS REGISTER READ STATUS REGISTER READ
SR.7 WRITE SR.7
WRITE
FULL STATUS CHECK DESIRED
FULL STATUS CHECK DESIRED
SUSPEND LOOP WRITE
SUSPEND LOOP WRITE
PAGE BUFFER FLASH COMPLETED
BLOCK ERASE COMPLETED
Sep. 1999 Rev.2.0
OPERATION STATUS EFFECTIVE COMMAND
Clear Status Register
Read/Standby State Read Status Register
Read Device Identifier
Read Lock Status
Read Array
16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144WORD 16-BIT 524,288-WORD 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
Setup State Clear Page Buffer Setup
Single Data Load Page Buffer Setup
Page Buffer Flash Setup
Page Program Setup
Byte Program Setup
Lock Program Setup
Block Erase Setup
Erase Unlocked Blocks Setup
OTHER
OTHER
Internal State
i=0-255
OTHER
OTHER
Program Verify
Ready
Erase Verify Read Status Register
Read Status Register
M6MGB/T160S4BVP
Suspend State
Change Bank Address
Read Status Register
Change Bank Address
Read State with Read Array
(From Other Bank)
Sep. 1999 Rev.2.0
Read Array
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144WORD 16-BIT 524,288-WORD 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
SRAM
SRAM M6MGB/T160S4BVP organized 262,144-word 16-bit/ 524,288-word 8-bit. These devices operate single +2.7~3.6V powersupply, directly compatible both input output. fully static circuit needs clocks refresh, makes useful. operation mode determined combination device control inputs BYTE#, S-CE OE#. Each mode summarized function table. write operation executed whenever level overlaps with high level S-CE. address(A-1~A17:byte mode, A0~A17:word mode) must before write cycle must stable during entire cycle. read operation executed setting high level level while S-CE active state(S-CE=H). When setting BYTE# level other pins anactive stage lower-byte selesctable mode whichboth reading writing enabled, upper-byte anon-selectable mode. When setting S-CE level,the chips non-selectable mode which both reading writing disabled. this mode, output stage ahigh-impedance state, allowing OR-tie with other chips memory expansion S-CE. power supply current reduced 0.3mA(25 C,typical), memory data held powersupply, enabling battery back-up operation during power failure power-down operation non-selected mode.
FUNCTION TABLE
S-CE BYTE# Write Read Mode
selection
DQ0~7 DQ8~15
Active Active Active Active Active Active
High-Z High-Z Standby Dout Dout Dout High-Z High-Z
Write Read
High-Z High-Z
High-Z High-Z
Sep. 1999 Rev.2.0
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144WORD 16-BIT 524,288-WORD 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Supply voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature
S-Vcc Tstg
Conditions With respect With respect With respect Ta=25 W-version
Ratings
Units
-0.5* +4.6 -0.5* S-Vcc S-Vcc +150
-3.0V case (Pulse width< 30ns)
ELECTRICAL CHARACTERISTICS
Symbol Parameter High-level input voltage Low-level input voltage High-level output voltage IOH= -0.5mA High-level output voltage IOH= -0.05mA Low-level output voltage Input leakage current Output leakage current Active supply current AC,MOS level Active supply current AC,TTL level Conditions
S-Vcc=2.7 3.6V, unless otherwise noted) Limits
S-Vcc+0.3V
Units
VOH1 VOH2 Icc1 Icc2
-0.3
S-Vcc-0.5V
IOL=2mA S-Vcc
S-CE=VIL OE#=VIH, VI/O=0 S-Vcc
S-CE S-Vcc-0.2V other inputs< 0.2V S-Vcc-0.2V Output open (duty 100%) S-CE=VIH other pins =VIH Output open (duty 100%)
10MHz 1MHz 10MHz 1MHz
Icc3
Stand supply current AC,MOS level
S-CE 0.2V Other inputs=0~S-Vcc
Icc4 Stand supply current
AC,TTL level
S-CE=VIL Other inputs= S-Vcc
Note Direction current flowing into indicated positive mark) Note Typical value S-Vcc=3.0V Ta=25
-3.0V case (Pulse width< 30ns)
CAPACITANCE
Symbol Parameter Input capacitance Output capacitance Conditions VI=GND, VI=25mVrms, f=1MHz VO=GND,VO=25mVrms, f=1MHz
(S-Vcc=2.7 3.6V, unless otherwise noted) Limits Units
Note: value common pins SRAM Flash Memory SRAM.
Sep. 1999 Rev.2.0
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144WORD 16-BIT 524,288-WORD 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
ELECTRICAL CHARACTERISTICS
(S-Vcc=2.7 3.6V, unless otherwise noted)
TEST CONDITIONS
Supply voltage Input pulse Input rise time fall time Reference level
2.7V~3.6V VIH=2.4V,VIL=0.4V VOH=VOL=1.5V
Transition measured ±500mV from steady state voltage.(for ten,tdis)
1TTL
Including scope capacitance
Output loads
Fig.1,CL=30pF CL=5pF (for ten,tdis)
Fig.1 Output load
READ CYCLE
Limits Symbol Parameter Read cycle time Address access time Chip select access time Output enable access time Output disable time after S-CE Output disable time after high Output enable time after S-CE high Output enable time after Data valid time after address
SRAM
Units
ta(A) ta(CE) ta(OE) tdis(CE) tdis(OE) ten(CE) ten(OE) tV(A)
WRITE CYCLE
Limits Symbol Parameter Write cycle time Write pulse width Address setup time Address setup time with respect Chip select setup time Data setup time Data hold time Write recovery time Output disable time from Output disable time from high Output enable time from high Output enable time from
SRAM
Units
tw(W) tsu(A) tsu(A-WH) tsu(CE) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE)
Sep. 1999 Rev.2.0
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144WORD 16-BIT 524,288-WORD 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
(4)TIMING DIAGRAMS Read cycle
A0~17 (Word Mode) A-1~17 (Byte Mode) ta(A)
S-CE
(Note3)
ta(CE) tdis (CE) (OE)
(Note3) (Note3)
(OE) (CE)
tdis (OE)
(Note3)
level
DQ0~15
(Word Mode) (Byte Mode)
DQ0~7
VALID DATA
Write cycle control mode
A0~17
(Word Mode)
A-1~17 (Byte Mode) (CE)
S-CE
(Note3)
(A-WH)
(Note3)
tdis(OE) DQ0~15 (Word Mode) DQ0~7 (Byte Mode)
DATA STABLE
tdis
trec ten(OE)
Sep. 1999 Rev.2.0
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144WORD 16-BIT 524,288-WORD 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
Write cycle (S-CE control mode)
A0~17
(Word Mode)
A-1~17 (Byte Mode) S-CE
(Note4)
(CE)
trec
(Note3)
DATA STABLE
(Note3)
DQ0~15 (Word Mode) DQ0~7 (Byte Mode)
Note Hatching indicates state "don't care". Note When falling edge simultaneously priorto rising edge S-CE, outputs maintained high impedance state. Note Don't apply inverted phase signal externally when output mode.
Sep. 1999 Rev.2.0
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144WORD 16-BIT 524,288-WORD 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
POWER DOWN CHARACTERISTICS ELECTRICAL CHARACTERISTICS
Symbol Parameter Test conditions Limits Units
S-Vcc (PD) Power down supply voltage
S-CE 0.2V other inputs=0~3V
(S-CE)
Chip select input S-CE
(PD)
Power down supply current
S-Vcc=3.0V
Typical value Ta=25
TIMING REQUIREMINTS
Symbol Limits Parameter Power down time Power down recovery time Test conditions Units
(PD) trec (PD)
TIMING DIAGRAM
S-CE control mode S-Vcc 2.7V S-CE 0.2V (PD) S-CE 0.2V trec (PD) 0.2V 2.7V
BYTE# TIMING DIAGRAM TIMING REQUIREMINTS
Symbol Limits Parameter BYTE# time BYTE# recovery time Test conditions Units
(BYTE) trec (BYTE)
S-CE
TIMING DIAGRAM
(BYTE)
trec (BYTE)
BYTE#
Sep. 1999 Rev.2.0

16,777,216-BIT (1,048,576 -WORD 16-BIT 2,097,152-WORD 8-BIT) CMOS 3.3V

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