SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST3
|
|
|
Top Searches for this datasheet
Kbit Mbit Mbit Mbit (x8) Multi-Purpose Flash
SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Data Sheet FEATURES: Organized 128K 256K 512K Single Voltage Read Write Operations 3.0-3.6V SST39LF512/010/020/040 2.7-3.6V SST39VF512/010/020/040 Superior Reliability Endurance: 100,000 Cycles (typical) Greater than years Data Retention Power Consumption: Active Current: (typical) Standby Current: (typical) Sector-Erase Capability Uniform KByte sectors Fast Read Access Time: SST39LF512/010 SST39LF020/040 SST39VF512/010/020/040 Latched Address Data Fast Erase Byte-Program: Sector-Erase Time:18 typical Chip-Erase Time: typical Byte-Program Time: typical Chip Rewrite Time: second typical SST39LF/VF512 seconds typical SST39LF/VF010 seconds typical SST39LF/VF020 seconds typical SST39LF/VF040 Automatic Write Timing Internal Generation End-of-Write Detection Toggle Data# Polling CMOS Compatibility JEDEC Standard Flash EEPROM Pinouts command sets Packages Available 32-Pin PLCC 32-Pin TSOP (8mm x14mm)
PRODUCT DESCRIPTION SST39LF512/010/020/040 SST39VF512/010/ 020/040 128K 256K 5124K CMOS Multi-Purpose Flash (MPF) manufactured with SST's proprietary, high performance CMOS SuperFlash technology. split-gate cell design thick oxide tunneling injector attain better reliability manufacturability compared with alternate approaches. SST39LF512/010/020/040 devices write (Program Erase) with 3.0-3.6V power supply. SST39VF512/010/020/040 devices write with 2.7-3.6V power supply. devices conform JEDEC standard pinouts memories. Featuring high performance Byte-Program, SST39LF512/010/020/040 SST39VF512/010/020/ devices provide maximum Byte-Program time µsec. These devices Toggle Data# Polling indicate completion Program operation. protect against inadvertent write, they have on-chip hardware Software Data Protection schemes. Designed, manufactured, tested wide spectrum applications, they offered with guaranteed endurance 10,000 cycles. Data retention rated greater than years. SST39LF512/010/020/040 SST39VF512/010/ 020/040 devices suited applications that require convenient economical updating program, configuration, data memory. system applications,
2000 Silicon Storage Technology, Inc. 395-2 8/00
they significantly improves performance reliability, while lowering power consumption. They inherently less energy during Erase Program than alternative flash technologies. total energy consumed function applied voltage, current, time application. Since given voltage range, SuperFlash technology uses less current program shorter erase time, total energy consumed during Erase Program operation less than alternative flash technologies. These devices also improve flexibility while lowering cost program, data, configuration storage applications. SuperFlash technology provides fixed Erase Program times, independent number Erase/ Program cycles that have occurred. Therefore system software hardware does have modified de-rated necessary with alternative flash technologies, whose Erase Program times increase with accumulated Erase/Program cycles. meet surface mount requirements, SST39LF512/ 010/020/040 SST39VF512/010/020/040 devices offered 32-pin TSOP 32-pin PLCC packages. Figures pinouts. Device Operation Commands used initiate memory operation functions device. Commands written device using standard microprocessor write sequences.
logo SuperFlash registered trademarks Silicon Storage Technology, Inc. trademark Silicon Storage Technology, Inc. These specifications subject change without notice.
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Data Sheet command written asserting while keeping low. address latched falling edge CE#, whichever occurs last. data latched rising edge CE#, whichever occurs first. Read Read operation SST39LF512/010/020/040 SST39VF512/010/020/040 device controlled OE#, both have system obtain data from outputs. used device selection. When high, chip deselected only standby power consumed. output control used gate data from output pins. data high impedance state when either high. Refer Read cycle timing diagram further details (Figure Byte-Program Operation SST39LF512/010/020/040 SST39VF512/010/ 020/040 programmed byte-by-byte basis. Program operation consists three steps. first step three-byte-load sequence Software Data Protection. second step load byte address byte data. During Byte-Program operation, addresses latched falling edge either WE#, whichever occurs last. data latched rising edge either WE#, whichever occurs first. third step internal Program operation which initiated after rising edge fourth CE#, whichever occurs first. Program operation, once initiated, will completed, within Figures controlled Program operation timing diagrams Figure flowcharts. During Program operation, only valid reads Data# Polling Toggle Bit. During internal Program operation, host free perform additional tasks. commands written during internal Program operation will ignored. Sector-Erase Operation Sector-Erase operation allows system erase device sector-by-sector basis. sector architecture based uniform sector size KByte. SectorErase operation initiated executing six-byte-command sequence with Sector-Erase command (30H) sector address (SA) last cycle. sector address latched falling edge sixth pulse while command (30H) latched rising edge sixth pulse. internal Erase operation begins after sixth pulse. End-of-Erase determined using either Data# Polling Toggle methods. Figure timing waveforms. commands written during Sector-Erase operation will ignored. Chip-Erase Operation SST39LF512/010/020/040 SST39VF512/010/020/ devices provide Chip-Erase operation, which allows user erase entire memory array "1's" state. This useful when entire device must quickly erased. Chip-Erase operation initiated executing six- byte Software Data Protection command sequence with ChipErase command (10H) with address 5555H last byte sequence. internal Erase operation begins with rising edge sixth CE#, whichever occurs first. During internal Erase operation, only valid read Toggle Data# Polling. Table command sequence, Figure timing diagram, Figure flowchart. commands written during Chip-Erase operation will ignored. Write Operation Status Detection SST39LF512/010/020/040 SST39VF512/010/ 020/040 devices provide software means detect completion Write (Program Erase) cycle, order optimize system write cycle time. software detection includes status bits Data# Polling (DQ7) Toggle (DQ6). End-of-Write detection mode enabled after rising edge which initiates internal Program Erase operation. actual completion nonvolatile write asynchronous with system; therefore, either Data# Polling Toggle read simultaneous with completion Write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either DQ6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed Write cycle, otherwise rejection valid. Data# Polling (DQ7) When SST39LF512/010/020/040 SST39VF512/ 010/020/040 internal Program operation, attempt read will produce complement true data. Once Program operation completed, will produce true data. device then ready next operation. During internal Erase operation, attempt read will produce `0'. Once internal Erase operation completed, will produce `1'. Data# Polling valid after rising edge fourth CE#) pulse Program operation. Sector- Chip-Erase, Data# Polling valid after rising edge sixth CE#) pulse. Figure Data# Polling timing diagram Figure flowchart.
2000 Silicon Storage Technology, Inc.
395-2 8/00
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Data Sheet Toggle (DQ6) During internal Program Erase operation, consecutive attempts read will produce alternating 1's, i.e., toggling between When internal Program Erase operation completed, toggling will stop. device then ready next operation. Toggle valid after rising edge fourth CE#) pulse Program operation. Sector- Chip-Erase, Toggle valid after rising edge sixth CE#) pulse. Figure Toggle timing diagram Figure flowchart. Data Protection SST39LF512/010/020/040 SST39VF512/010/ 020/040 provide both hardware software features protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: pulse less than will initiate Write cycle. Power Up/Down Detection: Write operation inhibited when less than 1.5V. Write Inhibit Mode: Forcing low, high, high will inhibit Write operation. This prevents inadvertent writes during power-up power-down. Software Data Protection (SDP) SST39LF512/010/020/040 SST39VF512/010/ 020/040 provide JEDEC approved Software Data Protection scheme data alteration operation, i.e., Program Erase. Program operation requires inclusion series three byte sequence. three byte-load sequence used initiate Program operation, providing optimal protection from inadvertent Write operations, e.g., during system power-up power-down. Erase operation requires inclusion byte load sequence. These devices shipped with Software Data Protection permanently enabled. Table specific software command FUNCTIONAL BLOCK DIAGRAM
X-Decoder EEPROM Cell Array
codes. During command sequence, invalid commands will abort device read mode, within TRC. Product Identification Product Identification mode identifies devices SST39LF/VF512, SST39LF/VF010, SST39LF/VF020 SST39LF/VF040 manufacturer SST. This mode accessed hardware software operations. hardware operation typically used programmer identify correct algorithm these devices. Users wish Software Product Identification operation identify part (i.e., using device code) when using multiple manufacturers same socket. details, Table hardware operation Table software operation, Figure Software Entry Read timing diagram Figure Software entry command sequence flowchart. TABLE PRODUCT IDENTIFICATION TABLE Address Manufacturer's Device SST39LF/VF512 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040 0000H 0001H 0001H 0001H 0001H Data
T1.1
Product Identification Mode Exit/Reset order return standard Read mode, Software Product Identification mode must exited. Exit accomplished issuing Software Exit command sequence, which returns device Read operation. Please note that Software Exit command ignored during internal Program Erase operation. Table software command codes, Figure timing waveform Figure flowchart.
Memory Address
Address Buffers Latches Y-Decoder
B1.0
Control Logic
Buffers Data Latches
2000 Silicon Storage Technology, Inc.
395-2 8/00
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Data Sheet
SST39LF/VF040 SST39LF/VF020 SST39LF/VF010 SST39LF/VF512
F01.0
SST39LF/VF512 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040
Standard Pinout View
FIGURE ASSIGNMENTS 32-PIN TSOP (8MM 14MM)
SST39LF/VF512 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040
SST39LF/VF040 SST39LF/VF020 SST39LF/VF010 SST39LF/VF512
SST39LF/VF512 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040
SST39LF/VF040 SST39LF/VF020 SST39LF/VF010 SST39LF/VF512
32-Pin PLCC View
F02b.1
FIGURE ASSIGNMENTS 32-PIN PLCC
2000 Silicon Storage Technology, Inc. 395-2 8/00
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Data Sheet TABLE DESCRIPTION Symbol Name AMS-A0 Address Inputs DQ7-DQ0 Data Input/output Functions provide memory addresses. During Sector-Erase AMS-A12 address lines will select sector. output data during Read cycles receive input data during Write cycles. Data internally latched during Write cycle. outputs tri-state when high. activate device when low. gate data output buffers. control Write operations. provide power supply voltage: 3.0-3.6V SST39LF512/010/020/040 2.7-3.6V SST39VF512/010/020/040 Unconnected Pins
T2.0
Chip Enable Output Enable Write Enable Power Supply Ground Connection
Note: Most significant address SST39LF/VF512, SST39LF/VF010, SST39LF/VF020 SST39LF/VF040
TABLE OPERATION MODES SELECTION Mode Read Program Erase Standby Write Inhibit Product Identification Hardware Mode Software Mode
DOUT High High Z/DOUT High Z/DOUT Manufacturer's (BF) Device Address Sector address, Chip-Erase AMS2 VIL, AMS2 VIL, Table
T3.1
Notes:1. Device SST39LF/VF512, SST39LF/VF010, SST39LF/VF020 SST39LF/VF040 Most significant address SST39LF/VF512, SST39LF/VF010, SST39LF/VF020 SST39LF/VF040
2000 Silicon Storage Technology, Inc.
395-2 8/00
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Data Sheet TABLE SOFTWARE COMMAND SEQUENCE
Command Sequence Write Cycle Addr1 Data Byte-Program 5555H Sector-Erase 5555H Chip-Erase 5555H Software Entry 5555H Software Exit Software Exit 5555H Write Cycle Addr1 Data 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH Write Cycle Addr1 Data 5555H 5555H 5555H 5555H 5555H
T4.0
Write Cycle Addr1 Data Data 5555H 5555H
Write Cycle Addr1 Data 2AAAH 2AAAH
Write Cycle Addr1 Data SAx2 5555H
Notes: Address format A14-A0 (Hex). Address "Don't Care" Command sequence SST39LF/VF512. Address "Don't Care" Command sequence SST39LF/VF010. Address A15, "Don't Care" Command sequence SST39LF/VF020. Address A15, A16, "Don't Care" Command sequence SST39LF/VF040. Sector-Erase; uses AMS-A12 address lines Most significant address SST39LF/VF512, SST39LF/VF010, SST39LF/VF020 SST39LF/VF040 Program Byte address Both Software Exit operations equivalent With Manufacturer's BFH, read with SST39LF/VF512 Device D4H, read with SST39LF/VF010 Device D5H, read with SST39LF/VF020 Device D6H, read with SST39LF/VF040 Device D7H, read with Most significant address SST39LF/VF512, SST39LF/VF010, SST39LF/VF020 SST39LF/VF040 device does remain Software Product Mode powered down.
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage Ground Potential -0.5V VDD+ 0.5V Transient Voltage (<20 Ground Potential -1.0V VDD+ 1.0V Voltage Ground Potential -0.5V 13.2V Package Power Dissipation Capability 25°C) 1.0W Through Hole Lead Soldering Temperature Seconds) 300°C Surface Mount Lead Soldering Temperature Seconds) 240°C Output Short Circuit Current1
Note: Outputs shorted more than second. more than output shorted time.
OPERATING RANGE SST39LF512/010/020/040 Range Ambient Temp Commercial 3.0-3.6V OPERATING RANGE SST39VF512/010/020/040 Range Ambient Temp Commercial 2.7-3.6V Industrial 2.7-3.6V
2000 Silicon Storage Technology, Inc.
CONDITIONS TEST Input Rise/Fall Time Output Load SST39LF512/010/020/040 SST39VF512/010/020/040 Figures
395-2 8/00
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Data Sheet TABLE OPERATING CHARACTERISTICS 3.0-3.6V SST39LF512/010/020/040 2.7-3.6V SST39VF512/010/020/040 Limits Symbol Parameter Units Test Conditions Power Supply Current Read Write Standby Current Input Leakage Current Output Leakage Current Input Voltage Input High Voltage Input High Voltage (CMOS) Output Voltage Output High Voltage Supervoltage Supervoltage Current VDD-0.3 VDD-0.2 11.4 12.6 CE#=OE#=VIL,WE#=VIH I/Os open, Address input VIL/VIH, f=1/TRC Min., VDD=VDD CE#=WE#=VIL, OE#=VIH, =VDD Max. CE#=VIHC, Max. =GND VDD, Max. VOUT =GND VDD, Max. Min. Max. Max. Min. -100µA, Min. =VIL, VIL, VIH, Max.
T5.0
VIHC
TABLE RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter TPU-READ1 TPU-WRITE1 Power-up Read Operation Power-up Write Operation
Minimum
Units
T6.0
TABLE CAPACITANCE Mhz, other pins open) Parameter Description Test Condition CI/O1 CIN1 Capacitance Input Capacitance VI/O
Maximum
T7.0
Note: This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE RELIABILITY CHARACTERISTICS Symbol Parameter NEND1 TDR1 VZAP_HBM1 VZAP_MM1 ILTH1 Endurance Data Retention Susceptibility Human Body Model Susceptibility Machine Model Latch
Minimum Specification 10,000 2000
Units Cycles Years Volts Volts
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard
T8.1
Note: This parameter measured only initial qualification after design process change that could affect this parameter.
2000 Silicon Storage Technology, Inc.
395-2 8/00
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Data Sheet CHARACTERISTICS TABLE READ CYCLE TIMING PARAMETERS 3.0-3.6V SST39LF512/010/020/040 2.7-3.6V SST39VF512/010/020/040 SST39VF512-70 SST39VF010-70 SST39LF512-45 SST39LF020-55 SST39VF020-70 SST39LF010-45 SST39LF040-55 SST39VF040-70 Symbol Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Active Output TCLZ TOLZ1 Active Output TCHZ High High-Z Output TOHZ High High-Z Output TOH1 Output Hold from Address Change
SST39VF512-90 SST39VF010-90 SST39VF020-90 SST39VF040-90 Units
T9.1
Note: This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol Parameter Byte-Program Time Address Setup Time Address Hold Time Setup Time Hold Time TOES High Setup Time TOEH High Hold Time Pulse Width Pulse Width TWPH Pulse Width High TCPH Pulse Width High Data Setup Time Data Hold Time TIDA Software Access Exit Time Sector-Erase TSCE Chip-Erase
Units
T10.0
Note: This parameter measured only initial qualification after design process change that could affect this parameter.
2000 Silicon Storage Technology, Inc.
395-2 8/00
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Data Sheet
ADDRESS AMS-0
DATA VALID Most significant address SST39LF/VF512, SST39LF/VF010, SST39LF/VF020 SST39LF/VF040 TCHZ HIGH-Z DATA VALID
F03.0
TOLZ
TOHZ
DQ7-0
HIGH-Z
TCLZ
Note:
FIGURE READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS ADDRESS AMS-0 5555 DQ7-0 Note: DATA BYTE (ADDR/DATA)
F04.0
2AAA
5555
ADDR
TWPH
Most significant address SST39LF/VF512, SST39LF/VF010, SST39LF/VF020 SST39LF/VF040
FIGURE CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
2000 Silicon Storage Technology, Inc.
395-2 8/00
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Data Sheet
INTERNAL PROGRAM OPERATION STARTS ADDRESS AMS-0 5555 DQ7-0 Note: DATA BYTE (ADDR/DATA) TCPH 2AAA 5555 ADDR
F05.0
Most significant address SST39LF/VF512, SST39LF/VF010, SST39LF/VF020 SST39LF/VF040
FIGURE CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS AMS-0 TOEH TOES
Note:
F06.0
Most significant address SST39LF/VF512, SST39LF/VF010, SST39LF/VF020 SST39LF/VF040
FIGURE DATA# POLLING TIMING DIAGRAM
2000 Silicon Storage Technology, Inc.
395-2 8/00
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Data Sheet
ADDRESS AMS-0 TOEH TOES
READ CYCLES WITH SAME OUTPUTS F07.0
Note:
Most significant address SST39LF/VF512, SST39LF/VF010, SST39LF/VF020 SST39LF/VF040
FIGURE TOGGLE TIMING DIAGRAM
SIX-BYTE CODE SECTOR-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA
F08.0
DQ7-0
Note: This device also supports controlled Sector-Erase operation. signals interchageable long minmum timings met. (See Table Sector Address Most significant address SST39LF/VF512, SST39LF/VF010, SST39LF/VF020 SST39LF/VF040
FIGURE CONTROLLED SECTOR-ERASE TIMING DIAGRAM
2000 Silicon Storage Technology, Inc. 395-2 8/00
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Data Sheet
SIX-BYTE CODE CHIP-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA 5555
TSCE
DQ7-0
F17.0
Note: This device also supports controlled Chip-Erase operation. signals interchageable long minmum timings met. (See Table Most significant address SST39LF/VF512, SST39LF/VF010, SST39LF/VF020 SST39LF/VF040
FIGURE CONTROLLED CHIP-ERASE TIMING DIAGRAM
Three-byte sequence Software Entry ADDRESS A14-0 5555 2AAA 5555 0000 0001
TWPH DQ7-0 Device
F09.1
TIDA
Note: Device SST39LF/VF512, SST39LF/VF010, SST39LF/VF020 SST39LF/VF040.
FIGURE SOFTWARE ENTRY READ
2000 Silicon Storage Technology, Inc.
395-2 8/00
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Data Sheet
THREE-BYTE SEQUENCE SOFTWARE EXIT RESET
ADDRESS A14-0
5555
2AAA
5555
DQ7-0
TIDA
F10.0
FIGURE SOFTWARE EXIT RESET
2000 Silicon Storage Technology, Inc.
395-2 8/00
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Data Sheet
VIHT
INPUT
REFERENCE POINTS
OUTPUT
VILT
F12.1
test inputs driven VIHT (0.9 VDD) logic VILT (0.1 VDD) logic "0". Measurement reference points inputs outputs (0.5 VDD) (0.5 VDD) Input rise fall times (10% 90%)
Note: VIT-VINPUT Test VOT-VOUTPUT Test VIHT-VINPUT HIGH Test VILT-VINPUT Test
FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS
TESTER
F11.1
FIGURE TEST LOAD EXAMPLE
2000 Silicon Storage Technology, Inc.
395-2 8/00
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Data Sheet
Start
Load data: Address: 5555
Load data: Address: 2AAA
Load data: Address: 5555
F13.0
Load Byte Address/Byte Data
Wait Program (TBP, Data# Polling bit, Toggle operation) Program Completed
FIGURE BYTE-PROGRAM ALGORITHM
2000 Silicon Storage Technology, Inc.
395-2 8/00
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Data Sheet
Internal Timer Byte-Program/ Erase Initiated
Toggle Byte-Program/ Erase Initiated
Data# Polling Byte-Program/ Erase Initiated
Wait TBP, TSCE,
Read byte
Read
Program/Erase Completed
Read same byte
true data?
Does match?
Program/Erase Completed
Program/Erase Completed
F14.0
FIGURE WAIT OPTIONS
2000 Silicon Storage Technology, Inc.
395-2 8/00
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Data Sheet
Software Entry Command Sequence Software Exit Reset Command Sequence
Load data: Address: 5555 Load data: Address: 5555 Load data: Address:
Load data: Address: 2AAA
Load data: Address: 2AAA
Wait TIDA
Load data: Address: 5555 Load data: Address: 5555 Return normal operation
Wait TIDA
Wait TIDA
Read Software Return normal operation
F15.1
FIGURE SOFTWARE COMMAND FLOWCHARTS
2000 Silicon Storage Technology, Inc.
395-2 8/00
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Data Sheet
Chip-Erase Command Sequence Load data: Address: 5555
Sector-Erase Command Sequence Load data: Address: 5555
Load data: Address: 2AAA
Load data: Address: 2AAA
Load data: Address: 5555
Load data: Address: 5555
Load data: Address: 5555
Load data: Address: 5555
Load data: Address: 2AAA
Load data: Address: 2AAA
Load data: Address: 5555
Load data: Address:
Wait TSCE
Wait
Chip erased
Sector erased
F16.0
FIGURE ERASE COMMAND SEQUENCE
2000 Silicon Storage Technology, Inc.
395-2 8/00
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Data Sheet Device SST39VFxxx Speed Suffix1 Suffix2
Package Modifier pins Numeric modifier Package Type PLCC TSOP (die (8mm 14mm) Unencapsulated Temperature Range Commercial 70°C Industrial -40° 85°C Minimum Endurance 10,000 cycles Read Access Speed Device Density Kilobit Megabit Megabit Megabit Voltage 3.0-3.6V 2.7-3.6V
2000 Silicon Storage Technology, Inc.
395-2 8/00
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Data Sheet SST39LF512 Valid combinations SST39LF512-45-4C-WH SST39LF512-45-4C-NH SST39VF512 Valid combinations SST39VF512-70-4C-WH SST39VF512-70-4C-NH SST39VF512-90-4C-WH SST39VF512-90-4C-NH SST39VF512-90-4C-U4 SST39VF512-70-4I-WH SST39VF512-70-4I-NH SST39VF512-90-4I-WH SST39VF512-90-4I-NH SST39LF010 Valid combinations SST39LF010-45-4C-WH SST39LF010-45-4C-NH SST39VF010 Valid combinations SST39VF010-70-4C-WH SST39VF010-70-4C-NH SST39VF010-90-4C-WH SST39VF010-90-4C-NH SST39VF010-90-4C-U4 SST39VF010-70-4I-WH SST39VF010-70-4I-NH SST39VF010-90-4I-WH SST39VF010-90-4I-NH SST39LF020 Valid combinations SST39LF020-55-4C-WH SST39LF020-55-4C-NH SST39VF020 Valid combinations SST39VF020-70-4C-WH SST39VF020-70-4C-NH SST39VF020-90-4C-WH SST39VF020-90-4C-NH SST39VF020-90-4C-U4 SST39VF020-70-4I-WH SST39VF020-70-4I-NH SST39VF020-90-4I-WH SST39VF020-90-4I-NH SST39LF040 Valid combinations SST39LF040-55-4C-WH SST39LF040-55-4C-NH SST39VF040 Valid combinations SST39VF040-70-4C-WH SST39VF040-70-4C-NH SST39VF040-90-4C-WH SST39VF040-90-4C-NH SST39VF040-90-4C-U1 SST39VF040-70-4I-WH SST39VF040-70-4I-NH SST39VF040-90-4I-WH SST39VF040-90-4I-NH
Example: Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
2000 Silicon Storage Technology, Inc.
395-2 8/00
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Data Sheet PACKAGING DIAGRAMS
VIEW SIDE VIEW BOTTOM VIEW
Optional Identifier
.485 .495 .447 .453 .042 .048
.106 .112 .020 MAX. .023 .029 .030 .040
.490 .530
.042 .048 .585 .595 .547 .553 .026 .032
.013 .021 .400
.050 BSC. .015 Min. .050 BSC. .125 .140 .075 .095 .026 .032
32.PLCC.NH-ILL.1
Note:
Complies with JEDEC publication MS-016 dimensions, although some dimensions more stringent. linear dimensions inches (min/max). Dimensions include mold flash. Maximum allowable mold flash .008 inches.
32-PIN PLASTIC LEAD CHIP CARRIER (PLCC) PACKAGE CODE:
2000 Silicon Storage Technology, Inc.
395-2 8/00
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Data Sheet
IDENTIFIER 1.05 0.95
8.10 7.90
.270 .170
12.50 12.30
0.15 0.05
0.70 0.50
14.20 13.80
Note:
Complies with JEDEC publication MO-142 dimensions, although some dimensions more stringent. linear dimensions millimeters (min/max). Coplanarity: (±.05)
32.TSOP-WH-ILL.3
32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 14MM PACKAGE CODE:
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.ssti.com Literature FaxBack 888-221-1178, International 732-544-2873
2000 Silicon Storage Technology, Inc.
395-2 8/00
Other recent searches
VLB40-12F - VLB40-12F VLB40-12F Datasheet
SY100EP58V - SY100EP58V SY100EP58V Datasheet
SPT5504C - SPT5504C SPT5504C Datasheet
SPT5504C-LF - SPT5504C-LF SPT5504C-LF Datasheet
SPT5504C-A3 - SPT5504C-A3 SPT5504C-A3 Datasheet
SPT5504CL - SPT5504CL SPT5504CL Datasheet
SPT5504Q - SPT5504Q SPT5504Q Datasheet
SPT5504Q-LF - SPT5504Q-LF SPT5504Q-LF Datasheet
SPT5204Q - SPT5204Q SPT5204Q Datasheet
SPT5204QL - SPT5204QL SPT5204QL Datasheet
SWP0714 - SWP0714 SWP0714 Datasheet
SHD120232 - SHD120232 SHD120232 Datasheet
ATV5000 - ATV5000 ATV5000 Datasheet
ATV5100 - ATV5100 ATV5100 Datasheet
2SK973 - 2SK973 2SK973 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
