Bi-CMOS LV1100 Digital Surround Audio Signal-Processing

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Bi-CMOS LV1100 Digital Surround Audio Signal-Processing

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Ordering number EN5506
Bi-CMOS
LV1100
Digital Surround Audio Signal-Processing
Overview
LV1100 audio signal-processing Bi-CMOS that integrates input output filters, delay line (builtin memory), delay/reverb function with maximum delay single chip. also provides built-in fixed matrix (L+R, L-R) front mixing (with level phase switching) functions. full complement surround modes easily implemented combining these functions.
Package Dimensions
unit: 3067-DIP24S
[LV1100]
Functions Features
Input switching (L+R, L-R, IN-A) On-chip memory (12K SRAM) Front adder Input output filters Input filter low-pass filter Output filter low-pass filter: switchable with low-pass filter On-chip circuit Input output muting function simulated surround system easily implemented with only chip. converters Variable delay times Short mode; Maximum delay: Delay time selectable from delay times 10-ms steps. Long mode; Maximum delay: Delay time selectable from delay times 20-ms steps.
SANYO: DIP24S
Specifications
Absolute Maximum Ratings 25°C
Parameter Maximum supply voltage Allowable power dissipation Operating temperature Storage temperature Symbol Topr Tstg 70°C Conditions Ratings +125 Unit
Allowable Operating Ranges 25°C
Parameter Recommended supply voltage Operating supply voltage range Symbol Conditions Ratings Unit
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, JAPAN
83196HA (OT) 5506-1/10
LV1100 Electrical Characteristics 25°C, unless otherwise specified.
Parameter Quiescent current Symbol ICCO OUT-A, CLOCK FAST, maxA maxL OUT-L, (effect off), OUT-A, CLOCK FAST L.P.F) OUT-A, CLOCK SLOW L.P.F) OUT-L (effect off), OUT-R (effect off), OUT-L (effect dB), OUT-R (effect dB), OUT-A, CLOCK FAST OUT-L (effect off) OUT-R (effect off) OUT-A, CLOCK FAST L.P.F): OUT-A, CLOCK SLOW L.P.F): OUT-L (effect off): B.P.F OUT-R (effect off): B.P.F maxR OUT-R, (effect off), VNOAF VNOAS Output noise voltage VNOL VNOR VNOLE VNORE Output level deviation THDAF THDAS THDL THDR Conditions Ratings -103 -103 0.01 0.01 0.03 0.03 Unit
Maximum output voltage
Total harmonic distortion
Control Data
Parameter Control data Input low-level voltage Control data Input high-level voltage Symbol Conditions Ratings Unit
5506-2/10
LV1100 Test Circuit
Notes: items through figure indicate points that switched serial data. capacitors with good high-frequency characteristics capacitors pins Also, connect 0.1-µF ceramic capacitors parallel.
Application Circuit Example
Note: items through figure indicate points that switched serial data.
5506-3/10
LV1100 Block Diagram
Functional Description 1.INPUT PHASE SELECT Selects either input summation signal (L+R) input difference signal (L-R). When low, selected, when high, selected. 2.INPUT SELECT Selects either IN-L IN-R input signals, IN-A input signal. 3.INPUT FILTER Selects whether signal input from either IN-L IN-R IN-A passed through 7-kHz low-pass filter, whether directly input delay block. 4.DELAY clock fast mode, creates delayed signals with delays 10-ms steps. clock slow mode, creates delayed signals with delays 20-ms steps. 5.VOL (effect volume) Selects amount front signals added delayed signal. Possible settings 6.OUTPUT PHASE SELECT Selects in-phase setting) out-of-phase setting) with respect left channel right channel output signal. 7.REVERVE this switch position specify that surround system output signal back. 8.IN-A OUTPUT FILTER Allows signal output after passing through 3-kHz low-pass filter.
5506-4/10
LV1100 Command List LV1100 Control Format
Selects LV1100. When low, mode settings listed below made.
L.P.F ON/OFF THROUGH FILTER INPUT MUTE IN-A DELAY DELAY Turns surround system feedback L+R, DELAY DELAY OFF; Turns surround system feedback
OUT-L, MUTE OUT-A MUTE FRONT INPHASE (In-phase addition)
OUT-L, MUTE OUT-A MUTE FRONT INVERTED PHASE (Out-of-phase addition)
FRONT EFFECT (Addition front left right channels) MUTE
When high, mode settings listed below made.
IN-A output filter L.P.F-OFF L.P.F-ON
don't care
5506-5/10
LV1100 Delay Time Data
FAST SLOW
Note: must used purposes other than above commands. SYSTEM MUTE FAST SYSTEM MUTE SLOW
Control Data Format
Data read rising edge clock. control data consists bits. input data latched rising edge enable signal. clock enable signals must held high when being used control LV1100. Command interval time timing intervals between enable signals must meet conditions shown figure.
Notes Mode Control (System Mute Usage) When power first applied, after fully operating (about seconds after power applied) applications must send commands that turn system muting then again. Applications must perform system muting on/off operations when switching delay time clock fast/slow settings. After sending system muting command along with data, send data again, this time with system muting command.
Note: performing operations described items here, memory contents initialized, thus preventing incorrect operation.
5506-6/10
LV1100 Data Timing
Timing Characteristics
Parameter Enable clock delay time Data clock delay time Clock high-level hold time Clock low-level hold time Clock cycle time Symbol Conditions Ratings Unit
5506-7/10
LV1100 Functions
DIGITAL-GND voltage Internal equivalent circuit
Control voltage Apply voltage
DATA
Control voltage Apply voltage
ENABLE
Control voltage Apply voltage
REV-OUT
REV-IN
Apply voltage output through external resistor.
(Power-supply voltage)
IN-L
IN-R
IN-AUX
OUT-AUX
DC-CUT
Continued next page
5506-8/10
LV1100
Continued from preceding page
voltage Internal equivalent circuit
L.P.F
VREF
OUT-R
OUT-L
ANALOG-GND
DC-CUT
integrator
noise shaper
integrator
Charged
5506-9/10
LV1100
products described contained herein intended surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment like, failure which directly indirectly cause injury, death property loss. Anyone purchasing products described contained herein above-mentioned shall: Accept full responsibility indemnify defend SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees, jointly severally, against claims litigation damages, cost expenses associated with such use: impose responsibility fault negligence which cited such claim litigation SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees jointly severally. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties. This catalog provides information August, 1996. Specifications information herein subject change without notice. 5506-10/10

Bi-CMOS LV1100 Digital Surround Audio Signal-Processing

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