LC80101M VICS Overview LC80101M special-purpose descram
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Ordering number EN54384465
LC80101M
VICS
Overview
LC80101M special-purpose descrambler VICS systems. multiplexed service data that VICS center scrambling applied descrambled received inserting this serial interface between LC72700E application CPU. This architecture also supports reception regular transmissions that have been scrambled. Note that sample evaluation product manufacture using this require contract with VICS Center organization.
Package Dimensions
unit: 3091A-MFP28
[LC80101M]
Functions
VICS scrambled/unscrambled recognition circuit Dedicated VICS descrambler circuit interface circuit (CCB: serial)
SANYO: MFP28
Specifications
Absolute Maximum Ratings
Parameter Maximum supply voltage Input voltage Symbol VIN1 VIN2 VOUT1 VOUT2 Pdmax Topr Tstg CL2, CE2, DI2, RST2, BACKUP, INT-R1, pins Input pins other than VIN1 Output pins other than VOUT1 85°C Conditions Ratings -0.3 +7.0 -0.3 +7.0 -0.3 +0.3 -0.3 +7.0 -0.3 +0.3 +125 Unit
Output voltage Allowable power dissipation Operating temperature Storage temperature
trademark SANYO ELECTRIC CO., LTD. SANYO's original format addresses controlled SANYO.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, JAPAN
53096HA (OT) 5438-1/9
LC80101M Serial Input Output (See serial data timing figures.)
Parameter Clock low-level time Clock high-level time Data setup time Data hold time wait time setup time hold time Data output time Symbol CL2, CL2, CL2, CL2, CL2, DO2: Varies with value pull-up resistor used Conditions Ratings Unit
Electrical Characteristics/Input Output Levels +85°C,
Parameter Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Output high-level voltage Output low-level voltage Output low-level voltage Standby current Input sensitivity Pull-down resistance Symbol IDD1 Current drain IDD2 IDD3 IDD4 Conditions CMOS-compatible Schmitt inputs Pull-down resistors: INT-R1, TEST1 TEST4, TESTON CMOS-compatible Schmitt inputs: BACKUP, CE2, CL2, DI1, DI2, RST2 CE1, CL1, DO1, INT-R2 CE1, CL1, DO1, INT-R2 With BACKUP FILCK1 MHz: FILCK1*1 INT-R1, TEST1 TESTON Sine wave input: p-p, Sine wave input: p-p, Square wave input: p-p, Square wave input: p-p, 0.01 Ratings Unit Vp-p
Note Since this operates based rising edge LC72700E output (the FILCK pin), LC72700E output signal must input FILCK1 without inverting polarity. current drain varies with input level shape clock signal input FILCK1 pin. current drain reduced using waveforms that closer square waves than sine waves, using signal level that close VDD. LC72700E output square wave with output level equal VDD.
Block Diagram
5438-2/9
LC80101M Assignments Functions
TEST1 TEST2 TEST3 TEST4 TESTON Function overview Test (Must connected ground left open normal operation.) Test (Must connected ground left open normal operation.) Test (Must connected ground left open normal operation.) Test (Must connected ground left open normal operation.) Test (Must connected ground normal operation.) Input internal pull-down resistor Inputs output LC72700E external pull-down resistor required. following page. Input that selects normal operation when high backup mode when low. Clock input serial interface Control input serial interface Data input serial interface System reset input (negative logic) Input output circuit type
BACKUP RST2 INT-R1
Inputs output LC72700E
Input internal pull-down resistor
INT-R2
Output LC72700E input Output LC72700E input Output LC72700E input Outputs output data interrupt external Data output serial interface
FILCK1 FICLK2
System clock generator input System clock generator output
External feedback resistor, (typical:
Power supply (+4.5 Ground connection connection pins. These pins must left open.
5438-3/9
LC80101M Assignment
Notes pull-up resistor used between LC72700E (DO) this LSI's (DI1)
value pull-up resistor must determined based printed circuit board's floating capacitance LC80101M's clock. time LC80101M clock (corresponding kHz). This clock used readout clock output LC72700E during period discussed note basic timing external interface discussed page clock from microprocessor longer than LC80101M clock, must used formulas below. that clock shorter than that LC80101M clock, then must substituted formulas below. example, configuration shown figure above, assuming (i.e. kHz), then: (the LC72700E data output time) Since
Assuming that then will 10.1 These considerations must used guidelines when determining value pull-up resistor Rp1.
5438-4/9
Serial Data Input LC80101M
Changes from serial data input timing LC72700E documentation
Since this outputs data LC72700E only after receiving latching bits data from microprocessor, sets high during interval marked figure. Therefore necessary create same periods those (b). However, necessary take into consideration either longer. Note that completion serial data input LC72700E section (c), this generates delay longer than previously. Also, writing reading serial data allowed during period (c). (CE2 must held during period (c).) Note: When application inputs 16-bit serial control data, data from same block required, application must first read data from that same block then input 16-bit serial control data. serial data input before data read out, data integrity cannot guaranteed.
5438-5/9
Serial Data Output LC80101M
Note: Since n-channel open-drain pin, time required data value change differs depending value pull-up resistor used. normally open.
Changes from serial data output timing LC72700E documentation
There changes related CE2, CL2, DI2, pins. trigger signal used microprocessor data acquisition falling edge either INT-R2 DO2.
5438-6/9
LC80101M External Interface Basic Timing
Figure Figure shows timing changes between LC72700E INT-R output this LSI's INT-R2 output. This requires period indicated "Note about following detection falling edge INT-R signal descrambling processing. outputs falling edge INT-R2 after note time elapsed. Serial data reads writes disabled during this period.
Figure Figure shows basic timing external interface. When this used system operated based INT-R trigger, only horizontal data output, there will data readout guaranteed period 0.068 17.932 both horizontal vertical data read out, there will 0.068 8.932 data readout guaranteed periods, each horizontal vertical data output. When this used system operated based INT-R2 trigger, these data readout guaranteed periods shortened exactly amount INT-R2 signal delayed, namely When only horizontal data output, data readout guaranteed period will 17.932 0.160 17.772 both horizontal vertical data output, data readout guaranteed periods will 8.932 0.160 8.772 both horizontal vertical data output.
5438-7/9
LC80101M Usage Notes Setting BACKUP switches LC80101M backup mode. This mode which oscillator chip operation stopped reduce current drain. This must high normal operation. Also note that reset must applied after BACKUP returned high from low. (See Figure page BACKUP must connected LC80101M backup mode used. lines connecting this LC72700E must dedicated lines only used these chips. connect these lines other circuits other connection. reset must applied when power first applied. LC72700E this LSI's RST2 driven from common signal. (See Figure page TESTON (pin must connected ground. Operation During Reset reset signal applied setting RST2 input level below least when power-supply voltage (VDD) higher. Figure
Figure registers other than those holding data required descrambling reset reset signal. crystal oscillator circuit does stop. BACKUP reset must applied after BACKUP returned high (for normal operation from (backup mode, which oscillator stopped). following figure.
Figure
5438-8/9
LC80101M Sample Circuit Connecting LC80101M, LC72700E, Microprocessor
products described contained herein intended surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment like, failure which directly indirectly cause injury, death property loss. Anyone purchasing products described contained herein above-mentioned shall: Accept full responsibility indemnify defend SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees, jointly severally, against claims litigation damages, cost expenses associated with such use: impose responsibility fault negligence which cited such claim litigation SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees jointly severally. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties. This catalog provides information December, 1997. Specifications information herein subject change without notice. 5438-9/9
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