LC75817E, 75817W 1/10 Duty Matrix Display Controller/Driver with
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Ordering number EN6144
LC75817E, 75817W
1/10 Duty Matrix Display Controller/Driver with Input Function
Overview
LC75817E LC75817W 1/10 duty matrix display controller/drivers that supports display characters, numbers, symbols. addition generating matrix drive signals based data transferred serially from microcontroller, LC75817E LC75817W also provide on-chip character display allow display systems implemented easily. These products also provide general-purpose output ports incorporate scan circuit that accepts input from keys reduce printed circuit board wiring.
Built-in display contrast adjustment circuit general-purpose output ports included. Serial data supports format communication with system controller. Independent drive block power supply VLCD voltage detection type reset circuit provided initialize prevent incorrect display. provided. This turns display, disables scanning, forces general-purpose output ports level. oscillator circuit
Features
input function keys scan performed only when pressed.) Controls drives matrix LCD. Supports accessory display segment drive segments) Display technique: duty bias drive dots) duty bias drive dots) 1/10 duty bias drive dots) Display digits: digits line dots, dots) digits line dots) Display control memory CGROM: characters dots) CGRAM: characters dots) ADRAM: bits DCRAM: bits Instruction function Display on/off control Display shift function Sleep mode used reduce current drain.
trademark SANYO ELECTRIC CO., LTD. SANYO's original format addresses controlled SANYO.
SANYO products described contained herein have specifications that handle applications that require extremely high levels reliability, such life-support systems, aircraft's control systems, other applications whose failure reasonably expected result serious physical and/or material damage. Consult with your SANYO representative nearest before using SANYO products described contained herein such applications. SANYO assumes responsibility equipment failures that result from using products values that exceed, even momentarily, rated values (such maximum ratings, operating condition ranges, other parameters) listed products specifications SANYO products described contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
51099RM (OT) 6144-1/43
LC75817E, 75817W
Package Dimensions
unit: 3151-QFP100E
[LC75817E]
0.825 0.65
unit: 3181B-SQFP100
[LC75817W]
0.575
0.575
23.2 20.0
16.0 14.0 0.15
0.145
15.6 16.0 14.0
17.2 14.0 0.825
0.65
3.0max
1.6max
21.6
SANYO: QFP100E
SANYO: SQFP100
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LC75817E, 75817W Assignments (Top View)
LC75817E QFP100E
LC75817W SQFP100
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LC75817E, 75817W
Specifications
Absolute Maximum Ratings 25°C,
Parameter Maximum supply voltage Symbol VLCD VIN1 Input voltage VIN2 VIN3 VOUT1 Output voltage VOUT2 VOUT3 IOUT1 Output current IOUT2 IOUT3 IOUT4 Allowable power dissipation Operating temperature Storage temperature Topr Tstg VLCD OSCI, KI5, TEST VLCD1, VLCD2, VLCD3, VLCD4 OSCO, KS6, VLCD0, S60, COM1 COM10 COM1 COM10 85°C Conditions Ratings -0.3 +7.0 -0.3 +11.0 -0.3 +7.0 -0.3 -0.3 VLCD -0.3 +7.0 -0.3 -0.3 VLCD +125 Unit
Allowable Operating Ranges +85°C,
Parameter Symbol Supply voltage VLCD Output voltage VLCD0 VLCD1 Input voltage VLCD2 VLCD3 VLCD4 VIH1 Input high level voltage VIH2 VIH3 Input level voltage Recommended external resistance Recommended external capacitance Guaranteed oscillation range Data setup time Data hold time wait time setup time hold time High level clock pulse width level clock pulse width output delay time rise time VIL1 VIL2 ROSC COSC fOSC When display contrast adjustment circuit used. When display contrast adjustment circuit used. VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 OSCI INH, OSCI OSCI, OSCO OSCI, OSCO Figure Figure Figure Figure Figure Figure Figure 4.7k, 10pF: Figure 4.7k, 10pF: Figure Conditions Ratings VLCD4+4.5 (VLCD0-VLCD4) (VLCD0-VLCD4) (VLCD0-VLCD4) 10.0 10.0 VLCD VLCD0 VLCD0 VLCD0 Unit
Note: Since open-drain output, these times depend values pull-up resistor load capacitance
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LC75817E, 75817W Electrical Characteristics Allowable Operating Ranges
Parameter Hysteresis Power-down detection voltage Input high level current Input level current Input floating voltage Pull-down resistance Output leakage current Symbol VDET IOFFH VOH1 VOH2 Output high level voltage VOH3 VOH4 VOH5 VOL1 VOL2 Output level voltage VOL3 VOL4 VOL5 VOL6 VMID1 Output middle level voltage*2 VMID2 VMID3 Oscillator frequency fOSC IDD1 IDD2 Current drain ILCD1 ILCD2 ILCD3 INH, OSCI: INH, OSCI: KI5: S60: COM1 COM10: -100 KS6: -500 OSCO: -500 S60: COM1 COM10: KS6: OSCO: S60: COM1 COM10: ±100 COM1 COM10: ±100 OSCI, OSCO: ROSC COSC VDD: sleep mode VDD: output open, fOSC VLCD: sleep mode VLCD: VLCD 10.0 output open, fOSC When display contrast adjustment circuit used. VLCD: VLCD 10.0 output open, fOSC When display contrast adjustment circuit used.
(VLCD0 VLCD4) (VLCD0 VLCD4) (VLCD0 VLCD4)
Conditions INH,
Ratings -5.0 0.05 VLCD0 VLCD0 VLCD4 VLCD4
(VLCD0 VLCD4) (VLCD0 VLCD4) (VLCD0 VLCD4)
Unit
1000
Note: Excluding bias voltage generation divider resistor built into VLCD0, VLCD1, VLCD2, VLCD3, VLCD4. (See figure
common segment drivers
Excluding these resistors
Figure
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LC75817E, 75817W When stopped level
When stopped high level
Figure Block Diagram
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LC75817E, 75817W Functions
S60/COM10 COM1 COM9 LC75817E LC75817W Function Segment driver outputs. S60/COM10 used common driver output under "set display technique" instruction. Common driver outputs. scan outputs. Although normal scan timing lines require diodes inserted timing lines prevent shorts, since these outputs unbalanced CMOS transistor outputs, these outputs will damaged shorting when these outputs used form matrix. scan inputs. These pins have built-in pull-down resistors. General-purpose output ports Oscillator connections. oscillator circuit formed connecting external resistor capacitor these pins. Serial data interface connections controller. Note that being open-drain output, requires pull-up resistor. Chip enable Synchronization clock Transfer data Output data Input that turns display off, disables scanning, forces general-purpose output ports low. When (VSS): Display (VLCD4). S60/COM10 (VLCD4). COM1 COM9 (VLCD4). General-purpose output ports (VSS) scanning disabled: (VSS) data reset low. When high (VDD): Display state general-purpose output ports executing "Set general-purpose output port state" instruction. scanning enabled. However, serial data transferred when low. This must connected ground. drive bias voltage (high level) supply pin. level this changed display contrast adjustment circuit. However, (VLCD0 VLCD4) must greater than equal Also, external power must applied this since circuit includes display contrast adjustment circuit. drive bias voltage (middle level) supply pin. This used supply (VLCD0 VLCD4) voltage level externally. drive bias voltage (middle level) supply pin. This used supply (VLCD0 VLCD4) voltage level externally. drive bias voltage (middle level) supply pin. This used supply (VLCD0 VLCD4) voltage level externally. drive bias voltage (low level) supply pin. Fine adjustment display contrast implemented connecting external variable resistor this pin. However, (VLCD0 VLCD4) must greater than equal VLCD4 must range inclusive. Logic block power supply connection. Provide voltage between driver block power supply connection. Provide voltage between 10.0 when display contrast adjustment circuit used provide voltage between 10.0 when circuit used. Power supply connection. Connect ground. Active Handling when unused
OPEN OPEN
OPEN
OSCI OSCO
OPEN OPEN
OPEN
TEST
VLCD0
OPEN
VLCD1 VLCD2 VLCD3
OPEN OPEN OPEN
VLCD4
VLCD
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LC75817E, 75817W Block Functions (address counter) counter that provides addresses used DCRAM ADRAM. address automatically modified internally, display state retained. DCRAM (data control RAM) DCRAM that used store display data expressed 8-bit character codes. (These character codes converted matrix character patterns using CGROM CGRAM.) DCRAM capacity bits, hold characters. table below lists correspondence between 6-bit DCRAM address loaded into display position panel.
When DCRAM address loaded into 00H.
Display digit DCRAM address (hexadecimal)
However, when display shift performed specifying MDATA, DCRAM address shifts shown below.
Display digit DCRAM address (hexadecimal) Display digit DCRAM address (hexadecimal) (Right shift) (Left shift)
Note: DCRAM addresses expressed hexadecimal. Least significant DCRAM address Most significant
Hexadecimal
Hexadecimal
Example: When DCRAM address 2EH.
dots dots dots
Note: dots 12-digit display dots 12-digit display dots 12-digit display
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LC75817E, 75817W ADRAM (Additional data RAM) ADRAM used store ADATA display data. ADRAM capacity bits, stored display data displayed directly without CGROM CGRAM. table below lists correspondence between 4-bit ADRAM address loaded into display position panel.
When ADRAM address loaded into (Number digit displayed:
Display digit ADRAM address (hexadecimal)
However, when display shift performed specifying ADATA, ADRAM address shifts shown below.
Display digit ADRAM address (hexadecimal) Display digit ADRAM address (hexadecimal) (Right shift) (Left shift)
Note: ADRAM addresses expressed hexadecimal. Least significant ADRAM address Most significant
Hexadecimal
Example: When ADRAM address
Note: dots 12-digit display dots 12-digit display dots 12-digit display
dots dots dots
CGROM (Character generator ROM) CGROM used generate kinds matrix character patterns from 8-bit character codes. CGROM capacity bits. When character code written DCRAM, character pattern stored CGROM corresponding character code displayed position corresponding DCRAM address loaded into CGRAM (Character generator RAM) CGRAM which user programs freely write arbitrary character patterns. kinds matrix character patterns stored. CGRAM capacity bits.
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LC75817E, 75817W Serial Data Input When stopped level
Instruction data bits)
When stopped high level
Instruction data bits)
address D63: Instruction data
data acquired rising edge signal latched falling edge signal. When transferring instruction data from microcontroller, applications must assure that time from transfer instruction data until next instruction data transfer significantly longer than instruction execution time.
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Instruction Table
Execution time
Instruction
D1.D39
display technique
Display on/off control
DG10 DG11 DG12
µs/27
Display shift
address
DCRAM data write
ADRAM data write
CGRAM data write
CD2.CD40
CD41 CD42 CD43 CD44 CD45
LC75817E, 75817W
display contrast
scan output state
general-purpose output port state
don't care
Notes:
data format differs when "DCRAM data write" instruction executed increment mode (See detailed instruction descriptions data format differs when "ADRAM data write" instruction executed increment mode (See detailed instruction descriptions.) execution times listed here apply when fosc kHz. execution times differ when oscillator frequency fosc differs. Example: When fosc *10.When sleep mode set, execution time (when fosc kHz).
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LC75817E, 75817W Detailed Instruction Descriptions display technique <Sets display technique>
Code
don't care
DT1, DT2: Setting display technique
Display technique duty, bias drive duty, bias drive 1/10 duty, bias drive Output pins COM9 Fixed VLCD4 level COM9 COM9 S60/COM10 COM10 Note: S60: Segment outputs COMn 10): Common outputs
Display on/off control <Turns display off>
Code
DG10 DG11 DG12
don't care
Specifies data turned
Display operating state Both MDATA ADATA turned (The display forcibly turned regardless DG12 data.) Only ADATA turned (The ADATA display digits specified DG12 data turned on.) Only MDATA turned (The MDATA display digits specified DG12 data turned on.) Both MDATA ADATA turned (The MDATA ADATA display digits specified DG12 data turned on.)
Note: *12. MDATA, ADATA matrix display matrix display matrix display
DG12: Specifies display digit
Display digit Display digit data DG10 DG11 DG12
example, DG12 then display digits will turned display digits will turned (blanked).
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LC75817E, 75817W Controls common segment output pins
Common segment output states Output drive waveforms Fixed VLCD4 level (all segments off)
Note: *13. When COM1 COM10 output pins VLCD4 level, regardless DG12 data.
Controls normal mode sleep mode
Normal mode Sleep mode common segment pins VLCD4 level oscillator OSCI, OSCO pins stopped (although operates during scan operations) reduce current drain. Although "display on/off control", "Set display contrast", "Set scan output state", "Set general-purpose output port state" instructions executed this mode, applications must return normal mode execute other instruction settings. Mode
Display shift <Shifts display>
Code
don't care
Specifies data shifted
Shift operating state Neither MDATA ADATA shifted Only ADATA shifted Only MDATA shifted Both MDATA ADATA shifted
R/L: Shift direction specification
Shift direction Left shift Right shift
address. <Specifies DCRAM ADRAM address
Code
don't care
DA5: DCRAM address
Least significant Most significant
RA3: ADRAM address
Least significant Most significant
This instruction loads 6-bit DCRAM address 4-bit ADRAM address into
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LC75817E, 75817W DCRAM data write <Specifies DCRAM address stores data that address>
Code
don't care
DA5: DCRAM address
Least significant Most significant
AC7: DCRAM data (character code)
Least significant Most significant
This instruction writes bits data DCRAM. This data character code, converted matrix display data using CGROM CGRAM. Setting method writing data DCRAM
DCRAM data write method Normal DCRAM data write (Specifies DCRAM address writes DCRAM data.) Increment mode DCRAM data write (Increments DCRAM address each time data written DCRAM.)
Notes: *14. DCRAM data write method when
address bits Instruction execution time
address bits Instruction execution time
address bits Instruction execution time DCRAM data write finishes
address bits Instruction execution time DCRAM data write finishes
DCRAM data write finishes
DCRAM data write finishes
DCRAM data write method when (Instructions other than "DCRAM data write" instruction cannot executed.)
address bits
address bits
address bits
address bits
address bits
address bits
Instruction execution time DCRAM data write finishes
Instruction execution time
Instruction execution time
Instruction execution time
Instruction execution time
Instruction execution time DCRAM data write finishes
DCRAM data write finishes
DCRAM data write finishes
DCRAM data write finishes
DCRAM data write finishes
Instructions other than "DCRAM data write" instruction cannot executed.
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LC75817E, 75817W Data format bits)
Code
don't care
Data format bits)
Code
Data format bits)
Code
don't care
ADRAM data write <Specifies ADRAM address stores data that address>
Code
don't care
RA3: ADRAM address
Least significant Most significant
AD5: ADATA display data addition matrix display data (MDATA), this supports direct display five accessory display segments provided each digit ADATA. This display function does CGROM CGRAM. figure below shows correspondence between data display. When (where integer between segment corresponding that data will turned
ADATA
Corresponding output integer between
integer between
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LC75817E, 75817W Setting method writing data ADRAM
ADRAM data write method Normal ADRAM data write (Specifies ADRAM address writes ADRAM data.) Increment mode ADRAM data write (Increments ADRAM address each time data written ADRAM.)
Notes: *15. ADRAM data write method when
address bits Instruction execution time
address bits Instruction execution time
address bits Instruction execution time ADRAM data write finishes
address bits
Instruction execution time ADRAM data write finishes
ADRAM data write finishes
ADRAM data write finishes
ADRAM data write method when (Instructions other than "ADRAM data write" instruction cannot excuted.)
address bits Instruction execution time
address bits
address bits Instruction execution time
address bits Instruction execution time
address bits
address bits Instruction execution time ADRAM data write finishes
Instruction execution time
Instruction execution time
ADRAM data write finishes
ADRAM data write finishes
ADRAM data write finishes
ADRAM data write finishes
ADRAM data write finishes
Instructions other than "ADRAM data write" instruction cannot excuted.
Data format bits)
Code
don't care
Data format bits)
Code
don't care
Data format bits)
Code
don't care
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LC75817E, 75817W CGRAM data write <Specifies CGRAM address stores data that address>
Code CD10 CD11 CD12 CD13 CD14 CD15 CD16
Code CD17 CD18 CD19 CD20 CD21 CD22 CD23 CD24 CD25 CD26 CD27 CD28 CD29 CD30 CD31 CD32
Code CD33 CD34 CD35 CD36 CD37 CD38 CD39 CD40 CD41 CD42 CD43 CD44 CD45
Code don't care
CA7: CGRAM address
Least significant Most significant
CD45: CGRAM data matrix display data) (where integer between corresponds matrix display data. figure below shows that correspondence. When dots which correspond that data will turned
CD11 CD16 CD21 CD26 CD31 CD36 CD41
CD12 CD17 CD22 CD27 CD32 CD37 CD42
CD13 CD18 CD23 CD28 CD33 CD38 CD43
CD14 CD19 CD24 CD29 CD34 CD39 CD44
CD10 CD15 CD20 CD25 CD30 CD35 CD40 CD45
Note: *16. CD35: matrix display data CD40: matrix display data CD45: matrix display data
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LC75817E, 75817W display contrast <Sets display contrast>
Code don't care
CT3: Display contrast setting steps)
drive bias voltage supply VLCD0 level 0.94 VLCD VLCD (0.03 VLCD 0.91 VLCD VLCD (0.03 VLCD 0.88 VLCD VLCD (0.03 VLCD 0.85 VLCD VLCD (0.03 VLCD 0.82 VLCD VLCD (0.03 VLCD 0.79 VLCD VLCD (0.03 VLCD 0.76 VLCD VLCD (0.03 VLCD 0.73 VLCD VLCD (0.03 VLCD 0.70 VLCD VLCD (0.03 VLCD 0.67 VLCD VLCD (0.03 VLCD 0.64 VLCD VLCD (0.03 VLCD
CTC: Display contrast adjustment circuit state setting
Display contrast adjustment circuit state display contrast adjustment circuit disabled, VLCD0 level forced VLCD level. display contrast adjustment circuit operates, display contrast adjusted.
Note that although display contrast adjusted operating built-in display contrast adjustment circuit, also possible apply fine adjustments contrast connecting external variable resistor VLCD4 modifying VLCD4 voltage. However, following conditions must met: (VLCD0 VLCD4) VLCD4
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LC75817E, 75817W scan output state <Sets scan output states>
Code don't care
KC6: scan output state settings.
Output scan output state setting data
example, then output pins will output high levels (VDD) output pins will output levels (VSS) scan standby state. Note that scan output signal output from output pins that low. general-purpose output port state <Sets states general-purpose output ports>
Code
PC4: General-purpose output port state settings
Output General-purpose output port state setting data
example, then output pins will output high levels (VDD) will output levels (VSS).
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LC75817E, 75817W Serial Data Output When stopped level
When stopped high level
address KD30 data Sleep acknowledge data
Note: *17. data read operation executed when high, read data (KD1 KD30) sleep acknowledge data(SA) will invalid.
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LC75817E, 75817W Output Data KD30 data When matrix keys formed from output pins input pins those keys pressed, output data corresponding that will table shows relationship between those pins data bits.
KD11 KD16 KD21 KD26 KD12 KD17 KD22 KD27 KD13 KD18 KD23 KD28 KD14 KD19 KD24 KD29 KD10 KD15 KD20 KD25 KD30
When states output pins during scan standby high with "set scan output state" instruction matrix keys formed from output pins input pins, KD10 data bits will Sleep acknowledge data This output data state when pressed. Also, while will this case, serial data input mode normal sleep mode) during this period, that mode will set. will sleep mode normal mode.
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LC75817E, 75817W Scan Operation Functions scan timing scan period 2304T(s). reliably determine on/off state keys, LC75817E/W scans keys twice determines that been pressed when data agrees. outputs data read request level 4800T(s) after starting scan. data dose agree pressed that point, scans keys again. Thus LC75817E/W cannot detect press shorter than 4800T(s).
fosc
4608T(s)
Note: *18. Note that high/low states these pins determined "set scan output state" instruction, that scan output signals output from pins that low.
normal mode pins high with "set scan output state" instruction. lines corresponding which high pressed, scan started keys scanned until keys released. Multiple presses recognized determining whether multiple data bits set. pressed longer than 4800T(s) (Where LC75817E/W outputs data read request fosc level controller. controller acknowledges this request reads data. However, high during serial data transfer, will high. After controller reads data, data read request cleared high) LC75817E/W performs another scan. Also note that being open-drain output, requires pull-up resistor (between
input
input
scan 4800T(s)
Serial data transfer Serial data transfer
address (43H)
4800T(s)
4800T(s)
Serial data transfer
address
address
data read data read request data read data read request data read data read request fosc
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LC75817E, 75817W sleep mode pins high with "set scan output state" instruction. lines corresponding which high pressed, oscillator OSCI, OSCO pins started scan performed. Keys scanned until keys released. Multiple presses recognized determining whether multiple data bits set. pressed longer than 4800T(s)(Where LC75817E/W outputs data read request fosc level controller. controller acknowledges this request reads data. However, high during serial data transfer, will high. After controller reads data, data read request cleared high) LC75817E/W performs another scan. However, this dose clear sleep mode. Also note that being open-drain output, requires pull-up resistor (between Sleep mode scan example Example: When "display on/off control instruction "set scan output state (KC1 instruction executed (i.e. sleep mode with only high)
Note: *19. These diodes required reliably recognize multiple presses line when sleep mode state with only high, above example. That these diodes prevent incorrect operations sneak currents scan output signal when keys lines pressed same time. When these keys pressed, oscillator OSCI, OSCO pins started keys scanned.
input (KS6 line)
scan 4800T(s)
Serial data transfer Serial data transfer address (43H) Serial data transfer address
4800T(s)
fosc
data read data read request data read data read request
Multiple Presses Although LC75817E/W capable scanning without inserting diodes dual presses, triple presses input lines, multiple presses output lines, multiple presses other than these cases result keys that were pressed recognized having been pressed. Therefore, diode must inserted series with each key. Applications that recognize multiple presses three more keys should check data three more bits ignore such data.
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LC75817E, 75817W Duty, Bias Drive Technique
VLCD0
VLCD4 VLCD0
VLCD4
VLCD0
VLCD4 VLCD0
driver output when segments corresponding COM1 COM8 turned
VLCD4
driver output when only segments corresponding COM1 turned
VLCD0
VLCD4
driver output when only segments corresponding COM2 turned
VLCD0
VLCD4 VLCD0
driver output when segments corresponding COM1 COM8 turned
VLCD4
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LC75817E, 75817W Duty, Bias Drive Technique
VLCD0
VLCD4 VLCD0
VLCD4
VLCD0
VLCD4 VLCD0
driver output when segments corresponding COM1 COM9 turned
VLCD4
driver output when only segments corresponding COM1 turned
VLCD0
VLCD4
driver output when only segments corresponding COM2 turned
VLCD0
VLCD4
driver output when segments corresponding COM1 COM9 turned
VLCD0
VLCD4
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LC75817E, 75817W 1/10 Duty, Bias Drive Technique
VLCD0
VLCD4 VLCD0
VLCD4
VLCD0
VLCD4 VLCD0
driver output when segments corresponding COM1 COM10 turned
VLCD4
driver output when only segments corresponding COM1 turned
VLCD0
VLCD4 VLCD0
driver output when only segments corresponding COM2 turned
VLCD4
driver output when segments corresponding COM1 COM10 turned
VLCD0
VLCD4
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LC75817E, 75817W Voltage Detection Type Reset Circuit (VDET) This circuit generates output signal resets system when logic block power first applied when voltage drops, i.e., when logic block power supply voltage less than equal power down detection voltage VDET, which 3.0V, typical. assure that this function operates reliably, capacitor must added logic block power supply line that logic block power supply voltage rise time when logic block power first applied logic block power supply voltage fall time when voltage drops both least (See Figure Power Supply Sequence following sequences must observed when power turned off. (See Figure Power :Logic block power supply(VDD) driver block power supply(VLCD) Power off:LCD driver block power supply(VLCD) Logic block power supply(VDD) However, logic driver blocks shared power supply, then power supplies turned same time. System Reset Reset function LC75817E/W performs system reset with VDET. When system reset applied, display turned off, scanning disabled, data reset, general-purpose ports held level (VSS). These states that created result system reset cleared executing instruction described below. (See figure Clearing display state Display operation enabled executing "display on/off control" instruction. However, since contents DCRAM, ADRAM, CGRAM undefined, applications must contents these memories before turning display with "display on/off control" instruction. That applications must execute following instructions. display technique DCRAM data write ADRAM data write ADRAM used.) CGRAM data write CGRAM used.) address display contrast display contrast adjustment circuit used.)
After executing above instructions, applications must turn display with "display on/off control" instruction. Note that when applications turn normal mode, applications must turn display with "display on/off control" instruction pin. Clearing scan disable data reset states Executing "set scan output state" instruction only creates state which scanning performed, also clears data reset. Clearing general-purpose output ports locked level (VSS) state Executing "set general-purpose output port state" instruction clears general-purpose output ports locked level (VSS) state sets states general-purpose output ports.
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LC75817E, 75817W
VDET VDET
VLCD
Instruction execution
Initial state settings
scan
Disabled
Execution enabled
General-purpose output ports
Fixed level (VSS)
either high (VDD) (VSS) level.
Display state
Display
Display
Display
"Set scan output "Set general-purpose output port state" state" instruction instruction execution execution
"Display on/off control" instruction execution (Turning display
"Display on/off control" instruction execution (Turning display off)
(Logic block power supply voltage rise time) (Logic block power supply voltage fall time) Initial state settings display technique DCRAM data write ADRAM data write ADRAM used.) CGRAM data write CGRAM used.) address display contrast display contrast adjustment circuit used.)
Figure
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LC75817E, 75817W Block states during system reset CLOCK GENERATOR, TIMING GENERATOR When reset applied, oscillator OSCI, OSCO pins started forcibly. This generates base clock enables instruction execution. INSTRUCTION REGISTER, INSTRUCTION DECODER When reset applied, these circuits forcibly initialized internally. Then, when instruction execution starts, operates according those instructions. ADDRESS REGISTER, ADDRESS COUNTER When reset applied, these circuits forcibly initialized internally. Then, DCRAM ADRAM addresses when "Set address" instruction executed. DCRAM, ADRAM, CGRAM Since contents DCRAM, ADRAM, CGRAM become undefined during reset, applications must execute "DCRAM data write", "ADRAM data write ADRAM used.)", "CGRAM data write CGRAM used.)" instructions before executing "display on/off control" instruction. CGROM Character patterns stored this ROM. LATCH Although value data latch undefined during reset, ADRAM, CGROM, CGRAM data stored executing "display on/off control" instruction. COMMON DRIVER, SEGMENT DRIVER These circuits forced display state when reset applied. CONTRAST ADJUSTER Display contrast adjustment circuit operation disabled when reset applied. After that, display contrast executing "set display contrast" instruction. SCAN, BUFFER When reset applied, these circuits forcibly initialized internally, scan operation disabled. Also, data After that, scanning performed executing "set scan output state" instruction. (10) GENERAL PORT general-purpose output ports fixed level (VSS) when reset applied. (11) INTERFACE, SHIFT REGISTER These circuits serial data input wait state.
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LC75817E, 75817W
GENERAL PORT
COMMON DRIVER
SEGMENT DRIVER
INSTRUCTION DECODER
CONTRAST ADJUSTER INSTRUCTION REGISTER
ADDRESS COUNTER
ADDRESS REGISTER
BUFFER VDET TIMING GENERATOR
CLOCK GENERATOR
SCAN
Blocks that reset
Output states during reset period
Output S60/COM10 COM1 COM9 State during reset (VLCD4) (VLCD4)*20 (VLCD4) (VSS) (VSS)
Notes: *20. This output forcibly segment output function held level (VLCD4). However, when "set display technique" instruction executed, segment output common output function selected specified that instruction. *21. Since this output open-drain output, pull-up resistor (between required. This held high level even data read operation performed before executing "set scan output state" instruction.
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LC75817E, 75817W Sample Application Circuit duty, bias drive technique (for with normal panels)
panel
0.047
From controller controller controller power supply (general-purpose output ports) used with backlight controller other circuit
matrix keys)
Notes: *22. capacitor logic block power supply line that logic block power supply voltage rise time when power applied logic block power supply voltage fall time when power drops both least LC75817E/W reset VDET. *23. variable resistor used display contrast fine adjustment, VLCD4 must connected ground. *24. used, must connected logic block power supply VDD. *25. pin, being open-drain output, requires pull-up resistor. Select resistance (between appropriate capacitance external wiring that signal waveforms degraded.
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LC75817E, 75817W Sample Application Circuit duty, bias drive technique (for with large panels)
panel
0.047
From controller controller controller power supply (general-purpose output ports) used with backlight controller other circuit
matrix keys)
Notes: *22. capacitor logic block power supply line that logic block power supply voltage rise time when power applied logic block power supply voltage fall time when power drops both least LC75817E/W reset VDET. *23. variable resistor used display contrast fine adjustment, VLCD4 must connected ground. *24. used, must connected logic block power supply VDD. *25. pin, being open-drain output, requires pull-up resistor. Select resistance (between appropriate capacitance external wiring that signal waveforms degraded.
6144-32/43
LC75817E, 75817W Sample Application Circuit duty, bias drive technique (for with normal panels)
panel
0.047
From controller controller controller power supply
(general-purpose output ports) used with backlight controller other circuit
matrix keys)
Notes: *22. capacitor logic block power supply line that logic block power supply voltage rise time when power applied logic block power supply voltage fall time when power drops both least LC75817E/W reset VDET. *23. variable resistor used display contrast fine adjustment, VLCD4 must connected ground. *24. used, must connected logic block power supply VDD. *25. pin, being open-drain output, requires pull-up resistor. Select resistance (between appropriate capacitance external wiring that signal waveforms degraded.
6144-33/43
LC75817E, 75817W Sample Application Circuit duty, bias drive technique (for with large panels)
panel
0.047
From controller controller controller power supply
(general-purpose output ports) used with backlight controller other circuit
matrix keys)
Notes: *22. capacitor logic block power supply line that logic block power supply voltage rise time when power applied logic block power supply voltage fall time when power drops both least LC75817E/W reset VDET. *23. variable resistor used display contrast fine adjustment, VLCD4 must connected ground. *24. used, must connected logic block power supply VDD. *25. pin, being open-drain output, requires pull-up resistor. Select resistance (between appropriate capacitance external wiring that signal waveforms degraded.
6144-34/43
LC75817E, 75817W Sample Application Circuit 1/10 duty, bias drive technique (for with normal panels)
panel
0.047
From controller controller controller power supply
(general-purpose output ports) used with backlight controller other circuit
matrix keys)
Notes: *22. capacitor logic block power supply line that logic block power supply voltage rise time when power applied logic block power supply voltage fall time when power drops both least LC75817E/W reset VDET. *23. variable resistor used display contrast fine adjustment, VLCD4 must connected ground. *24. used, must connected logic block power supply VDD. *25. pin, being open-drain output, requires pull-up resistor. Select resistance (between appropriate capacitance external wiring that signal waveforms degraded.
6144-35/43
LC75817E, 75817W Sample Application Circuit 1/10 duty, bias drive technique (for with large panels)
panel
0.047
From controller controller controller power supply
(general-purpose output ports) used with backlight controller other circuit
matrix keys)
Notes: *22. capacitor logic block power supply line that logic block power supply voltage rise time when power applied logic block power supply voltage fall time when power drops both least LC75817E/W reset VDET. *23. variable resistor used display contrast fine adjustment, VLCD4 must connected ground. *24. used, must connected logic block power supply VDD. *25. pin, being open-drain output, requires pull-up resistor. Select resistance (between appropriate capacitance external wiring that signal waveforms degraded.
6144-36/43
LC75817E, 75817W Sample Correspondence between Instructions Display (When LC75817-8720 used)
Instruction (hexadecimal) Display Initializes display state. Sets duty bias display drive technique Operation
Power application (Initialization with VDET.) display technique DCRAM data write (increment mode)
Writes display data DCRAM address
DCRAM data write (increment mode) DCRAM data write (increment mode) DCRAM data write (increment mode) DCRAM data write (increment mode) DCRAM data write (increment mode) DCRAM data write (increment mode) DCRAM data write (increment mode) DCRAM data write (increment mode) DCRAM data write (increment mode) DCRAM data write (increment mode) DCRAM data write (increment mode) DCRAM data write (increment mode) DCRAM data write (increment mode) DCRAM data write (increment mode) DCRAM data write (increment mode) DCRAM data write (increment mode) DCRAM data write (increment mode) DCRAM data write (increment mode)
Writes display data DCRAM address
Writes display data DCRAM address
Writes display data DCRAM address
Writes display data DCRAM address
Writes display data DCRAM address
Writes display data DCRAM address
Writes display data DCRAM address
Writes display data DCRAM address
Writes display data DCRAM address
Writes display data DCRAM address
Writes display data DCRAM address
Writes display data DCRAM address
Writes display data DCRAM address
Writes display data DCRAM address
Writes display data DCRAM address
Writes display data DCRAM address
Writes display data DCRAM address
Writes display data DCRAM address
Continued next page.
6144-37/43
LC75817E, 75817W
Continued from preceding page.
Instruction (hexadecimal) Display Operation Loads DCRAM address ADRAM address into Turns digits digits) MDATA
address
Display on/off control
Display shift Display shift Display shift Display shift Display shift Display shift Display shift Display on/off control
Shifts display (MDATA only) left
Shifts display (MDATA only) left
Shifts display (MDATA only) left
Shifts display (MDATA only) left
Shifts display (MDATA only) left
Shifts display (MDATA only) left
Shifts display (MDATA only) left
sleep mode, turns digits
Display on/off control
Turns digits digits) MDATA Loads DCRAM address ADRAM address into don't care
address
Note: *26. This example above assumes digits matrix LCD. CGRAM ADRAM used.
6144-38/43
LC75817E, 75817W Notes controller data read techniques Timer based data acquisition Flowchart
data read processing
Timing chart
input
scan data read request Controller determination (Key Controller determination (Key Controller determination (Key off) Controller determination (Key Controller determination (Key off) address data read
scan execution time when data agreed scans. (4800T(s)) scan execution time when data agree scans scan executed again. (9600T(s)) address (43H) transfer time data read time fosc
Explanation this technique, controller uses timer determine on/off states read data. controller must check state when every period without fail. low, controller recognizes that been pressed executes data read operation. period this technique must satisfy following condition. t9>t6+t7+t8 data read operation executed when high, read data (KD1 KD30) sleep acknowledge data (SA) will invalid.
6144-39/43
LC75817E, 75817W Interrupt based data acquisition Flowchart
data read processing
Wait least
Timing chart
input
scan data read request Controller determination (Key Controller determination (Key off) Controller determination (Key Controller determination (Key Controller determination (Key Controller determination (Key off) address data read
scan execution time when data agreed scans. (4800T(s)) scan execution time when data agree scans scan executed again. (9600T(s)) address (43H) transfer time data read time fosc
6144-40/43
LC75817E, 75817W Explanation this technique, controller uses interrupts determine on/off states read data. controller must check state when low. low, controller recognizes that been pressed executes data read operation. After that next on/off determination performed after time elapsed checking state when reading data. period this technique must satisfy following condition. data read operation executed when high, read data (KD1 KD30) sleep acknowledge data (SA) will invalid.
6144-41/43
LC75817-8720 Character Font (Standard)
LC75817E, 75817W
6144-42/43
A10735
LC75811E, 75811W
Specifications SANYO products described contained herein stipulate performance, characteristics, functions described products independent state, guarantees performance, characteristics, functions described products mounted customer's products equipment. verify symptoms states that cannot evaluated independent device, customer should always evaluate test devices mounted customer's products equipment. SANYO Electric Co., Ltd. strives supply high-quality high-reliability products. However, semiconductor products fail with some probability. possible that these probabilistic failures could give rise accidents events that could endanger human lives, that could give rise smoke fire, that could cause damage other property. When designing equipment, adopt safety measures that these kinds accidents events cannot occur. Such measures include limited protective circuits error prevention circuits safe design, redundant design, structural design. event that SANYO products (including technical data, services) described contained herein controlled under applicable local export control laws regulations, such products must exported without obtaining export license from authorities concerned accordance with above law. part this publication reproduced transmitted form means, electronic mechanical, including photocopying recording, information storage retrieval system, otherwise, without prior written permission SANYO Electric Co., Ltd. information described contained herein subject change without notice product/technology improvement, etc. When designing equipment, refer "Delivery Specification" SANYO product that intend use. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties.
This catalog provides information May, 1999. Specifications information herein subject change without notice. 6144-43/43
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