LC75742E, 75742W Duty Driver with Input Function Overview
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Ordering number EN6142
LC75742E, 75742W
Duty Driver with Input Function
Overview
LC75742E LC75742W duty drivers that used electronic tuning frequency display other applications under control microcontroller. These products directly drive VFDs with segments. also includes scan circuit support input from keys thus reduce number lines front panel application systems.
Package Dimensions
unit: 3151-QFP64E
[LC75742E]
17.2 14.0 0.35
0.15
input from keys (Key scans only performed when keys pressed.) segment outputs. Noise reduction circuits built into output drivers. Serial data supports format communication with system controller. Dimmer sleep mode controlled serial data input. High generality since display data displayed without intervention decoder. segments turned with pin.
Features
17.2 14.0
3.0max
15.6
SANYO: QFP64E (QIP64E)
unit: 3190-SQFP64
[LC75742W]
12.0 10.0 1.25
0.18
1.25
0.15
12.0 10.0
1.25
1.7max
1.25
SANYO: SQFP64
trademark SANYO ELECTRIC CO., LTD. SANYO's original format addresses controlled SANYO.
SANYO products described contained herein have specifications that handle applications that require extremely high levels reliability, such life-support systems, aircraft's control systems, other applications whose failure reasonably expected result serious physical and/or material damage. Consult with your SANYO representative nearest before using SANYO products described contained herein such applications. SANYO assumes responsibility equipment failures that result from using products values that exceed, even momentarily, rated values (such maximum ratings, operating condition ranges, other parameters) listed products specifications SANYO products described contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
43099TH (OT) 6142-1/18
LC75742E, LC75742W
Specifications
Absolute Maximum Ratings 25°C,
Parameter Maximum Supply voltage Symbol VIN1 VIN2 VOUT1 Output voltage VOUT2 VOUT3 IOUT1 Output current IOUT2 IOUT3 Allowable power dissipation Operating temperature Storage temperature Topr Tstg OSCI, S41, OSCO, 85°C (LC75742E) 85°C (LC75742W) Conditions Ratings -0.3 +6.5 -0.3 +21.0 -0.3 +6.5 -0.3 +0.3 -0.3 +0.3 -0.3 +0.3 -0.3 +6.5 +150 Unit
Input voltage
Allowable Operating Ranges +85°C,
Parameter Symbol VIH1 High-level input voltage VIH2 VIH3 Low-level input voltage Guaranteed oscillator frequency range Recommended external resistor value Recommended external capacitor value Clock low-level pulse width Clock high-level pulse width Data setup time Data hold time wait time setup time hold time output delay time rise time switching time fOSC ROSC COSC OSCI BLK, OSCI, OSCI, OSCO OSCI, OSCO OSCI, OSCO figure figure figure figure figure figure figure pF*: figure pF*: figure BLK, figure Conditions Ratings Unit
Supply voltage
Note: Since open-drain output, these values will vary with pull-up resistance load capacitance
6142-2/18
LC75742E, LC75742W Electrical Characteristics Allowable Operating Ranges
Parameter Symbol IIH1 IIH2 IOFFH VOH1 High-level output voltage VOH2 VOH3 VOH4 VOL1 Low-level output voltage VOL2 VOL3 VOL4 Oscillator frequency Hysteresis voltage Current drain fOSC IDD1 IDD2 Conditions BLK: OSCI: BLK, OSCI: KI5: S41: OSCO: -0.5 KS6: -500 S41, OSCO: KS6: ROSC COSC BLK, Sleep mode Outputs open: fOSC 0.05 Ratings Unit
High-level input current Low-level input current Input floating voltage Pull-down resistance Output leakage current
When stopped with level
When stopped with high level
Figure
6142-3/18
LC75742E, LC75742W Assignment
LC75742E LC75742W
view
6142-4/18
LC75742E, LC75742W Block Diagram
Descriptions
OSCI OSCO Function Driver block power supply. Applications must provide voltage range 18.0 Logic block power supply. Applications must provide voltage range Power supply ground. This must connected system ground. Oscillator circuit connections. oscillator circuit formed connecting resistor capacitor externally these pins. Reset signal input used initialize internal state. During reset, display turned forcibly regardless internal display data. Also note that internal data reset scan operations disabled. However, serial data input possible this state. Serial data interface. These pins must connected system microcontroller. Note that since open-drain output, pull-up resistor required. Synchronization clock Chip enable Transfer data Output data Handling when unused OPEN
OPEN OPEN OPEN OPEN
Digit outputs. frame frequency (fOSC/4096) Segment outputs that display display data transferred over serial interface. scan outputs. Normally, when matrix formed, diodes inserted scan timing lines prevent shorts. However, since this uses unbalanced CMOS outputs output transistor circuit, will damaged these outputs shorted. scan inputs. Pull-down resistors built into internal circuits.
6142-5/18
LC75742E, LC75742W Serial Data Input When stopped with level
Note: don't care Direction data
When stopped with high level
Note: don't care Direction data
Figure
address: Applications must send value 01110001B (8EH) shown figure D41: Segment display data digit output Segment Segment D82: Segment display data digit output Segment Segment Sleep control data DM9: Dimmer data
6142-6/18
LC75742E, LC75742W Control Data Sleep control data This control data controls switching between sleep mode normal mode, also sets states scan output pins scan standby mode.
Control data Mode Normal Sleep Sleep Sleep Clock generator (oscillator circuit) Oscillator operating Stopped Stopped Stopped Segment outputs Digit output Operating Output states during scan standby
DM9: Dimmer data This data controls duty digit output pins. This data forms 10-bit binary value which LSB. brightness display controlled adjusting duty digit output pins. table lists relationship between dimmer data dimmer value.
Dimmer value (t4/t3) 0/1024 1/1024 2/1024 1020/1024 1021/1024 1022/1024 Illegal setting
figure
Relationship between Display Data D82) Segment Output Pins
Segment output Segment output Segment output
example, table below lists operation segment output pin.
Display data Segment output (S11) state segments corresponding digit output pins segment corresponding digit output turned segment corresponding digit output segments corresponding digit output pins
6142-7/18
LC75742E, LC75742W Serial Data Output When stopped with level
When stopped with high level
Figure
address: Applications must send value 11110001B (8FH) shown figure KD30: data Sleep acknowledge data
Note: data (KD1 KD30) sleep acknowledge data (SA) will invalid data read when high.
6142-8/18
LC75742E, LC75742W Output Data KD30: data These bits represent output states when matrix with keys formed using scan output pins scan input pins. When pressed, corresponding that will correspondence listed following table.
Item KD11 KD16 KD21 KD26 KD12 KD17 KD22 KD27 KD13 KD18 KD23 KD28 KD14 KD19 KD24 KD29 KD10 KD15 KD20 KD25 KD30
Sleep acknowledge data This output data state when pressed. that case will level. serial data input during this period mode (normal mode sleep mode), will that mode. sleep mode normal mode. Sleep Mode sleep mode setting either control data segment outputs digit outputs low, clock generator (oscillator circuit) stopped (although restarted when pressed), thus power dissipation reduced. This mode cleared setting control data
Scan Operation scan timing scan period 12000T [s]. scan performed twice reliably recognize on/off states verifying that data scans agrees. data agrees, recognizes press 25600T after start scan execution issues scan data read request outputting level from data does agree pressed later scan, executes another scan operation. Note that this means that this cannot recognize press shorter than 25600T [s].
Note high-level low-level states sleep mode according control data scan output signals output from pins state.
6142-9/18
LC75742E, LC75742W normal mode pins high. scan started when keys pressed, keys kept scanning until keys released. controller recognize simultaneous multiple presses checking data multiple bits being set. pressed over 25600T (where 1/fOSC), outputs data read request controller setting low. controller acknowledges this state reads data. However, note that will high when high during serial data transfer. After controller data readout completes, data read request will cleared will high), performs another scan. Note that since open-drain output, pull-up resistor (between required.
input
input
scan
Serial data transfer
Serial data transfer
address (8FH)
Serial data transfer
address
address
data read data read request
data read data read request
data read data read request
sleep mode pins high according values control data. (See description control data elsewhere this document.) connected lines that high pressed, clock generator (oscillator circuit) started scan performed, keys kept scanning until keys released. controller recognize simultaneous multiple presses checking data multiple bits being set. pressed over 25600T (where 1/fOSC), outputs data read request controller setting low. controller acknowledges this state reads data. However, note that will high when high during serial data transfer. After controller data readout completes, data read request will cleared will high), performs another scan. However, sleep mode will cleared. Note that since open-drain output, pull-up resistor (between required. Example scan operation sleep mode Example: Sleep mode with (Only high)
these keys pressed, clock generator (oscillator circuit) started scan performed.
Note These diodes required reliably recognize multiple presses line when sleep mode with only high example above. That they prevent incorrect recognition presses sneak currents arising from simultaneous presses keys through lines.
6142-10/18
LC75742E, LC75742W
input (KS6 line)
scan
Serial data transfer
Serial data transfer
address (8FH)
Serial data transfer
address
data read data read request
data read data read request
Multiple Presses LC75742E/W, even without diodes scan lines, scan combination dual presses, combination triple presses scan input lines, combination multiple presses scan output lines. However, keys that pressed seen having been pressed other multiple press combination. Accordingly, applications must insert diodes each key. Also, reject triple higher multiple presses, three more data readout ignore data software other ways. Notes Display Control Since states internal data D82, control data) undefined when power first applied, applications should turn display (i.e. S41, low) setting same time power applied. Applications should transfer bits serial data while held low, only then high. This will prevent random meaningless display power (See figure Note Power Sequence Applications must observe following sequences when turning power off. power First turn logic system power (VDD), then turn driver power (VFL) power off: First turn driver power (VFL), then turn logic system power (VDD).
Figure
6142-11/18
LC75742E, LC75742W Output Waveforms S41)
waveform when segment corresponding
waveform when segment corresponding
waveform when seguments corresponding
waveform when seguments corresponding off.
6142-12/18
LC75742E, LC75742W Relationship between Segment Digit Outputs
Example
Example
Example
Figure Figure shows case where display data that segment outputs output level with same timing digit outputs, output level with same timing digit output. Here, segments corresponding will turned relationship between oscillator frequency fOSC this case 2048/fOSC. digit output waveforms example correspond dimmer data (DM0 DM9) 3FEH. relationship between oscillator frequency fOSC 2/fOSC. Note that example identical times. digit output waveforms example correspond dimmer data (DM0 DM9) smaller value. Although does change, becomes longer. Here, dimmer data (DM0 DM9) 1FFH oscillator frequency fOSC MHz, then calculated follows. (1FFH 1024 fOSC
0.64 [ms] dimmer data (DM0 DM9) even smaller value, will become even longer shown example Note that does change this case well.
6142-13/18
LC75742E, LC75742W Block States during Reset Period (when low) Divider timing generator These circuits reset their base clock stopped. Dimmer timing generator circuit reset operation stopped. Digit segment drivers These circuits reset display turned low.) scan circuit reset, internal circuits initial state, scanning disabled. buffer circuit reset data Clock generator state (normal sleep mode) this block (the clock oscillator circuit) determined after sleep control data transferred. interface, shift register, control register, latch, multiplexer These circuits reset that serial data input during reset period.
DIGIT DRIVER
SEGMENT DRIVER
DIMMER TIMING GENERATOR
TIMING GENERATOR DIVIDER
BUFFER
SCAN
Blocks that reset.
6142-14/18
LC75742E, LC75742W Output States during Reset Period (when low)
Output State during reset
Notes: state this undefined after power been applied until sleep control data transferred. Since this open-drain output, pull-up resistor (between required. remains high during reset period even controller attempts read data.
Sample Application Circuit
From controller controller controlle power supply
matrix with keys
Note Since open-drain output, pull-up resistor required. Select value range that most appropriate capacitance external lines that waveform distorted.
Notes Segment Digit Waveforms
Segment waveform
Digit waveform
Digit waveform
Figure segment waveform somewhat deformed panel itself circuit wiring. Furthermore, digit waveform such digit waveform which dimming applied used, display will glow dimly. Therefore, applications must take this waveform deformation into account apply adequate dimming such that shown digit waveform that this phenomenon does occur.
6142-15/18
panel with segments
LC75742E, LC75742W Notes Controller Transfer Display Data Since display data D82) transferred operations shown figure strongly recommend that applications transfer data within period assure display quality. Controller Data Readout Procedure When controller uses timer read data Flowchart
Timing chart
Controller determination (Key
Controller determination (Key
Controller determination (Key off)
Controller determination (Key
Controller determination (Key off)
.Key scan execution time (25600T [s]) when data scan operations matches. .Key scan execution time (51200T [s]) when data first scan operations .does match. fOSC .Key address (8FH) transfer time .Key data readout time Operation When controller timer processing on/off determination data readout, must check state least once every period. low, controller must recognize that been pressed read data. period must obey following inequality: Note that controller reads data when high, both data (KD1 KD30) sleep acknowledge data will invalid data.
6142-16/18
LC75742E, LC75742W When controller uses interrupt processing read data Flowchart
Wait period least t10)
Timing chart
Controller determination (Key
Controller Controller determination determination (Key off) (Key
Controller determination (Key
Controller determination (Key
Controller determination (Key off)
t5.Key scan execution time (25600T [s]) when data scan operations matches. .Key scan execution time (51200T [s]) when data first scan operations .does match. address (8FH) transfer time fOSC t8.Key data readout time Operation When controller uses interrupt processing on/off determination data readout, must check state when low, perform data readout low. next time controller checks on/off states keys, must make that determination time after last readout based state when low, then read data. time must obey following inequality: Note that controller reads data when high, both data (KD1 KD30) sleep acknowledge data will invalid data.
6142-17/18
LC75742E, LC75742W
Specifications SANYO products described contained herein stipulate performance, characteristics, functions described products independent state, guarantees performance, characteristics, functions described products mounted customer's products equipment. verify symptoms states that cannot evaluated independent device, customer should always evaluate test devices mounted customer's products equipment. SANYO Electric Co., Ltd. strives supply high-quality high-reliability products. However, semiconductor products fail with some probability. possible that these probabilistic failures could give rise accidents events that could endanger human lives, that could give rise smoke fire, that could cause damage other property. When designing equipment, adopt safety measures that these kinds accidents events cannot occur. Such measures include limited protective circuits error prevention circuits safe design, redundant design, structural design. event that SANYO products (including technical data, services) described contained herein controlled under applicable local export control laws regulations, such products must exported without obtaining export license from authorities concerned accordance with above law. part this publication reproduced transmitted form means, electronic mechanical, including photocopying recording, information storage retrieval system, otherwise, without prior written permission SANYO Electric Co., Ltd. information described contained herein subject change without notice product/technology improvement, etc. When designing equipment, refer "Delivery Specification" SANYO product that intend use. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties.
This catalog provides information April, 1999. Specifications information herein subject change without notice. 6142-18/18
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