LC72723, LC72723M Demodulation Overview LC72723 (Radio

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LC72723, LC72723M Demodulation Overview LC72723 (Radio

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Ordering number EN6037
LC72723, LC72723M
Demodulation
Overview
LC72723 (Radio Data System) signal demodulation This integrates bandpass filter, demodulation circuit, buffer single chip read data slave mode operation with provision external clock input. also supports master mode, which data read synchronization with clock output provided itself.
Package Dimensions
unit: 3006B-DIP16
[LC72723]
7.62
19.2
Functions
Bandpass filter: Switched capacitor filter (SCF) demodulation: Functions include 57kHz carrier regeneration, clock regeneration, biphase decoding, differential decoding Buffer RAM: Stores bits (about data. Data output: Output switched between master mode slave mode readout. detection: Supports reset Standby control: Stops crystal oscillator. Fully adjustment free.
0.71
2.54
0.48
3.65max
SANYO: DIP16
unit: 3035A-MFP16
[LC72723M]
0.625
Ratings
Operating supply voltage: Operating temperature: 85°C Packages: DIP16 MFP16
10.1 5.15
1.8max
0.15
0.35
1.27
0.605
SANYO: MFP16
SANYO products described contained herein have specifications that handle applications that require extremely high levels reliability, such life-support systems, aircraft's control systems, other applications whose failure reasonably expected result serious physical and/or material damage. Consult with your SANYO representative nearest before using SANYO products described contained herein such applications. SANYO assumes responsibility equipment failures that result from using products values that exceed, even momentarily, rated values (such maximum ratings, operating condition ranges, other parameters) listed products specifications SANYO products described contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
40299RM (OT) 6037-1/8
0.25
LC72723, LC72723M Assignment (DIP16/MFP16)
Block Diagram
6037-2/8
LC72723, LC72723M Descriptions
Function circuit type
VREF
Reference voltage output (Vdda/2)
Output
MPXIN
Base band (multiplex) signal input
Input
FLOUT
Subcarrier output (filter output)
Output
Subcarrier input (comparator input)
Input
Vdda Vssa XOUT
Analog system power supply Analog system ground Crystal element output (4.332 MHz)
Output
Crystal element input external reference signal input)
TEST MODE
Test input Readout mode setting master, slave) reset (Active high logic)
Input
RDDA
data output
Output
RDCL
clock output (master mode) clock input (slave mode)
RDS-ID/READY
ID/ready output (Active low)
Output
Vddd Vssd
Digital system power supply Digital system ground
6037-3/8
LC72723, LC72723M
Specifications
Absolute Maximum Ratings 25°C, Vssd Vssa
Parameter Maximum supply voltage Symbol VIN1 Maximum input voltage VIN2 VIN3 Maximum output voltage Maximum output current Topr Tstg Vddd, Vdda TEST, MODE, XIN, RDCL MPXIN, RDS-ID (READY) XOUT, RDDA, RDCL FLOUT XOUT, FLOUT, RDDA, RDCL RDS-ID (READY) 85°C) Conditions Ratings -0.3 -0.3 +7.0 -0.3 Vddd -0.3 Vdda -0.3 +7.0 -0.3 Vddd -0.3 Vdda +3.0 +20.0 DIP16 MFP16 +125 Unit
Allowable power dissipation Operating temperature Storage temperature
Note that Vdda must less than equal Vddd
Allowable Operating Ranges +85°C, Vssd Vssa Vddd Vdda
Parameter Supply voltage High-level input voltage Low-level input voltage Output voltage Symbol VIH1 VIH2 VIN1 Input amplitude VIN2 VXIN Guaranteed oscillator operating range Crystal oscillator frequency deviation RDCL setup time RDCL high-level time RDCL low-level time Data output time READY output time READY low-level time Xtal TXtal Conditions Vddd, Vdda: Vddd Vdda TEST, MODE, RDCL TEST, MODE, RST, RDCL RDDA, RDCL RDS-ID (READY) MPXIN XIN, XOUT: XIN, XOUT: 4.332 RDCL, RDDA RDCL RDCL RDCL, RDDA RDCL, READY READY 0.75 0.75 0.75 0.75 100% modulation, composite 4.332 ±100 1500 Ratings Vddd Vddd Vddd Vddd Vddd Unit mVrms mVrms mVrms
6037-4/8
LC72723, LC72723M Electrical Characteristics +85°C, Vssd Vssa Vddd Vdda
Parameter Symbol Rmpxin Rcin BW-3dB Gain Att1 Stop band attenuation Att2 Att3 Reference voltage output Hysteresis Low-level output voltage High-level output voltage High-level input current Vref VHIS VOL1 VOL2 IIH1 IIH2 IIL1 IIL2 IOFF Conditions MPXIN-Vssa: CIN-Vssa: FLOUT FLOUT MPXIN-FLOUT: FLOUT: FLOUT: KHz, FLOUT: Vref: Vdda TEST, MODE, RST, RDCL RDDA, RDCL RDS-ID (READY): RDDA, RDCL TEST, MODE, RST, RDCL XIN: Vddd TEST, MODE, RST, RDCL XIN: RDS-ID (READY): Vddd Vdda Vddd 56.5 Vddd Ratings 57.0 57.5 Unit
Input resistance Internal feedback resistance Center frequency -3dB bandwidth Gain
Low-level input current Output leakage current Current drain
Inputs Outputs
TEST MODE Master mode Slave mode Standby mode (crystal oscillator stopped) test mode (Cannot users.) Circuit operating mode RDCL Clock output Clock input RDS-ID/READY RDS-ID output READY output
Normal operation RDS-ID demodulation circuits cleared, slave mode) READY state memory cleared.
ID/READY Master mode RDS-ID output (active low) Slave mode Readout data ready output (active low)
Note: RDS-ID (READY) n-channel open-drain output, data read connecting pull-up resistor.
6037-5/8
LC72723, LC72723M RDCL/RDDA Output Timing Master mode
Operation Master mode
Caution: After input, RDCL RDDA outputs stop high level until first detection.
RDCL Control Slave Mode
Parameter RDCL setup time RDCL high-level time RDCL low-level time Data output time READY output time Ready low-level time
Symbol RDCL, RDDA RDCL RDCL RDCL, RDDA RDCL, READY READY
Conditions
Ratings 0.75 0.75 0.75 0.75
Unit
Notes:1. Start RDCL clock input after READY signal goes low. Applications must stand with RDCL held when READY high. Each time RDCL input switched from high low, application must check READY signal level after period elapsed once RDCL been low. READY level, application apply next RDCL clock cycle. READY high, application must stop RDCL input that point. When above timing conditions met, RDDA read either rise fall RDCL signal. After last data from memory been read, READY will high once period elapsed after fall RDCL signal. even data been written memory, READY will application will able read that data.
6037-6/8
LC72723, LC72723M
When switching channels, desirable immediately reset memory READY with input. this done, data received previous channel remain memory. When reset, data written until RDS-ID detected, therefore, READY signal will after RDS-ID detected. (Although RDS-ID output slave mode, detected internally IC.) After input, once RDSID been detected, received data will written memory regardless RDS-ID detection state. readout mode switched between master slave modes during readout. Applications must observe following points assure data continuity during this operation. Data acquisition timing master mode Data must read falling edge RDCL. Timing switch from master mode slave mode After RDCL output goes RDDA data been acquired, application must MODE high immediately. Then, microcontroller starts output setting RDCL signal low. microcontroller RDCL output must start within (tms) after RDCL went low. this case, last data read master mode data item then data starting with item will written memory. Timing switch from slave mode master mode After data been read from memory READY gone high, application must then wait until READY goes once again next time (timing figure), immediately read data input RDCL clock. Then, point READY goes high, microcontroller must terminate RDCL output then MODE low. application must switch MODE within (tms) after READY goes (timing figure).
RDCL (microcontroller status) RDCL status)
6037-7/8
LC72723, LC72723M LC72723 Sample Application Connection Circuit (for slave mode operation)
Caution: unused, must connected ground.
Specifications SANYO products described contained herein stipulate performance, characteristics, functions described products independent state, guarantees performance, characteristics, functions described products mounted customer's products equipment. verify symptoms states that cannot evaluated independent device, customer should always evaluate test devices mounted customer's products equipment. SANYO Electric Co., Ltd. strives supply high-quality high-reliability products. However, semiconductor products fail with some probability. possible that these probabilistic failures could give rise accidents events that could endanger human lives, that could give rise smoke fire, that could cause damage other property. When designing equipment, adopt safety measures that these kinds accidents events cannot occur. Such measures include limited protective circuits error prevention circuits safe design, redundant design, structural design. event that SANYO products (including technical data, services) described contained herein controlled under applicable local export control laws regulations, such products must exported without obtaining export license from authorities concerned accordance with above law. part this publication reproduced transmitted form means, electronic mechanical, including photocopying recording, information storage retrieval system, otherwise, without prior written permission SANYO Electric Co., Ltd. information described contained herein subject change without notice product/technology improvement, etc. When designing equipment, refer "Delivery Specification" SANYO product that intend use. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties.
This catalog provides information April, 1999. Specifications information herein subject change without notice. 6037-8/8

LC72723, LC72723M Demodulation Overview LC72723 (Radio

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