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16-BIT WITH UNIT, 256K BYTE FLASH MEMORY BYTE HIGH PERFORMANCE 40


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ST10F269
16-BIT WITH UNIT, 256K BYTE FLASH MEMORY BYTE
HIGH PERFORMANCE 40MHz WITH FUNCTION 16-BIT WITH 4-STAGE PIPELINE 50ns INSTRUCTION CYCLE TIME 40MHz CLOCK MULTIPLY/ACCUMULATE UNIT (MAC) 16-BIT MULTIPLICATION, 40-BIT ACCUMULATOR REPEA UNIT ENHAN BOOLEAN MANIPULATION FACILITIES ADDITIONAL INSTRUCTIONS SUPPORT OPERATING SYSTEMS SINGLE-CYCLE CONTEXT SWITCHING SUPPORT MEMORY ORGANIZATION 256K BYTE ON-CHIP FLASH MEMORY SINGLE VOLTAGEWITH ERASE/PROGRAMCONTROLLER. 100K ERASING/PROGRAMMING CYCLES BYTE LINEAR ADDRESS SPACE CODE DATA BYTES WITH CAN) BYTE ON-CHIP INTERNAL (IRAM) BYTE ON-CHIP EXTENSION (XRAM) FAST FLEXIBLE PROGRAMMABLE EXTERNAL CHARACTERISTICS DIFFERENT ADDRESS RANGES 8-BIT 16-BIT EXTERNAL DATA MULTIPLEXED DEMULTIPLEXED EXTERNAL ADDRE SS/DATA BUSES FIVE PROGRAMMABLE CHIP-SELECT SIGNALS HOLD-ACKNOWLEDGE ARBITRATION SUPPORT INTERRUPT 8-CHANNEL PERIPHERAL EVENT CONTROLLER SINGLE CYCLE INTERRUPT DRIVEN DATA TRANSFER 16-PRIORITY-LEVEL INTERRUPT SYSTEM WITH SOURCES, SAMPLING RATE DOWN 25ns TIMERS MULTI-FUNCTIONAL GENERA PURPOSE TIMER UNITS WITH TIMERS 16-CHANNEL CAPTURE COMPARE UNITS CONVERTER 16-CHANNEL 10-BIT 4.85µs CONVERSION TIME 40MHz CLOCK 4-CHANNEL UNIT SERIAL CHANNELS SYNCH RONOUS ASYNCHRONOUS SERIAL CHANNE HIGH-SPEED SYNCHR ONOUS CHANNEL
PQFP144 (Plastic Quad Flat Pack) ORDER CODE: ST10F269-Q3
2.0B INTERFACES OPERATING BUSSES 2x15 MESSAGE OBJECTS) FAIL-SAFE PROTECTION PROGRAMMABLE WATCHDOG TIMER OSCILLATOR WATCHDOG ON-CHIP BOOTSTRAP LOADER CLOCK GENERATION ON-CHIP DIRECT PRESCALE CLOCK INPUT REAL TIME CLOCK GENERAL PURPOSE LINES INDIVIDUALLY PROGRAMMABLE INPUT, OUTPUT SPECIA FUNCTION PROGRAMMABLE THRESHOLD (HYSTERES IDLE POWER DOWN MODES SINGLE VOLTAGE SUPPLY: ±10% (EMBEDDED REGULATOR CORE SUPPLY). TEMPERATURE RANGE: +125°C 144-PIN PQFP PACKAGE
256K Byte FlashMemory CPU-Core andMACUnit
Byte Internal Watchdog Oscillator andPLL XTAL1 3.3V XTAL2
10KByte XRAM
CAN1_RXD CAN1_TXD CAN2_RXD CAN2_TXD
CAN1 CAN2
Interrupt Controller
Voltage Regulator
Port Port Port
GPT1
usart
CAPCOM2
10-Bit
External Controller
CAPCOM1
GPT2
Port
Port
Port7 Port
Port6
Port
June 2002
This advance information product development undergoing evaluation. Details subject change without notice.
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ST10F269
TABLE CONTENTS 123455.1 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.5.1 5.5.2 5.5.3 5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 66.1 6.1.1 6.1.1.1 6.1.1.2 6.1.1.3 77.1 PAGE
INTRODUCTION DATA FUNCTIONAL DESCRIPTION MEMORY ORGANIZATION. INTERNAL FLASH MEMORY OVERVIEW OPERATIONAL OVERVIEW ARCHITECTURAL DESCRIPTION Read Mode Command Mode Ready/Busy Signal Flash Status Register Flash Protection Register Instructions Description Reset Processing Initial State. FLASH MEMORY CONFIGURATION. APPLICATION EXAMPLES Handling Flash Addresses Basic Flash Access Control Programming Examples BOOTSTRAP LOADER Entering Bootstrap Loader Memory Configuration After Reset Loading Startup Code Exiting Bootstrap Loader Mode Choosing Baud Rate CENTRAL PROCESSING UNIT (CPU) MULTIPLIER-ACCUMULATOR UNIT (MAC). Features Enhanced Addressing Capabilities. Multiply-Accumulate Unit. Program Control INSTRUCTION SUMMARY COPROCESSOR SPECIFIC INSTRUCTIONS. EXTERNAL CONTROLLER. PROGRAMMABLE CHIP SELECT TIMING CONTROL READY PROGRAMMABLE POLARITY.
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ST10F269
TABLE CONTENTS 88.1 10.1 10.2 12.1 12.2 12.2.1 12.2.2 12.2.3 12.2.4 12.3 12.3.1 12.4 12.4.1 12.5 12.5.1 12.6 12.6.1 12.7 12.7.1 12.8 12.8.1 12.8.2 12.9 12.9.1 12.10 12.10.1 12.11 12.11.1 PAGE
INTERRUPT SYSTEM EXTERNAL INTERRUPTS INTERRUPT REGISTERS VECTORS LOCATION LIST INTERRUPT CONTROL REGISTERS. EXCEPTION ERROR TRAPS LIST. CAPTURE/COMPARE (CAPCOM) UNITS. GENERAL PURPOSE TIMER UNIT
GPT1 GPT2 MODULE PARALLEL PORTS INTRODUCTION I/O'S SPECIAL FEATURES Open Drain Mode Input Threshold Control Output Driver Control Alternate Port Functions Alternate Functions PORT0 Alternate Functions PORT1 Alternate Functions Port Alternate Functions Port
PORT0 PORT1 PORT PORT PORT Alternate Functions Port PORT Alternate Functions Port Port Schmitt Trigger Analog Inputs.
PORT Alternate Functions Port PORT Alternate Functions Port Alternate Functions Port PORT
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ST10F269
TABLE CONTENTS 14.1 14.1.1 14.1.2 14.2 15.1 15.1.1 15.1.2 15.2 16.1 16.1.1 16.1.2 16.1.3 16.1.4 16.1.5 16.2 18.1 18.1.1 18.1.2 18.1.3 18.2 18.3 18.4 18.5 18.5.1 18.5.2 18.5.3 18.6 19.1 19.2 19.2.1 19.2.2 4/160
PAGE
CONVERTER SERIAL CHANNELS ASYNCHRONOUS SYNCHRONOUS SERIAL INTERFACE (ASCO). ASCO Asynchronous Mode ASCO Synchronous Mode HIGH SPEED SYNCHRONOUS SERIAL CHANNEL (SSC) MODULES MODULES MEMORY MAPPING
CAN1 CAN2 CONFIGURATIONS REAL TIME CLOCK
REGISTERS RTCCON: Control Register RTCPH RTCPL: PRESCALER Registers. RTCDH RTCDL: DIVIDER Counters RTCH RTCL: Programmable COUNTER Registers. RTCAH RTCAL: ALARM Registers
PROGRAMMING WATCHDOG TIMER SYSTEM RESET LONG HARDWARE RESET Asynchronous Reset Synchronous Reset (RSTIN pulse 1040TCL high level). Exit Long Hardware Reset
SHORT HARDWARE RESET SOFTWARE RESET WATCHDOG TIMER RESET RSTOUT, RSTIN, BIDIRECTIONAL RESET RSTOUT Bidirectional Reset RSTIN RESET CIRCUITRY POWER REDUCTION MODES IDLE MODE POWER DOWN MODE Protected Power Down Mode Interruptable Power Down Mode
ST10F269
TABLE CONTENTS 20.1 20.2 21.1 21.2 21.3 21.3.1 21.3.2 21.4 21.4.1 21.4.2 21.4.3 21.4.4 21.4.5 21.4.6 21.4.7 21.4.8 21.4.9 21.4.10 21.4.11 21.4.12 21.4.13 21.4.14 21.4.14.1 21.4.14.2 SPECIAL FUNCTION REGISTER OVERVIEW. PAGE
IDENTIFICATION REGISTERS SYSTEM CONFIGURATION REGISTERS ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS PARAMETER INTERPRETATION CHARACTERISTICS Converter Characteristics Conversion Timing Control CHARACTERISTICS Test Waveforms Definition Internal Timing Clock Generation Modes Prescaler Operation Direct Drive Oscillator Watchdog (OWD) Phase Locked Loop External Clock Drive XTAL1 Memory Cycle Variables Multiplexed Demultiplexed CLKOUT READY External Arbitration High-Speed Synchronous Serial Interface (SSC) Timing. Master Mode. Slave mode. PACKAGE MECHANICAL DATA
ORDERING INFORMATION
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ST10F269
INTRODUCTION ST10F269 derivative STMicroelectronics ST10 family 16-bit single-chip CMOS microcontrollers. combines high performance million instructions second) with high peripheral functionality enhanced I/O-capabilities. also provides on-chip high-speed single voltage Flash memory, on-chip high-speed RAM, clock generation PLL. ST10F269 processed 0.35 CMOS technology. core logic supplied with 3.3V chip voltage regulator. part supplied with single supply I/Os work device upward compatible with ST10F168 device, with following differences: Multiply/Accumulate unit available standard. This unit adds powerful functions ST10 architecture, maintains full compatibility existing code. Flash control interface based STMicroelectronics third generation stand-alone Flash memories, with embedded Erase/Program Controller. This completely Figure Logic Symbol
frees during programming erasing Flash. dedicated pins (DC1 DC2) PQFP-144 package used decoupling internally generated 3.3V core logic supply.Do connect these pins 5.0V external supply. Instead, these pins should connected decoupling capacitor (ceramic type, value nF). Converter characteristics different from previous ST10 derivatives ones. Refer Section 21.3.1 Converter Characteristics. parameters adapted 40MHz maximum frequency. characterization performed with 50pF output pins. Refer Section 21.3 Characteristics. order reduce EMC, rise/fall time sink/source capability drivers pads programmable. Refer toSection 12.2 Special Features. Real Time Clock functionnality added. external interrupt sources selected with EXISEL register. reset source identified dedicated status WDTCON register.
XTAL1 XTAL2 RSTIN RSTOUT VAREF VAGND READY WR/WRL Port 16-bit ST10F269
Port 16-bit Port 16-bit Port 16-bit Port 15-bit Port 8-bit Port 8-bit Port 8-bit Port 8-bit
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DATA
P6.0/CS0 P6.1/CS1 P6.2/CS2 P6.3/CS3 P6.4/CS4 P6.5/HOLD P6.6/HLDA P6.7/BREQ P8.0/CC16IO P8.1/CC17IO P8.2/CC18IO P8.3/CC19IO P8.4/CC20IO P8.5/CC21IO P8.6/CC22IO P8.7/CC23IO P7.0/POUT0 P7.1/POUT1 P7.2/POUT2 P7.3/POUT3 P7.4/CC28I0 P7.5/CC29I0 P7.6/CC30I0 P7.7/CC31I0 P5.0/AN0 P5.1/AN1 P5.2/AN2 P5.3/AN3 P5.4/AN4 P5.5/AN5 P5.6/AN6 P5.7/AN7 P5.8/AN8 P5.9/AN9
VAREF VAGND
RSTOUT RSTIN
P5.10/AN10/T6EUD P5.11/AN11/T5EUD P5.12/AN12/T6IN P5.13/AN13/T5IN P5.14/AN14/T4EUD P5.15/AN15/T2EUD
XTAL1 XTAL2
P2.0/CC0IO
Figure Configuration (top view)
P1H.7/A15/CC27IO P1H.6/A14/CC26IO P1H.5/A13/CC25IO P1H.4/A12/CC24IO P1H.3/A11 P1H.2/A10
P2.1/CC1IO P2.2/CC2IO P2.3/CC3IO P2.4/CC4IO P2.5/CC5IO P2.6/CC6IO P2.7/CC7IO
P1H.1/A9 P1H.0/A8
P1L.7/A7
P2.8/CC8IO/EX0IN
ST10F269-Q3
P2.9/CC9IO/EX1IN P2.10/CC10IOEX2IN P2.11/CC11IOEX3IN
P1L.6/A6
P1L.5/A5 P1L.4/A4
P1L.3/A3
P1L.2/A2 P1L.1/A1
P2.12/CC12IO/EX4IN P2.13/CC13IO/EX5IN P2.14/CC14IO/EX6IN P2.15/CC15IO/EX7IN/T7IN
P1L.0/A0
P0H.7/AD15
P0H.6/AD14
P0H.5/AD13 P0H.4/AD12
P3.0/T0IN P3.1/T6OUT P3.2/CAPIN P3.3/T3OUT
P3.4/T3EUD
P3.5/T4IN
P0H.3/AD11
P0H.2/AD10 P0H.1/AD9
P0H.0/AD8 P0L.7/AD7 P0L.6/AD6 P0L.5/AD5 P0L.4/AD4 P0L.3/AD3 P0L.2AD2 P0L.A/AD1 P0L.0/AD0 READY WR/WRL P4.7A23/CAN2_TxD P4.6A22/CAN1_TxD P4.5A21/CAN1_RxD P4.4A20/CAN2_RxD P4.3/A19 P4.2/A18 P4.1/A17 P4.0/A16 P3.15/CLKOUT P3.13/SCLK P3.12/BHE/WRH P3.11/RXD0 P3.10/TXD0 P3.9/MTSR P3.8/MRST P3.7/T2IN P3.6/T3IN
ST10F269
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ST10F269
Table Description
Symbol P6.0 P6.7 Type Function 8-bit bidirectional port, bit-wise programmable input output direction bit. Programming input forces corresponding output driver high impedance state. Port outputs configured push-pull open drain drivers. following Port pins have alternate functions: P6.0 P6.4 P6.5 P6.6 P6.7 HOLD HLDA BREQ Chip Select Output Chip Select Output External Master Hold Request Input Hold Acknowledge Output Request Output
P8.0 P8.7 9-16
8-bit bidirectional port, bit-wise programmable input output direction bit. Programming input forces corresponding output driver high impedance state. Port outputs configured push-pull open drain drivers. input threshold Port selectable (TTL special). following Port pins have alternate functions: P8.0 P8.7 CC16IO CC23IO CAPCOM2: CC16 Capture Input Compare Output CAPCOM2: CC23 Capture Input Compare Output
P7.0 P7.7 19-26
8-bit bidirectional port, bit-wise programmable input output direction bit. Programming input forces corresponding output driver high impedance state. Port outputs configured push-pull open drain drivers. input threshold Port selectable (TTL special). following Port pins have alternate functions: P7.0 P7.3 P7.4 P7.7 POUT0 POUT3 CC28IO CC31IO Channel Output Channel Output CAPCOM2: CC28 Capture Input Compare Output CAPCOM2: CC31 Capture Input Compare Output
P5.0 P5.9 P5.10 P5.15 27-36 39-44
16-bit input-only port with Schmitt-Trigger characteristics. pins Port analog input channels converter, where P5.x equals (Analog input channel they timer inputs: P5.10 P5.11 P5.12 P5.13 P5.14 P5.15 T6EUD T5EUD T6IN T5IN T4EUD T2EUD GPT2 Timer External Down Control Input GPT2 Timer External Down Control Input GPT2 Timer Count Input GPT2 Timer Count Input GPT1 Timer External Down Control Input GPT1 Timer External Down Control Input
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ST10F269
Symbol P2.0 P2.7 P2.8 P2.15
47-54 57-64
Type
Function 16-bit bidirectional port, bit-wise programmable input output direction bit. Programming input forces corresponding output driver high impedance state. Port outputs configured push-pull open drain drivers. input threshold Port selectable (TTL special). following Port pins have alternate functions: P2.0 P2.7 P2.8 CC0IO CC7IO CC8IO EX0IN P2.15 CC15IO EX7IN T7IN CAPCOM: Capture Input Compare Output CAPCOM: Capture Input Compare Output CAPCOM: Capture Input Compare Output Fast External Interrupt Input CAPCOM: CC15 Capture Input Compare Output Fast External Interrupt Input CAPCOM2 Timer Count Input
P3.0 P3.5 P3.6 P3.13, P3.15
65-70, 73-80,
15-bit (P3.14 missing) bidirectional port, bit-wise programmable input output direction bit. Programming input forces corresponding output driver high impedance state. Port outputs configured push-pull open drain drivers. input threshold Port selectable (TTL special). following Port pins have alternate functions: P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12 T0IN T6OUT CAPIN T3OUT T3EUD T4IN T3IN T2IN MRST MTSR TxD0 RxD0 CAPCOM Timer Count Input GPT2 Timer Toggle Latch Output GPT2 Register CAPREL Capture Input GPT1 Timer Toggle Latch Output GPT1 Timer External Down Control Input GPT1 Timer Input Count Gate Reload Capture GPT1 Timer Count Gate Input GPT1 Timer Input Count Gate Reload Capture Master-Receiver Slave-Transmitter Master-Transmitter Slave-Receiver ASC0 Clock Data Output (Asynchronous Synchronous) ASC0 Data Input (Asynchronous) (Synchronous) External Memory High Byte Enable Signal External Memory High Byte Write Strobe Master Clock Output Slave Clock Input System Clock Output (=CPU Clock)
P3.13 P3.15
SCLK CLKOUT
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ST10F269
Symbol P4.0 -P4.7
85-92
Type
Function Port 8-bit bidirectional port. bit-wise programmable input output direction bit. Programming input forces corresponding output driver high impedance state. input threshold selectable (TTL special). Port outputs configured push-pull open drain drivers. case external configuration, Port used output segment address lines: P4.0 P4.1 P4.2 P4.3 P4.4 CAN2_RxD P4.5 CAN1_RxD P4.6 CAN1_TxD P4.7 CAN2_TxD Segment Address Line Segment Address Line Segment Address Line Segment Address Line Segment Address Line CAN2 Receive Data Input Segment Address Line CAN1 Receive Data Input Segment Address Line CAN1 Transmit Data Output Most Significant Segment Address Line CAN2 Transmit Data Output
WR/WRL
External Memory Read Strobe. activated every external instruction data read access. External Memory Write Strobe. WR-mode this activated every external data write access. mode this activated Byte data write accesses 16-bit bus, every data write access 8-bit bus. WRCFG SYSCON register mode selection. Ready Input. active level programmable. When Ready function enabled, selected inactive level this pin, during external memory access, will force insertion waitstate cycles until returns selected active level. Address Latch Enable Output. case external addressing multiplexed mode, this signal latch command address lines. External Access Enable pin. level applied this during after Reset forces ST10F269 start program from external memory space. high level forces start internal memory space.
READY/ READY
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ST10F269
Symbol
Type
Function 8-bit bidirectional ports P0H, bit-wise programmable input output direction bit. Programming input forces corresponding output driver high impedance state. case external configuration, PORT0 serves address address data (AD) multiplexed modes data demultiplexed modes.
P0L.0 P0L.7, 100-107, 108, P0H.0 P0H.1 P0H.7 111-117
Demultiplexed modeData Path Width: P0L.0 P0L.7: P0H.0 P0H.7 8-bit 16-bit
Multiplexed modeData Path Width: P0L.0 P0L.7: P0H.0 P0H.7 P1L.0 P1L.7 P1H.0 P1H.7 118-125 128-135 8-bit 16-bit
AD15
8-bit bidirectional ports P1H, bit-wise programmable input output direction bit. Programming input forces corresponding output driver high impedance state. PORT1 used 16-bit address demultiplexed modes also after switching from demultiplexed mode multiplexed mode. following PORT1 pins have alternate functions: P1H.4 P1H.5 P1H.6 P1H.7 XTAL1 XTAL2 CC24IO CC25IO CC26IO CC27IO CAPCOM2: CC24 Capture Input CAPCOM2: CC25 Capture Input CAPCOM2: CC26 Capture Input CAPCOM2: CC27 Capture Input
XTAL1 XTAL2
Oscillator amplifier and/or external clock input. Oscillator amplifier circuit output.
clock device from external source, drive XTAL1 while leaving XTAL2 unconnected. Minimum maximum high rise fall times specified Characteristics must observed. RSTIN Reset Input with Schmitt-Trigger characteristics. level this specified duration while oscillator running resets ST10F269. internal pull-up resistor permits power-on reset using only capacitor connected VSS. bidirectional reset mode (enabled setting BDRSTEN SYSCON register), RSTIN line pulled duration internal reset sequence. Internal Reset Indication Output. This driven level during hardware, software watchdog timer reset. RSTOUT remains until EINIT (end initialization) instruction executed. Non-Maskable Interrupt Input. high transition this causes vector trap routine. PWDCFG SYSCON register, when PWRDN (power down) instruction executed, must order force ST10F269 into power down mode. high PWDCFG ='0', when PWRDN executed, part will continue normal mode. used, should pulled high externally. converter reference voltage. converter reference ground. Timing return from interruptible powerdown mode synchronous asynchronous reset selection.
RSTOUT
VAREF VAGND
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ST10F269
Symbol
82,93, 109, 126, 136, 18,45, 55,71, 83,94, 110, 127, 139,
Type
Function Digital Supply Voltage: during normal operation idle mode.
Digital Ground.
3.3V Decoupling pin: decoupling capacitor must connected between this nearest pin.
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ST10F269
FUNCTIONAL DESCRIPTION architecture ST10F269 combines advantages both RISC CISC processors advanced peripheral subsystem. Figure Block Diagram
256K Byte Flash Memory CPU-Core Unit Byte Internal
block diagram gives overview different on-chip components high bandwidth internal structure ST10F269.
Byte XRAM
Watchdog Oscillator
P4.5 CAN1_RXD P4.6 CAN1_TXD P4.4 CAN2_RXD P4.7 CAN2_TXD
CAN1 Interrupt Controller CAN2
XTAL1 3.3V
XTAL2
Voltage Regulator
Port Port Port
GPT1
usart
CAPCOM2
10-Bit
External Controller
CAPCOM1
GPT2
Port
Port
Port Port
Port
Port
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ST10F269
MEMORY ORGANIZATION memory space ST10F269 configured unified memory architecture. Code memory, data memory, registers ports organized within same linear address space Bytes. entire memory space accessed Byte wise Word wise. Particular portions on-chip memory have additionally been made directly addressable. Flash: 256K Bytes on-chip Flash memory. IRAM: Bytes on-chip internal (dual-port) provided storage data, system stack, general purpose register banks code. register bank Wordwide R15) Bytewide (RL0, RH0, RL7, RH7) general purpose registers. XRAM: Bytes on-chip extension (single port XRAM) provided storage data, user stack code. XRAM divided into areas, first Bytes named XRAM1 second Bytes named XRAM2, connected internal XBUS accessed like external memory 16-bit demultiplexed bus-mode without wait state read/write delay (50ns access 40MHz clock). Byte Word accesses allowed. XRAM1 address range 00'E000h 00'E7FFh XPEN (bit SYSCON register), XRAM1EN (bit XPERCON register) set. XRAM1EN XPEN cleared, then access address range 00'E000h 00'E7FFh will directed external memory interface, using BUSCONx register corresponding address matching ADDRSELx register XRAM2 address range 00'C000h 00'DFFFh XPEN (bit SYSCON register), XRAM2 (bit XPERCON register set). XRAM2EN XPEN cleared, then access address range 00'C000h 00'DFFFh will directed external memory interface, using BUSCONx register corresponding address matching ADDRSELx register. XRAM appears like external memory, cannot used system stack register banks. XRAM provided single storage therefore addressable. SFR/ESFR: 1024 Bytes Bytes) address space reserved special function register areas. SFRs Wordwide registers which used control monitor function different on-chip units. CAN1: Address range 00'EF00h 00'EFFFh reserved CAN1 Module access. CAN1 enabled setting XPEN SYSCON register setting CAN1EN XPERCON register. Accesses Module demultiplexed addresses 16-bit data (Byte accesses possible). wait states give access time 100ns 40MHz clock. tri-state wait states used. CAN2: Address range 00'EE00h 00'EEFFh reserved CAN2 Module access. CAN2 enabled setting XPEN SYSCON register setting CAN2EN XPERCON register. Accesses Module demultiplexed addresses 16-bit data (Byte accesses possible). wait states give access time 100ns 40MHz clock. tri-state wait states used. order meet needs designs where more memory required than provided chip, Bytes external and/or connected microcontroller. Note modules used, Port cannot programmed output segment address lines. Thus, only segment address lines used, reducing external memory space Bytes Byte line).
Visibility XBUS Peripherals order keep ST10F269 compatible with ST10C167 with ST10F167, XBUS peripherals selected visible accessible external address data bus. CAN1EN CAN2EN bits XPERCON register must set. these bits cleared before global enabling with XPEN-bit SYSCON register, corresponding address space, port pins interrupts occupied peripheral, thus peripheral visible available. Refer Chapter Special Function Register Overview.
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ST10F269
Figure ST10F269 On-chip Memory Mapping
Segment Segment Segment
05'0000
RAM, X-pheripherals mapped into address space.
00'FFFF
Block6 Bytes 04'0000 00'FE00 Byte
00'FDFF
Block5 Bytes 03'0000 00'F600 IRAM Byte
Block4 Bytes 02'0000
00'F1FF
ESFR Bytes Block3 Bytes Bank 00'F000
Segment
01'8000 Block2* Block1* Block0*
00'EFFF
CAN1 Bytes Bank 00'EF00
01'0000
00'EEFF
CAN2 Byte
00'C000
00'EE00
Segment
00'EC14
Real Time Clock 00'EC00 Block2 Bytes Block1 Bytes Bank Block0 Bytes 00'0000
00'6000 00'4000
00'E7FF
XRAM1 Byte
00'E000
00'DFFF
Internal Flash Memory XRAM2 Bytes 00'C000
Data Page Number
Absolut Memory Addres
Bank remapped from segment segment (Bank setting SYSCON -ROMS1 (before EINIT) Data Page Number Absolute Memory Address hexadecimal values.
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ST10F269
XPERCON (F024h 12h)
ESFR
Reset Value:
RTCEN
XRAM2EN
XRAM1EN
CAN2EN
CAN1EN
CAN1EN CAN1 Enable
`0': Accesses on-chip CAN1 XPeripheral functions disabled. P4.5 P4.6 pins used general purpose I/Os. Address range 00'EF00h-00'EFFFh only directed external memory CAN2EN also `0'. `1': on-chip CAN1 XPeripheral enabled accessed. CAN2EN CAN2 Enable `0': Accesses on-chip CAN2 XPeripheral functions disabled. P4.4 P4.7 pins used general purpose I/Os. Address range 00'EE00h-00'EEFFh only directed external memory CAN1EN also `0'. `1': on-chip CAN2 XPeripheral enabled accessed. XRAM1EN XRAM1 Enable `0': Accesses external memory within space 00'E000h 00'E7FFh. Bytes internal XRAM1 disabled. '1': Accesses internal Bytes XRAM1. XRAM2EN XRAM2 Enable `0': Accesses external memory within space 00'C000h 00'DFFFh. Bytes internal XRAM2 disabled. '1': Accesses internal Bytes XRAM2. RTCEN Enable '0': Accesses on-chip Real Time Clock disabled, external access performed. Address range 00'EC00h-00'ECFFh only directed external memory CAN1EN CAN2EN also '1': on-chip Real Time Clock enabled accessed.
Note: When both disabled XPERCON setting, then access address range 00'EE00h 00'EFFFh will directed external memory interface, using BUSCONx register corresponding address matching ADDRSELx register. P4.4 P4.7 used General Purpose when CAN2 disabled, P4.5 P4.6 used General Purpose when CAN1 disabled. default XPER selection after Reset identical XBUS configuration ST10C167: XCAN1 enabled, XCAN2 disabled, XRAM1 Byte compatible XRAM) enabled, XRAM2 (new Byte XRAM) disabled.
Register XPERCON cannot changed after global enabling XPeripherals, i.e. after setting XPEN SYSCON register. EMUlation mode, XPERipherals enabled (XPERCON set). access external memory and/or XBus controlled bondout chip. When Real Time Clock disabled (RTCEN clock oscillator switch-off ST10 enters power-down mode. Otherwise, when Real Time Clock enabled, RTCOFF RTCCON register allows choose power-down mode clock oscillator (See Chapter Real Time Clock).
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ST10F269
INTERNAL FLASH MEMORY Overview 256K Byte on-chip Flash memory possibilities Flash mapping into address space Flash memory used code data storage 32-bit, zero waitstate read access (50ns cycle time fCPU 40MHz) Erase-Program Controller (EPC) similar M29F400B STM's stand-alone Flash memory Word-by-Word Programmable typical) Data polling Toggle Protocol Status Ready/Busy signal connected XP2INT interrupt line Internal Power-On detection circuit Memory Erase blocks Byte, Byte, Byte, three Byte blocks Each block (1.5 second typical) erased separately Access data internal Flash only performed with inner protected program Erase Suspend Resume Modes Read Program another Block during erase suspend Single Voltage operation need dedicated supply Power Consumption: 45mA max. Read current 60mA max. Program Erase current Automatic Stand-by-mode maximum) 100,000 Erase-Program Cycles block, years data retention time
Operating temperature: +125
Operational Overview Read Mode standard mode (the normal operating mode) Flash appears like on-chip with same timing functionality. Flash module offers fast access time, allowing zero waitstate access with frequency 40MHz. Instruction fetches data operand reads performed with addressing modes ST10F269 instruction set. order optimize programming time internal Flash, blocks Bytes, Bytes, Bytes, Bytes used. size blocks does apply whole memory space, details Table
Chip erase (8.5 second typical) Each block separately protected against programming erasing Each protected block temporary unprotected When enabled, read protection prevents access data Flash memory using program running Flash memory space.
Table 256K Byte Flash Memory Block Organisation
Block Addresses (Segment 00'0000h 00'3FFFh 00'4000h 00'5FFFh 00'6000h 00'7FFFh 01'8000h 01'FFFFh 02'0000h 02'FFFFh 03'0000h 03'FFFFh 04'0000h 04'FFFFh Addresses (Segment 01'0000h 01'3FFFh 01'4000h 01'5FFFh 01'6000h 01'7FFFh 01'8000h 01'FFFFh 02'0000h 02'FFFFh 03'0000h 03'FFFFh 04'0000h 04'FFFFh Size (byte) 17/160
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Instructions Commands operations besides normal read operations initiated controlled command sequences written Flash Command Interface (CI). Command Interface (CI) interprets words written Flash memory enables following operations: Read memory array Program Word Block Erase Chip Erase Erase Suspend Erase Resume Block Protection Block Temporary Unprotection Code Protection Commands composed several write cycles specific addresses Flash memory. different write cycles such command sequences offer fail-safe feature protect against inadvertent write. command only starts when Command Interface decoded last write cycle operation. Until that last write performed, Flash memory remains Read Mode Notes: possible perform write operations Flash while fetching code from Flash, Flash commands must written instructions executed from internal external memory. Command write cycles need consecutively received, pauses allowed, save Block Erase command. During this operation Erase Confirm commands must sent complete block erase operation before time-out period expires (typically 96µs). Command sequencing must followed exactly. invalid combination commands will reset Command Interface Read Mode. Status Register This register used flag status memory result operation. This register accessed read cycles during Erase-Program Controller (EPC) operation. Erase Operation This Flash memory features block erase architecture with chip erase capability too. Erase accomplished executing cycle erase command sequence. Additional command write cycles then performed erase more than
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block parallel. When time-out period elaps (96µs) after last cycle, Erase-Program Controller (EPC) automatically starts times erase pulse executes erase operation. There need program block erased with `0000h' before erase operation. Termination operation indicated Flash status register. After erase operation, Flash memory locations read 'FFFFh' value. Erase Suspend block erase operation typically executed within second Byte block. Erasure memory block suspended, order read data from another block program data another block, then resumed. In-System Programming In-system programming fully supported. special programming voltage required. Because automatic execution erase programming algorithms, write operations reduced transferring commands data Flash reading status. code that programs erases Flash memory locations (that writes data Flash) must executed from memory outside on-chip Flash memory itself (on-chip external memory). boot mechanism provided support in-system programming. works using serial link USART interface compatible other programming host. Read/Write Protection Flash module supports read write protection very comfortable advanced protection functionality. Read Protection installed, whole Flash memory protected against "external" read access; read accesses only possible with instructions fetched directly from program Flash memory. update Flash memory temporary disable Flash Read Protection supported. device also features block write protection. Software locking selectable memory blocks provided protect code data. This feature will disable both program erase operations selected block(s) memory. Block Protection accomplished block specific lock-bit which programmed executing four cycle command sequence. locked state blocks indicated specific flags according block status registers. block only temporarily unlocked update (write) operations.
ST10F269
With possibilities write protection whole memory block specific flexible installation write protection supported protect Flash memory parts from unauthorized programming erase accesses provide virus-proof protection system code blocks. write protection also enabled during boot operation. Power Supply, Reset Flash module uses single power supply both read write functions. Internally generated regulated voltages provided program erase operations from supply. Once program erase cycle been completed, device resets standard read mode. power-on, Flash memory setup phase some microseconds (dependent power supply ramp-up). During this phase, Flash read. Thus, high (execution will start from Flash memory), will remains reset state until Flash accessed. Architectural Description Flash module distinguishes basic operating modes, standard read mode command mode. initial state after power-on after reset standard read mode. 5.3.1 Read Mode Flash module enters standard operating mode, read mode: After Reset command After every completed erase operation After every completed programming operation After every other completed command execution microseconds after CPU-reset started After incorrect address data values command sequences writing them improper sequence After incorrect write access read protected Flash memory read mode remains active until last command command sequence decoded which starts directly Flash array operation, such erase several blocks program word into Flash array protect temporary unprotect block. standard read mode read accesses directly controlled Flash memory array, delivering 32-bit double Word from addressed position. Read accesses always aligned double Word boundaries. Thus, both order address used Flash array read accesses. high order address A17/A16 define physical Byte segment being accessed within Flash array. 5.3.2 Command Mode Every operation besides standard read operations initiated commands written Flash command register. addresses used command cycles define conjunction with actual state specific step within command sequences. With last command command sequence, Erase-Program Controller (EPC) starts execution command. status indicated during command execution Status Register, Ready/Busy signal. 5.3.3 Ready/Busy Signal Ready/Busy (R/B) signal connected XPER2 interrupt node (XP2IC). WhenR/B high, Flash busy with Program Erase operation will accept additional program erase instruction. When Low, Flash ready Read/Write Erase operation. will also when memory Erase Suspend mode. This signal polled reading XP2IC register, used trigger interrupt when Flash goes from Busy Ready. 5.3.4 Flash Status Register Flash Status register used flag status Flash memory result operation. This register accessed Read cycles during program-Erase Controller operations. program erase operation controlled data polling FSB.7 Status Register, detection Toggle FSB.6 FSB.2, Error FSB.5 Erase Timeout FSB.3 bit. read attempt Flash during operation will automatically output these five bits. sets FSB.2, FSB.3, FSB.5, FSB.6 FSB.7. Other bits reserved future should masked.
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Flash Status (see note address)
FSB.3 FSB.2
FSB.7 FSB.6 FSB.5
FSB.7
Flash Status Data Polling Programming Operation: this outputs complement word being programmed, after completion, will output word programmed. Erasing Operation: outputs during erasing, after erasing completion. block selected erasure (are) protected, FSB.7 will about then return previous addressed memory data value. FSB.7 will also flag Erase Suspend Mode switching from start Erase Suspend. During Program operation Erase Suspend Mode, FSB.7 will have same behaviour normal Program execution outside Suspend mode. Flash Status Toggle Programming Erasing Operations: successive read operations Flash Status register will deliver complementary values. FSB.6 will toggle each time Flash Status register read. Program operation completed when successive reads yield same value. next read will output last programmed, after Erase operation FSB.6 will to`1' read operation attempted Erase Suspended block. addition, Erase Suspend/Resume command will cause FSB.6 toggle. Flash Status Error This when there failure Program, block chip erase operations.This will also user tries program Flash location that currently programmed with `0'. error resets after Read/Reset instruction. case success, Error will during Program Erase then will output last programmed after erasing Flash Status Erase Time-out This cleared when last Block Erase command been entered Command Interface awaiting Erase start. When time-out period finished, after FSB.3 returns back `1'. Flash Status Toggle This toggle bit, together with FSB.6, used determine chip status during Erase Mode Erase Suspend Mode. used also identify block being Erased Suspended. Read operation will cause FSB.2 Toggle during Erase Mode. Flash Erase Suspend Mode, Read operation from Erase suspended block Program operation into Erase suspended block will cause FSB.2 toggle. When Flash Program Mode during Erase Suspend, FSB.2 will read address used address word being programmed. After Erase completion with Error status, FSB.2 will toggle when reading faulty sector.
FSB.6
FSB.5
FSB.3
FSB.2
Note: Address Flash Status Register address word being programmed when Programming operation progress, address within block being erased when Erasing operation progress.
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5.3.5 Flash Protection Register Flash Protection register non-volatile register that contains protection status. This register read using Read Protection Status (RP) command, programmed using dedicated Protection command. Flash Protection Register (PR)
Block Protection 0.6) `0': Block Protection enabled block Programming erasing block possible, unless Block Temporary Unprotection command issued. Block Protection disabled block default, programmed permanently using Protection command then cannot again. therefore possible temporally disable Block Protection using Block Temporary Unprotection instruction.
Code Protection `0': Flash Code Protection enabled. Read accesses Flash execution performed Flash itself allowed, returned value will 009Bh, whatever content Flash Flash Code Protection disabled: read accesses Flash from external internal allowed default, programmed permanently using Protection command then cannot again. therefore possible temporally disable Code Protection using Code Temporary Unprotection instruction.
5.3.6 Instructions Description Twelve instructions dedicated Flash memory accesses defined follow: Read/Reset (RD). Read/Reset instruction consist write cycle with data XXF0h optionally preceded enable coded cycles (data xxA8h address 1554h data xx54h address 2AA8h). successive read cycle following Read/Reset instruction will read memory array. Wait cycle 10µs necessary after Read/Reset command memory program Erase mode. Program Word (PW). This instruction uses four write cycles. After enable coded cycles, Program Word command xxA0h written address 1554h. following write cycle will latch address data word programmed. Memory programming done only writing instead 1's, otherwise error occurs. During programming, Flash Status checked reading Flash Status FSB.2, FSB.5, FSB.6 FSB.7 which show status EPC. FSB.2, FSB.6 FSB.7 determine programming going
completed, FSB.5 allows check made possible error. Block Erase (BE). This instruction uses minimum command cycles. erase enable command xx80h written address 1554h after two-cycle enable sequence. erase confirm code xx30h must written address related block erased preceded execution second enable sequence. Additional erase confirm codes must given erase more than block parallel. Additional erase confirm commands must written within defined time-out period. input Block Erase command will restart time-out period. When this time-out period elapsed, erase starts. status internal timer monitored through level FSB.3, FSB.3 `0', Block Erase command been given timeout running; FSB.3 `1', timeout expired erasing block(s).
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second command given erase confirm coded cycles wrong, instruction aborts, device reset Read Mode. necessary program block with 0000h will this automatically before erasing FFFFh. Read operations after started, output Flash Status Register. During execution erase EPC, device accepts only Erase Suspend Read/Reset instructions. Data Polling FSB.7 returns while erasure progress, when completed. Toggle FSB.2 FSB.6 toggle during erase operation. They stop when erase completed. After completion, Error FSB.5 returns there been erase failure because erasure completed even after maximum number erase cycles have been executed EPC, this case, will necessary input Read/Reset Command Interface order reset EPC. Chip Erase (CE). This instruction uses write cycles. Erase Enable command xx80h, must written address 1554h after CI-Enable cycles. Chip Erase command xx10h must given sixth cycle after second CI-Enable sequence. error command sequence will reset Read mode. necessary program block with 0000h will this automatically before erasing FFFFh. Read operations after started output Flash Status Register. During execution erase EPC, Data Polling FSB.7 returns while erasure progress, when completed. FSB.2 FSB.6 toggle during erase operation. They stop when erase finished. FSB.5 error returns case failure erase operation. error flag after maximum number erase cycles have been executed EPC. this case, will necessary input Read/Reset Command Interface order reset EPC. Erase Suspend (ES). This instruction used suspend Block Erase operation giving command xxB0h without specific address. CI-Enable cycles required. Erase Suspend operation allows reading data from another block and/or programming another block while erase progress. this command given during time-out period, will terminate time-out period addition erase Suspend. Toggle FSB.6, when monitored address that belongs block being erased, stops toggling when Erase Suspend Command effective, happens between 15µs after Erase Suspend Command been
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written. Flash will then normal Read Mode, read from blocks being erased valid, while read from block being erased will output FSB.2 toggling. During Suspend phase only instructions valid Erase Resume Program Word. Read Reset instruction during Erase suspend will definitely abort Erase result invalid data block being erased. Erase Resume (ER). This instruction given when memory Erase Suspend State. Erase resumed writing command xx30h address without Cl-enable sequence. Program during Erase Suspend. Program Word instruction during Erase Suspend allowed only blocks that Erase-suspended. This instruction same than Program Word instruction. Protection (SP). This instruction used enable both Block Protection protect each block independently from accidental Erasing-Programming Operation) Code Protection avoid code dump). Protection Command must given after special CI-Protection Enable cycles (see instruction table). following Write cycle, will program Protection Register. protect block data must `0'. protect code, data must `0'. Enabling Block Code Protection ispermanent cleared only STM. Block Temporary Unprotection Code Temporary Unprotection instructions available allow customer update code. Notes: value programmed protection register will only become active after reset. that already protection register must confirmed also data latched during cycle protection command, otherwise error occur. Read Protection Status (RP).This instruction used read Block Protection status Code Protection status. read protection register (see Table CI-Protection Enable cycles must executed followed command xx90h address x2A54h. following Read Cycles word address will output Block Protection Status. Read/ Reset command xxF0h must written reset protection interface. Note: After modification protection register (using Protection command), Read Protection Status will return value only after reset.
ST10F269
Block Temporary Unprotection (BTU). This Instruction used temporary unprotect blocks from Program Erase protection. Unprotection disabled after Reset cycle. Block Temporary Unprotection command xxC1h must given enable Block Temporary Unprotection. Command must preceded CI-Protection Enable cycles followed Read/Reset command xxF0h. Code Protection (SCP). This kind protection allows customer protect proprietary code written Flash. installed active, Flash Code Protection prevents data operand accesses program branches into on-chip Flash area from location outside Flash memory itself. Data operand accesses branches Flash locations only exclusively allowed instructions executed from Flash memory itself. Every read jump Flash performed from another memory (like internal RAM, external memory) while Code Protection enabled, will give opcode 009Bh related TRAP illegal instruction. CI-Protection Enable cycles must sent Code Protection. writing data 7FFFh word address, Code Protected status stored Flash Protection Register (PR). Protection permanent cannot cleared user. possible temporarily disable Code Protection using Code Temporary Unprotection instruction. Note: Bits that already protection register must confirmed also data latched during cycle protection command, otherwise error occur. Code Temporary Unprotection (CTU). This instruction must used temporary disable Code Protection. This instruction effective only executed from Flash memory space. restore protection status, without using reset, necessary Code Temporary Protection instruction. System reset will reset also Code Temporary Unprotected status. Code Temporary Unprotection command consists following write cycle: MEM, This instruction MUST executed from Flashmemory space Where absolute address inside memory space, register loaded with data 0FFFFh. Code Temporary Protection (CTP).This instruction allows restore Code Protection. This operation effective only executed from Flash memory necessary restore protection status after Code Temporary Unprotection instruction. Code Temporary Protection command consists following write cycle: MEM, This instruction MUST executed from Flashmemory space Where absolute address inside memory space, register loaded with data 0FFFBh. Note that Code Temporary Unprotection instruction must used when necessary modify Flash with protected code (SCP), since write/erase routines must executed from memory external Flash space. Usually, write/erase routines, executed RAM, ends with return Flash space where instruction restore protection.
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Table InstructionInstruction Cycle Addr.1 Data Read/Reset Addr.1 Data Program Word Addr.1 Data Addr.1 Data Chip Erase Addr.
Cycle xxF0h x1554h xxA8h x1554h xxA8h x1554h xxA8h x1554h xxA8h xxB0h xx30h x2A54h
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Read/Reset
Read Memory Array until write cycle initiated x2AA8h xx54h x2AA8h xx54h x2AA8h xx54h x2AA8h xx54h xxxxxh xxF0h x1554h xxA0h x1554h xx80h x1554h xx80h Read Memory Array until write cycle initiated x1554h xxA8h x1554h xxA8h Read Data Polling Toggle until Program completes. x2AA8h xx54h x2AA8h xx54h xx30h x1554h xx10h Note xx30h
Block Erase
Data Erase Suspend Addr.1 Data Erase Resume Block/Code Protection Data Read Protection Status Addr.1 Data Block Temporary Unprotection Code Temporary Unprotection Code Temporary Protection Addr.1 Data Addr.1 Data Addr.1 Data Addr.1 Data Addr.1
Read until Toggle stops, then read program data needed from block(s) being erased then Resume Erase. Read Data Polling Toggle until Erase completes Erase supended another time. x15A8h x2A54h word address word address Read xxF0h Read Protection Register until write cycle initiated.
xxA8h x2A54h
xx54h x15A8h
xxC0h x2A54h
xxA8h x2A54h xxA8h FFFFh FFFBh
xx54h x15A8h xx54h
xx90h x2A54h xxC1h
Write cycles must executed from Flash.
Write cycles must executed from Flash.
Notes Address A14, above don't care coded address inputs. Don't Care. Write Address: address memory location programmed. Write Data: 16-bit data programmed Optional, additional blocks addresses must entered within time-out delay after last write entry, timeout status verified through FSB.3 value. When full command entered, read Data Polling Toggle until Erase completed suspende Read Data Polling Toggle until Erase completes. Write protection register. protect code, must `0'. protect block (N=0,1,.), `0'. that already protection register must also WPR, else writing error will occurs possible write already programmed `0'). address inside Flash memory space. Absolute addressing mode must used (MOV MEM, Rn), instruction must executed from Flash memory space. word address 4n-2 where 0002h, 0006h.
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Generally, command sequences cannot written Flash instructions fetched from Flash itself. Thus, Flash commands must written instructions, executed from internal external memory. Command cycles interface need consecutively received (pauses allowed). interface delivers dummy read data used cycles within command sequences. addresses command cycles shall defined only with Register-indirect addressing mode according move instructions. Direct addressing allowed command sequences. Address segment data page pointer taken into account command address value. 5.3.7 Reset Processing Initial State Flash module distinguishes kinds reset types lengthening reset: reported external devices bidirectional enabled case external start after reset. Flash Memory Configuration default memory configuration ST10F269 Memory determined state reset. This value stored Internal Enable (named ROMEN) SYSCON register. When ROMEN internal Flash disabled external used startup control. Flash memory later enabled setting ROMEN SYSCON code performing this setting must from segment external replaced segment Flash memory, otherwise unexpected behaviour occur. example, external code located first Bytes segment first Bytes Flash must then enabled segment This done setting ROMS1 SYSCON before simultaneously with setting ROMEN bit. This must done externally supplied program before execution EINIT instruction. program execution starts from external memory, access Flash memory mapped segment later required, then code that performs setting ROMEN must executed either segment above address 00'8000h, from internal RAM. ROMS1 only affects mapping first Bytes Flash memory. other parts Flash memory (addresses 01'8000h 04'FFFFh) remain unaffected. SGTDIS Segmentation Disable Enable must also allow full 256K Bytes on-chip memory addition external boot memory. correct procedure changing segmentation registers must also observed prevent unwanted trap condition: Instructions that configure internal memory must only executed from external memory from internal RAM. Absolute Inter-Segment Jump (JMPS) instruction must executed after Flash enabling, next instruction, even this next instruction located consecutive address. Whenever internal Memory disabled, enabled remapped, DPPs must explicitly (re)loaded enable correct data accesses internal memory and/or external memory. Application Examples 5.5.1 Handling Flash Addresses command, Block, Data register addresses Flash have located within active Flash memory space. active space that address range which physical Flash addresses mapped defined user. When using data page pointer (DPP) block addresses make sure that address block address reflected both LSBs selected DPPS. Note: Command Instructions, address A14, A15, don't care. This simplify application software, because minimize registers when using Command Command Interface. Direct addressing allowed Command sequence operations Flash. Only Register-indirect addressing used command, block write-data accesses.
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5.5.2 Basic Flash Access Control When accessing Flash command write addresses have located within active Flash memory space. active Flash memory space that logical address range which covered Flash after mapping. When using data page pointer (DPP) addressing Flash, make sure that address command addresses reflected both LSBs selected data page pointer (A15 DPPx.1 DPPx.0). case command write addresses, address A14, above don't care. Thus, command writes performed only using register. This allow have more simple compact application software. Another advantageous possibility extended segment instruction addressing. Note: direct addressing mode allowed write access Flash address/command register. aware that compiler this kind addressing. write accesses Flash module always theindirect addressing mode selected. following basic instruction sequences show examples different addressing possibilities. Principle example address generation Flash commands registers: When using data page pointer (DPP0 this example) DPP0,#08h ;adjust data page pointers according ;addresses: DPP0 used this example, thus ;ADDRESS must have `0'. ;ADDRESS could dedicated command sequence ;address 2AA8h, 1554h Flash write ;address ;DATA could dedicated command sequence data ;(xxA0h,xx80h data programmed ;indirect addressing
Rwm,#ADDRESS
Rwn,#DATA [Rwm],Rwn
When using extended segment instruction: Rwm,#ADDRESS ;ADDRESS could dedicated command sequence ;address (2AA8h, 1554h Flash write ;address ;DATA could dedicated command sequence data ;(xxA0h,xx80h data programmed ;the value SEGMENT represent segment ;number could (depending sector mapping) 256KByte Flash. ;the value determines 8-bit segment ;valid corresponding data access ;long indirect address following(s) ;instruction(s). LENGTH define number ;the effected instruction(s) value ;between ;indirect addressing with segment number from ;EXTS
Rwo,#DATA Rwn,#SEGMENT
EXTS
Rwn,#LENGTH
[Rwm],Rwo
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5.5.3 Programming Examples Most microcontroller programs written language where data page pointers automatically compiler. because compiler allowed direct addressing mode Flash write addresses, necessary program organisational Flash accesses (command sequences) with assembler in-line routines which indirect addressing. Example Performing command Read/Reset assume that initialization phase lowest Bytes Flash memory (sector have been mapped segment According usual ST10 data addressing with data page pointers, address 16-bit command write address select data page pointer (DPP) which contains upper 10-bit building 24-bit physical data address. Address A13.A0 represent address offset. A14.A17 "don't care" when written Flash command Command Interface (CI), choose most conveniant DPPx register address handling. following examples making usage DPP0. just have make sure, that DPP0 points active Flash memory space. independent mapping sector choose allDPPs which used Flash address handling, point segment this reason load DPP0 with value 0000 l000b). #01554h ;load auxilary register with command address ;(used command cycle #02AA8h ;load auxilary register with command address ;(used command cycle SCXT DPPO, #08h ;push data page pointer load point ;segment #0A8h ;load register with enable command [R5], ;command cycle #054h ;load register with enable command [R6], ;command cycle #0F0h ;load register with Read/Reset command [R5], ;command cycle Address don't care DPP0 ;restore DPP0 value example above 16-bit registers used auxilary registers indirect addressing. Example Performing Program Word command assume that initialization phase lowest Bytes Flash memory (sector have been mapped segment 1.The data written loaded register R13, address programmed loaded register R11/R12 (segment number R11, segment offset R12). #01554h ;load auxilary register with command address ;(used command cycle #02AA8h ;load auxilary register with command address ;(used command cycle SXCT DPPO, #08h ;push data page pointer load point ;segment #0A8h ;load register with enable command [R5], ;command cycle #054h ;load register with enable command [R6], ;command cycle #0A0h ;load register with Program Word command [R5], ;command cycle
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DPP0 ;restore DPP0: following addres sing Flash ;will EXTended instructions ;R11 contains segment programmed ;R12 contains segment offset address ;programmed ;R13 contains data programmed EXTS R11, [R12], ;use EXTended addressing next instruction ;command cycle starts execution ;Programming Command ;use EXTended addressing next instruction ;read Flash Status register (FSB) ;save register ;Check FSB.7 Data.7 (i.e. R7.7 R13.7) R7.7, Prog_OK ;Check FSB.5 (Programmi Error) R6.5, Data_Polling ;Programming Error: verify Flash programmed ;data EXTS R11, [R12] R7.7, Prog_OK ;Programming failed: Flash remains Write ;Operation. back normal Read operations, Read/Reset ;command ;must performed Prog_Error: EXTS #0F0h R11, [R12], ;load register with Read/Reset command ;use EXTended addressing next instruction ;address don't care Read/Reset command ;here place specific Error handling code ;use EXTended addressing next instruction ;read Flash Status register (FSB) ;Check FSB.7 Data.7
Data_Polling: EXTS R11, [R12]
;When programming operation finished succesfully, ;Flash back automatically normal Read Mode
Prog_OK:
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Example Performing Block Erase command assume that initialization phase lowest Bytes Flash memory (sector have been mapped segment 1.The registers R11/R12 contain address related block erased (segment number R11, segment offset R12, example 01h, R12= 4000h will erase block first byte block). #01554h ;load auxilary register with command address ;(used command cycle #02AA8h ;load auxilary register with command address ;(used command cycle SXCT DPPO, #08h ;push data page pointer load point ;segment #0A8h ;load register with enable command [R5], ;command cycle #054h ;load register with enable command [R6], ;command cycle #080h ;load register with Block Erase command [R5], ;command cycle #0A8h ;load register with enable command [R5], ;command cycle #054h ;load register with enable command [R6], ;command cycle DPP0 ;restore DPP0: following addres sing Flash ;will EXTended instructions ;R11 contains segment block erased ;R12 contains segment offset address ;block erased #030h ;load register with erase confirm code EXTS R11, ;use EXTended addressing next instruction [R12], ;command cycle starts execution ;Erasing Command Erase_Polling: EXTS R11, ;use EXTended addressing next instruction [R12] ;read Flash Status register (FSB) ;Check FSB.7 (i.e. R7.7 `1') R7.7, Erase_OK ;Check FSB.5 (Erasing Error) R7.5, Erase_Polling ;Programming failed: Flash remains Write ;Operation. back normal Read operations, Read/Reset ;command ;must performed Erase_Error: #0F0h EXTS R11, [R12], ;load register with Read/Reset command ;use EXTended addressing next instruction ;address don't care Read/Reset command ;here place specific Error handling code
;When erasing operation finished succesfully, ;Flash back automatically normal Read Mode
Erase_OK:
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Bootstrap Loader built-in bootstrap loader (BSL) ST10F269 provides mechanism load startup program through serial interface after reset. this case, external memory internal Flash memory required initialization code starting location 00'0000h (see Figure bootstrap loader moves code/data into internal RAM, also transfer data serial interface into external using second level loader routine. Flash Memory (internal external) necessary, used provide lookup tables "core-code" like general purpose subroutines operations, number crunching, system initialization, etc. bootstrap loader used load complete application software into ROMless systems, load temporary software into complete systems testing calibration, load programming routine Flash devices. mechanism used standard system startup well special occasions like system maintenance (firmer update) end-of-line programming testing. Figure Bootstrap Loader Sequence RSTIN 5.6.1 Entering Bootstrap Loader ST10F269 enters mode when P0L.4 sampled hardware reset. this case built-in bootstrap loader activated independent selected mode. bootstrap loader code stored special Boot-ROM. part standard mask Memory Flash Memory area required this. After entering mode respective initialization ST10F269 scans RXD0 line receive zero Byte, start bit, eight data bits stop bit. From duration this zero Byte calculates corresponding Baud rate factor with respect current clock, initializes serial interface ASC0 accordingly switches TxD0 output. Using this Baud rate, identification Byte returned host that provides loaded data. This identification Byte identifies device booted. identification byte ST10F269.
P0L.4
RxD0
TxD0
CSP:IP
initialization time Zero Byte start bit, eight data bits, stop bit), sent host. Identification Byte (D5h), sent ST10F269. Bytes code data, sent host. Caution: TxD0 only driven certain time after reception zero Byte. Internal Boot ROM.
Internal Boot Memory (BSL) routine
Byte user software
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When ST10F269 entered mode, following configuration automatically (values that deviate from normal reset values, aremarked):
Watchdog Timer: Context Pointer Stack Pointer Register S0CON: Register S0BG:
Disabled
FA00h FA40h
Register SYSCON: Register STKUN: Register STKOV: Register BUSCON0: P3.10 TXD0:
0E00h FA40h FA0Ch 0<->C acc. startup configuration
8011h
Acc. `00' Byte
DP3.10:
this case, watchdog timer disabled, bootstrap loading sequence time limited. TXD0 configured output, ST10F269 return identification Byte. Even internal Flash enabled, code executed hardware that activates during reset simple pull-down resistor P0L.4 systems that this feature upon every hardware reset. switchable solution (via jumper external signal) used systems that only temporarily bootstrap loader (see Figure After sending identification Byte ASC0 receiver enabled ready receive initial Bytes from host. half duplex connection therefore sufficient feed BSL. Figure Hardware Provisions Activate
5.6.2 Memory Configuration After Reset configuration (and accessibility) ST10F269's memory areas after reset Bootstrap-Loader mode differs from standard case. evaluated when mode selected, accesses internal Flash area partly redirected, while ST10F269 mode (see Figure code fetches made from special Boot-ROM, while data accesses read from internal user Flash. Data accesses will return undefined values ROMless devices. code Boot-ROM invariant feature ST10F269. User software should execute code from internal Flash area while mode still active, these fetches will redirected Boot-ROM. Boot-ROM will also "move" segment when internal Flash area mapped segment (see Figure
External Signal
POL.4
POL.4
Normal Boot RPOL.4
POL.4
Circuit Circuit
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Figure Memory Configuration after Reset ByteSegment external disabled Access Segment external enabled Bytes Access Bytes Access: Segment depends reset config Port0
IRAM Test Flash mode active Code fetch from internal Flash area Data fetch from internal Flash area
IRAM
IRAM
internal Flash Flash enabled User (P0L.4='0') High
Test Flash
internal Flash Flash enabled User (P0L.4='0')
User Flash
depends reset config Port0
(P0L.4='1') Access application User Flash access User Flash acces
Test-Flash access User Flash acces
Test-Flash access User Flash acces
5.6.3 Loading Startup Code After sending identification Byte enters loop receive Bytes ASC0. These Byte stored sequentially into locations 00'FA40h through 00'FA5Fh internal RAM. instructions placed into area. execute loaded code then jumps location 00'FA40h, which first loaded instruction. bootstrap loading sequence terminated, ST10F269 remains mode, however. Most probably initially loaded routine will load additional code data, average application likely require substantially more than instructions. This second receive loop directly pre-initialized interface ASC0 receive data store arbitrary user-defined locations. This second level loaded code final application code. also another, more sophisticated, loader routine that adds transmission protocol enhance integrity loaded code data. also contain code sequence change system configuration enable interface store received data into external memory.
This process through several iterations directly execute final application. cases ST10F269 will still mode, that means with watchdog timer disabled limited access internal Flash area. code fetches from internal Flash area (00'0000h.00'7FFFh 01'0000h.01'7FFFh, mapped segment redirected special Boot-ROM. Data fetches access will access internal Boot-ROM ST10F269, available, will return undefined data ROMless devices. 5.6.4 Exiting Bootstrap Loader Mode order execute program normal mode, mode must terminated first. ST10F269 exits mode upon software reset (ignores level P0L.4) hardware reset (P0L.4 must high). After reset ST10F269 will start executing from location 00'0000h internal Flash external memory, programmed
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5.6.5 Choosing Baud Rate calculation serial Baud rate ASC0 from length first zero Byte that received, allows operation bootstrap loader ST10F269 with wide range Baud rates. However, upper lower limits have kept, order insure proper data transfer. BST10F269 S0BRL Note: Function (FB) does consider tolerances oscillators other devices supporting serial communication. This Baud rate deviation nonlinear function depending clock Baud rate host. maxima function increase with host Baud rate smaller Baud rate pre-scaler factors implied higher quantization error (see Figure minimum Baud rate(BLow Figure determined maximum count capacity timer when measuring zero Byte, depends clock. Using maximum count formula minimum Baud rate calculated. lowest standard Baud rate this case would 1200 Baud. Baud rates below BLow would cause overflow. this case ASC0 cannot initialized properly. maximum Baud rate (BHigh Figure highest Baud rate where deviation still does exceed limit, Baud rates between BLow BHigh below deviation limit. maximum standard Baud rate that fulfills this requirement 19200 Baud. Higher Baud rates, however, used long actual deviation does exceed limit. certain Baud rate (marked Figure violate deviation limit, while even higher Baud rate (marked 'II' Figure stays very well below This depends host interface.
ST10F269 uses timer measure length initial zero Byte. quantization uncertainty this measurement implies first deviation from real Baud rate, next deviation implied computation S0BRL reload value from timer contents. formula below shows association: Host
S0BRL
correct data transfer from host ST10F269 maximum deviation between internal initialized Baud rate ASC0 real Baud rate host should below 2.5%. deviation (FB, percent) between host Baud rate ST10F269 Baud rate calculated formula below: ontr ontr
Figure Baud Rate Deviation Between Host ST10F269
2.5%
BHigh
BHOST
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CENTRAL PROCESSING UNIT (CPU) includes 4-stage instruction pipeline, 16-bit arithmetic logic unit (ALU) dedicated SFRs. Additional hardware been added separate multiply divide unit, bit-mask generator barrel shifter. Most ST10F269's instructions executed instruction cycle which requires 50ns 40MHz clock. example, shift rotate instructions processed instruction cycle independent number bits shifted. Multiple-cycle instructions have been optimized: branches carried cycles, 16-bit multiplication cycles 32/16-bit division cycles. jump cache reduces execution time repeatedly performed jumps loop, from cycles cycle. uses bank word registers current context. This bank General Purpose Registers (GPR) physically stored within on-chip Internal (IRAM) area. Context Pointer (CP) register determines base address active register bank accessed CPU. number register banks only restricted available Internal space. easy parameter passing, register bank overlap others. system stack 1024 bytes provided storage temporary data. system stack allocated on-chip area, accessed stack pointer (SP) register. separate SFRs, STKOV STKUN, implicitly compared against stack pointer value upon each stack access detection stack overflow underflow.
Figure Block Diagram (MAC Unit included)
STKOV STKUN 256K Byte Flash memory SYSCON BUSCON BUSCON BUSCON BUSCON BUSCON Data Ptrs Exec. Unit Instr. 4-Stage Pipeline Mul./Div.-HW Bit-Mask Gen. Byte Internal Bank
16-Bit Barrel-Shift ADDRSEL ADDRSEL ADDRSEL ADDRSEL Code Seg. Ptr.
General Purpose Register
Bank
Bank
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System Configuration Register SYSCON This bit-addressable register provides general system configuration control functions. reset value register SYSCON depends state PORT0 pins during reset. SYSCON (FF12h 89h)
STKSZ
Reset Value: 0xx0h
STEN
XPEN
VISI
XPERSHARE
Notes: These bits directly indirectly according PORT0 configuration during reset sequence. Register SYSCON cannot changed after execution EINIT instruction.
XPEN BDRSTEN OWDDIS XBUS Peripheral Enable
Function
Accesses on-chip X-Peripherals their functions disabled on-chip X-Peripherals enabled accessed. Bidirectional Reset Enable RSTIN input only. Reset Reset have effect this RSTIN bidirectional pin. This pulled during 1024 during reset sequence. Oscillator Watchdog Disable Control Oscillator Watchdog (OWD) enabled. bypassed, monitors XTAL1 activity. there activity XTAL1 least clock switched automatically PLL's base frequency 10MHz). disabled. bypassed, clock always driven XTAL1 signal. turned reduce power supply current. Power Down Mode Configuration Control
PWDCFG
Power Down Mode only entered during PWRDN instruction execution low, otherwise instruction effect. exit Power Down Mode, external reset must occurs asserting RSTIN pin. Power Down Mode only entered during PWRDN instruction execution enabled fast external interrupt EXxIN pins their inactive level. Exiting this mode done asserting enabled EXxIN pin. Chip Select Config uration Control
CSCFG
Latched Chip Select lines: change after rising edge Unlatched Chip Slect lines change with rising edge
Multiplier-accumulator Unit (MAC) co-processor specialized co-processor added ST10 Core order improve performances ST10 Family signal processing algorithms. Signal processing needs least three specialized units operating parallel achieve maximum performance Multiply-Accumulate Unit, Address Generation Unit, able feed Unit with operands cycle, Repeat Unit, execute series multiply-accumulate instructions.
existing ST10 been modified include addressing capabilities which enable supply co-processor with operands instruction cycle. This co-processor (so-called MAC) contains fast multiply-accumulate unit repeat unit. co-processor instructions extend ST10 instruction with multiply, multiply-accumulate, 32-bit signed arithmetic operations. transfer instruction CoMOV also been added take benefit addressing capabilities.
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6.1.1 Features 6.1.1.1 Enhanced Addressing Capabilities addressing modes including double indirect addressing mode with pointer post-modification. Parallel Data Move this mechanism allows operand move during Multiply-Accumulate instructions without penalty. tranfer instructions CoSTORE (for fast access SFRs) CoMOV (for fast memory memory table transfer). 6.1.1.2 Multiply-Accumulate Unit One-cycle execution operations. Figure Unit Architecture
Operand Operand
16-bit signed/unsigned parallel multiplier. 40-bit signed arithmetic unit with automatic saturation mode. 40-bit accumulator. 8-bit left/right shifter. Full instruction with multiply multiply-accumulate, 32-bit signed arithmetic compare instructions. 6.1.1.3 Program Control Repeat Unit allows some co-processor instructions repeated 8192 times. Repeated instructions interrupted. interrupt (Class Trap) condition flags.
Pointers IDX0 Pointer IDX1 Pointer Offset Register Offset Register Offset Register Offset Register
Concatenation
signed/unsigned Multiplier
Sign Extend
Scaler 08000h
Repeat Unit Interrupt Controller ST10
40-bit Signed Arithmetic Unit
Flags
Control Unit
8-bit Left/Right Shifter
Note: Shared with standard ALU.
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Instruction Summary Table lists instructions theST10F269. various addressing modes, instruction operation, parameters conditional execution instructions, opcodes detailed description each instruction found "ST10 Family Programming Manual". Table Instruction Summary
Mnemonic ADD(B) ADDC(B) SUB(B) SUBC(B) MUL(U) DIV(U) DIVL(U) CPL(B) NEG(B) AND(B) OR(B) XOR(B) BCLR BSET BMOV(N) BAND, BOR, BXOR BCMP BFLDH/L CMP(B) CMPD1/2 CMPI1/2 PRIOR ASHR MOV(B) MOVBS MOVBZ JMPA, JMPI, JMPR JMPS J(N)B word (byte) operands word (byte) operands with Carry Subtract word (byte) operands Subtract word (byte) operands with Carry (Un)Signed multiply direct direct (16-16-bit) (Un)Signed divide register direct (16-/16-bit) (Un)Signed long divide reg. direct (32-/16-bit) Complement direct word (byte) Negate direct word (byte) Bit-wise AND, (word/byte operands) Bit-wise (word/byte operands) Bit-wise XOR, (word/byte operands) Clear direct direct Move (negated) direct direct AND/OR/XOR direct with direct Compare direct direct Bit-wise modify masked high/low byte bit-addressable direct word memory with immediate data Compare word (byte) operands Compare word data decrement Compare word data increment Determine number shift cycles normalize direct word store result direct word Shift left/right direct word Rotate left/right direct word Arithmetic (sign bit) shift right direct word Move word (byte) data Move byte operand word operand with sign extension Move byte operand word operand with zero extension Jump absolute/indirect/relative condition Jump absolute code segment Jump relative direct (not) Jump relative clear direct Description Bytes 37/160
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Table Instruction Summary
Mnemonic JNBS CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, SCXT RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) Description Jump relative direct Call absolute/indirect/relative subroutine condition Call absolute subroutine code segment Push direct word register onto system stack call absolute subroutine Call interrupt service routine immediate trap number Push/pop direct word register onto/from system stack Push direct word register onto system stack update register with word operand Return from intra-segment subroutine Return from inter-segment subroutine Return from intra-segment subroutine direct word register from system stack Return from interrupt service subroutine Software Reset Enter Idle Mode Enter Power Down Mode (supposes NMI-pin being low) Service Watchdog Timer Disable Watchdog Timer Signify End-of-Initialization RSTOUT-pin Begin ATOMIC sequence Begin EXTended Register sequence Begin EXTended Page (and Register) sequence Begin EXTended Segment (and Register) sequence Null operation Bytes
Coprocessor Specific Instructions following table gives overview instruction set. mnemonics listed with addressing modes that used with each instruction. each combination mnemonic addressing mode this table indicates repeatable not. addressing capabilities enable supply with operands instruction cycle. instructions: multiply, multiply-accumulate, 32-bit signed arithmetic operations CoMOV transfer instruction have been
added standard instruction set. Full details provided `ST10 Family Programming Manual'. Double indirect addressing requires pointers. used pointer, other pointer provided specific SFRs IDX0 IDX1. pairs offset registers QR0/QR1 QX0/QX1 associated with each pointer (GPR IDXi). pointer allows access entire memory space, IDXi limited internal Dual-Port RAM, except CoMOV instruction.
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Mnemonic CoMUL CoMULu CoMULus CoMULsu CoMULCoMULuCoMULusCoMULsuCoMUL, CoMULu, CoMULus, CoMULsu, CoMAC CoMACu CoMACus CoMACsu CoMACCoMACuCoMACusCoMACsuCoMAC, CoMACu, CoMACus, CoMACsu, CoMACR CoMACRu CoMACRus CoMACRsu CoMACR, CoMACRu, CoMACRus, CoMACRsu, CoNOP [IDXi]
Addressing Mode
Repeatability
Rwn, [IDXi], [Rwm] Rwn,
Rwn, [IDXi], [Rwm] Rwn,
Rwn, [IDXi], [Rwn] Rwn, [RWm
[IDXi], [Rwm] CoNEG CoNEG, CoRND CoSTORE CoMOV Rwn, CoReg Coreg [IDXi], [Rwm]
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Mnemonic CoMACM CoMACMu CoMACMus CoMACMsu CoMACMu, CoMACMus, CoMACMsu, CoMACMR CoMACMRu CoMACMRus CoMACMRsu CoMACMR, CoMACMRu, CoMACMRus, CoMACMRsu, CoADD CoADD2 CoSUB CoSUB2 CoSUBR CoSUB2R CoMAX CoMIN CoLOAD CoLOADCoLOAD2 CoLOAD2CoCMP CoSHL CoSHR CoASHR CoASHR, #data4
Addressing Mode
Repeatability
[IDXi], [Rwm]
Rwn, [IDXi], [Rwm] Rwn,
Rwn, [IDXi], [Rwm] Rwn,
CoABS
Rwn, [IDXi], [Rwm] Rwn,
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Table shows various combinations pointer post-modification each these addressing modes. this document symbols "[Rw "[IDXi]" refer these addressing modes. Table Pointer Post-modification Combinations IDXi
Symbol "[IDXi]" stands Mnemonic [IDXi [IDXi [IDXi [IDXi QXj] [IDXi "[Rwn]" stands [Rwn] [Rwn+] [Rwn-] [Rwn QRj] [Rwn (IDXi (IDXi) (IDXi (IDXi) (IDXi (IDXi) (IDXi (IDXi) (QXj (IDXi (IDXi) (QXj (Rwn) (Rwn) (Rwn) (Rwn) (Rwn) (Rwn) (Rwn) (Rwn) (QRj) (Rwn) (Rwn) (QRj) Address Pointer Operation (no-op) (i=0,1) (i=0,1) =0,1) =0,1) (no-op) (n=0-15) (n=0-15) (n=0-15; =0,1) (n=0-15; =0,1)
Table Registers Referenced `CoReg`
Registers MAC-Unit Status Word MAC-Unit Accumulator High "limited" /signed MAC-Unit Accumulator MAC-Unit Control Word MAC-Unit Repeat Word Description Address Opcode 00000b 00001b 00010b 00100b 00101b 00110b
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EXTERNAL CONTROLLER external memory accesses performed on-chip external controller. programmed single chip mode when external memory required, four different external memory access modes: 24-bit addresses 16-bit data, demultiplexed 24-bit addresses 16-bit data, multiplexed 24-bit addresses 8-bit data, multiplexed 24-bit addresses 8-bit data, demultiplexed demultiplexed modes addresses output PORT1 data input output PORT0 P0L, respectively. multiplexed modes both addresses data PORT0 input output. Timing characteristics external interface (memory cycle time, memory tri-state time, length read write delay) programmable giving choice wide range memories external peripherals. independent address windows defined (using register pairs ADDRSELx BUSCONx) access different resources characteristics. These address windows arranged hierarchically where BUSCON4 overrides BUSCON3 BUSCON2 overrides BUSCON1. accesses locations covered these address windows controlled BUSCON0. external signals windows plus default) generated order save external glue logic. Access very slow memories supported `Ready' function. HOLD HLDA protocol available arbitration which shares external resources with other masters. arbitration enabled setting HLDEN register PSW. After setting HLDEN once, pins P6.7.P6.5 (BREQ, HLDA, HOLD) automatically controlled EBC. master mode (default after reset) HLDA output. setting DP6.7 to'1' slave mode selected where HLDA switched input. This directly connects slave controller another master controller without glue logic. applications which require less external memory space, address space restricted Byte, 256K Bytes Bytes. Port outputs address lines address space Bytes used, otherwise four, address lines. Chip select timing made programmable. default (after reset), lines change half clock cycle after rising edge ALE. With CSCFG SYSCON register lines change with rising edge ALE. active level READY RDYPOL BUSCONx registers. When READY function enabled specific address window, each cycle within window must terminated with active level defined RDYPOL associated BUSCON register. Programmable Chip Select Timing Control ST10F269 allows user adjust position line changes. default (after reset), lines change half clock cycle (12.5ns 40MHz clock) after rising edge ALE. With CSCFG SYSCON register lines change with rising edge ALE, thus lines address lines change same time (see Figure 11). READY Programmable Polarity active level READY selected software RDYPOL BUSCONx registers. When READY function enabled specific address window, each cycle within this window must terminated with active level defined this RDYPOL associated BUSCON register. BUSCONx registers described inSection 20.2 System Configuration Registers. Note ST10F269 internal pull-up resistor READY pin.
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Figure Chip Select Delay
Normal Demultiplexed Segment (P4) Address (P1) Cycle Lengthen Demultiplexed Cycle
Normal Unlatched
(P0)
Data
Data
(P0)
Data
Data
Read/Write Delay Read/Write Delay
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INTERRUPT SYSTEM interrupt response time internal program execution from 125ns 300ns 40MHz clock. ST10F269 architecture supports several mechanisms fast flexible response service requests that generated from various sources (internal external) microcontroller. these interrupt requests serviced Interrupt Controller Peripheral Event Controller (PEC). contrast standard interrupt service where current program execution suspended branch interrupt vector table performed, just cycle `stolen' from current activity perform service. service implies single Byte Word data transfer between memory locations with additional increment either source destination pointer. individual transfer counter implicitly decremented each service except when performing continuous transfer mode. When this counter reaches zero, standard interrupt performed corresponding source related vector location. services very well suited perform transmission reception blocks data. ST10F269 channels, each them offers such fast interrupt-driven data transfer capabilities. EXISEL (F1DAh EDh)
interrupt control register which contains interrupt request flag, interrupt enable flag interrupt priority bit-field dedicated each existing interrupt source. Thanks related register, each source programmed sixteen interrupt priority levels. Once starting processed CPU, interrupt service only interrupted higher prioritized service request. standard interrupt processing, each possible interrupt sources dedicated vector location. Software interrupts supported means `TRAP' instruction combination with individual trap (interrupt) number. External Interrupts Fast external interrupt inputs provided service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge both edges). Fast external interrupts also have interrupt sources selected from other peripherals; example CANx controller receive signal (CANx_RxD) used interrupt system. This function controlled using `External Interrupt Source Selection' register EXISEL. Reset Value:0000h
ESFR
EXI7SS
EXI6SS
EXI5SS
EXI4SS
EXI3SS
EXI2SS
EXI1SS
EXI0SS
EXIxSS
External Interrupt Source Selection (x=7.0) `00': Input from associated Port pin. `01': Input from "alternate source". `10': Input from Port ORed with "alternate source". `11': Input from Port ANDed with "alternate source".
EXIxSS Port P2.8 P2.9 P2.10 P2.11 P2.12.15 Alternate Source CAN1_RxD CAN2_RxD RTCSI (Timed) RTCAI (Alarm) used (zero)
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Interrupt Registers Vectors Location List Table shows available ST10F269 interrupt sources corresponding hardware-related interrupt flags, vectors, vector locations trap (interrupt) numbers: Table Interrupt SourceSource Interrupt Service Request CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Register CAPCOM Timer Request Flag CC0IR CC1IR CC2IR CC3IR CC4IR CC5IR CC6IR CC7IR CC8IR CC9IR CC10IR CC11IR CC12IR CC13IR CC14IR CC15IR CC16IR CC17IR CC18IR CC19IR CC20IR CC21IR CC22IR CC23IR CC24IR CC25IR CC26IR CC27IR CC28IR CC29IR CC30IR CC31IR T0IR Enable Flag CC0IE CC1IE CC2IE CC3IE CC4IE CC5IE CC6IE CC7IE CC8IE CC9IE CC10IE CC11IE CC12IE CC13IE CC14IE CC15IE CC16IE CC17IE CC18IE CC19IE CC20IE CC21IE CC22IE CC23IE CC24IE CC25IE CC26IE CC27IE CC28IE CC29IE CC30IE CC31IE T0IE Interrupt Vector CC0INT CC1INT CC2INT CC3INT CC4INT CC5INT CC6INT CC7INT CC8INT CC9INT CC10INT CC11INT CC12INT CC13INT CC14INT CC15INT CC16INT CC17INT CC18INT CC19INT CC20INT CC21INT CC22INT CC23INT CC24INT CC25INT CC26INT CC27INT CC28INT CC29INT CC30INT CC31INT T0INT Vector Location 00'0040h 00'0044h 00'0048h 00'004Ch 00'0050h 00'0054h 00'0058h 00'005Ch 00'0060h 00'0064h 00'0068h 00'006Ch 00'0070h 00'0074h 00'0078h 00'007Ch 00'00C0h 00'00C4h 00'00C8h 00'00CCh 00'00D0h 00'00D4h 00'00D8h 00'00DCh 00'00E0h 00'00E4h 00'00E8h 00'00ECh 00'00F0h 00'0110h 00'0114h 00'0118h 00'0080h Trap Number 45/160
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Table Interrupt Sources (continued)
Source Interrupt Service Request CAPCOM Timer CAPCOM Timer CAPCOM Timer GPT1 Timer GPT1 Timer GPT1 Timer GPT2 Timer GPT2 Timer GPT2 CAPREL Register Conversion Complete Overrun Error ASC0 Transmit ASC0 Transmit Buffer ASC0 Receive ASC0 Error Transmit Receive Error Channel CAN1 Interface CAN2 Interface FLASH Ready Busy Unlock/OWD Request Flag T1IR T7IR T8IR T2IR T3IR T4IR T5IR T6IR CRIR ADCIR ADEIR S0TIR S0TBIR S0RIR S0EIR SCTIR SCRIR SCEIR PWMIR XP0IR XP1IR XP2IR XP3IR Enable Flag T1IE T7IE T8IE T2IE T3IE T4IE T5IE T6IE CRIE ADCIE ADEIE S0TIE S0TBIE S0RIE S0EIE SCTIE SCRIE SCEIE PWMIE XP0IE XP1IE XP2IE XP3IE Interrupt Vector T1INT T7INT T8INT T2INT T3INT T4INT T5INT T6INT CRINT ADCINT ADEINT S0TINT S0TBINT S0RINT S0EINT SCTINT SCRINT SCEINT PWMINT XP0INT XP1INT XP2INT XP3INT Vector Location 00'0084h 00'00F4h 00'00F8h 00'0088h 00'008Ch 00'0090h 00'0094h 00'0098h 00'009Ch 00'00A0h 00'00A4h 00'00A8h 00'011Ch 00'00ACh 00'00B0h 00'00B4h 00'00B8h 00'00BCh 00'00FCh 00'0100h 00'0104h 00'0108h 00'010Ch Trap Number
Hardware traps exceptions error conditions that arise during run-time. They cause immediate non-maskable system reaction similar standard interrupt service (branching dedicated vector table location). occurrence hardware trap additionally signified individual trap flag register (TFR). Except when another higher prioritized trap service progress, hardware trap will interrupt other program execution. Hardware trap services cannot interrupted standard interrupt interrupts. Interrupt Control Registers interrupt control registers identically organized. lower bits interrupt control register contain complete interrupt status information associated source, which i46/160
required during round prioritization, upper bits respective register reserved. interrupt control registers bit-addressable bits read written software. This allows each interrupt source programmed modified with just instruction. When accessing interrupt control registers through instructions which operate Word data types, their upper bits (15.8) will return zeros, when read, will discard written data. layout Interrupt Control registers shown below applies each xxIC register, where stands mnemonic respective source.
ST10F269
xxIC (yyyyh zzh)
Area
xxIR xxIE ILVL
Reset Value:
GLVL
GLVL Group Level
Function
Defines internal order simultaneous requests same priority. Highest group priority Lowest group priority ILVL Interrupt Priority Level Defines priority level arbitration requests. Highest priority level Lowest priority level xxIE Interrupt Enable Control (individually enables/disables specific source) `0': Interrupt Request disabled `1': Interrupt Request enabled xxIR Interrupt Request Flag `0': request pending `1': This source raised interrupt request
Exception Error Traps List Table shows possible exceptions error conditions that arise during run-time Table Trap PrioritieException Condition Reset Functions: Hardware Reset Software Reset Watchdog Timer Overflow Class Hardware Traps: Non-Maskable Interrupt Stack Overflow Stack Underflow Class Hardware Traps: Undefined Opcode Protected Instruction Fault Illegal word Operand Access Illegal Instruction Access Illegal External Access Reserved Software Traps TRAP Instruction STKOF STKUF UNDOPC PRTFLT ILLOPA ILLINA ILLBUS Trap Flag Trap Vector RESET RESET RESET NMITRAP STOTRAP STUTRAP BTRAP BTRAP BTRAP BTRAP BTRAP Vector Location 00'0000h 00'0000h 00'0000h 00'0008h 00'0010h 00'0018h 00'0028h 00'0028h 00'0028h 00'0028h 00'0028h [002Ch 003Ch] 0000h 01FCh steps Trap Number [0Bh 0Fh] [00h 7Fh] Current Priority Trap* Priority
class traps have same trap number (and vector) same lower priority compare class traps resets. Each class traps dedicated trap number (and vector). They prioritized second priority level. resets have highest priority level same trap number. PSW.ILVL priority forced highest level (15) when these exeptions serviced.
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CAPTURE/COMPARE (CAPCOM) UNITS ST10F269 channels CAPCOM units described Figure These support generation control timing sequences channels with maximum resolution 200ns 40MHz clock. CAPCOM units typically used handle high speed tasks such pulse waveform generation, pulse width modulation (PMW), Digital Analog (D/A) conversion, software timing, time recording relative external events. Four 16-bit timers (T0/T1, T7/T8) with reload registers provide independent time bases capture/compare register array (See Figures 14). input clock timers programmable several prescaled values internal system clock, derived from overflow/ underflow timer module GPT2. This Figure CAPCOM Unit Block Diagram
ReloadRegister TxREL
provides wide range variation timer period resolution allows precise adjustments application specific requirements. addition, external count inputs CAPCOM timers allow event scheduling capture/compare registers relative external events. Each capture/compare register arrays contain dual purpose capture/compare registers, each which individually allocated either CAPCOM timer respectively), programmed capture compare functions. Each registers associated port which serves input triggering capture function, output indicate occurrence compare event. Figure shows basic structure CAPCOM units.
Clock
3.10 TxIN Input Control Interrupt Request CAPCOMTimer
GPT2 Timer Over Underflow Mode Control (Capture Compare)
Capture inputs Compareoutput
Sixteen 16-bit (Capture/Compare) Register
Capture Compare* Interrupt Request
Clock
3.10 Input Control GPT2 Timer Over Underflow CAPCOMTimer
Interrupt Request
ReloadRegister TyREL
CAPCOM2 unit provides capture inputs, only compare outputs. CC24I CC27I inputs only.
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Figure Block Diagram CAPCOM Timers
Input Control Clock Interrupt Request Reload Register TxREL
GPT2 Timer Over Underflow Edge Select
CAPCOMTimer
TxIR
TxIN
Figure Block Diagram CAPCOM Timers
Reload Register TxREL
Clock
CAPCOM Timer TxIR Interrupt Request
GPT2 Timer Over Underflow
Note: When external input signal connected input lines both these timers count input signal synchronously. Thus timers regarded timer whose contents compared with capture registers. When capture/compare register been selected capture mode, current contents allocated timer will latched (captured) into capture/compare register response external event port which associated with this register. addition, specific interrupt request this capture/compare register generated. Either positive, negative, both positive negative external signal transition selected triggering event. contents registers which have been selected
five compare modes continuously compared with contents allocated timers. When specific selected match occurs between timer value value capture /compare register, actions will taken based compare mode (see Table
input frequencies timer input selector determined function clocks. timer input frequencies, resolution periods which result from selected pre-scaler option when using 40MHz clock listed Table numbers timer periods based reload value 0000h. Note that some numbers rounded significant figures.
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Table Compare ModeCompare Modes Mode Mode Mode Mode Double Register Mode Function Interrupt-only compare mode; several compare interrupts timer period possible toggles each compare match; several compare events timer period possible Interrupt-only compare mode; only compare interrupt timer period generated match; reset compare time overflow; only compare event timer period generated registers operate pin; toggles each compare match; several compare events timer period possible.
Table CAPCOM Timer Input Frequencies, Resolution PeriodTimer Input Selection fCPU 40MHz 000b Pre-scaler fCPU Input Frequency Resolution Period 5MHz 200ns 13.1ms 001b 2.5MHz 400ns 26.2ms 010b 1.25MHz 0.8µs 52.4ms 011b 625kHz 1.6µs 104.8ms 100b 312.5kHz 3.2µs 209.7ms 101b 156.25kHz 6.4µs 419.4ms 110b 78.125kHz 12.8µs 838.9ms 111b 1024 39.1kHz 25.6µs 1.678
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GENERAL PURPOSE TIMER UNIT unit flexible multifunctional timer/ counter structure which used time related tasks such event timing counting, pulse width duty cycle measurements, pulse generation, pulse multiplication. unit contains five 16-bit timers organized into separate modules GPT1 GPT2. Each timer each module operate independently several different modes, concatenated with another timer same module. 10.1 GPT1 Each three timers GPT1 module configured individually four basic modes operation: timer, gated timer, counter mode incremental interface mode. timer mode, input clock timer derived from clock, divided programmable prescaler. counter mode, timer clocked reference external events. Pulse width duty cycle measurement supported gated timer mode where operation timer controlled `gate' level external input pin. these purposes, each timer associated port (TxIN) which serves gate clock input. Table lists timer input frequencies, resolution periods each pre-scaler option 40MHz clock. This also applies Gated Timer Mode auxiliary timers Timer Gated Timer Mode. count direction (up/down) each timer programmable software altered dynamically external signal port (TxEUD). Incremental Interface Mode, GPT1 timers (T2, directly connected incremental position sensor signals their respective inputs TxIN TxEUD. Direction count signals internally derived from these input signals that contents respective timer corresponds sensor position. third position sensor signal TOP0 connected interrupt input. Timer output toggle latches (TxOTL) which changes state each timer over flow underflow. state this latch output port pins (TxOUT) time monitoring external hardware components, used internally clock timers high resolution long duration measurements. addition their basic operating modes, timers configured reload capture registers timer When used capture reload registers, timers stopped. contents timer captured into response signal their associated input pins (TxIN). Timer reloaded with contents triggered either external signal selectable state transition toggle latch T3OTL. When both configured alternately reload opposite state transitions T3OTL with high times signal, this signal constantly generated without software intervention.
Table GPT1 Timer Input Frequencies, Resolution PeriodTimer Input Selection fCPU 40MHz 000b Pre-scaler factor Input Freq Resolution Period maximum 5MHz 200ns 13.1ms 001b 2.5MHz 400ns 26.2ms 010b 1.25MHz 0.8µs 52.4ms 011b 625kHz 1.6µs 104.8ms 100b 312.5kHz 3.2µs 209.7ms 101b 156.25kHz 6.4µs 419.4ms 110b 78.125kHz 12.8µs 838.9ms 111b 1024 39.1kHz 25.6µs 1.678s 51/160
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Figure Block Diagram GPT1
T2EUD Clock T2IN
GPT1 Timer n=3.10 Mode Control Reload Capture Interrupt Request
Clock
n=3.10
T3IN T3EUD
Mode Control
T3OUT GPT1 Timer Capture Reload T3OTL
T4IN Clock
n=3.10
Mode Control
Interrupt Request Interrupt Request
GPT1 Timer
T4EUD
10.2 GPT2 GPT2 module provides precise event control time measurement. includes timers (T5, capture/reload register (CAPREL). Both timers clocked with input clock which derived from clock programmable prescaler with external signals. count direction (up/down) each timer programmable software additionally altered dynamically external signal port (TxEUD). Concatenation timers supported output toggle latch (T6OTL) timer which changes state each timer overflow/underflow. state this latch used clock timer output port (T6OUT). overflow underflow timer additionally used clock CAPCOM timers
cause reload from CAPREL register. CAPREL register capture contents timer based external signal transition corresponding port (CAPIN), timer optionally cleared after capture procedure. This allows absolute time differences measured pulse multiplication performed without software overhead. capture trigger (timer CAPREL) also generated upon transitions GPT1 timer inputs T3IN and/or T3EUD. This advantageous when operates Incremental Interface Mode. Table lists timer input frequencies, resolution periods each pre-scaler option 40MHz clock. This also applies Gated Timer Mode auxiliary timer Timer Gated Timer Mode.
Table GPT2 Timer Input Frequencies, Resolution Period
Timer Input Selection fCPU 40MHz 000b Pre-scaler factor Input Freq Resolution Period maximum 10MHz 100ns 6.55ms 001b 5MHz 200ns 13.1ms 010b 2.5MHz 400ns 26.2ms 011b 1.25MHz 0.8µs 52.4ms 100b 625kHz 1.6µs 104.8ms 101b 312.5kHz 3.2µs 209.7ms 110b 156.25kHz 6.4µs 419.4ms 111b 78.125kHz 12.8µs 838.9m
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ST10F269
Figure Block Diagram GPT2
T5EUD Clock T5IN
n=2.9 Mode Control GPT2 Timer Clear Capture Interrupt Request
CAPIN GPT2 CAPREL
Interrupt Request
Reload
Interrupt Request
T6IN Clock
n=2.9
Mode Control
Toggle GPT2 Timer T60TL T6OUT CAPCOM Timer
T6EUD
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ST10F269
MODULE pulse width modulation module generate four output signals using edge-aligned centre-aligned PWM. addition, module generate burst signals Figure Block Diagram Module
Period Register Match
single shot outputs. TheTable shows frequencies different resolutions. level output signals selectable module generate interrupt requests.
Comparator
Clock Clock
Input Control
16-bit Up/Down Counter
Up/Down/ Clear Control
Comparator
Match
Output Control Enable
POUTx
Shadow Register
Write Control
User readable writeableregister
Pulse Width Register*
Table Unit Frequencies Resolution 40MHz Clock
Mode Clock/1 Clock/64 Mode Clock/1 Clock/64 Resolutio 25ns 1.6µs Resolutio 25ns 1.6µs 8-bit 156.25kHz 2.44Hz 8-bit 78.12kHz 1.22kHz 10-bit 39.1kHz 610Hz 10-bit 19.53kHz 305.17Hz 12-bit 9.77kHz 152.6Hz 12-bit 4.88kHz 76.29Hz 14-bit 2.44Hz 38.15Hz 14-bit 1.22kHz 19.07Hz 16-bit 610Hz 9.54Hz 16-bit 305.17Hz 4.77Hz
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ST10F269
PARALLEL PORTS 12.1 Introduction ST10F269 provides lines with programmable features. These capabilities bring very flexible adaptation this wide range applications. ST10F269 groups lines gathered following: Port time 8-bit port named (Low less significant Byte) (high most significant Byte) Port time 8-bit port named Port 16-bit port Port 15-bit port (P3.14 line implemented) Port 8-bit port Port 16-bit port input only Port Port Port 8-bit port These ports used general purpose bidirectionnal input output, software controlled with dedicated registers. example output drivers ports configured (bit-wise) push-pull open drain operation using ODPx registers. addition, sink source capability rise fall time transition signal some push-pull buffers programmed driving requirements application minimize EMI. This feature implemented Port with control registers POCONx. output drivers capabilities ALE, control lines programmable with dedicated bits POCON20 control register. input threshold levels programmable (TTL/CMOS) ports logic level clocked into input latch once state time, regardless whether port configured input output. threshold selected with PICON register control bits. write operation port configured input causes value written into port output latch, while read operation returns latched state itself. read-modify-write operation reads value pin, modifies writes back output latch. Writing configured output (DPx.y=`1') causes output latch have written value, since output buffer enabled. Reading this returns value output latch. read-modify-write operation reads value output latch, modifies writes back output latch, thus also modifying level pin. lines support alternate function which detailed following description each port.
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Direction Control Register15 DP0L DP0H YYYYYYYYYY YYYYYYYYYY P5DIDIS YYYYYYYY ODP8 YYYYYYYY ODP7 YYYYYYYY ODP6 YYYYYYYYYY POCON6 POCON7 POCON8 YYYYYY YYYYYY YYYYYYYY ODP4 ODP3 POCON3 POCON4 ODP2 POCON2 YYYYYYYY POCON1H YYYYYYYY POCON1L YYYYYYYY POCON0H DP1L DP1H YYYYYYYY PICON POCON0L
ST10F269
Data Input Output Register
Threshold Open Drain Control
Output Driver Control Register
YYYYYYYY
YYYYYYYY
YYYYYYYY
YYYYYYYY
YYYYYYYYYY
YYYYYYYYYY
YYYYYYYY
YYYYYYYYYY
YYYYYYYY
Figure SFRs Pins Associated with Parallel Port
YYYYYYYY
YYYYYYYY
PICON:
POCON20
YYYYYY
P2LIN P2HIN P3LIN P3HIN P4LIN P6LIN implemented) P7LIN P8LIN
lines only
function dedicated function implemented Register belongs ESFR area
ST10F269
12.2 I/O's Special Features 12.2.1 Open Drain Mode Some ports ST10F269 support open drain capability. This programmable feature used with external pull-up resistor, order wired logical function. This feature implemented ports (see respective sections), controlled through respective Open Drain Control Registers ODPx. These registers allow individual bit-wise selection open drain mode each port line. respective control ODPx.y (default after reset), output driver push-pull mode. ODPx.y `1', open drain configuration selected. Note that ODPx registers located ESFR space (See Figure 19). PICON (F1C4h E2h)
12.2.2 Input Threshold Control standard inputs ST10F269 determine status input signals according levels. order accept recognize noisy signals, CMOS-like input thresholds selected instead standard thresholds pins Port Port Port Port Port These special thresholds defined above thresholds feature defined hysteresis prevent inputs from toggling while respective input signal level near thresholds. Port Input Control register PICON used select these thresholds each Byte indicated ports, this means 8-bit ports controlled each while ports controlled bits each. options individual direction output mode control available each pin, independent selected input threshold. input hysteresis provides stable inputs from noisy slowly changing external signals (See Figure 20). Reset Value: -00h
ESFR
P8LIN P7LIN
P4LIN P3HIN P3LIN P2HIN P2LIN
PxLIN Port Byte Input Level Selection PxHIN
Function
Pins Px.7.Px.0 switch standard input levels Pins Px.7.Px.0 switch special threshold input levels Pins Px.15.Px.8 switch standard input levels Pins Px.15.Px.8 switch special threshold input level
Port High Byte Input Level Selection
Figure Output Drivers Push-pull Mode Open Drain Mode
External Pullup
Push-Pull Output Driver
Open Drain Output Driver
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ST10F269
Figure Hysteresis Special Input Threshold
Hysteresis Input level state 12.2.3 Output Driver Control port output control registers POCONx allow select port output driver characteristics port. these selections adapt output drivers application's requirements, improve behaviour device. characteristics selected: Edge characteristic defines rise/fall time respective output. Slow edges reduce peak currents that sinked/sourced when changing voltage level external capacitive load. interface pins that changing frequency higher than 1MHz, however, fast edges still required. Driver characteristic defines either general driving capability respective driver, POCONx (F0yyh zzh) 8-bit Port15
driver strength reduced after target output level been reached not. Reducing driver strength increases output's internal resistance, which attenuates noise that imported output line. driving LEDs power transistors, however, stable high output current still required described below. This rise fall time pads nibble) selected using 2-bit named PNxEC. That means Port Nibble nibble number, could Port 2.15 2.12) Edge Characteristic. sink source capability same pads selected using 2-bit named PNxDC. That means Port Nibble nibble number) Drive Characteristic (See Table 14). Reset Value: -00h
PN1DC PN1EC PN0DC PN0EC
ESFR
POCONx (F0yyh zzh) 16-bit Port15 PN3DC PN3EC PN2DC PN2EC
ESFR
Function PN1DC PN1EC
Reset Value: 0000h
PN0DC PN0EC
PNxEC
PNxDC
Port Nibble Edge Characteristic (rise/fall time) Fast edge mode, rise/fall times depend size driver. Slow edge mode, rise/fall times Reserved Reserved Port Nibble Driver Characteristic (output current) High Current mode: Driver always operates with maximum strength. Dynamic Current mode: Driver strength reduced after target level been reached. Current mode: Driver always operates with reduced strength. Reserved
Note: case reading P0CONX register, high Byte 15.8) read
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ST10F269
table lists defined POCON registers allocation control bit-fields port pins. Table Port Control Register Allocation
Control Register POCON0L POCON0H POCON1L POCON1H POCON2 POCON3 POCON4 POCON6 POCON7 POCON8 Physical Address F080h F082h F084h F086h F088h F08Ah F08Ch F08Eh F090h F092h 8-bit Address P2.15.12 P3.15, 3.13, 3.12 P2.11.8 P3.11.8 Controlled Port Nibble
P0L.7.4 P0H.7.4 P1L.7.4 P1H.7.4 P2.7.4 P3.7.4 P4.7.4 P6.7.4 P7.7.4 P8.7.4
P0L.3.0 P0H.3.0 P1L.3.0 P1H.3.0 P2.3.0 P3.3.0 P4.3.0 P6.3.0 P7.3.0 P8.3.0
Dedicated Pins Output Control Programmable drivers also supported dedicated pins ALE,RD these pads, special POCON20 register provided. POCON20 (F0AAh 55h)
ESFR
PN1DC PN1EC
Reset Value: -00h
PN0DC PN0EC
PN0EC
Edge Characteristic (rise/fall time) Fast edge mode, rise/fall times depend size driver. Slow edge mode, rise/fall times Reserved Reserved Driver Characteristic (output current) High Current mode: Driver always operates with maximum strength. Dynamic Current mode: Driver strength reduced after target level been reached. Current mode: Driver always operates with reduced strength. Reserved Edge Characteristic (rise/fall time) Fast edge mode, rise/fall times depend size driver. Slow edge mode, rise/fall times Reserved Reserved Driver Characteristic (output current) High Current mode: Driver always operates with maximum strength. Dynamic Current mode: Driver strength reduced after target level been reached. Current mode: Driver always operates with reduced strength. Reserved
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PN0DC
PN1EC
PN1DC
ST10F269
12.2.4 Alternate Port Functions Each port line associated programmable alternate input output function. PORT0 PORT1 used address data lines when accessing external memory. Port Port Port associated with capture inputs compare outputs CAPCOM units and/or with outputs module. Port also used fast external interrupt inputs timer input. Port includes alternate functions timers, serial interfaces, optional control signal system clock output (CLKOUT). Port outputs additional segment address systems where segmentation enabled access more than Bytes memory. this case, reflects state port output latch. Thus, alternate input function reads value stored port output latch. This used testing purposes allow software trigger alternate input function writing port output latch. most port lines, application software must proper direction when using alternate input output function pin. This done setting clearing direction control DPx.y before enabling alternate function. There port lines, however, where direction port line switched automatically. instance, multiplexed external modes PORT0, direction must switched several times instruction fetch order output addresses input data. Obviously, this cannot done through instructions. these cases, direction port line switched automatically hardware alternate function such enabled. determine appropriate level port output latches check alternate data output combined with respective port latch output. There basic structure port lines supporting only alternate input function. Port lines with only alternate output function, however, have different structures. adapted support normal alternate function features. port lines that used these alternate functions used general purpose lines. When using port pins general purpose output, initial output value should written port latch prior enabling output drivers, order avoid undesired transitions output pins. This applies single pins well groups (see examples below). Initial output level "high" Switch output driver Initial output level "high" Switch output driver
Port used analog input channels converter timer control signals.
Port provides optional arbitration signals (BREQ, HLDA, HOLD) chip select signals. alternate output function used, direction this must programmed output (DPx.y=`1'), except some signals that used directly after reset configured automatically. Otherwise remains high-impedance state effected alternate output function. respective port latch should hold `1', because output ANDed with alternate output data (except output signals). alternate input function used, direction must programmed input (DPx.y=`0') external device driving pin. input direction default after reset. external device connected pin, however, also direction this output. SINGLE_BIT: BSET BSET BIT_GROUP: BFLDH BFLDH P4.7 DP4.7 #24H, #24H DP4, #24H, #24H
Note: When using several BSET pairs control more pins port, these pairs must separated instructions, which apply respective port (SeeChapter Central Processing Unit (CPU)).
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ST10F269
12.3 PORT0 8-bit ports represent higher lower part PORT0, respectively. Both halves PORT0 written (via transfer) without effecting other half. (FF00h 80h)
this port used general purpose I/O, direction each line configured corresponding direction registers DP0H DP0L. Reset Value: -00h
P0L.7 P0L.6 P0L.5 P0L.4 P0L.3 P0L.2 P0L.1 P0L.0
(FF02h 81h)
Reset Value: -00h
P0H.7 P0H.6 P0H.5 P0H.4 P0H.3 P0H.2 P0H.1 P0H.0
P0X.y
Port Data Register ESFR
DP0L.7 DP0L.6 DP0L.5 DP0L.4 DP0L.3 DP0L.2
DP0L (F100h 80h)
Reset Value: -00h
DP0L.1 DP0L.0
DP0H (F102h 81h)
ESFR
Reset Value: -00h
DP0H.7 DP0H.6 DP0H.5 DP0H.4 DP0H.3 DP0H.2 DP0H.1 DP0H.0
DP0X.y
Port Direction Register DP0H DP0L DP0X.y Port line P0X.y input (high-impedance) DP0X.y Port line P0X.y output
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ST10F269
12.3.1 Alternate Functions PORT0 When external enabled, PORT0 used data address/data bus. Note that external 8-bit demultiplexed only uses P0L, while free

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