LC7073, 7073M Error Detection Correction Demodulators Prelim

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LC7073, 7073M Error Detection Correction Demodulators Prelim

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Ordering number:ENN *3932
LC7073, 7073M
Error Detection Correction Demodulators
Preliminary Overview
LC7073 LC7073M error detection correction that provide easy interface LA2230 LA2231 radio data system (RDS) demodulators. Both devices incorporate on-chip oscillator that connects directly external ceramic resonator. LC7073 LC7073M provide group synchronization, selectable error detection correction, output clock polarity selection, block data start signal output error output that signals error correction failures. LC7073 LC7073M operate from supply available 18-pin DIPs MFPs, respectively.
Package Dimensions
unit:mm 3007B-DIP18
[LC7073]
24.0
7.62
error detection correction. Easy interface with LA2230 LA2231 demodulator ICs. Serial data transfer system. Group synchronization capability. Selectable error detection correction. Output clock polarity selection. Block data start output. Error output. On-chip oscillator. supply. 18-pin (LC7073) 18-pin (LC7073M). Assignment
(1.84)
2.54
0.51min
SANYO DIP18
unit:mm 3095-MFP18
[LC7073M]
12.6
0.35
1.27
1.22
SANYO MFP18
view
SANYO products described contained herein have specifications that handle applications that require extremely high levels reliability, such life-support systems, aircraft's control systems, other applications whose failure reasonably expected result serious physical and/or material damage. Consult with your SANYO representative nearest before using SANYO products described contained herein such applications. SANYO assumes responsibility equipment failures that result from using products values that exceed, even momentarily, rated values (such maximum ratings, operating condition ranges,or other parameters) listed products specifications SANYO products described contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
71901TN (KT)/5281JN(US) No.3932-1/9
0.625
1.8max
0.15
6.35
Features
3.85max
(3.25)
0.25
LC7073, 7073M
Block Diagram
Function
Number Name Equivalent circuit Description
OSC1
External ceramic resonator connection
VSS1 VSS2
Ground Ground
Schmitt-trigger reset input. Held minimum clock cycles
CKIN
Serial data input clock. Connects demodulator output clock
Serial data input. Connects demodulator data output
COREN
Error-correction enable input. disables error correction HIGH enables error correction
Continued next page.
No.3932-2/9
LC7073, 7073M
Continued from preceding page.
Number Name Equivalent circuit Description
CKPOL
Serial data output clock polarity select input
supply
Serial data receive detect output. while receiving, after sync detection. High impedance when receiving. High impedance after reset
DSTCTL
Data start control input. initiates data start second block, HIGH, blocks
Error-correction enabled/disabled output. when error correction occurs HIGH when error correction occurs. High impedance after reset
Error-detect output. when error correction fails. High impedance when error correction does fail. High impedance after reset
Serial data start output. indicates data start, HIGH, data start. HIGH after reset
DOUT
Serial data output. HIGH after reset
CKOUT
Serial data output clock
VSS3
Ground
OSC2
External ceramic resonator connection
No.3932-3/9
LC7073, 7073M Specifications
Absolute Maximum Ratings +25°C, VSS1, VSS2, VSS3
Parameter Maximum supply voltage OSC2, DST, DOUT CKOUT output voltage REC, output voltage OSC1 input voltage CKIN, DIN, COREN, CKPOL DSCTL input voltage REC, output current DST, DOUT CKOUT output current Output pins total current allowable power dissipation allowable power dissipation Operating temperature Storage temperature Symbol Topr Tstg DIP: Ta=-40 +85°C MFP: Ta=-40 +85°C Conditions Ratings +7.0 VDD+0.3
VDD+0.3
Unit
+125
Reommended Operating Conditions +85°C, VSS1, VSS2, VSS3 6.0V
Parameter Supply voltage range CKIN, DIN, COREN, CKPOL DSCTL highlevel input voltage OSC1 high-level input voltage CKIN, DIN, COREN, CKPOL DSCTL lowlevel input voltage low-level input voltage Symbol VIH1 VIH2 VIL1 VIL2 Conditions Ratings 0.7VDD 0.8VDD 13.5 0.3VDD
0.25VDD
Unit
Electrical Characteristics +85°C, VSS1, VSS2, VSS3 6.0V
Parameter CKIN, DIN, COREN, CKPOL DSCTL highlevel input current CKIN, DIN, COREN, CKPOL DSCTL lowlevel input current low-level input current DST, DOUT CKOUT high-level output voltage REC, COR, ERR, DST, DOUT CKOUT low-level output voltage REC, output leakage current hysteresis voltage Supply current Oscillator stabilization time Symbol IIH1 IIL1 IIL2 IOFF VHYS tCFS note figure VI=13.5V VI=VSS VI=VSS IOH=- 50µA IOH=- 10µA IOL=10mA IOL=1.8mA, note VO=13.5V VO=VSS 0.1VDD
VDD- VDD-
Conditions
Ratings
Unit
Note Idle pins have output currents less than 1mA. Oscillator running, VI=VDD, IO=0mA
No.3932-4/9
LC7073, 7073M
Timing Diagrams relationship between LC7073 LC7073M input data (RDS demodulated data output) output data shown figure
Figure Input output data Note dotted lines show data start (DST) pulses when data start control (DSTCTL) LOW. serial output data delayed block between input output. error (ERR) correction (COR) signals remain active errors detected continually. Serial Output Data Timing Format following list shows symbols used serial output data string figure Start (normally Error flag (See table Correction flag (See table Offset (normally used) Offset (normally used) Group. 0-group 1-group Block bits. 00-1st block, 01-2nd block, 10-3rd block, 11-4th block Output data
Table Error correction flags
Indication error Error corrected correctable
Note don't care
No.3932-5/9
LC7073, 7073M
Figure Serial output data format timing CKPOL Input Read Delay CKPOL read after reset shown figure
Figure CKPOL input read delay
No.3932-6/9
LC7073, 7073M
COREN DSTCTL Input Read COREN DSTCTL monitored intervals input clock cycle, their logic states changed time. During sync detection, change input state occurs either remains steady four successive clock intervals shown figure
Figure Input read during sync detection After sync detection change input state occurs either COREN DSTCTL remains steady four successive input data blocks shown figure
Figure Input read after sync detection Design Notes Oscillator specifications shown table figure Oscillator stabilization delay shown figure Reset input circuitry shown figure Supply rise time versus delay shown figure Table Oscillator capacitor values
resonator type Murata-CSA4.00MG Kyocera-KBR4.0M ±10% ±10%
OSC1
OSC2
Ceramic resonator
Figure Oscillator circuit
4.5V
tCFS tCFS oscillator stabilization time
Figure Oscillator stabilization delay
No.3932-7/9
LC7073, 7073M
C=0.1µF
Figure Reset input
Start point 4.5V 1.125V (0.25VDDmin) 0.8VDD
Oscillator stabilization time
Figure Supply rise time reset delay minimum delay should allowed oscillator stabilization. reset delay generated using reset capacitor, larger capacitor should used supply rise time longer.
Figure System block diagram Device Comparison LC7070N, LC7070M LC7071NM have identical basic functions, pinouts input/output timing those LC7073 LC7073M. Their respective packages output circuitry compared table Table Device comparison
Device LC7070N LC7070NM LC7071NM LC7073 LC7073M Package 18-pin 18-pin 18-pin 18-pin 18-pin Totem-pole using transistors Open-drain Output type
differences output data format between LC7070N/LC7070NM/LC7071NM LC7073/LC7073M follows. Offset Words LC7070N/LC7070NM/LC7071NM recognizes offset words performs group sync detection. LC7073/ LC7073M does recognize offset words F-it only detects Input Data Bits data bits LC7070N/LC7070NM/LC7071NM only recognizes offset word LC7073/LC7073M does recognize offset word block. sync detection occurs input data bits Once data cutoff been determined, output data stops sync cutoff sequence begins.
No.3932-8/9
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Sync Detection Method LC7070N/LC7070NM/LC7071NM searches consecutive blocks correct sequence within each group blocks. LC7073/LC7073M searches consecutive blocks correct sequence within each group blocks. Data Output After Sync Detection LC7070N/LC7070NM/LC7071NM starts data output with first block (offset directly after last block sync detection group. sync detection occurs during first block (offset LC7073/LC7073M starts data output with second block (offset sync detection occurs during second third block (offset finishes before fourth block (offset LC7073/LC7073M starts data output with first block (offset second group. Sync Error sync error occurs offset word detected more than five consecutive blocks. This applies both LC7070N/ LC7070NM/LC7071NM LC7073/LC7073M. Error Correction error-correction mode, error less than bits corrected accuracy bits. This applies both LC7070N/LC7070NM/LC7071NM LC7073/LC7073M. Precaution Note that solder-dip method should used LC7073M (MFP).
Specifications SANYO products described contained herein stipulate performance, characteristics, functions described products independent state, guarantees performance, characteristics, functions described products mounted customer's products equipment. verify symptoms states that cannot evaluated independent device, customer should always evaluate test devices mounted customer's products equipment. SANYO Electric Co., Ltd. strives supply high-quality high-reliability products. However, semiconductor products fail with some probability. possible that these probabilistic failures could give rise accidents events that could endanger human lives, that could give rise smoke fire, that could cause damage other property. When designing equipment, adopt safety measures that these kinds accidents events cannot occur. Such measures include limited protective circuits error prevention circuits safe design, redundant design, structural design. event that SANYO products(including technical data,services) described contained herein controlled under applicable local export control laws regulations, such products must expor without obtaining expor license from authorities concerned accordance with above law. part this publication reproduced transmitted form means, electronic mechanical, including photocopying recording, information storage retrieval system, otherwise, without prior written permission SANYO Electric Co., Ltd. information described contained herein subject change without notice product/technology improvement, etc. When designing equipment, refer "Delivery Specification" SANYO product that intend use. Information (including circuit diagrams circuit parameters) herein example only guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties.
This catalog provides information July, 2001. Specifications information herein subject change without notice.
No.3932-9/9

LC7073, 7073M Error Detection Correction Demodulators Prelim

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