MN102H55D/55G/F55G User's Manual Pub.No.22355-020E PanaXSeri
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MICROCOMPUTER MN102H00
MN102H55D/55G/F55G User's Manual
Pub.No.22355-020E
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About This Manual
This manual intended assembly-language programming engineers. describes internal configuration hardware functions MN102H55D/55G/F55G microcontrollers.
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Contents
Chapter General Description
Chapter Interface
Chapter Interrupts
Chapter Timers
Chapter Serial Interface
Chapter Analog Interface
Chapter ATC,
Chapter Ports
Chapter System Control
Chapter Low-power Modes
Chapter Appendix
Contents
Contents
Chapter
1-1-1 1-1-2 1-1-3
General Description
Introduction Feature Overview
General Description
Basic Specifications Block Diagram Description 1-4-1 1-4-2 1-4-3 1-4-4 1-4-5 1-4-6 1-4-7 1-4-8 1-4-9 1-4-10 Single-chip Mode Memory Expansion Mode with 8-bit Address/Data Separate Mode Memory Expansion Mode with 16-bit Address/Data Separate Mode Memory Expansion Mode with 8-bit Address/Data Shared Mode Memory Expansion Mode with 16-bit Address/Data Address/Data Shared Mode Processor Mode with 8-bit Address/Data Separate Mode Processor Mode with 16-bit Address/Data Separate Mode Processor Mode with 8-bit Address/Data Shared Mode Processor Mode with 16-bit Address/Data Shared Mode List Functions
Chapter
2-1-1 2-1-2 2-1-3 2-1-4
Interface
Overview Control Registers Memory Connection Examples Access External Memory
Summary Interface
Control Signals
2-2-1 2-3-1 2-4-1
Overview Overview Activation Sequence Each Mode
Handshake Wait Control Activation Sequence
Chapter
3-1-1
Interrupts
Overview
Interrupt Groups 3-1-2 Control Registers Interrupt Setup Examples 3-2-1 3-2-2 3-2-3 3-2-4 External Interrupt Setup Examples Input Interrupt Setup Examples Watchdog Timer Interrupt Setup Examples Watchdog Timer Interrupt Setup Examples
Chapter
4-1-1 4-1-2 4-1-3 4-2-1 4-2-2 4-2-3
Timers
Overview 8-bit Timer Control Registers 8-bit Timer Block Diagrams Event Counter Using 8-bit Timer Clock Output Using 8-bit Timer Interval Timer Using 8-bit Timer
Summary 8-bit Timer Functions
8-bit Timer Setup Examples
Summary 16-bit Timer Functions 4-3-1 Overview 4-3-2 4-3-3 16-bit Timer Control Registers 16-bit Timer Block Diagrams Event Counter Using 16-bit Timer One-phase Output Using 16-bit Timer Two-phase Output Using 16-bit Timer One-phase Capture Output Using 16-bit Timer
16-bit Timer Setup Examples 4-4-1 4-4-2 4-4-3 4-4-4
4-4-5 4-4-6 4-4-7 4-4-8 4-4-9 4-4-10 4-5-1 4-5-2
Two-phase Capture Input Using 16-bit Timer Two-phase Encoder Input (4x) Using 16-bit Timer Two-phase Encoder Input (1x) Using 16-bit Timer One-shot Pulse Using 16-bit Timer External Count Direction Control Using 16-bit Timer External Reset Control Using 16-bit Timer Overview Control Registers
Summary 8-bit Functions
8-bit Setup Examples 4-6-1 8-bit Output 16-bit Pulse Width Measure Functions 4-7-1 4-7-2 Overview Control Registers 16-bit Pulse Width Measure Counter
16-bit Pulse Width Counter Setup 4-8-1
Chapter
5-1-1 5-1-2 5-1-3 5-2-1 5-2-2 5-2-3 5-2-4 5-2-5
Serial Interface
Overview Control Registers Serial Interface Connection Serial Transmission Asynchronous Mode Serial Reception Synchronous Mode Serial Clock Operation Example Transmission Reception
Serial Interface
Serial Interface Setup Examples
Chapter
6-1-1 6-1-2
Analog Interface
Overview Control Registers
Summary Converter
Converter Setup Examples
6-2-1 6-2-2 6-3-1
Single Channel Conversion Three Channel Conversion Overview
Summary Converter 6-3-2 Control Registers Converter Setup Examples
Chapter
7-1-1 7-1-2 7-2-1 7-3-1 7-3-2 7-4-1 7-4-2 7-4-3
ATC,
Overview Control Registers Serial Reception Overview Control Registers Transfer from External Memory External Device Transfer from External Device External Memory (Burst Transfer) Transfer from External Device External Memory (One Byte Transfer)
Summary
Setup Examples Summary
Setup Examples
Chapter
8-1-1 8-1-2 8-1-3 8-2-1 8-3-1
Ports
Overview Control Registers Port Block Diagram General-purpose Port Setup Overview
Summary Ports
Port Setup Examples Summary Byte-swapped Registers
Chapter
9-1-1 9-1-2 9-1-3 9-2-1 9-2-2
System Control
Overview Control Registers Address Break Setup Examples Overview Control Registers
Address Break
System Related Register Protection
Chapter Low-power Modes
10-1 Summary Low-power Modes 10-1-1 10-1-2 10-1-3 10-1-4 Overview Transferring between SLOW Mode NORMAL Mode Switching Standby Mode
Mode Control Registers
Chapter Appendix
11-1 Electrical Characteristics 11-1-1 11-1-2 11-2-1 11-2-2 11-2-3 MN102H55D/55G MN102HF55G List Special Registers MN102H55D/55G/F55G Address List Functions
11-2 Data Appendix
11-3 Initialization Program 11-4 Flash EEPROM Version 11-4-1 11-4-2 11-4-3 11-4-4 11-4-5 11-4-6 11-4-7 Overview Flash EEPROM Programming PROM Writer Mode Onboard Serial Programming Mode Hardware Used Serial Programming Mode Connecting Onboard Serial Programming Mode System Configuration Onboard Serial Programming
11-4-8 11-4-9 11-4-10 11-4-11
Onboard Serial Programming Mode Setup Branch User Program Serial Interface Onboard Serial Programming PROM Writer/Onboard Serial Programming
11-5 List MN102H00 Series Linear Address High-speed Edition Instructions
List Figures
Figure 1-1-1 Figure 1-1-2 Figure 1-1-3 Figure 1-1-4 Figure 1-3-1 Figure 1-4-1 Figure 1-4-2 Figure 1-4-3 Figure 1-4-4 Figure 1-4-5 Figure 1-4-6 Figure 1-4-7 Figure 1-4-8 Figure 1-4-9 Figure 1-4-10 Figure 1-4-11 Figure 1-4-12 Figure 1-4-13 Figure 1-4-14 Figure 2-1-1 Figure 2-1-2 Figure 2-1-3 Figure 2-1-4 Figure 2-1-5
Processor Status Word (PSW) Address Space (Memory Expansion Mode) Interrupt Controller Configuration Interrupt Servicing Sequence Block Diagram Configuration Single-chip Mode Configuration Memory Expansion Mode with 8-bit Address/Data Separate Mode Configuration Memory Expansion Mode with 16-bit Address/Data Separate Mode Configuration Memory Expansion Mode with 8-bit Address/Data Shared Mode Configuration Memory Expansion Mode with 16-bit Address/Data Shared Mode Configuration Processor Mode with 8-bit Address/Data Separate Mode Configuration Processor Mode with 16-bit Address/Data Separate Mode Configuration Processor Mode with 8-bit Address/Data Shared Mode Configuration Processor Mode with 16-bit Address/Data Shared Mode OSCI, OSCO Connection Example Connection Example Reset Connection Example WAIT Signal Control Circuit Connection Example External Dimensions Address Space SRAM (Mask ROM) Connection Example (16-bit Width) SRAM (Mask ROM) Connection Example (8-bit Width) DRAM (2WE Method) Connection Example (16-bit Width) Burst Connection Example (8-bit Width)
Figure 2-1-6 Figure 2-1-7 Figure 2-1-8 Figure 2-3-1 Figure 2-3-2 Figure 2-4-1 Figure 3-1-1 Figure 3-1-2 Figure 3-1-3 Figure 3-2-1 Figure 3-2-2 Figure 3-2-3 Figure 3-2-4 Figure 3-2-5 Figure 3-2-6 Figure 3-2-7 Figure 3-2-8 Figure 4-1-1 Figure 4-1-2 Figure 4-1-3 Figure 4-1-4 Figure 4-1-5 Figure 4-1-6 Figure 4-1-7 Figure 4-1-8 Figure 4-1-9 Figure 4-1-10 Figure 4-1-11 Figure 4-1-12 Figure 4-2-1 Figure 4-2-2 Figure 4-2-3
DRAM Connection Example (8-bit Width) External Access Wait Cycle) External Access (0.5 Wait Cycle) Handshake Wait Control Timing Wait Cycles, Data Write) Fixed Wait Handshake Wait Control Timing Wait Cycle Fixed Wait, Wait Cycles Whole Wait, Data Write) Activation Sequence Each Mode Interrupt Controller Block Diagram Watchdog Timer Block Diagram Interrupt Servicing Time External Interrupt Block Diagram External Interrupt Timing Input Interrupt Block Diagram Input Interrupt Timing Input Interrupt Timing Watchdog Timer Interrupt Block Diagram Watchdog Timer Interrupt Timing Extended Watchdog Timer Interrupt Timing 8-bit Timer Block Diagram Timer Configuration 8-bit Event Counter Input Timing 8-bit Timer Output Interval Timer Timing Timer Block Diagram Timer Block Diagram Timer Block Diagram Timer Block Diagram Timer Block Diagram Timer Block Diagram Timer Block Diagram Timer Block Diagram Event Counter Block Diagram Event Counter Timing Clock Output Configuration Example (8-bit Timer)
Figure 4-2-4 Figure 4-2-5 Figure 4-2-6 Figure 4-2-7 Figure 4-2-8 Figure 4-3-1 Figure 4-3-2 Figure 4-3-3 Figure 4-3-4 Figure 4-3-5 Figure 4-3-6 Figure 4-3-7 Figure 4-3-8 Figure 4-3-9 Figure 4-3-10 Figure 4-3-11 Figure 4-3-12 Figure 4-3-13 Figure 4-3-14 Figure 4-3-15 Figure 4-3-16 Figure 4-4-1 Figure 4-4-2 Figure 4-4-3 Figure 4-4-4 Figure 4-4-5 Figure 4-4-6 Figure 4-4-7 Figure 4-4-8 Figure 4-4-9 Figure 4-4-10 Figure 4-4-11 Figure 4-4-12
Clock Output Block Diagram (8-bit Timer) Clock Output Timing (8-bit Timer) Interval Timer Configuration Example (8-bit Timer) Interval Timer Block Diagram (8-bit Timer) Interval Timer Timing (8-bit Timer) 16-bit Timer Block Diagram One-phase Output Timing One-phase Output Timing (with Data Rewrite) Two-phase Output Timing One-shot Pulse Output Timing External Control Timing Event Counter Input Timing Input Capture Timing Input Capture Timing Two-phase Encoder (4x) Timing Two-phase Encoder (1x) Timing Timer Block Diagram Timer Block Diagram Timer Block Diagram Timer Block Diagram Timer Block Diagram Event Counter Block Diagram Event Counter Timing (16-bit Timer) One-phase Output Block Diagram (16-bit Timer) One-phase Output Timing (16-bit Timer) One-phase Output Timing (16-bit Timer) (Dynamical Duty Change) Two-phase Output Block Diagram (16-bit Timer) Two-phase Output Timing (16-bit Timer) Two-phase Output Timing (16-bit Timer) (Dynamical Duty Change) One-phase Capture Input Block Diagram (16-bit Timer) One-phase Capture Input Timing (16-bit Timer) Two-phase Capture Input Block Diagram (16-bit Timer) Two-phase Capture Input Timing (16-bit Timer)
Figure 4-4-13 Figure 4-4-14 Figure 4-4-15 Figure 4-4-16 Figure 4-4-17 Figure 4-4-18 Figure 4-4-19 Figure 4-4-20 Figure 4-4-21 Figure 4-4-22 Figure 4-4-23 Figure 4-4-24 Figure 4-4-25 Figure 4-4-26 Figure 4-4-27 Figure 4-5-1 Figure 4-5-2 Figure 4-6-1 Figure 4-6-2 Figure 4-6-3 Figure 4-7-1 Figure 4-7-2 Figure 4-8-1 Figure 4-8-2 Figure 5-1-1 Figure 5-1-2 Figure 5-1-3 Figure 5-1-4 Figure 5-1-5 Figure 5-1-6 Figure 5-1-7 Figure 5-1-8 Figure 5-2-1 Figure 5-2-2
Two-phase Encoder Input (4x) Block Diagram (16-bit Timer) Two-phase Encoder Input (4x) Configuration Example Two-phase Encoder Input (4x) Configuration Example Two-phase Encoder Input Timing (4x) (16-bit Timer) Two-phase Encoder Input (1x) Block Diagram (16-bit Timer) Two-phase Encoder Input (1x) Configuration Example Two-phase Encoder Input (1x) Configuration Example Two-phase Encoder Input Timing (1x) (16-bit Timer) One-shot Pulse Output Block Diagram (16-bit Timer) One-shot Pulse Output Timing (16-bit Timer) External Count Direction Control Block Diagram (16-bit Timer) External Count Direction Control Configuration Example External Count Direction Control Timing (16-bit Timer) External Reset Control Block Diagram (16-bit Timer) External Reset Control Timing (16-bit Timer) 8-bit Function Output Waveform 8-bit Block Diagram Timer Timing 8-bit Timing 16-bit Pulse Width Measure Counter 16-bit Pulse Width Measure Counter Operation Example 16-bit Pulse Width Measure Counter Block Diagram 16-bit Pulse Width Measure Counter Timing Serial Interface Configuration Synchronous Mode Connections Asynchronous Mode Connections Mode Connections Asynchronous Serial Timing (Transmission) Asynchronous Serial Timing (Reception) Synchronous Serial Timing (Transmission) Synchronous Serial Timing (Reception) Asynchronous Transmission Block Diagram Asynchronous Transmission Timing
Figure 5-2-3 Figure 5-2-4 Figure 5-2-5 Figure 5-2-6 Figure 5-2-7 Figure 5-2-8 Figure 6-1-1 Figure 6-1-2 Figure 6-1-3 Figure 6-1-4 Figure 6-1-5 Figure 6-1-6 Figure 6-1-7 Figure 6-2-1 Figure 6-2-2 Figure 6-2-3 Figure 6-2-4 Figure 6-2-5 Figure 6-2-6 Figure 6-3-1 Figure 6-4-1 Figure 6-4-2 Figure 7-1-1 Figure 7-2-1 Figure 7-2-2 Figure 7-3-1 Figure 7-4-1 Figure 7-4-2 Figure 7-4-3 Figure 7-4-4
Synchronous Reception Block Diagram Clock Generation Synchronous Reception Serial Clock Block Diagram Serial Clock Timing Master Transmission Timing (with ACK) Master Reception Timing Analog Interface Configuration Converter Timing Single Channel/Single Conversion Timing
Multiple Channels/Single Conversion Timing Single Channel/Continuous Conversion Timing Multiple Channels/Continuous Conversion Timing Converter Block Diagram Analog Voltage Input Example Single Channel Conversion Block Diagram Single Channel Conversion Timing 3-channel Conversion Configuration 3-channel Conversion Block Diagram 3-channel Conversion Timing Converter Configuration Analog Voltage Output Example Conversion Block Diagram Using Channel Acquisition Timing Serial Reception Block Diagram Serial Reception Sequence Acquisition Timing External Memory External Device Transfer Block Diagram External Memory External Device Transfer Connection External Memory External Device Burst Transfer Timing External Device External Memory (Burst) Transfer Block Diagram
Figure 7-4-5 Figure 7-4-6 Figure 7-4-7 Figure 7-4-8 Figure 7-4-9
External Device External Memory (Burst) Transfer Configuration External Device External Memory Burst Transfer Timing External Device External Memory (One Byte) Transfer Block Diagram External Device External Memory (One Byte) Transfer Connection External Device External Memory (One Byte) Transfer Timing
Figure 8-1-1 Figure 8-2-1 Figure 8-2-2 Figure 8-2-3 Figure 8-3-1 Figure 9-1-1 Figure 9-1-2 Figure 9-1-3 Figure 9-1-4 Figure 10-1-1 Figure 10-1-2 Figure 10-1-3 Figure 11-1-1 Figure 11-1-2 Figure 11-1-3 Figure 11-1-4 Figure 11-1-5 Figure 11-1-6 Figure 11-1-7
Port Configuration General-purpose Port Setup Example Basic Flowchart General-purpose Port Input Basic Flowchart General-purpose Port Output Byte-swapped Register Address Break Block Diagram Address Break Operation Example Program Flow Address Break Setup Stack State after Interrupt Operating Mode Changes Operating Mode Control Clock Oscillation On/Off Sequence Switching to/from Standby Mode System Clock Timing Reset Timing Voltage Rise Timing Data Transfer Signal Timing (Address/Data Separate, without Wait, Read/Write) Data Transfer Signal Timing (Address/Data Separate, with Wait (1.5 More), Read/Write) Data Transfer Signal Timing (Address/Data Separate, with Wait (1.5 More), Late, Short Mode) Data Transfer Signal Timing (Address/Data Separate, with Wait (1.5 More), Late, Short Mode)
Figure 11-1-8 Figure 11-1-9 Figure 11-1-10
Data Transfer Signal Timing (Address/Data Shared, without Wait, Read/Write) Data Transfer Signal Timing (Address/Data Shared, with Wait (1.5 More), Read/Write) Data Transfer Signal Timing (Address/Data Shared, with Wait (1.5 More), Late, Long Mode, Long Mode, Read)
Figure 11-1-11
Data Transfer Signal Timing (Address/Data Shared, with Wait (1.5 More), Late, Long Mode, Long Mode, Write) Authority Request Signal Timing Interrupt Signal Timing Serial Interface Signal Timing (Synchronous Serial Transmission: Transfer Progress) Serial Interface Signal Timing (Synchronous Serial Transmission: Transfer Timing Input) Serial Interface Signal Timing (Synchronous Serial Transmission: Transfer Timing Output) Serial Interface Signal Timing (Synchronous Serial Reception: Transfer Timing Input) Timer/Counter Signal Timing Memory Flash EEPROM Version Flash EEPROM Program Flow 8-bit Serial Interface Block Diagram Serial Writer Flash EEPROM Memory Space Configuration During Serial Programming System Configuration Onboard Serial Writer Target Board-Serial Writer Connection Timing Onboard Serial Programming Mode Load Program Start Flow Reset Service Routine Flow Interrupt Service Routine Flow Data Transfer Timing Programming Flow
Figure 11-1-12 Figure 11-1-13 Figure 11-1-14 Figure 11-1-15 Figure 11-1-16 Figure 11-1-17 Figure 11-1-18 Figure 11-4-1 Figure 11-4-2 Figure 11-4-3 Figure 11-4-4 Figure 11-4-5 Figure 11-4-6 Figure 11-4-7 Figure 11-4-8 Figure 11-4-9 Figure 11-4-10 Figure 11-4-11 Figure 11-4-12 Figure 11-4-13
List Tables
Table 1-1-1 Table 1-2-1 Table 1-3-1 Table 1-4-1 Table 2-1-1 Table 2-1-2 Table 2-1-3 Table 2-1-4 Table 2-1-5 Table 2-1-6 Table 2-1-7 Table 2-1-8 Table 2-1-9 Table 2-1-10 Table 2-2-1 Table 2-2-2 Table 2-2-3 Table 2-2-4 Table 2-2-5 Table 2-2-6 Table 2-2-7 Table 3-1-1 Table 3-1-2 Table 3-1-3 Table 3-1-4
Memory Modes Basic Specifications Block Functions List Functions Mode Setting List Interface Control Registers Address/Data Multiplex Mode (16-bit Data Access) Address/Data Multiplex Mode (8-bit Data Access) Address/Data Separate Mode (16-bit Data Access) Address/Data Separate Mode (8-bit Data Access) Address/Data Separate Mode (16-bit DRAM Method) Address/Data Separate Mode (8-bit DRAM Method) Address/Data Separate Mode (16-bit Burst Access) Address/Data Separate Mode (8-bit Burst Access) External Memory Control Signal Timing Late Short Modes (Address/Data Shared Mode) Late Short Modes (Address/Data Shared Mode) Late Short Modes (Address/Data Separate Mode) Late Short Modes (Address/Data Separate Mode) Late Long Modes (Address/Data Shared Mode) Long Mode (Address/Data Shared Mode) Comparison MN102H55D/55G/F55G MN102B00/MN102L00 Interrupt Vector Class Assignment Handler Preprocessing Handler Postprocessing
Table 3-1-5 Table 4-1-1 Table 4-1-2 Table 4-3-1 Table 4-3-2 Table 4-5-1 Table 4-5-2 Table 4-7-1 Table 5-1-1 Table 5-1-2 Table 5-1-3 Table 5-2-1 Table 6-1-1 Table 6-1-2 Table 6-3-1 Table 6-3-2 Table 7-1-1 Table 7-1-2 Table 7-3-1 Table 7-3-2 Table 8-1-1 Table 8-1-2 Table 10-1-1 Table 11-4-1
List Interrupt Control Registers 8-bit Timer Functions List 8-bit Timer Control Registers 16-bit Timer Functions List 16-bit Timer Control Registers 8-bit Functions List 8-bit Registers List 16-bit Pulse Width Measure Registers Serial Interface Functions List Serial Interface Control Registers Baud Rate Setting Example Asynchronous Mode Transfer Clock Setup Example Converter Functions List Converter Control Registers Converter Functions List Converter Control Registers Functions List Control Registers Connection Examples List Control Registers List Port Control Registers Port Block Diagrams Watchdog Interrupt Interval Clock Frequency
Chapter General Description
Chapter General Description
1-1-1
General Description
Introduction
16-bit MN102 series high-speed linear addressing version designs architecture C-language programming based detailed analysis embedded applications. This improves previous system architecture speed function meet requirements user systems including miniaturization power consumption.
This series adapts load/store architecture method computing within registers instead accumulator system computing within memory space previous series. basic instructions byte/one machine cycle. This reduces code size improves compiler efficiency. This series uses circuit designed submicron technology providing optimized hardware system power consumption. This series Mbytes linear address space develop highly efficient programs. optimized hardware architecture allows lower power consumption even large systems.
1-1-2
Features
This series contains flexible optimized hardware architecture well simple efficient instruction set. This allows economy speed. This section describes features this series CPU. High-speed Signal Processing
internal multiplier operates 16-bit x16-bit 32-bit single cycle. addition, hardware contains saturation calculator which must used signal processing increases signal processing speed.
Linear Addressing Large Systems
MN102H series contains Mbytes linear address space. does detect borders between address spaces, which provides effective development environment. hardware architecture also optimized large systems. memory divided into instruction areas data areas that operations share instructions.
MN102H55D/55G/F55G
Chapter General Description
Single-byte Basic Instruction Length
Conventional Register Assignment
MN102H series replaced general registers with eight internal registers divided four address registers (A0-A3) four data registers (D0-D3). register specification fields four bits less, code size basic instructions including register-to register operations load/store operations byte.
Register Specification Field
Register Specification Field
Register Assignement
High-speed Pipeline Processing
MN102H series executes instructions 3-stage pipeline: fetch, decode, execute. This allows MN102H series execute instructions single byte machine cycle.
Machine Cycle
Instruction
Fetch
Decode Address calculation Execute
Instruction
Fetch
Decode Address calculation Execute
Simple Instruction
MN102H series uses instruction instructions, designed specially programming model embedded applications. shrink code size, instructions have variable length seven bytes. most frequently used instructions C-language compiler single byte.
High-speed Interrupt Response
Main Program
MN102H series halts instructions execution even during execution instruction with long execution cycles. After interrupt occurs, program moves interrupt service routine within cycles less. MN102H series improves real-time control performance using interrupt handler which adjusts interrupt servicing speed.
Instruction
Interrupt Service Routine
Instruction Interrupt Request
Instruction
Instruction
MN102H55D/55G/F55G
Chapter General Description
Flexible Interrupt Control Structure
interrupt controller supports maximum interrupt vectors them, interrupt vectors reserved nonmaskable interrupts). addition, groups four vectors assigned classes. Each class seven priority levels. This provides software design flexibility control. compatible with software from previous Panasonic peripheral modules.
High-speed, High-functional External Interface
MN102H series supports external interface functions including DMA, handshake function arbitration.
C-language Development Environment
MN102H series simple hardware optimized C-language programming highly efficient compiler. With this advantage, this series improves development environment C-language embedded applications without expanding program size. PanaXSeries development tools support MN102H series devices.
Outstanding Power Savings
MN102H series contains separate buses instructions, data peripheral functions, which distribute reduce load capacitance. This reduces overall power consumption. MN102H series also supports three modes SLOW, HALT STOP power savings.
PanaXSeries trademark Matsushita Electric Industrial Co., Ltd.
MN102H55D/55G/F55G
Chapter General Description
1-1-3
Overview
This section describes basic configuration functions MN102H55D/55G/F55G. Processor Status Word (PSW)
register contains operating result flags interrupt mask level flags.
Note Note
Note These bits change depending bits operation result. Note These bits change depending lower bits operation result. flag should before IM[2:0] flags changed.
Reset
Zero flag (ZF) lower bits operation result otherwise reset. Negative flag (NF) operation result otherwise reset. Carry flag (CF) operation resulted carry borrow otherwise reset.
Overflow flag (VF) operation causes sign change 16-bit signed number; otherwise reset. Extension zero flag (ZX) bits operation result otherwise reset. Extension negative flag (NX) operation result reset Extension carry flag (CX) operation resulted carry borrow MSB; otherwise reset.
Extension overflow flag (VX) operation causes sign change 24-bit signed number; otherwise reset. IM[2:0] indicate mask level (from interrupts that will accept from seven interrupt input pins. will accept interrupt higher level than indicated level here. Interrupt enable flag (IE) controls maskable interrupt enable. flag IE=1, reset IE=0. S[1:0] software control bits. These reserved Saturation flag controls whether performs saturation operation. When this execute saturate operation. When this operates normal operation. PXST instruction reserve meaning this next instruction.
Figure 1-1-1 Processor Status Word (PSW)
Please refer "11-5 MN102H00 series High-speed Linear Address Instruction Set" flags reflected instructions.
MN102H55D/55G/F55G
Chapter General Description
Internal Registers, Memory, Special Function Registers
Program Counter
program counter specifies 24-bit address program during execution.
Address Registers
address registers specify data location memory. four registers, assigned stack pointer.
Data Registers
data registers perform arithmetic logic operations. When byte-length (8-bit) word-length (16-bit) data transferred memory another register, instruction adds zero sign extension.
Multiplication/Division Register
multiplication/division register stores upper bits 32-bit product multiplication operations. division operations, this register stores upper bits 32-bit dividend before execution, 16-bit remainder quotient after execution.
Processor Status Word
Memory, Special Function Registers, Ports
Internal Control Registers Interrupt Control Registers Serial Interfacel Registers Converter Registers Timer/Counter Registers Memory Control Registers Port Registers This allocation example. Actual memory, peripheral functions, special function registers port allocation depends model. Memory (ROM, RAM), special function registers peripheral function control ports assigned same address space.
CPUM, EFCR, IAGR NMICR, xxICR SCCTRn, TRXBUFn, SCSTRn ANCTR, ANnBUF TMn, BCn, MEMMD PnOUT, PnIN, PnDIR
MN102H55D/55G/F55G
Address Space
memory contains Mbytes linear address space. instruction data areas separated, that internal RAM, special function registers internal peripheral functions allocated into first kbytes memory basic configuration. There three memory modes following depending models.
x'000000' x'008000' Internal x'009000' (*4) Reserved x'00FC00' x'010000'
External Memory
Control Registers
External Memory Program start address x'080000' Interrupt handler start address x'080008' x'0A0000' (*2) x'200000' x'080000' Internal
Reserved
External Memory
x'FFFFFF'
Note*) Parameters right table differ each chip model.
MN102HF55G KBytes MN102H55G KBytes MN102H55D KBytes
x'0A0000' x'0A0000' x'090000'
Figure 1-1-2 Address Space (Memory Expansion Mode)
Kbytes (*3) Kbyte Mbytes Kbytes (*1) 4096 Bytes 4096 Bytes 4096 Bytes x'009000' x'009000' x'009000' External Memory Access accessible Accessible MN102H55D/55G/F55G
Chapter General Description
Table 1-1-1 Memory Modes
Mode Single-chip mode Memory expansion mode Processor mode bits None Address Width Capacity k/128 kbytes
Chapter General Description
Interrupt Controller
interrupt controller allocated outside core controls nonmaskable maskable interrupts except reset. Each class four interrupt vectors specifies seven priority levels.
Core
Maskable Interrupt Receive
Interrupt Enable
Nonmaskable Interrupt Receive
Reset Receive
Reset
Interrupt Controller
Nonmaskable interrupts Groups Nonmaskable Interrupt Controllers
Nonmaskable Interrupt Control Register (NMICR)
Interrupt Masking
(WDICR) (UNICR) (EIICR)
External input Watchdog timer Undefined instruction vector exists when interrupt occurs.
Group Maskable Interrupt Controller
Maskable Interrupt Control Register (xxICH)
Maskable interrupts Max. vectors External interrupts Peripheral interrupts
Group Maskable Interrupt Controller
Maskable Interrupt Control Register (xxICH)
hardware configuration interrupt controller depends model.
Figure 1-1-3 Interrupt Controller Configuration
checks processor status word determine whether interrupt request accepted not. interrupt accepted, automatic servicing hardware starts program counter pushed stack. Next, program moves interrupt, searches interrupt vector branches entry address interrupt service routine that interrupt.
Interrupt preprocessing
Push registers, branch entry address, etc. Main program x'080008' Interrupt service routine Resets interrupt vector beginning JMP, etc.
Hardware processing Push
Interrupt
Max. machine cycles machine cycles
Figure 1-1-4 Interrupt Servicing Sequence
MN102H55D/55G/F55G
Chapter General Description
Basic Specification
Table 1-2-1 Basic Specifications
Structure
Internal multiplier internal saturate operation calculator Load/store architecture Eight registers: Four 24-bit data registers Four 24-bit address registers Others: 24-bit program counter 16-bit processor status word 16-bit multiplication/division register
Instruction
instructions addressing modes 1-byte basic instruction length Code assignment: byte (basic) bytes (extension)
Performance
Maximum 17-MHz internal operating frequency with 34-MHz external oscillator MN102H55D/55G Maximum 15-MHz internal operating frequency with 30-MHz external oscillator MN102HF55G Instruction execution clock cycles: register-to-register operations, minimum cycle branch operations, minimum cycles load/store operations, minimum cycle
Pipeline Address Space Interrupt
stage: instruction fetch, decode, execute 16-Mbyte linear address space Shared instruction/data space external nonmaskable interrupt maskable interrupts priority level settings
Low-power Mode Oscillation Frequency Timer/Counter
SLOW, STOP, HALT Eight 8-bit timers (TM0 TM7) Cascading function (form 16-bit 64-bit timer) Timer output Internal clock source external clock source Serial Interface clock generation Start timing generation converter
MN102H55D/55G/F55G
Chapter General Description
Table 1-2-1 Basic Specifications Timer/Counter Five 16-bit timers (TM8 TM12) channels compare/capture registers Selectable internal external clock PWM/one-shot pulse output Two-phase encoder input method) 8-bit (TM13, TM14) internal compare registers each channel pattern outputs 16-bit pulse width counter (TM15) Capture counter value whenever input pulse rises 16-bit watchdog timer Four Channels Automatic transfer possible between memories, memory peripheral each interrupt vector. Transfer unit: byte word Transfer mode: single-chip burst mode Transfer addressing: source, destination pointer, increment 4096 words transferred Access 16-Mbyte address space Channels Automatic transfer possible between external device external memory. Transfer unit: byte word Transfer mode: single-chip burst mode Transfer addressing: source, destination pointer, increment 4096 words transferred Access 16-Mbyte address space Serial Interface Converter Converter External Expansion Memory Interface Port Three Synchronous Interfaces (ASCI0 ASCI2) shared UART/Synchronous/I2C (single master only) Interfaces (ASCI3, ASCI4) 10-bit with channels (can used 8-bit) Automatic Scanning 8-bit channels Address/data multiplex port function Address/data separate port function DRAM Interface (8-bit/16-bit width) Burst Interface Maximum ports single-chip mode Maximum ports address/data multiplex mode Maximum ports address/data separate mode Package 100-pin LQFP
MN102H55D/55G/F55G
Chapter General Description
Block Diagram
Address Registers Data Registers
Multiplier Program Counter Incrementer
Multiplication/Division Register
Clock Generator
Clock Source
Instruction Execution Controller Instruction Decoder
Instruction Queue Program Address Operand Address
Interrupt Controller Interrupt
Controller
Peripheral Execution
External Interface Internal Internal External Extension Internal Peripheral Functions
Figure 1-3-1 Block Diagram
MN102H55D/55G/F55G
Chapter General Description
Table 1-3-1 Block Functions
Blcok Clock Generator Program Counter
Function oscillation circuit connected external crystal supplies clock blocks CPU. program counter generates addresses instruction queues. Normally increments based sequencer indications, branch instructions interrupt acceptance, sets branch address operation result. instruction queue contains four bytes prefetched instructions. instruction decoder decodes contents instruction queue generates control signals needed instruction execution. instruction executes controlling each block CPU. quick decoder decodes 2-byte larger instruction faster speed. instruction execution controller controls operations based results from instruction decoder interrupt requests. calculates operand addresses arithmetic operations, logic operations, shift operations, register relative indirect addressing, indexed addressing, register indirect addressing. multiplier calculates bits bits bits. These memory allocate program, data stack areas. address registers (An) store addresses memory accessed during data transfer. They also store base addresses register relative indirect addressing, indexed addressing register indirect addressing modes. data registers (Dn) store data transferred memory results arithmetic operations. They also store offset addresses indexed addressing register indirect addressing modes. multiplication/division register (MDR) stores data multiplication/division operations. processor status word register stores flags that indicate status interrupt controller operation results. interrupt controller detects interrupt requests from peripheral functions, requests move interrupt servicing routine. Controller controls connection between internal external bus. also contains arbitration function. MN102H55D/55G/F55G contains internal peripheral functions including timers, serial interface, converter converters. Internal peripheral functions vary depending chip models.
Instruction Queue Instruction Decoder
Quick Decoder Instruction Execution Controller
Multiplier Internal Address Registers (An)
Operation Registers
Interrupt Controller Controller Internal Peripheral Function
MN102H55D/55G/F55G
Chapter General Description
1-4-1
Description
Single-chip Mode
P86,TM9IOB,SBI4 VREF+ P85,TM9IOA,SBT4,SCL4,SBO2 P84,TM7IO,SBO3,SDA3
P93,TM10IC P92,TM10IOB P91,TM10IOA,BIBT2
P87,TM9IC,SBO4,SDA4
P90,TM8IOA,BIBT1
P74,SBI1 P73,SBT1 P72,SBO0 P71,SBI0
P75,SBO1
P97,AN3
PA0,IRQ0 PA1,IRQ1 PA2,IRQ2 PA3,IRQ3 PA4,IRQ4,TM15IB P10,TM8IOB P11,TM8IC P12,TM11IOA P13,TM11IOB P14,TM11IC P15,TM12IOA P16,TM12IOB P17,TM12IC
P83,TM4IO,SBI3
P70,SBT0 (Vpp)
P96,AN2 P95,AN1 P94,AN0 AVSS
MN102H55D MN102H55G MN102HF55G (TOP VIEW)
P82,TM0IO,SBT3,SCL3,SBI2 P81,DAC1 P80,DAC0 P47,AN7,WDOUT P46,AN6,STOP P45,AN5 P44,AN4 VREFP43 P37, P36, P35, P34, AVDD P33, P32, P31, P30, P24,TM15IA
P60,SBT2
P51,TM13OB P52,TM14OA P53,TM14OB
P50,TM13OA
XI,PB1
P56,BSTRE,TM15IA P20,SBT2 P21,SBI2 P22,SBO2
BOSC,PB0,BIBT1,BIBT2
Figure 1-4-1 Configuration Single-chip Mode
Unused pins require handling circuit (input pins connected VDD/VSS, output pins leave open, input/output pins connected VDD/VSS leave open depending direction setting).
OSCI OSCO (MODE)
MN102H55D/55G/F55G
Chapter General Description
1-4-2
Memory Expansion Mode with 8-bit Address/ Data Separate Mode
P93,TM10IC,DMAACK0 P92,TM10IOB,DMAREQ0 P91,TM10IOA,BIBT2,DMAACK1 P86,TM9IOB,SBI4 VREF+ P85,TM9IOA,SBT4,SCL4,SBO2 P84,TM7IO,SBO3,SDA3
P90,TM8IOA,BIBT1,DMAREQ1
P74,SBI1 P73,SBT1,DMUX P72,SBO0 P71,SBI0,LCAS,CAS
P87,TM9IC,SBO4,SDA4
P75,SBO1
P70,SBT0,RAS (Vpp)
P97,AN3
PA0,IRQ0 PA1,IRQ1 PA2,IRQ2 PA3,IRQ3 PA4,IRQ4,TM15IB (ADSEP) P10,TM8IOB P11,TM8IC P12,TM11IOA P13,TM11IOB P14,TM11IC P15,TM12IOA P16,TM12IOB P17,TM12IC
P83,TM4IO,SBI3
P96,AN2 P95,AN1 P94,AN0 AVSS
MN102H55D MN102H55G MN102HF55G (TOP VIEW)
P82,TM0IO,SBT3,SCL3,SBI2 P81,DAC1 P80,DAC0 A23,P47,AN7,WDOUT A22,P46,AN6,STOP A21,P45,AN5 A20,P44,AN4 VREFA19,P43 A18,P42 A17,P41 A16,P40 A15,P37, A14,P36, A13,P35, A12,P34, AVDD A11,P33, A10,P32, A9,P31, A8,P30, A7,P27 A6,P26 A5,P25 A4,P24,TM15IA
P60,WAIT,SBT2 RE,P61
P51,CS1,TM13OB P52,CS2,TM14OA P53,CS3,TM14OB P54,BREQ P55,BRACK P56,BSTRE,TM15IA (WORD) A0,P20,SBT2 A1,P21,SBI2 A2,P22,SBO2 A3,P23
XI,PB1
BOSC,PB0,BIBT1,BIBT2
WEL,P62 WE,P63
P50,CS0,TM13OA
Figure 1-4-2 Configuration Memory Expansion Mode with 8-bit Address/Data Separate Mode
Unused pins require handling circuit (input pins connected VDD/VSS, output pins leave open, input/output pins connected VDD/VSS leave open depending direction setting).
MN102H55D/55G/F55G
OSCI OSCO (MODE)
Chapter General Description
1-4-3
Memory Expansion Mode with 16-bit Address/Data Separate Mode
P93,TM10IC,DMAACK0 P92,TM10IOB,DMAREQ0 P91,TM10IOA,BIBT2,DMAACK1 P86,TM9IOB,SBI4 VREF+ P85,TM9IOA,SBT4,SCL4,SBO2 P84,TM7IO,SBO3,SDA3
P90,TM8IOA,BIBT1,DMAREQ1
P74,SBI1 P73,SBT1,DMUX P72,SBO0,UCAS P71,SBI0,LCAS,CAS
P87,TM9IC,SBO4,SDA4
P75,SBO1
P70,SBT0,RAS (Vpp)
P97,AN3
PA0,IRQ0 PA1,IRQ1 PA2,IRQ2 PA3,IRQ3 PA4,IRQ4,TM15IB (ADSEP)
P83,TM4IO,SBI3
P96,AN2 P95,AN1 P94,AN0 AVSS
MN102H55D MN102H55G MN102HF55G (TOP VIEW)
P82,TM0IO,SBT3,SCL3,SBI2 P81,DAC1 P80,DAC0 A23,P47,AN7,WDOUT A22,P46,AN6,STOP A21,P45,AN5 A20,P44,AN4 VREFA19,P43 A18,P42 A17,P41 A16,P40 A15,P37, A14,P36, A13,P35, A12,P34, AVDD A11,P33, A10,P32, A9,P31, A8,P30, A7,P27 A6,P26 A5,P25 A4,P24,TM15IA
P60,WAIT,SBT2 RE,P61
P51,CS1,TM13OB P52,CS2,TM14OA P53,CS3,TM14OB P54,BREQ P55,BRACK P56,BSTRE,TM15IA (WORD) A0,P20,SBT2 A1,P21,SBI2 A2,P22,SBO2 A3,P23
XI,PB1
BOSC,PB0,BIBT1,BIBT2
WEL,P62 WE,WEH,P63
P50,CS0,TM13OA
OSCI OSCO (MODE)
Figure 1-4-3 Configuration Memory Expansion Mode with 16-bit Address/Data Separate Mode
Unused pins require handling circuit (input pins connected VDD/VSS, output pins leave open, input/output pins connected VDD/VSS leave open depending direction setting).
MN102H55D/55G/F55G
Chapter General Description
1-4-4
Memory Expansion Mode with 8-bit Address/Data Shared Mode
P93,TM10IC,DMAACK0 P92,TM10IOB,DMAREQ0 P91,TM10IOA,BIBT2,DMAACK1 P86,TM9IOB,SBI4 VREF+ P85,TM9IOA,SBT4,SCL4,SBO2 P84,TM7IO,SBO3,SDA3
P90,TM8IOA,BIBT1,DMAREQ1
P74,SBI1 P73,SBT1,DMUX P72,SBO0 P71,SBI0,LCAS,CAS
P87,TM9IC,SBO4,SDA4
P75,SBO1
P97,AN3
PA0,IRQ0 PA1,IRQ1 PA2,IRQ2 PA3,IRQ3 PA4,IRQ4,TM15IB (ADSEP) P10,TM8IOB P11,TM8IC P12,TM11IOA P13,TM11IOB P14,TM11IC P15,TM12IOA P16,TM12IOB P17,TM12IC
P83,TM4IO,SBI3
P70,SBT0,RAS (Vpp)
P96,AN2 P95,AN1 P94,AN0 AVSS
MN102H55D MN102H55G MN102HF55G (TOP VIEW)
P82,TM0IO,SBT3,SCL3,SBI2 P81,DAC1 P80,DAC0 A23,P47,AN7,WDOUT A22,P46,AN6,STOP A21,P45,AN5 A20,P44,AN4 VREFA19,P43 A18,P42 A17,P41 A16,P40 A15,P37, A14,P36, A13,P35, A12,P34, AVDD A11,P33, A10,P32, A9,P31, A8,P30, P24,TM15IA
P60,WAIT,SBT2 RE,P61
P51,CS1,TM13OB P52,CS2,TM14OA P53,CS3,TM14OB P54,BREQ P55,BRACK ALE,ALE
XI,PB1
BOSC,PB0,BIBT1,BIBT2
WEL,P62 WE,P63
P50,CS0,TM13OA
(WORD) P20,SBT2 P21,SBI2 P22,SBO2
OSCI OSCO (MODE)
Figure 1-4-4 Configuration Memory Expansion Mode with 8-bit Address/Data Shared Mode
Unused pins require handling circuit (input pins connected VDD/VSS, output pins leave open, input/output pins connected VDD/VSS leave open depending direction setting).
MN102H55D/55G/F55G
Chapter General Description
1-4-5
Memory Expansion Mode with 16-bit Address/Data Shared Mode
P93,TM10IC,DMAACK0 P92,TM10IOB,DMAREQ0 P91,TM10IOA,BIBT2,DMAACK1 P86,TM9IOB,SBI4 VREF+ P85,TM9IOA,SBT4,SCL4,SBO2 P84,TM7IO,SBO3,SDA3
P90,TM8IOA,BIBT1,DMAREQ1
P74,SBI1 P73,SBT1,DMUX P72,SBO0,UCAS P71,SBI0,LCAS,CAS
P87,TM9IC,SBO4,SDA4
P75,SBO1
P97,AN3
PA0,IRQ0 PA1,IRQ1 PA2,IRQ2 PA3,IRQ3 PA4,IRQ4,TM15IB (ADSEP) AD10 AD11 AD12 AD13 AD14 AD15
P83,TM4IO,SBI3
P70,SBT0,RAS (Vpp)
P96,AN2 P95,AN1 P94,AN0 AVSS
MN102H55D MN102H55G MN102HF55G (TOP VIEW)
P82,TM0IO,SBT3,SCL3,SBI2 P81,DAC1 P80,DAC0 A23,P47,AN7,WDOUT A22,P46,AN6,STOP A21,P45,AN5 A20,P44,AN4 VREFA19,P43 A18,P42 A17,P41 A16,P40 P37, P36, P35, P34, AVDD P33, P32, P31, P30, P24,TM15IA
P60,WAIT,SBT2 RE,P61
P51,CS1,TM13OB P52,CS2,TM14OA P53,CS3,TM14OB P54,BREQ P55,BRACK ALE,ALE (WORD) A0,P20,SBT2 A1,P21,SBI2 A2,P22,SBO2 A3,P23
XI,PB1
WEL,P62 WE,WEH,P63
BOSC,PB0,BIBT1,BIBT2
P50,CS0,TM13OA
Figure 1-4-5 Configuration Memory Expansion Mode with 16-bit Address/Data Shared Mode
Unused pins require handling circuit (input pins connected VDD/VSS, output pins leave open, input/output pins connected VDD/VSS leave open depending direction setting).
OSCI OSCO (MODE)
MN102H55D/55G/F55G
Chapter General Description
1-4-6
Processor Mode with 8-bit Address/Data Separate Mode
P93,TM10IC,DMAACK0 P92,TM10IOB,DMAREQ0 P91,TM10IOA,BIBT2,DMAACK1 P86,TM9IOB,SBI4 VREF+ P85,TM9IOA,SBT4,SCL4,SBO2 P84,TM7IO,SBO3,SDA3
P90,TM8IOA,BIBT1,DMAREQ1
P74,SBI1 P73,SBT1,DMUX P72,SBO0 P71,SBI0,LCAS,CAS
P87,TM9IC,SBO4,SDA4
P75,SBO1
P97,AN3
PA0,IRQ0 PA1,IRQ1 PA2,IRQ2 PA3,IRQ3 PA4,IRQ4,TM15IB (ADSEP) P10,TM8IOB P11,TM8IC P12,TM11IOA P13,TM11IOB P14,TM11IC P15,TM12IOA P16,TM12IOB P17,TM12IC
P83,TM4IO,SBI3
P70,SBT0,RAS (Vpp)
P96,AN2 P95,AN1 P94,AN0 AVSS
MN102H55D MN102H55G MN102HF55G (TOP VIEW)
P82,TM0IO,SBT3,SCL3,SBI2 P81,DAC1 P80,DAC0 A23,P47,AN7,WDOUT A22,P46,AN6,STOP A21,P45,AN5 A20,P44,AN4 VREFA19,P43 A18,P42 A17,P41 A16,P40 AVDD
CS1,P51,TM13OB CS2,P52,TM14OA CS3,P53,TM14OB P54,BREQ P55,BRACK P56,BSTRE,TM15IA (WORD)
XI,PB1
P60,WAIT,SBT2
BOSC,PB0,BIBT1,BIBT2
WEL,P62 WE,P63
OSCI OSCO (MODE)
Figure 1-4-6 Configuration Processor Mode with 8-bit Address/Data Separate Mode
Unused pins require handling circuit (input pins connected VDD/VSS, output pins leave open, input/output pins connected VDD/VSS leave open depending direction setting).
MN102H55D/55G/F55G
Chapter General Description
1-4-7
Processor Mode with 16-bit Address/Data Separate Mode
P93,TM10IC,DMAACK0 P92,TM10IOB,DMAREQ0 P91,TM10IOA,BIBT2,DMAACK1 P86,TM9IOB,SBI4 VREF+ P85,TM9IOA,SBT4,SCL4,SBO2 P84,TM7IO,SBO3,SDA3
P90,TM8IOA,BIBT1,DMAREQ1
P74,SBI1 P73,SBT1,DMUX P72,SBO0,UCAS P71,SBI0,LCAS,CAS
P87,TM9IC,SBO4,SDA4
P75,SBO1
P70,SBT0,RAS (Vpp)
P97,AN3
PA0,IRQ0 PA1,IRQ1 PA2,IRQ2 PA3,IRQ3 PA4,IRQ4,TM15IB (ADSEP)
P83,TM4IO,SBI3
P96,AN2 P95,AN1 P94,AN0 AVSS
MN102H55D MN102H55G MN102HF55G (TOP VIEW)
P82,TM0IO,SBT3,SCL3,SBI2 P81,DAC1 P80,DAC0 A23,P47,AN7,WDOUT A22,P46,AN6,STOP A21,P45,AN5 A20,P44,AN4 VREFA19,P43 A18,P42 A17,P41 A16,P40 AVDD
CS1,P51,TM13OB CS2,P52,TM14OA CS3,P53,TM14OB P54,BREQ P55,BRACK BSTRE,P56,TM15IA (WORD)
XI,PB1
P60,WAIT,SBT2
BOSC,PB0,BIBT1,BIBT2
WEL,P62 WE,WEH,P63
OSCI OSCO (MODE)
Figure 1-4-7 Configuration Processor Mode with 16-bit Address/Data Separate Mode
Unused pins require handling circuit (input pins connected VDD/VSS, output pins leave open, input/output pins connected VDD/VSS leave open depending direction setting).
MN102H55D/55G/F55G
Chapter General Description
1-4-8
Processor Mode with 8-bit Address/Data Shared Mode
P93,TM10IC,DMAACK0 P92,TM10IOB,DMAREQ0 P91,TM10IOA,BIBT2,DMAACK1 P86,TM9IOB,SBI4 VREF+ P85,TM9IOA,SBT4,SCL4,SBO2 P84,TM7IO,SBO3,SDA3
P90,TM8IOA,BIBT1,DMAREQ1
P74,SBI1 P73,SBT1,DMUX P72,SBO0 P71,SBI0,LCAS,CAS
P87,TM9IC,SBO4,SDA4
P75,SBO1
P70,SBT0,RAS (Vpp)
P97,AN3
PA0,IRQ0 PA1,IRQ1 PA2,IRQ2 PA3,IRQ3 PA4,IRQ4,TM15IB (ADSEP) AD10 AD11 AD12 AD13 AD14 AD15
P83,TM4IO,SBI3
P96,AN2 P95,AN1 P94,AN0 AVSS
MN102H55D MN102H55G MN102HF55G (TOP VIEW)
P82,TM0IO,SBT3,SCL3,SBI2 P81,DAC1 P80,DAC0 A23,P47,AN7,WDOUT A22,P46,AN6,STOP A21,P45,AN5 A20,P44,AN4 VREFA19,P43 A18,P42 A17,P41 A16,P40 P37, P36, P35, P34, AVDD P33, P32, A9,P31, A8,P30, P24,TM15IA
CS1,P51,TM13OB CS2,P52,TM14OA CS3,P53,TM14OB P54,BREQ P55,BRACK (WORD)
XI,PB1
P60,WAIT,SBT2
BOSC,PB0,BIBT1,BIBT2
WEL,P62 WE,P63
P22,SBO2
P20,SBT2 P21,SBI2
OSCI OSCO (MODE)
Figure 1-4-8 Configuration Processor Mode with 8-bit Address/Data Shared Mode
Unused pins require handling circuit (input pins connected VDD/VSS, output pins leave open, input/output pins connected VDD/VSS leave open depending direction setting).
MN102H55D/55G/F55G
Chapter General Description
1-4-9
Processor Mode with 16-bit Address/Data Shared Mode
P93,TM10IC,DMAACK0 P92,TM10IOB,DMAREQ0 P91,TM10IOA,BIBT2,DMAACK1 P86,TM9IOB,SBI4 VREF+ P85,TM9IOA,SBT4,SCL4,SBO2 P84,TM7IO,SBO3,SDA3
P90,TM8IOA,BIBT1,DMAREQ1
P74,SBI1 P73,SBT1,DMUX P72,SBO0,UCAS P71,SBI0,LCAS,CAS
P87,TM9IC,SBO4,SDA4
P75,SBO1
P97,AN3
PA0,IRQ0 PA1,IRQ1 PA2,IRQ2 PA3,IRQ3 PA4,IRQ4,TM15IB (ADSEP) AD10 AD11 AD12 AD13 AD14 AD15
P83,TM4IO,SBI3
P70,SBT0,RAS (Vpp)
P96,AN2 P95,AN1 P94,AN0 AVSS
MN102H55D MN102H55G MN102HF55G (TOP VIEW)
P82,TM0IO,SBT3,SCL3,SBI2 P81,DAC1 P80,DAC0 A23,P47,AN7,WDOUT A22,P46,AN6,STOP A21,P45,AN5 A20,P44,AN4 VREFA19,P43 A18,P42 A17,P41 A16,P40 P37, P36, P35, P34, AVDD P33, P32, P31, P30, P24,TM15IA
CS1,P51,TM13OB CS2,P52,TM14OA CS3,P53,TM14OB P54,BREQ P55,BRACK
XI,PB1
P60,WAIT,SBT2
WEL,P62 WE,WEH,P63
BOSC,PB0,BIBT1,BIBT2
P22,SBO2
(WORD)
P20,SBT2 P21,SBI2
OSCI OSCO (MODE)
Figure 1-4-9 Configuration Processor Mode with 16-bit Address/Data Shared Mode
Unused pins require handling circuit (input pins connected VDD/VSS, output pins leave open, input/output pins connected VDD/VSS leave open depending direction setting).
MN102H55D/55G/F55G
Chapter General Description
1-4-10
List Functions
Refer "11-2-3 List Functions" each pin's input level Schmidt availability. input level column means that input determined level. CMOS input level column means that input determined CMOS level. column with "yes" sign shows Schmidt, while column with mark shows Schmidt. Pull-up programmable with pull-up control registers. Please refer "Chapter Ports" details. unused pins require handling board. input pins connected VSS. output pins leave open. lack this handling causes increase current unstable operation.
Table 1-4-1 List Functions (1/26)
Number Name (VPP) Power Power Power Power Function Description There four pins. mask chip (MN102H55D/55G) must connect these four pins power supply flash chip (MN102HF55G) must connect power supply because becomes power flash programming. During normal operation, must input same voltage other pins. There pins. They must connected power supply
Power (Ground) Power (Ground)
AVDD
Analog Voltage
There AVDD. must connected same voltage VDD.
AVSS
Analog Voltage (Ground)
There AVSS. must connected same voltage VSS.
Vref
Analog Basic Voltage
There Vref must connected with relation Vref Vref VDD.
Vref
Analog Basic Voltage
There Vref must connected with relation Vref Vref VDD.
MN102H55D/55G/F55G
Chapter General Description
Table 1-4-1 List Functions (2/26)
Number Name OSCI OSCO Input Output Function High-speed Oscillator Input High-speed Oscillator Output Description self-excited oscillator configuration, connect crystal ceramic oscillator across these pins. They have built-in feedback resistor between them. stability, insert capacitor between OSCI OSCO (For exact capacitance, consult oscillator manufacturer). external oscillator configuration, connect OSCI oscillator with amplitude width between VSS. Leave OSCO open. Refer "Figure 1-4-10". Connecting OSCO with external circuit directly allowed when oscillator clock taken from chip. Select BOSC synchronous signal.
Input Output
Low-speed Oscillator Input Low-speed Oscillator Output
self-excited oscillator configuration, connect crystal ceramic oscillator across these pins. They have builtin feedback resistor between them. stability, insert capacitor between (For exact capacitance, consult oscillator manufacturer). external oscillator configuration, connect oscillator with amplitude width between VSS. Leave open. Refer "Figure 1-4-11". used low-speed oscillator input pin, connect VDD. used low-speed oscillator output pin, leave open. When oscillation clock taken from chip, connecting with external circuit directly allowed. Select BOSC synchronous signal.
General-purpose port
used pin, this used general-purpose port. PBMD register switches function. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
MN102H55D/55G/F55G
Chapter General Description
Table 1-4-1 List Functions (3/26)
Number Name Input Function Reset Input Description This resets chip. With 34-MHz oscillator, reset starts when level input this more than Reset starts even when noise input this When high level input pin, reset released. After reset becomes high level, oscillation waits high-speed oscillation pins (OSCI OSCO) performed (approximately 3.855 with 34MHz oscillator). After that, chip starts executing instruction from x'080000'. Refer "Figure 1-4-12".
BOSC
Output
System Clock Output
This provides system clock. After reset release, outputs BOSC. When high-speed oscillation operating MHz, outputs clock MHz.
BIBT1 BIBT2
Output Output
Internal System Clock Output
output BIBT1 BIBT2 signal internal system clock setting PBMD register. These signals inverted signals.
General-purpose Port
used BOSC pin, used general-purpose input/output port. PBMD register switches function. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
MODE
Input
Mode Setup Input
This sets either processor mode single-chip mode (memory expansion mode). Pulling sets processor mode. processor mode, Internal becomes external memory area, chip executes instruction from x'080000' memory connected externally. Pulling high sets single-chip mode (memory expansion mode). chip executes instruction from x'080000' Internal ROM. memory expansion mode, port mode register address output data output instruction. change mode setting this during operation. When setting changed, proper operation cannot guaranteed. Refer "2-1 Summary Interface".
MN102H55D/55G/F55G
Chapter General Description
Table 1-4-1 List Functions (4/26)
Number Name WORD Input Function Data Width Setup Input Description This sets either 8-bit data width 16-bit data width external memory space immediately after reset release processor mode memory expansion mode. Pulling high sets 8-bit width while pulling sets 16-bit width. processor mode memory expansion mode, this must used data width setup pin. MEMMD1 register determines data width external memory spaces MEMMD1 register reset data width external memory space after reset release, regardless level this pin. Refer "2-1 Summary Interface". General-purpose Port This used general-purpose input/output port single-chip mode. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
ADSEP
Input
Address/Data Separate, Shared Mode Setup
This sets either address/data separate mode address/data shared mode processor mode memory expansion mode. Pulling high sets address/ data separate mode while pulling sets address/data shared mode. processor mode memory expansion mode, this must used address/ data separate, shared mode setup pin. change this pin's input during operation. When setting changed, proper operation cannot guaranteed. Refer "2-1 Summary Interface".
General-purpose Port
This used general-purpose input/output port single-chip mode. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
MN102H55D/55G/F55G
Chapter General Description
Table 1-4-1 List Functions (5/26)
Number Name BREQ Input Function Request Input Description BREQ BRACK pins operate arbitration. Pulling BREQ suspends execution current instruction, makes addresses, data control signals high impedance, then releases bus. After that, pull BRACK low. While chip accessing bus, chip releases after access completed. Pulling BREQ high level detector restores bus. General-purpose Port This used general-purpose input/output port single-chip mode. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
BRACK
Output
Request Enable Output
BREQ BRACK pins operate arbitration. Refer "Pin BREQ Description" details.
General-purpose Port
This used general-purpose input/output port single-chip mode. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
Output
Read Enable Output
This provides control signal external memory read processor mode memory expansion mode. When connecting SRAM ROM, connect memory. outputs level during read operation chip reads contents memory. Refer "2-1 Summary Interface". During request, STOP mode HALT mode, this will high impedance state. Refer "11-2-3 List Functions".
General-purpose Port
This used general-purpose input/output port used single-chip mode, processor mode memory expansion mode. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
MN102H55D/55G/F55G
Chapter General Description
Table 1-4-1 List Functions (6/26)
Number Name Output Function Lower Byte Write Enable Output Description This provides control signal external memory write processor mode memory expansion mode. When connecting SRAM ROM, connect memory. outputs level when writing lower bytes (bits data) writes data memory. Refer "2-1 Summary Interface". During request, STOP mode HALT mode, this will high impedance state. Refer "11-2-3 List Functions".
General-purpose Port
This used general-purpose input/output port used single-chip mode, processor mode memory expansion mode. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
Output
Upper Byte Write Enable Output
This provides control signal external memory write processor mode memory expansion mode. When connecting SRAM ROM, connect memory. outputs level when writing upper bytes (bits data) writes data memory. invalid when 8-bit width selected processor mode memory expansion mode that used general-purpose port pin. Refer "2-1 Summary Interface". During request, STOP mode HALT mode, this will high impedance state. Refer "11-2-3 List Functions".
Output
Write Enable Output DRAM Connection
This provides write enable when connecting DRAM processor mode memory expansion mode. When connecting DRAM with 2CAS method, connect this DRAM. outputs during write operation writes data DRAM. Refer "2-1 Summary Interface". During request, STOP mode HALT mode, this will high impedance state. Refer "11-2-3 List Functions".
MN102H55D/55G/F55G
Chapter General Description
Table 1-4-1 List Functions (7/26)
Number Name Function General-purpose Port Description This used general-purpose input/output port when 8-bit width selected single-chip mode, processor mode memory expansion mode. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
Output
Chip Select Output
This provides chip select signal corresponding each external memory space when accessing SRAM connected external memory spaces processor mode memory expansion mode. Connect pins external memory. cannot output when accessing Internal Internal RAM. Refer "2-1 Summary Interface". During request, STOP mode HALT mode, this will high impedance state. Refer "11-2-3 List Functions".
TM13OA
Output
Timer Output
This used timer output used chip select output single-chip mode, processor mode memory expansion mode. Refer "Chapter Timers".
Output
Chip Select Output
Refer "Pin Description" details.
TM13OB
Output
Timer Output
This used timer output used chip select output single-chip mode, processor mode memory expansion mode. Refer "Chapter Timers".
Output
Chip Select Output
Refer "Pin Description" details.
TM14OA
Output
Timer Output
This used timer output used chip select output single-chip mode, processor mode memory expansion mode. Refer "Chapter Timers".
MN102H55D/55G/F55G
Chapter General Description
Table 1-4-1 List Functions (8/26)
Number Name Output Function Chip Select Output Description Refer "Pin Description" details.
TM14OB
Output
Timer Output
This used timer output used chip select output single-chip mode, processor mode memory expansion mode. Refer "Chapter Timers".
Output Output
Address Latch Enable Output (Positive Logic) Address Latch Enable Output (Negative Logic)
This provides timing signal latching address which outputs AD15 pins during address/data shared mode processor mode memory expansion mode. outputs positive logic reset release, P5HMD changes negative logic. Because this, cannot used negative logic processor mode. Refer "2-1 Summary Interface". During request, STOP mode HALT mode, this will high impedance state.
BSTRE
Output
Read Enable Burst
When connecting burst external memory space processor mode memory expansion mode, connect this burst ROM. Refer "2-1 Summary Interface". During request, STOP mode HALT mode, this will high impedance state.
General-purpose Port
This used general-purpose input/output port used ALE, BSTRE single-chip mode, processor mode memory expansion mode. input/ output direction controlled units. builtin software control pull-up resistor. Refer "Chapter Ports".
TM15IA
Input
Timer Input
This used timer pulse input used ALE, BSTRE single-chip mode, processor mode memory expansion mode. Because same function, either must selected. Refer "Chapter Timers".
MN102H55D/55G/F55G
Chapter General Description
Table 1-4-1 List Functions (9/26)
Number Name WAIT Input Function Cycle Wait Input Description This extends shortens cycle accessing external memory based signal inputted this when external memory wait handshake mode processor mode memory expansion mode. Pulling this ends access external memory. Refer "Figure 1-4-13, Table 2-1-3 Table 2-1-6".
General-purpose Port
This used general-purpose input/output port used WAIT single-chip mode, processor mode memory expansion mode. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
SBT2
Serial Interface Clock Input/Output
This used synchronous transfer clock signal input/output serial interface used WAIT single-chip mode, processor mode memory expansion mode. Because same function, either must selected. Refer "Chapter Serial Interface".
Output
Address Output
This outputs address external memory processor mode memory expansion mode. Connect this address external memory address decode circuit. When accessing external memory, output value undefined. Refer "2-1 Summary Interface". During request, STOP mode HALT mode, this will high impedance state.
General-purpose Port
This used general-purpose input/output port used address output single-chip mode, processor mode memory expansion mode. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports". This used synchronous transfer clock signal input/output serial interface used WAIT single-chip mode, processor mode memory expansion mode. Because same function, either must selected. Refer "Chapter Serial Interface".
SBT2
Serial Interface Clock Input/Output
MN102H55D/55G/F55G
Chapter General Description
Table 1-4-1 List Functions (10/26)
Number Name Output Function Address Output Description Refer "Pin Description" details.
General-purpose Port
Refer "Pin Description" details.
SBI2
Input
Serial Interface Data Input
This used data input serial interface used address output single-chip mode, processor mode memory expansion mode. Because same function, either must selected. Refer "Chapter Serial Interface".
Output
Address Output
Refer "Pin Description" details.
General-purpose Port
Refer "Pin Description" details.
SBO2
Output
Serial Interface Data Output
This used data output serial interface used address output singlechip mode, processor mode memory expansion mode. Because same function, either must selected. Refer "Chapter Serial Interface".
Output
Address Output
Refer "Pin Description" details.
General-purpose Port
Refer "Pin Description" details.
MN102H55D/55G/F55G
Chapter General Description
Table 1-4-1 List Functions (11/26)
Number Name Output Function Address Output Description Refer "Pin Description" details.
General-purpose Port
Refer "Pin Description" details.
TM15IA
Input
Timer Pulse Input
This used timer pulse input used address output single-chip mode, processor mode memory expansion mode. Because same function, either must selected. Refer "Chapter Timers".
27-29
A5-A7
Output
Address Output
Refer "Pin Description" details.
P25-P27
General-purpose Port 25-27
Refer "Pin Description" details.
30-33, 35-38
A8-A15
Output
Address Output
Refer "Pin Description" details.
P30-P37
General-purpose Port 30-37 Input Interrupt
Refer "Pin Description" details.
KI0-KI7
Input
These pins used input interrupt pins they used address output pins single-chip mode, processor mode memory expansion mode. input interrupt pins controlled units. Refer "3-2-2 Input Interrupt Setup Examples".
MN102H55D/55G/F55G
Chapter General Description
Table 1-4-1 List Functions (12/26)
Number Name Function Description
39-42
A16-A19
Output
Address Output
Refer "Pin Description" details.
P40-P43
General-purpose Port 40-43
Refer "Pin Description" details.
44-45
A20-A21
Output
Address Output
Refer "Pin Description" details.
P44-P45
General-purpose Port 44-45
Refer "Pin Description" details.
AN4-AN5
Input
Conversion Input
These pins used conversion input pins they used address output pins single-chip mode, processor mode memory expansion mode. Refer "6-1 Summary Converter".
Output
Address Output
Refer "Pin Description" details.
General-purpose Port
Refer "Pin Description" details.
Input
Converter Conversion Input
This used conversion input used address output single-chip mode, processor mode memory expansion mode. Refer "6-1 Summary Converter".
STOP
Output
STOP Status Output
This outputs high indicate STOP status used address output single-chip mode, processor mode memory expansion mode.
MN102H55D/55G/F55G
Chapter General Description
Table 1-4-1 List Functions (13/26)
Number Name Output Function Address Output Description Refer "Pin Description" details.
General-purpose Port
Refer "Pin Description" details.
Input
Converter Conversion Input
This used conversion input used address output single-chip mode, processor mode memory expansion mode. Refer "6-1 Summary Converter".
WDOUT
Output
Watchdog Timer Overflow Output
This outputs high when watchdog timer overflows used address output single-chip mode, processor mode memory expansion mode.
84-91
D0-D7 AD0-AD7
Data Address/Data
These pins input output lower 8-bit data external memory during address/data separate mode processor mode memory expansion mode. During address/ data shared mode, these pins time-divides input output lower 8-bit address lower 8-bit data external memory. They become input when external memory accessed. Refer "2-1 Summary Interface". During request, STOP mode HALT mode, this will high impedance state.
P00-P07
General-purpose Ports 00-07
These pins used general-purpose ports they used data input/output pins address/data input/output pins single-chip mode, processor mode memory expansion mode. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
MN102H55D/55G/F55G
Chapter General Description
Table 1-4-1 List Functions (14/26)
Number Name Function Data Address/Data Description This inputs outputs upper 8-bit data external memory during address/data separate mode processor mode memory expansion mode. During address/ data shared mode, this time-divides input output upper 8-bit address upper 8-bit data external memory. becomes input when external memory accessed. Refer "2-1 Summary Interface". During request, STOP mode HALT mode, this will high impedance state. General-purpose Port Refer "Pins 84-91 P00-P07 Description" details.
TM8IOB
Timer Input/Output
This used timer input capture input timer output compare output used data input/output address/data input/output single-chip mode, processor mode memory expansion mode. Refer "Chapter Timers".
Data Address/Data General-purpose Port
Refer "Pin Description" details.
Refer "Pins 84-91 P00-P07 Description" details.
TM8IC
Input
Timer Input
This used timer counter clear used data input/output address/data input/ output single-chip mode, processor mode memory expansion mode. Refer "Chapter Timers".
MN102H55D/55G/F55G
Chapter General Description
Table 1-4-1 List Functions (15/26)
Number Name AD10 Function Data Address/Data Description Refer "Pin Description" details.
General-purpose Port
Refer "Pins 84-91 P00-P07 Description" details.
TM11IOA
Timer Input/Output
This used timer input capture input timer output compare output used data input/output address/data input/output single-chip mode, processor mode memory expansion mode. Refer "Chapter Timers".
AD11
Data Address/Data General-purpose Port
Refer "Pin Description" details.
Refer "Pins 84-91 P00-P07 Description" details.
TM11IOB
Timer Input/Output
This used timer input capture input timer output compare output used data input/output address/data input/output single-chip mode, processor mode memory expansion mode. Refer "Chapter Timers".
AD12
Data Address/Data General-purpose Port
Refer "Pin Description" details.
Refer "Pins 84-91 P00-P07 Description" details.
TM11IC
Input
Timer Input
This used timer counter clear used data input/output address/data input/output single-chip mode, processor mode memory expansion mode. Refer "Chapter Timers".
MN102H55D/55G/F55G
Chapter General Description
Table 1-4-1 List Functions (16/26)
Number Name AD13 Function Data Address/Data Description Refer "Pin Description" details.
General-purpose Port
Refer "Pins 84-91 P00-P07 Description" details.
TM12IOA
Timer Input/Output
This used timer input capture input timer output compare output used data input/output address/data input/output single-chip mode, processor mode memory expansion mode. Refer "Chapter Timers".
AD14
Data Address/Data General-purpose Port
Refer "Pin Description" details.
Refer "Pins 84-91 P00-P07 Description" details.
TM12IOB
Timer Input/Output
This used timer input capture input timer output compare output used data input/output address/data input/output single-chip mode, processor mode memory expansion mode. Refer "Chapter Timers".
AD15
Data Address/Data General-purpose Port
Refer "Pin Description" details.
Refer "Pins 84-91 P00-P07 Description" details.
TM12IC
Input
Timer Input
This used timer counter clear used data input/output address/data input/output single-chip mode, processor mode memory expansion mode. Refer "Chapter Timers".
MN102H55D/55G/F55G
Chapter General Description
Table 1-4-1 List Functions (17/26)
Number Name Output Function DRAM Control Output Description This outputs signal when connecting DRAM processor mode memory expansion mode. Refer "2-1 Summary Interface". During request, STOP mode HALT mode, this will high impedance state.
General-purpose Port
This used general-purpose input/output port used single-chip mode, processor mode memory expansion mode. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
SBT0
Serial Interface Clock Input/Output
This used synchronous transfer clock signal input/output serial interface used single-chip mode, processor mode memory expansion mode. Refer "Chapter Serial Interface".
LCAS
Output Output
DRAM Control Output DRAM Control Output
This outputs LCAS signal when connecting DRAM processor mode memory expansion mode. Refer "2-1 Summary Interface". During request, STOP mode HALT mode, this will high impedance state.
General-purpose Port
This used general-purpose input/output port used LCAS single-chip mode, processor mode memory expansion mode. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
SBI0
Input
Serial Interface Data Input
This used data input serial interface used LCAS single-chip mode, processor mode memory expansion mode. Refer "Chapter Serial Interface".
MN102H55D/55G/F55G
Chapter General Description
Table 1-4-1 List Functions (18/26)
Number Name UCAS Output Function DRAM Control Output Description This outputs UCAS signal when connecting DRAM processor mode memory expansion mode. Refer "2-1 Summary Interface". During request, STOP mode HALT mode, this will high impedance state.
General-purpose Port
This used general-purpose input/output port used UCAS single-chip mode, processor mode memory expansion mode. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
SBO0
Output
Serial Interface Data Output
This used data output serial interface used UCAS single-chip mode, processor mode memory expansion mode. Refer "Chapter Serial Interface".
DMUX
Output
DRAM Control Output
This outputs DMUX signal when connecting DRAM processor mode memory expansion mode. Refer "2-1 Summary Interface". During request, STOP mode HALT mode, this will high impedance state.
General-purpose Port
This used general-purpose input/output port used DMUX single-chip mode, processor mode memory expansion mode. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
SBT1
Serial Interface Clock Input/Output
This used synchronous transfer clock signal input/output serial interface used DMUX single-chip mode, processor mode memory expansion mode. Refer "Chapter Serial Interface".
MN102H55D/55G/F55G
Chapter General Description
Table 1-4-1 List Functions (19/26)
Number Name Function General-purpose Port Description This used general-purpose input/output port. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
SBI1
Input
Serial Interface Data Input
This used data input serial interface Refer "Chapter Serial Interface".
General-purpose Port
This used general-purpose input/output port. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
SBO1
Output
Serial Interface Data Output
This used data output serial interface Refer "Chapter Serial Interface".
General-purpose Port
This used general-purpose input/output port. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
DAC0
Output
Converter Conversion Output
This used output conversion results. Refer "6-3 Summary Converter".
General-purpose Port
This used general-purpose input/output port. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
DAC1
Output
Converter Conversion Output
This used output conversion results. Refer "6-3 Summary Converter".
MN102H55D/55G/F55G
Chapter General Description
Table 1-4-1 List Functions (20/26)
Number Name Function General-purpose Port Description This used general-purpose input/output port. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
TM0IO
Timer Input/Output
This used timer input/output pin. Refer "Chapter Timers".
SBI2
Input
Serial Interface Data Input
This used data input serial interface Because same function, either must selected. Refer "Chapter Serial Interface".
SBT3
Serial Interface Clock Input/Output
This used synchronous transfer clock signal input/output serial interface Refer "Chapter Serial Interface".
SCL3
Output
Serial Interface Clock Output
This used clock signal output serial interface Refer "Chapter Serial Interface".
General-purpose Port
This used general-purpose input/output port. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
TM4IO
Timer Input/Output
This used timer input/output pin. Refer "Chapter Timers".
SBI3
Input
Serial Interface Data Input
This used data input serial interface Refer "Chapter Serial Interface".
MN102H55D/55G/F55G
Chapter General Description
Table 1-4-1 List Functions (21/26)
Number Name Function General-purpose Port Description This used general-purpose input/output port. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
TM7IO
Timer Input/Output
This used timer input/output pin. Refer "Chapter Timers".
SBO3
Output
Serial Interface Data Output
This used data output serial interface Refer "Chapter Serial Interface".
SDA3
Serial Interface Data Input/Output
This used data input/output serial interface Refer "Chapter Serial Interface".
General-purpose Port
This used general-purpose input/output port. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
TM9IOA
Timer Input/Output
This used timer input/output pin. Refer "Chapter Timers".
SBO2
Output
Serial Interface Data Output
This used data output serial interface Because same function, either must selected. Refer "Chapter Serial Interface".
SBT4
Serial Interface Clock Input/Output
This used synchronous transfer clock signal input/output serial interface Refer "Chapter Serial Interface".
SCL4
Output
Serial Interface Clock Output
This used clock signal output serial interface Refer "Chapter Serial Interface".
MN102H55D/55G/F55G
Chapter General Description
Table 1-4-1 List Functions (22/26)
Number Name Function General-purpose Port Description This used general-purpose input/output port. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
TM9IOB
Timer Input/Output
This used timer input/output pin. Refer "Chapter Timers".
SBI4
Input
Serial Interface Data Input
This used data input serial interface Refer "Chapter Serial Interface".
General-purpose Port
This used general-purpose input/output port. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
TM9IC
Input
Timer Input
This used timer count clear input pin. Refer "Chapter Timers".
SBO4
Output
Serial Interface Data Output
This used data output serial interface Refer "Chapter Serial Interface".
SDA4
Serial Interface Data Input/Output
This used data input/output serial interface Refer "Chapter Serial Interface".
MN102H55D/55G/F55G
Chapter General Description
Table 1-4-1 List Functions (23/26)
Number Name Function General-purpose Port Description This used general-purpose input/output port. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
TM8IOA
Timer Input/Output
This used timer input/output pin. Refer "Chapter Timers".
BIBT1
Output
Internal System Clock Output
Refer "Pin BIBT1 Description" details. Refer "Chapter Serial Interface".
DMAREQ1
Input
ETC1 Activation Request Input
This activation request pin. When starts, data transferred automatically between external memory external device which requires address specification. Refer "Chapter ATC, ETC".
General-purpose Port
This used general-purpose input/output port. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
TM10IOA
Timer Input/Output
This used timer input/output pin. Refer "Chapter Timers".
BIBT2
Output
Internal System Clock Output
Refer "Pin BIBT1 Description" details. Refer "Chapter Serial Interface".
DMAACK1
Output
ETC1 Acknowledge Output
This acknowledge signal output activation request. Refer "Chapter ATC, ETC".
MN102H55D/55G/F55G
Chapter General Description
Table 1-4-1 List Functions (24/26)
Number Name Function General-purpose Port Description This used general-purpose input/output port. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
TM10IOB
Timer Input/Output
This used timer input/output pin. Refer "Chapter Timers".
DMAREQ0
Input
ETC0 Activation Request Input
This activation request pin. When starts, data transferred automatically between external memory external device which requires address specification. Refer "Chapter ATC, ETC".
General-purpose Port
This used general-purpose input/output port. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
TM10IC
Input
Timer Input
This used timer counter clear input pin. Refer "Chapter Timers".
DMAACK0
Output
ETC0 Acknowledge Output
This acknowledge signal output activation request. Refer "Chapter ATC, ETC".
General-purpose Port
This used general-purpose input/output port. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
Input
Converter Conversion Input
This used conversion input pin. Refer "6-1 Summary Converter".
MN102H55D/55G/F55G
Chapter General Description
Table 1-4-1 List Functions (25/26)
Number Name Function General-purpose Port Description This used general-purpose input/output port. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
Input
Converter Conversion Input
This used conversion input pin. Refer "6-1 Summary Converter".
General-purpose Port
This used general-purpose input/output port. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
Input
Converter Conversion Input
This used conversion input pin. Refer "6-1 Summary Converter".
General-purpose Port
This used general-purpose input/output port. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
Input
Converter Conversion Input
This used conversion input pin. Refer "6-1 Summary Converter".
General-purpose Port
This used general-purpose input/output port. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
IRQ0
Input
External Interrupt Input
This used external interrupt request input pin. Refer "Chapter Interrupts".
General-purpose Port
This used general-purpose input/output port. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
IRQ1
Input
External Interrupt Input
This used external interrupt request input pin. Refer "Chapter Interrupts".
MN102H55D/55G/F55G
Chapter General Description
Table 1-4-1 List Functions (26/26)
Number Name Function General-purpose Port Description This used general-purpose input/output port. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
IRQ2
Input
External Interrupt Input
This used external interrupt request input pin. Refer "Chapter Interrupts".
General-purpose Port
This used general-purpose input/output port. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
IRQ3
Input
External Interrupt Input
This used external interrupt request input pin. Refer "Chapter Interrupts".
General-purpose Port
This used general-purpose input/output port. input/output direction controlled units. built-in software control pull-up resistor. Refer "Chapter Ports".
IRQ4
Input
External Interrupt Input
This used external interrupt request input pin. Refer "Chapter Interrupts".
TM15IB
Input
Timer Input
This used base clock input timer pulse width measurement. Refer "Chapter Timers".
Input
Nonmaskable Interrupt Input
This used interrupt pin. /NMI interrupt occurs falling edge level. addition, this reads state general-purpose input port P76. Refer "Chapter Interrupts".
73-74
PULLUP
Input
Pull-up
These pins must pullde with
MN102H55D/55G/F55G
Chapter General Description
Connection Examples Power Pins, Oscillator Circuits, Reset Pins
OSCI OSCO
OSCI
OSCO
Note capacitance values vary depending crystal oscillator.
Oscillation Circuit
Figure 1-4-10 OSCI, OSCO Connection Example
kHz-166
Oscillation Circuit Note capacitance values vary depending crystal oscillator.
Figure 1-4-11 Connection Example
Figure 1-4-12 Reset Connection Example
RESET Delay Circuit
WAIT
Figure 1-4-13 WAIT Signal Control Circuit Connection Example
MN102H55D/55G/F55G
Chapter General Description
Package Code: LQFP100-P-1414
Unit:
Body Material: Epoxy Resin, Lead Material: FeNi42 Alloy, Lead Finish Method: Solder Plating
Figure 1-4-14 External Dimensions 100-pin LQFP
External dimensions subject change. Before using, please contact your nearest sales office latest product specifications.
MN102H55D/55G/F55G
Chapter General Description
MN102H55D/55G/F55G
Chapter Interface
Chapter Interface
2-1-1
Summary Interface
Overview
MN102H55D/55G/F55G function expand memory external devices. Table 2-1-1 shows memory modes. 16-bit data width selected setting pins.
Table 2-1-1 Mode Setting
Modes Single-chip mode External Connecting Modes External Data Width 8-bit 16-bit Address/data shared mode Processor mode Address/data separate mode Address/data shared mode 8-bit 16-bit 8-bit 16-bit 8-bit 16-bit MODE ADSEP WORD P0MD-P6MD Registers Note Note Note Note Note Note Note Note
Memory Expansion Address/data separate mode
Note each mode register input output address/data control signal from single-chip mode using user program internal becuase starts single-chip mode after reset. Note Initialize setting input output address/data control signal after reset release.
Memory Expansion Mode
x'000000' x'000000'
Processor Mode
External Device
x'008000' x'009000'(*4) x'00FC00'
External Device
x'008000' x'009000'(*4) x'00FC00'
Internal (4096 bytes (*3))
Internal (4096 bytes (*3))
External Memory Space (CS0 output)
Peripheral Register
x'010000'
Peripheral Register
External Memory Space (CS0 output)
Reset Start x'010000' x'080000'
External Device
Reset Start x'080000'
Internal (128K bytes (*1))
x'0A0000'(*2) x'200000' x'400000' x'400000' x'800000' x'C00000'
External Device
External Device
x'800000' x'C00000'
External Memory Space (CS1 output) External Memory Space (CS2 output) External Memory Space (CS3 output)
External Memory Space (CS1 output) External Memory Space (CS2 output) External Memory Space (CS3 output)
x'FFFFFF'
space expansion possible.
x'FFFFFF'
space exapnsion possible.
MN102HF55G 128K bytes x'0A0000' 4096 bytes x'009000' MN102H55G 128Kbytes x'0A0000' 4096 bytes x'009000' MN102H55D 64Kbytes x'090000' 4096 bytes x'009000'
Figure 2-1-1 Address Space
MN102HF55G/H55G/H55D
Chapter Interface
2-1-2
Control Registers
These registers control interface: external memory wait register (EXWMD), memory mode setup register (MEMMD1), memory mode setup register (MEMMD2), DRAM control register (DRAMMD1), DRAM control register (DRAMMD2), waveform control register (REEDGE), waveform control register (WEEDGE), waveform control register (ALEEDGE) address output time control register (MPXADR).
EXWMD register sets number waits devices external memory spaces
EXWMD: x'00FF80'
EW33 EW32 EW31 EW30 EW23 EW22 EW21 EW20 EW13 EW12 EW11 EW10 EW03 EW02 EW01 EW00 Reset:
EW[03:00] EW[13:10] EW[23:20] EW[33:30]
number wait external memory space number wait external memory space number wait external memory space number wait external memory space
Wait 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 perform handshake mode WAIT
Cycle
Please refer Figure 2-1-1 Address Space page address allocation external memory spaces.
wait cycle corresponds BOSC cycle. wait corresponds cycle instruction. With 34-MHz external oscillator, wait: 29.4 wait: 58.8
MN102HF55G/H55G/H55D
Chapter Interface
MEMMD1 register sets wait cycles internal peripherals, widths burst modes external memory spaces
MEMMD1: x'00FF82'
EB31 EB30 EB21 EB20 EB11 EB10 EB01 EB00 BRS1 BRS0 BRC3 BRC2 BRC1 BRC0 IOW1 IOW0 Reset
IOW[1:0] Wait Setting Internal Space wait cycle wait cycles wait cycles wait cycles
BRC[3:0] Burst Setting External Memory Space Disable Enable
BRS[1:0] Address Setting 16-bit Width 8-bit Width Burst Operation words bytes words bytes words bytes words bytes EB[01:00] Width Setting External Memory Space (*1,*2) 16-bit width 8-bit width Reserved 8-bit width when high 16-bit width when reset value '00' when /WORD while reset value '01' when /WORD high. EB[11:10] Width Setting External Memory Space (*1) 16-bit width 8-bit width Reserved 8-bit width when high 16-bit width when
EB[21:20] Width Setting External Memory Space (*1) 16-bit width 8-bit width Reserved 8-bit width when high 16-bit width when
EB[31:30] Width Setting External Memory Space (*1) 16-bit width 8-bit width Reserved 8-bit width when high 16-bit width when
Please refer Figure 2-1-1 Memory Space page address allocation external memory spaces.
access burst area other areas consecutively.
MN102HF55G/H55G/H55D
Chapter Interface
MEMMD2 register sets cycles during burst mode fixed wait cycles during handshake mode.
MEMMD2: x'00FF84'
Reset
reser reser
BST2 BST1 BST0
BST[2:0] Cycle Setting Burst Shortening (First Cycle Setting Burst Access) Reserved HS[2:0] cycle cycle cycles cycles cycles cycles cycles cycles Fixed Wait Setting When Controlling Wait Cycles WAIT Handshake Mode wait wait cycle wait cycle wait cycles wait cycles wait cycles wait cycles wait cycles
MN102HF55G/H55G/H55D
Chapter Interface
DRAMMD1 register sets external memory DRAM operation, timing CAS, size address shift.
DRAMMD1: x'00FF90'
ARE3 ARE2 ARE1 ARE0 MMD1 MMD0 ASFN SEL2 SEL1 SEL0 CAS2 CAS1 CAS0 RAS2 RAS1 RAS0 Reset
RAS[2:0] CAS[2:0] SEL[2:0] ASFN
Timing Setting RAS's Falling Edge beginning cycle beginning cycle beginning cycles beginning cycles beginning cycles beginning cycles beginning cycles beginning cycles Timing Setting CAS's Falling Edge beginning cycle beginning cycle beginning cycles beginning cycles beginning cycles beginning cycles beginning cycles beginning cycles Timing Setting Shifting from address Column Address beginning cycle beginning cycle beginning cycles beginning cycles beginning cycles beginning cycles beginning cycles beginning cycles Shift Setting from Address AD15 pins Column Address shift Shift
MMD[1:0] Shift Size DRAM Address 8-bit 9-bit 10-bit Reserved
Shift Shift Shift Address Output Address Output (A11) (A11) (A10) (A10) (Lo) (Lo) (A0)
MMD(1:0) Setting Name
ARE[3:0] DRAM Operation External Memory Space 3-0* Disable Enable
Please refer Figure 2-1-1 Memory Space page address allocation external memory spaces.
MN102HF55G/H55G/H55D
Chapter Interface
DRAMMD2 register sets DRAM refresh operation, refresh timing access method.
DRAMMD2: x'00FF92'
DRAM DRAM reserv reserv reserv RCY3 RCY2 RCY1 RCY0 RCS2 RCS1 RCS0 RRS2 RRS1 RRS0
Reset
RRS[2:0] RCS[2:0] RCY[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 Others
Timing Setting RAS's Falling Edge Refresh beginning cycle beginning cycle beginning cycles beginning cycles beginning cycles beginning cycles beginning cycles beginning cycles Timing Setting CAS's Falling Edge Refresh beginning cycle beginning cycle beginning cycles beginning cycles beginning cycles beginning cycles beginning cycles beginning cycles Cycle Setting Refresh cycles cycles cycles cycles cycles cycles cycles cycles cycles cycles cycles DRAM Refresh Enable Disable Enable
DRAM refreshed once when timer 10/12 underflow interrupt generated. times/8 refresh interval 31.25 less. Reserved DRAMClock Source Selection DRAM Refresh Timer underflow Timer underflow
DRAMACC DRAM Access Method Selection
method Reserved
MN102HF55G/H55G/H55D
Chapter Interface
REEDGE register sets waveform control modes external memory spaces
REEDGE: x'00FF86'
Reset
REES REES REEL REEL REES REES REEL REEL REES REES REEL REEL REES REES REEL REEL
REEL[01:00] Late Mode Area late mode reset) late mode late mode late mode
REES[01:00] Short Mode Area short mode short mode reset) short mode short mode
REEL[11:10] Late Mode Area late mode reset) late mode late mode late mode
REES[11:10] Short Mode Area short mode reset) short mode short mode short mode
REEL[21:20] Late Mode Area late mode reset) late mode late mode late mode
REES[21:20] Short Mode Area short mode reset) short mode short mode short mode
REEL[31:30] Late Mode Area late mode reset) late mode late mode late mode
REES[31:30] Short Mode Area
Please refer Table 2-2-2 page Table 2-2-4 page timing.
short mode reset) short mode short mode short mode
MN102HF55G/H55G/H55D
Chapter Interface
WEEDGE register sets waveform control modes external memory spaces
WEEDGE: x'00FF88'
WEESWEESWEEL WEELWEESWEESWEEL WEELWEESWEESWEEL WEELWEESWEESWEEL WEEL Reset
WEEL[01:00] Late Mode Area late mode reset) late mode late mode Reserved
WEES[01:00] Short Mode Area short mode reset) short mode short mode short mode
WEEL[11:10] Late Mode Area late mode reset) late mode late mode Reserved
WEES[11:10] Short Mode Area short mode reset) short mode short mode short mode
WEEL[21:20] Late Mode Area late mode reset) late mode late mode Reserved
WEES[21:20] Short Mode Area short mode reset) short mode short mode short mode
WEEL[31:30] Late Mode Area late mode reset) late mode late mode Reserved
WEES[31:30] Short Mode Area short mode reset) short mode short mode short mode
Please refer Table 2-2-3 page Table 2-2-5 page timing.
MN102HF55G/H55G/H55D
Chapter Interface
ALEEDGE register sets waveform control modes external memory spaces during address/data shared mode.
ALEEDGE: x'00FF8A'
ALEG ALEG ALEL ALEL ALEG ALEG ALEL ALEL ALEG ALEG ALEL ALEL ALEG ALEG ALEL ALEL
Reset
ALEL[01:00] ALEG[01:00] ALEL[11:10] ALEG[11:10] ALEL[21:20] ALEG[21:20] ALEL[31:30] ALEG[31:30]
Late Mode Area late mode late mode late mode reset) late mode Long Mode Area long mode long mode long mode reset) long mode Late Mode Area late mode reset) late mode late mode late mode Long Mode Area long mode reset) long mode long mode long mode
Late Mode Area late mode reset) late mode late mode late mode Long Mode Area long mode reset) long mode long mode long mode Late Mode Area late mode reset) late mode late mode late mode Long Mode Area long mode reset) long mode long mode long mode
Please refer Table 2-2-6 page timing.
MN102HF55G/H55G/H55D
Chapter Interface
MPXADR register sets address output timing external memory spaces during address/data shared mode.
MPXADR: x'00FF8C'
Reset
ADL[01:00] Address Long Mode Area long mode long mode long mode long mode reset)
ADL[11:10] Address Long Mode Area long mode reset) long mode long mode long mode
ADL[21:20] Address Long Mode Area long mode reset) long mode long mode long mode
ADL[31:30] Address Long Mode Area long mode reset) long mode long mode long mode
Table 2-1-2 List Interface Control Registers
Register EXWMD MEMMD1 MEMMD2 DRAMMD1 DRAMMD2 REEDGE WEEDGE ALEEDGE MPXADR Address x'00FF80' x'00FF82' x'00FF84' x'00FF90' x'00FF92' x'00FF86' x'00FF88' x'00FF8A' x'00FF8C' Function External Memory Wait Register Memory Mode Setup Register Memory Mode Setup Register DRAM Control Register DRAM Control Register Waveform Control Register Waveform Control Register Waveform Control Register Address Output Time Control Register Please refer Table 2-2-7 page timing.
MN102HF55G/H55G/H55D
Chapter Interface
2-1-3
Memory Connection Examples
MN102H55D/55G/F55G connect SRAM, DRAM, mask burst ROM. This section shows connection Examples. Example SRAM (Mask ROM) Connection (16-bit Width, Wait)
MN102HF55G SRAM (256 K*8bit) A18-0 D7-0 SRAM (256 K*8bit) A18-0 D7-0
(P50)
When connecting mask ROM, need connect WEL.
(P61) (P63) (P62)
A19-1 D15-8 D7-0
Figure 2-1-2 SRAM (Mask ROM) Connection Example (16-bit Width)
EXWMD
MEMMD1
DRAMMD1
P0MD
P1LMD
LMD1 LMD0 HMD7 HMD6 HMD5 HMD4 HMD3 HMD2 HMD1 HMD0 LMD7 LMD6 LMD5 LMD4 LMD3 LMD2 LMD1 LMD0
P2MD
P3HMD
P3LMD
P4LMD
LMD3 LMD2 LMD1 LMD0
P5LMD
LMD1 LMD0
P6MD
MN102HF55G/H55G/H55D
Chapter Interface
Example SRAM (Mask ROM) Connection (8-bit Width, Wait)
MN102HF55G SRAM (256 K*8bit) A18-0 D7-0
(P50)
A18-0 D7-0
When connecting mask ROM, need connect WEL.
(P61) (P62)
Figure 2-1-3 SRAM (Mask ROM) Connection Example (8-bit Width)
EXWMD
MEMMD1
DRAMMD1
P0MD
P1LMD
LMD1 LMD0
P2MD
P3HMD
HMD7 HMD6 HMD5 HMD4 HMD3 HMD2 HMD1 HMD0
P3LMD
LMD7 LMD6 LMD5 LMD4 LMD3 LMD2 LMD1 LMD0
P4LMD
LMD2 LMD1 LMD0
P5LMD
LMD1 LMD0
P6MD
MN102HF55G/H55G/H55D
Chapter Interface
Example DRAM (2WE Method) Connection (16-bit Width, Wait)
MN102HF55G
DRAM
MN41V4170 (256 K*16bit) D15-8 D7-0 Row=10 Colum=8
(P70) (P71) (P61) (P63) (P62)
D15-8 D7-0
Figure 2-1-4 DRAM (2WE Method) Connection Example (16-bit Width)
EXWMD
MEMMD1
DRAMMD1
DRAMMD2
DRAM DRAM
P0MD
P1LMD
LMD1 LMD0
P3HMD
HMD7 HMD6 HMD5 HMD4 HMD3 HMD2 HMD1 HMD0
P3LMD
LMD7 LMD6 LMD5 LMD4 LMD3 LMD2
P4LMD
LMD2 LMD1 LMD0
P6MD
P7LMD
LMD4 LMD3 LMD2 LMD1 LMD0
MN102HF55G/H55G/H55D
Chapter Interface
Example Burst Connection (8-bit Width, 4-3-3-3 Waits, Lower bits Address)
MICOM MN102HF55G (P50) A18-0 D7-0 BSTRE Burst (256 K*8bit) A18-0 D7-0
(P56)
Figure 2-1-5 Burst Connection Example (8-bit Width)
EXWMD
MEMMD1
MEMMD2
P0MD
P1LMD
LMD1 LMD0
P2MD
P3HMD
HMD7 HMD6 HMD5 HMD4 HMD3 HMD2 HMD1 HMD0
P3LMD
LMD7 LMD6 LMD5 LMD4 LMD3 LMD2 LMD1 LMD0
P4LMD
LMD2 LMD1 LMD0
P5LMD
LMD1 LMD0
P5HMD
HMD4 HMD3 HMD2
MN102HF55G/H55G/H55D
Chapter Interface
Example DRAM Connection (8-bit Width, Wait)
MN102HF55G
(P70) (P71) (P61) (P62) D7-0
DRAM
MN41V4800 (512 K*8bit) D7-0 Row=10 Colum=9
Figure 2-1-6 DRAM Connection Example (8-bit Width)
EXWMD
MEMMD1
DRAMMD1
DRAMMD2
DRAM DRAM
P0MD
P1LMD
P2MD
P3HMD
HMD7 HMD6 HMD5 HMD4 HMD3 HMD2 HMD1 HMD0
P3LMD
LMD7 LMD6 LMD5 LMD4 LMD3 LMD2
P4LMD
LMD2 LMD1 LMD0
P6MD
P7LMD
LMD4 LMD3 LMD2 LMD1 LMD0
MN102HF55G/H55G/H55D
Chapter Interface
2-1-4
Access External Memory
MN102H55D/55G/F55G access external memory. external memory space divided into four areas. When MN102H55D/ 55G/F55G accesses each area, corresponded (n=0 outputs chip select signal. addition, number wait cycles 8-bit 16-bit width selected each area.
clock output from BOSC base clock external access. address, data control signals output synchronizing with BOSC clock. BOSC clock frequency same oscillation clock frequency input from OSCI pin. example, BOSC clock frequency become with 40-MHz external oscillator. (The clock input from OSCI BOSC clock have phase difference.) BIBT1 BIBT2 internal clock synchronizing with BOSC clock, shows memory access cycle. During memory access, first BIBT2 clock becomes high level then BIBT1 clock becomes high level. When number wait cycles set, BIBT1 clock cycle being high level will extended. When wait cycle selected, BIBT2 clock cycle BIBT1 clock cycle being high level equals BOSC cycle. necessary cycle access should BOSC clock cycles.
BOSC BIBT2 BIBT1 Access Cycle
Figure 2-1-7 External Access Wait Cycle)
When number wait cycles (0.5 wait cycle wait cycles) set, BIBT1 clock cycle being high level extended BOSC clock cycle each wait cycle. necessary cycle access should BOSC clock cycles.
BOSC BIBT2 BIBT1 Access Cycle
Figure 2-1-8 External Access (0.5 Wait Cycle)
MN102HF55G/H55G/H55D
Chapter Interface
Table 2-1-3 Address/Data Multiplex Mode (16-bit Data Access)
length wait cycle 0.5-cycle units.
Wait BOSC Base Clock BIBT2 BIBT1 A23-A16 16-bit Data Read AD15-AD0
(The selects necessary data H-side L-side under 8-bit width)
A23-16 A15-0 A23-16 A15-0 D15-0 A23-16 A15-0 A23-16 A15-0 A15-0
Wait
A23-16 D15-0
A23-16 A15-0
A23-A16 AD15-AD0 16-bit Data Write A23-A16 AD15-AD0 8-bit H-side Data Write A23-A16 AD15-AD0 8-bit L-side Data Write A23-A16 AD15-AD0 Access
external access, internal ROM,RAM access) ((Internal peripheral register access)
A23-16 A15-0
A23-16 A15-0 D15-0
A23-16 A15-0
A23-16 A15-0 A15-0
A23-16 D15-0
A23-16 A15-0
A23-16 A15-0
A23-16 A15-0 D15-0
A23-16 A15-0
A23-16 A15-0 A15-0
A23-16 D15-0
D15-8 valid output
A23-16 A15-0
D15-8 valid output
A23-16 A15-0
A23-16 A15-0 D15-0
A23-16 A15-0
A23-16 A15-0 A15-0
A23-16 D15-0
D7-0 valid output
A23-16 A15-0
D7-0 valid output
A23-16 A15-0
Hold last output address
A23-16 A15-0
Hold last output address
External Wait
WAIT
next don't care Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z wait wait next don't care
A23-A16 AD15-AD0 Request BREQ BRACK
A23-16 A15-0
A23-16 A15-0
MN102HF55G/H55G/H55D
Chapter Interface
Table 2-1-4 Address/Data Multiplex Mode (8-bit Data Access)
length wait cycle 0.5-cycle units.
Wait BOSC Base Clock BIBT2 BIBT1 A23-A8 8-bit Data Read AD7-AD0 A23-A8 AD7-AD0 8-bit Data Write* general-purpose port 8-bit width mode.
A23-8 A7-0 A23-8 A7-0 D7-0 A23-8 A7-0 A23-8 A7-0 A7-0 A23-8 A7-0 A23-8 A7-0 D7-0 A23-8 A7-0 A23-8 A7-0 A7-0
Wait
A23-8 D7-0
A23-8 A7-0
A23-8 D7-0
A23-8 A7-0
8-bit H-side Data Write
(N/A)
(N/A)
8-bit L-side Data Write
(N/A)
(N/A)
A23-A8 AD7-AD0 Access
A23-8 A7-0
Hold last output address.
A23-8 A7-0
Hold last output address.
external access, Internal ROM,RAM access)
(Internal peripheral register access)
External Wait
WAIT
next don't care Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z wait wait next don't care
A23-A8 AD7-AD0 Request BREQ BRACK
A23-8 A7-0
A23-8 A7-0
MN102HF55G/H55G/H55D
Chapter Interface
Table 2-1-5 Address/Data Separate Mode (16-bit Data Access)
length wait cycle 0.5-cycle units.
Wait BOSC BIBT2 BIBT1 CS3-CS0 16-bit Data Read
(The selects necessary data H-side L-side 8-bit width.)
Wait
Base Clock
A23-A0 D15-D0 CS3-CS0 A23-A0
A23-0
A23-0 D15-0
A23-0
A23-0
A23-0 D15-0
A23-0
A23-0
A23-0 D15-0
A23-0
A23-0
A23-0 D15-0
A23-0
16-bit Data Write
D15-D0 CS3-CS0 A23-A0
A23-0
A23-0 D15-8
A23-0
A23-0
A23-0 D15-8
A23-0
8-bit H-side Data Write
D15-D0 CS3-CS0 A23-A0
A23-0
A23-0 D7-0
A23-0
A23-0
A23-0 D7-0
A23-0
8-bit L-side Data Write
D15-D0 CS3-CS0 A23-A0 D15-D0
A23-0
Hold last output address.
Hold last output address.
Access
external access, Internal ROM, access) (Internal peripheral register access)
External Wait
WAIT
next don't care Hi-Z wait wait next don't care
CS3-CS0 A23-A0 D15-D0 Request BREQ BRACK
A23-0
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
A23-0
MN102HF55G/H55G/H55D
Chapter Interface
Table 2-1-6 Address/Data Separate Mode (8-bit Data Access)
length wait cycle 0.5-cycle units.
Wait BOSC BIBT2 BIBT1 CS3-CS0 A23-A0 8-bit Data Read D7-D0 CS3-CS0 A23-A0 8-bit Data Write* D7-D0
general-purpose port 8-bit width mode.
A23-0 A23-0 D7-0 A23-0 A23-0 A23-0 A23-0 D7-0 A23-0 A23-0
Wait
Base Clock
A23-0 D7-0
A23-0
A23-0 D7-0
A23-0
(N/A)
(N/A)
(N/A)
(N/A)
CS3-CS0 A23-A0 D15-D0 Access
external access, internal ROM,RAM access) (Internal peripheral register access)
A23-0
Hold last output address.
Hold last output address.
External Wait
WAIT
next don't care Hi-Z wait wait next don't care
CS3-CS0 A23-A0 D15-D0 Reqeust BREQ BRACK
A23-0
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
A23-0
MN102HF55G/H55G/H55D
Chapter Interface
Table 2-1-7 Address/Data Separate Mode (16-bit DRAM, Method)
length wait cycle 0.5-cycle units.
Wait BOSC BIBT2 BIBT1 A22-A8 16-bit Data Read
(The selects necessary data H-side L-side 8-bit width.)
A22-8 COLUMN D15-0 A22-8
Waits
Base Clock
COLUMN D15-0
D15-D0 OE(RE)
A22-A8 16-bit Data Write
(The outputs necessary signal H-side L-side 8-bit width.)
A22-8
COLUMN D15-0
A22-8
COLUMN D15-0
D15-D0 OE(RE)
Wait, RAS, address switch timing controlled registers BOSC level. Wait BOSC BIBT2 BIBT1 A22-A8 D15-D0 Access OE(RE)
external access, Internal ROM, access) (Internal peripheral register access)
Wait
Base Clock
A22-8
A22-8
A22-A8 D15-D0
A22-8
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
A22-8
A22-8
A22-8
A22-8
Request
Refresh
OE(RE) BREQ BRACK
Undefined Undefined Undefined
auto refresh)
must delayed externally hold setup time COLUMN address.
MN102HF55G/H55G/H55D
Chapter Interface
Table 2-1-8 Address/Data Separate Mode (8-bit DRAM, Method)
length wait cycle 0.5-cycle units.
Wait BOSC BIBT2 BIBT1 A22-A8 D7-D0 8-bit Data Read OE(RE)
A22-8 COLUMN D7-0 A22-8
Waits
Base Clock
COLUMN D7-0
A22-A8 D7-D0 8-bit Data Write OE(RE)
A22-8
COLUMN D7-0
A22-8
COLUMN D15-0
Wait, RAS, address switch timing controlled registers BOSC level. Wait BOSC BIBT2 BIBT1 A22-A8 D7-D0 Access OE(RE)
external access, Internal ROM, access) (Internal peripheral register access)
Wait
Base Clock
A22-8
A22-8
A22-A8 D7-D0
A22-8
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
A22-8
A22-8
A22-8
A22-8
Request
Refresh
OE(RE) BREQ BRACK
Undefined Undefined Undefined
auto refresh)
must delayed externally hold setup time COLUMN address.
MN102HF55G/H55G/H55D
Chapter Interface
Table 2-1-9 Address/Data Separate Mode (16-bit Burst Access)
length wait cycle 0.5-cycle units.
4-3-3-3 Waits BOSC Base Clock BIBT2 BIBT1
16-bit Data Read (CPU select read necessary 8-bit data either D15-D8 D7-D0.)
CS3-CS0 A23-A0 D15-D0 BSTRE
A23-0 D15-0 A23-0 D15-0 A23-0 D15-0 A23-0 D15-0 A23-0 D15-0
CS3-CS0 Access A23-A0 D15-D0 BSTRE
Hold last output data.
Table 2-1-10 Address/Data Separate Mode (8-bit Burst Access)
length wait cycle 0.5-cycle units.
4-3-3-3 Waits BOSC BIBT2 BIBT1
Base Clock
CS3-CS0 8-bit Data Read A23-A0 D7-D0 BSTRE
A23-0 D7-0 A23-0 D7-0 A23-0 D7-0 A23-0 D7-0 A23-0 D7-0
CS3-CS0 Access A23-A0 D7-D0 BSTRE
Hold last output data.
MN102HF55G/H55G/H55D
Chapter Interface
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