LC74785, LC74785M On-Screen Display Controller Overview

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LC74785, LC74785M On-Screen Display Controller Overview

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Ordering number EN5520A
LC74785, LC74785M
On-Screen Display Controller
Overview
LC74785 LC74785M on-chip CMOS LSIs on-screen display, function that displays characters patterns screen under microprocessor control. These LSIs support characters display lines characters text.
Package Dimensions
unit:
3067-DIP24S
[LC74785]
Features
Display format: characters rows characters) Character format: (horizontal) (vertical) dots Character sizes: Three sizes each horizontal vertical directions Characters font: Initial display positions: horizontal positions vertical positions Blinking: Specifiable character units Blinking types: periods supported: About second about second Blanking: Over whole font dots) Background color Background coloring: colors (internal synchronization mode): 4fsc Background coloring: colors (internal synchronization mode): 2fsc Line background color lines Line background coloring: colors (internal synchronization mode): 4fsc Line background coloring: colors (internal synchronization mode): 2fsc External control input: 8-bit serial input format On-chip sync separator circuit support Video output NTSC-format composite output Package 24-pin plastic (300 mil) 24-pin plastic (375 mil)
SANYO: DIP24S
unit:
3045B-MFP24
[LC74785M]
SANYO: MFP24
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, JAPAN
63097HA (OT) 5520-1/24
LC74785, LC74785M Assignment
Functions
VSS1 Xtal Xtal (MUTE) Crystal oscillator (MUTE input) Function Ground Notes Ground connection (digital system ground) These pins used either connect crystal capacitor used form external crystal oscillator used generate internal synchronizing signals, input external clock signal (2fsc 4fsc). mask option, Xtalout function MUTE input pin. When this low, video output held pedestal level. pull-up resistor built input hysteresis characteristics.) Switches mode between external clock input crystal oscillator operation. level selects crystal oscillator operation high level selects external clock input. mask option, CTRL1 input function CHABLK (character border) output. This 3-value output. Line pulse output (Even fields when MOD1 low, both fields when MOD1 high) Connections coil capacitor that form character output clock generation oscillator.
Outputs state external synchronizing signal presence/absence judgment. Outputs high level when synchronizing signals present. Outputs field discrimination pulse (O/E pulse) when SEL2 high.(HLFTON: Valid when HLFTON: signal range specified LNA*, LNB*, LNC* output when HLFTON high.) Outputs clock oscillator) when high low. (This signal output command resets.) Outputs crystal oscillator clock when low. (This signal output command resets.)
CTRL1 (CHABLK)
Crystal oscillator input switching (CHABLK output)
LN21
Data output
oscillator
SYNC
External synchronizing signal judgment output
Enable input
Enable input serial data input function. Serial data input enabled when this low. pull-up resistor built (The input hysteresis characteristics.) Input serial data input clock. pull-up resistor built (The input hysteresis characteristics.) Serial data input. pull-up resistor built (The input hysteresis characteristics.) Composite video signal level adjustment power supply (analog system power supply) Composite video signal output Ground connection (analog system ground)
SCLK VDD2 CVOUT VSS2
Clock input Data input Power supply Video signal output Ground
Continued next page. 5520-2/24
LC74785, LC74785M
Continued from preceding page.
VDD1 SYNIN CDLR SEPOUT Function Video signal input Power supply Sync separator circuit input Background color phase adjustment Composite synchronizing signal output Composite video signal input Power supply digital system power supply) Video signal input built-in sync separator circuit Background color phase adjustment. Connect ground through resistor capacitor. Video signal output built-in sync separator circuit. switched function output signal (high pulse) MOD0 setting SEL0 high. Inputs vertical synchronizing signal created integrating SEPOUT output signal. integration circuit must connected SEPOUT pin. This must tied VDD1 unused. This switched function frame signal input mode setting SEL1 high. (This valid when CTL3 data output enable input. data output enabled when this low. pull-up resistor built (The input hysteresis characteristics.) data output (This either n-channel open-drain output CMOS output.) System reset input pull-up resistor built (The input hysteresis characteristics.) Power supply digital system power supply) Notes
Vertical synchronizing signal input
Enable input
CPDT
Data output
VDD1
Reset input Power supply
Note: Both VDD1 pins must connected power supply.
Specifications
Absolute Maximum Ratings 25°C
Parameter Supply voltage Input voltage Output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VOUT Topr Tstg VDD1 VDD2 input pins LN21, CPDT, SEPOUT, SYNCJDG 25°C Conditions Ratings VSS-0.3 VSS+7.0 VSS-0.3 VDD+0.3 VSS-0.3 VDD+0.3 +125 Unit
Allowable Operating Ranges +70°C
Parameter Symbol VDD1 VDD2 VIH1 VIH2 Input low-level voltage VIL1 VIL2 Pull-up resistance Composite video signal input voltage Input voltage VIN1 VIN2 VIN3 FOSC1 Oscillator frequency FOSC1 FOSC2 VDD1 VDD2 RST, CS1, CS2, SIN, SCLK, SEPIN, MUTE CTRL1 RST, CS1, CS2, SIN, SCLK, SEPIN, MUTE CTRL1 Applies pins RST, CS1, CS2, SIN, SCLK, MUTE options. CVIN; VDD1 SYNIN; VDD1 XtalIN (When external clock input used) VDD1 XtalIN XtalOUT oscillator pins fsc: NTSC) XtalIN XtalOUT oscillator pins fsc: NTSC) OSCIN OSCOUT oscillator pins oscillator) 0.10 7.159 14.318 Conditions Ratings 0.8VDD1 0.7VDD1 1.27VDD1 VDD1 VDD1 0.2VDD1 0.3VDD1 Unit Vp-p Vp-p Vp-p
Supply voltage
Input high-level voltage
Note: When XtalIN used clock input mode, extreme care must taken prevent noise from entering input signal.
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LC74785, LC74785M Electrical Characteristics +70°C, VDD1 unless otherwise specified.
Parameter Input leakage current Output leakage current Output high-level voltage Output low-level voltage Symbol Ileak1 Ileak2 VOH1 VOL1 CVIN CVOUT LN21, SYNCJDG, CPDT, SEPOUT; VDD1 -1.0 LN21, SYNCJDG, CPDT, SEPOUT; VDD1 CHABLK; VDD1 Three-value output voltage Input current Operating mode current drain IDD1 IDD2 SYNC level RST, CS1, CS2, SIN, SCLK, CTRL1, SEPIN, MUTE; VDD1 CTRL1 OSCIN; VSS1 VDD1; outputs open, Xtal: 7.159 MHz, VDD2: VDD2 CVOUT; VDD1 VDD2 0.70 0.89 1.18 1.32 1.52 1.81 0.98 1.17 1.46 1.63 1.83 2.11 1.17 1.36 1.65 2.33 2.52 2.81 1.08 1.27 1.56 1.49 1.68 1.97 1.97 2.17 2.46 1.40 1.60 1.89 1.97 2.17 2.46 2.55 2.75 3.04 0.82 1.01 1.30 1.44 1.64 1.93 1.10 1.29 1.58 1.75 1.95 2.23 1.29 1.48 1.77 2.45 2.64 2.93 1.20 1.39 1.68 1.61 1.80 2.09 2.09 2.29 2.58 1.52 1.72 2.01 2.09 2.29 2.58 2.67 2.87 3.16 0.94 1.13 1.42 1.56 1.76 2.05 1.22 1.41 1.70 1.87 2.07 2.35 1.41 1.60 1.89 2.57 2.76 3.05 1.32 1.51 1.80 1.83 1.92 2.21 2.21 2.41 2.70 1.64 1.84 2.13 2.21 2.41 2.70 2.79 2.99 3.28 Conditions Ratings Unit
Pedestal level
CVOUT; VDD1 VDD2
Color burst level
VCBL
CVOUT; VDD1 VDD2
Color burst high level
VCBH
CVOUT; VDD1 VDD2
Background color other than blue level
VRSL0
CVOUT; VDD1 VDD2
Background color other than blue high level
VRSH0
CVOUT; VDD1 VDD2
Blue background color 1low level
VRSL1
CVOUT; VDD1 VDD2
Blue background color level
VRSL2 VRSH1 VRSH2 VBK0
CVOUT; VDD1 VDD2
Blue background color high level
CVOUT; VDD1 VDD2
Frame level
CVOUT; VDD1 VDD2
Frame level
VBK1
CVOUT; VDD1 VDD2
Character level
VCHA
CVOUT; VDD1 VDD2
Note:
When sync level When sync level When sync level
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LC74785, LC74785M Timing Characteristics +70°C, VDD1 ±0.5 write (See Figure
Parameter Symbol tW(SCLK) tW(CS1) tSU(CS1) tSU(SIN) th(CS1) th(SIN) tword SCLK (The period when high) time write bits data data write time Conditions Ratings Unit
Minimum input pulse width
Data setup time
Data hold time
word write time
read (For n-channel open-drain circuit, Figure
Parameter Symbol tCKCY Minimum input pulse width tCKL tCKH Setup time Output delay time tICK tCKO SCLK SCLK SCLK SCLK CPDT Conditions Ratings Unit
Note: CMOS output circuit follows timing.
First byte
Second byte
Figure Serial Data Input Timing
Note: CPDT goes high-impedance state when high.
Figure Serial Output Test Conditions (For n-channel open-drain circuit.)
5520-5/24
field
(Line number)
Pulse output when MOD1 high
Even field
LC74785, LC74785M
Figure LN21 Output Timing
signal output from SYNCJDG when SEL2 high. LN21 output even fields when MOD1 both fields when MOD1 high.
(Line number)
Pulse output when MOD1 high
Note:
5520-6/24
pulse output line even fields when MOD1 low. pulse output line both fields when MOD1 High. Caption data transferred data output buffer.
LC74785, LC74785M
switched from high after decoder (microcontroller) detects falling edge LN21.
High-impedance previous data output.
High-impedance
bits caption data output first synchronization with SCLK falling edges.
Figure Transferring caption data from LC74785/M decoder (microcontroller): Method (Basic LC74785/M usage)
Note: When extracting closed caption character data when MOD1 high (NTSC-TV), applications must determine whether current field even checking signal level output from SYNCJDG (with SEL2 high) when falling edge detected LN21.
5520-7/24
LC74785, LC74785M timing transfer caption data data output buffer synchronized with falling edge pulse output from LN21. Therefore, software processing shown below required decoder (microcontroller) does detect LN21 falling edges.
Activity within given frame (MOD1: low)
Transfer data bits
Data which bits zero
Figure Transferring caption data from LC74785/M decoder (microcontroller): Method (When possible allocate port decoder (microcontroller) detect falling edges LN21.) Since data output output buffer once (during even field) when MOD1 low, data transfer control operation from decoder (microcontroller) must performed least twice single frame (about ms). transfer control operation performed twice same frame, CPDT output second operation will bits zero data. This allows decoder determine that data next frame been transferred yet.
Note: remains low, hardware will able transfer data output buffer. Therefore, decoder (microcontroller) must reset high from after completes data transfer control operation. Transfer method cannot used MOD1 high (NTSC-TV).
5520-8/24
Serial parallel converter Horizontal character size register Vertical character size register Output control Horizontal display position detector
Vertical display position register Blinking reverse video control register
8-bit latch command decode Display control register
write address counter
System Block Diagram
Data output buffer
Decoder
Data slicer
Horizontal size counter Vertical size counter
Horizontal counter
Vertical counter
Blinking reverse video control circuit
Display
Horizontal display position detector
Vertical display position detector
Character control counter Line control counter
Decoder
LC74785, LC74785M
Font
Synchronization determination
Data peak hold (data slice) HSYNC peak hold (HSYNC slice)
Composite sync signal separation control
Timing generator
Pedestal clamp Character output clock generator
Synchronizing signal generator
Character output control Background control Video output control
Shift register
5520-9/24
LC74785, LC74785M Display Control Commands Display control commands have 8-bit format transferred using serial input function. Commands consist command identification code first byte command data following bytes. following commands supported. COMMAND0: COMMAND1: COMMAND2: COMMAND3: COMMAND4: COMMAND5: COMMAND6: COMMAND7: COMMAND8: COMMAND9: COMMAND10: Display memory (VRAM) write address setup command Display character data write command Vertical display start position vertical character size setup command Horizontal display start position horizontal character size setup command Display control setup command Display control setup command Synchronizing signal detection setup command Display control setup command Display control setup command Display control setup command Display control setup command
Display Control Command Table
First byte Command Command identification code COMMAND0 Write address setup COMMAND1 Character write COMMAND2 Vertical character size vertical display start position COMMAND3 Horizontal character size horizontal display start position COMMAND4 Display control COMMAND5 Display control COMMAND6 Synchronizing signal detection COMMAND7 Display control COMMAND8 Display control COMMAND9 Display control COMMAND10 Display control Data Second byte Data
Once written, command identification code first byte stored until next first byte written. However, when display character data write command (COMMAND1) written, LC74785/M locks into display character data write mode, another first byte cannot written. When high, LC74785/M COMMAND0 (display memory write address setup mode) state.
5520-10/24
LC74785, LC74785M COMMAND0 (Display memory write address setup command) First byte
Register Contents State Display memory line address hexadecimal) Command identification code Sets display memory write address. Function Notes
Second byte
Register Contents State Display memory column address hexadecimal) Second byte identification code Function Notes
Note: registers when LC74785/M reset pin.
COMMAND1 (Display character data write setup command) First byte
Register Contents State Command identification code Sets display character data write mode. When this command input, LC74785/M locks display character data write mode until goes high. Function Notes
5520-11/24
LC74785, LC74785M Second byte
Register Contents State Character code hexadecimal) Character attribute Character attribute Function Notes
Note: registers when LC74785/M reset pin.
COMMAND2 Vertical display start position vertical character size setup command First byte
Register VS21 VS20 VS11 VS10 Contents State
VS11 VS21 VS20
Function Command identification code Sets vertical display start position vertical character size
Notes
1H/dot 3H/dot
2H/dot 1H/dot 2H/dot 1H/dot First line vertical character size Second line vertical character size
VS10
1H/dot 3H/dot
Second byte
Register (MSB) (LSB) Contents State Character display area Second byte identification Crystal oscillator frequency: 2fsc Crystal oscillator frequency: 4fsc vertical display start position then: VPn) horizontal synchronization pulse period vertical display start position bits VP5. weight Function Notes
Note: registers when LC74785/M reset pin.
5520-12/24
LC74785, LC74785M COMMAND3 (Horizontal display start position horizontal size setup command) First byte
Register HS21 HS20 HS11 HS10 Contents State HS11 HS21 HS10 HS20 1Tc/dot 3Tc/dot 1Tc/dot 3Tc/dot 2Tc/dot 1Tc/dot 2Tc/dot 1Tc/dot First line horizontal character size Second line horizontal character size Command identification code Sets horizontal display start position horizontal character size. Function Notes
Second byte
Register (MSB) (LSB) Contents State Second byte identification oscillator clock crystal oscillator clock horizontal start position then: HPn) Period oscillator connected OSCIN/OSCOUT operating mode. horizontal display start position bits HP5. weight 2Tc. Selects clock used character display horizontal direction. Function Notes
Note: registers when LC74785/M reset pin.
5520-13/24
LC74785, LC74785M COMMAND4 (Display control setup command) First byte
Register TSTMOD RAMERS OSCSTP SYSRST Contents State Reset registers turn display off. Erase display RAM. (Set data hexadecimal.) stop crystal oscillators. Stop crystal oscillators. Normal operating mode Test mode This must Erasing takes about (This operation must executed DSPOFF state.) Valid external synchronization mode when character display off. registers reset when low, reset state cleared when high, Command identification code Display control setup Function Notes
Second byte
Register BLK2 BLK1 BLK0 DSPON Contents State
BLK1
Function Second byte identification Character display area Video display area
BLK0
Notes
Specifies size complete fill Blanking Character size Changes blanking size
Blinking period: About Blinking period: About Blinking Blinking
Border size Full character size Switches blinking period Blinking reverse video mode switches display between normal character display reverse video display.
Reverse (character reversing) Reverse (character reversing) Character display Character display
Note: registers when LC74785/M reset pin.
5520-14/24
LC74785, LC74785M COMMAND5 (Display control setup command) First byte
Register HLFTON Contents State External synchronizing signal judgment output signal signal range specified LNA*, LNB*, LNC* output. Interlaced Noninterlaced External synchronization Internal synchronization Switches SYNCJDG (pin output. Switches between interlaced noninterlaced video. Switches between external internal synchronization Command identification code Display control setup Function Notes
Second byte
Register Contents State Background coloring background coloring (Only background level set) Color burst signal output. Color burst signal output stopped. Background color (phase) Cyan Yellow Blue Cyan blue Green Orange Magenta When used. Background color specification Only valid when high. Only valid internal synchronization mode. Second byte identification Function Notes
Note: registers when LC74785/M reset pin.
5520-15/24
LC74785, LC74785M COMMAND6 (Synchronizing signal detection setup command) First byte
Register SEL0 MOD0 DISLIN Contents State Sync separator signal Output signal MOD0 High-level output pulse signal lines lines Normal output CVIN CVOUT held pedestal level. CVOUT switching Switches number lines displayed. Only valid when SEL0 high. Switches SEPOUT (pin output. Command identification code Sets synchronizing signal control. Function Notes
Second byte
Register Contents State Number times HSYNC detected detected times times times times External synchronizing signal detection control Signal present signal absent transition detection Sets sampling period which SYNC cannot detected continuously horizontal synchronizing signal period (1H). Second byte identification Number times HSYNC detected times times times times External synchronizing signal detection control Signal absent signal present transition detection Sets sampling period which SYNC detected continuously horizontal synchronizing signal period (1H). Function Notes
Note: registers when LC74785/M reset pin.
5520-16/24
LC74785, LC74785M COMMAND7 (Display control setup command) First byte
Register SEL1 CTL3 Contents State Extended command identification code Vertical synchronizing signal (external separation) input Frame signal input internal separation. internal separation. Switches separation. Switches SEPIN (pin input. Only valid when CTL3 high. Command identification code Display control setup Function Notes
Second byte
Register VNPSEL VSPSEL MSKERS MSKSEL Contents State falling edge detection rising edge detection VSEP: about VSEP: about 17.8 Mask valid Mask invalid Border level only (VBK0) Two-stage border level (VBK0 VBK1) Switches VSYNC mask. Switches border level. (Only valid when BLK0 BLK1 Clears HSYNC VSYNK masks. Switches internal separation period. Switches acquisition polarity external mode when internal separation used. Second byte identification Function Notes
Note: registers when LC74785/M reset pin.
5520-17/24
LC74785, LC74785M COMMAND8 (Display control setup command) First byte
Register SEL2 MOD1 Contents State Extended command identification code External synchronizing signal judgment output signal signal Even field line data extraction (VCR) Line data extraction both even fields (NTSC-TV) Switches SYNCJDG (pin output Valid when HLFTON low. Switches line data extraction. Command identification code Display control setup Function Notes
Second byte
Register Contents State LNA3 LNA2 LNA1 LNA0 LPA2 LPA1 LPA0 LPA2 LPA1 LPA0 Background color (phase) Cyan Yellow Blue Cyan blue Green Orange Magenta When used. Specifies background color. Second byte identification LNA3 LNA2 LNA1 LNA0 Specified line change line background Line Line Line Line Line Line Line Line Line Line Line Line Specifies line whose background changed same line specified have different background colors with LNA*, LNB*, LNC*, then setting specified last command issued will valid. previously specification registers (LN* LP*) will reset Function Notes
Note: registers when LC74785/M reset pin.
5520-18/24
LC74785, LC74785M COMMAND9 (Display control setup command) First byte
Register LNBSEL Contents State Extended command identification code Normal line background color operation characters have background color specified character background color white. LNBSEL: setting specification characters have background color specified PH*, characters white. Valid when LNBSEL high Switches mode background color line specified LNB* characters specified display. Command identification code Display control setup Function Notes
MOD2
Second byte
Register Contents State LNB3 LNB2 LNB1 LNB0 LPB2 LPB1 LPB0 LPB2 LPB1 LPB0 Background color (phase) Cyan Yellow Blue Cyan blue Green Orange Magenta When used. Specifies background color. Second byte identification LNB3 LNB2 LNB1 LNB0 Specified line change line background Line Line Line Line Line Line Line Line Line Line Line Line Specifies line whose background changed same line specified have different background colors with LNA*, LNB*, LNC*, then setting specified last command issued will valid. previously specification registers (LN* LP*) will reset Function Notes
Note: registers when LC74785/M reset pin.
5520-19/24
LC74785, LC74785M COMMAND10 (Display control setup command) First byte
Register LNCSEL Contents State Extended command identification code Normal line background color operation characters have background color specified character background color white. LNCSEL: setting specification characters have background color specified PH*, characters white. Valid when LNCSEL high Switches mode background color line specified LNC* characters specified display. Command identification code Display control setup Function Notes
MOD3
Second byte
Register Contents State LNC3 LNC2 LNC1 LNC0 LPC2 LPC1 LPC0 LPC2 LPC1 LPC0 Background color (phase) Cyan Yellow Blue Cyan blue Green Orange Magenta When used. Specifies background color. Second byte identification LNC3 LNC2 LNC1 LNC0 Specified line change line background Line Line Line Line Line Line Line Line Line Line Line Line Specifies line whose background changed. same line specified have different background colors with LNA*, LNB*, LNC*, then setting specified last command issued will valid. previously specification registers (LN* LP*) will reset Function Notes
Note: registers when LC74785/M reset pin.
5520-20/24
LC74785, LC74785M Display Screen Structure display consists lines characters. characters displayed. number characters that displayed reduced when enlarged characters displayed. Display memory addresses specified decimal) column decimal) addresses. Display Screen Structure (display memory addresses)
Characters
Rows
5520-21/24
LC74785, LC74785M Composite Video Signal Output Levels (internally generated levels) CVOUT output level waveform (VDD2 5.00
Output level VCHA: Character
Output voltage 2.67 2.45
Output voltage 2.87 2.64
Output voltage 3.16 2.93
VRSH0: High background colors other than blue VRSH1,2 High blue background colors VBK1: VCBH: Border High color burst signal
2.09 2.09 1.75
2.29 2.29 1.95
2.58 2.58 2.23
VRSL2: blue background color VBK0: VPD: Border Pedestal level
1.61 1.52 1.44 1.29
1.80 1.72 1.64 1.48
2.09 2.01 1.93 1.77
VRSL0: background colors other than blue VRSL1 VCBL: VSN: blue background color color burst signal Sync
1.20
1.39
1.68
1.10 0.82
1.29 1.01
1.58 1.30
Note: VDD2
5520-22/24
LC74785, LC74785M Sample Application Circuit (When LC74785/M used conjunction with single-chip circuit.) External system clock input
Crystal oscillator
External system clock input (when functions modified mask options)
Note: When sync level (CVIN input signal: sync selected internal generated video signals option settings, electrolytic capacitor connected SYNIN must connected with correct polarity. When VDD1 SYNIN input video signal pedestal level clamped about
Microprocessor
Microprocessor
Microprocessor
5520-23/24
LC74785, LC74785M
products described contained herein intended surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment like, failure which directly indirectly cause injury, death property loss. Anyone purchasing products described contained herein above-mentioned shall: Accept full responsibility indemnify defend SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees, jointly severally, against claims litigation damages, cost expenses associated with such use: impose responsibility fault negligence which cited such claim litigation SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees jointly severally. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties. This catalog provides information June, 1997. Specifications information herein subject change without notice. 5520-24/24

LC74785, LC74785M On-Screen Display Controller Overview

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