LC74725, 74725M On-Screen Display Controller Overview L
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Ordering number EN5213A
LC74725, 74725M
On-Screen Display Controller
Overview
LC74725 LC74725M built-in on-screen display controller CMOS products that display characters patterns screen under microprocessor control. characters displayed have format, interpolation function provided. These LSIs display lines characters each.
Package Dimensions
unit: 3067-DIP24S
[LC7425]
Features
Display format: characters lines characters) Character format: (horizontal) (vertical) dots (interpolation function provided) Character sizes: horizontal vertical sizes Characters font: characters Initial display positions: horizontal positions vertical positions Blinking: Specifiable per-character basis Blinking types: periods, second second Blue background screen display: Available internal synchronization mode External control input: 8-bit serial input format Built-in sync separator circuit support Video outputs: Composite video signal output either NTSC PAL-M Package: 24-pin plastic (300 mil) 24-pin plastic (375 mil)
SANYO: DIP24S
3045B-MFP24
[LC7425M]
SANYO: MFP24
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, JAPAN
41096HA (OT)/O3195HA (OT) 5213-1/16
LC74725, 74725M Assignment
Functions
Symbol VSS1 XtalIN XtalOUT CTRL1 LN21 OSCIN OSCOUT Crystal oscillator input switching Data output oscillator Ground Crystal oscillator Function Description Ground connection (digital system ground) Connections external crystal capacitors used form crystal oscillator internal synchronizing signal generation. Alternatively, these pins used external clock input (2fsc 4fsc). Switches between external clock input mode crystal oscillator mode. Low: crystal oscillator mode, high: external clock input mode. Line pulse output (MOD0 low: even field, MOD0 high: both fields output) Connections external coil capacitor used form character output clock generation oscillator. Outputs judgment where there external synchronizing signals present. Outputs high level when there synchronizing signals. SEL0 high: Outputs field discrimination pulses (O/E pulses) Outputs clock oscillator) when high low. command provided that turns this output off. Outputs crystal oscillator clock when low. command provided that turns this output off. Enable input serial data input. Serial data input enabled when this low. pullup resistor built (hysteresis input). Serial data input clock input. pull-up resistor built (hysteresis input). Serial data input. pull-up resistor built (hysteresis input). Composite video signal level adjustment power supply (analog system power supply) Composite video signal output Must either connected ground left open. Video signal input Power supply Sync separator circuit input Ground Composite synchronizing signal output Vertical synchronizing signal input Enable input Data output Reset input Power supply Composite video signal input Power supply digital system power supply) Video signal input built-in sync separator circuit Ground (digital system ground) Video signal output from built-in sync separator circuit Inputs vertical synchronizing signal generated integrating SEPOUT output signal. integrating circuit must inserted between SEPOUT this pin. This must tied VDD1 unused. Enable input data output. data output enabled when this input low. pull-up resistor built (hysteresis input). data output (either n-channel open-drain CMOS output circuit) System reset input. pull-up resistor built (hysteresis input). Power supply digital system power supply)
SYNCJDG
External synchronizing signal judgment output
SCLK VDD2 CVOUT CVIN VDD1 SYNIN VSS1 SEPOUT SEPIN
Enable input Clock input Data input Power supply Video signal output
CPDT VDD1
Note: Both VDD1 pins must connected power supply.
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LC74725, 74725M
Specifications
Absolute Maximum Ratings 25°C
Parameter Maximum supply voltage Maximum input voltage Maximum output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VOUT Topr Tstg VDD1, VDD2 input pins LN21, CPDT, SEPOUT, SYNCJDG 25°C Conditions Ratings +125 Unit
Allowable Operating Ranges +70°C
Parameter Supply voltage Symbol VDD1 VDD2 VIH1 VIH2 VIL1 VIL2 VIN1 VIN2 VIN3 fOSC1 fOSC1 Oscillator frequency fOSC1 fOSC1 fOSC2 VDD1 VDD2 RST, CS1, CS2, SIN, SCLK CTRL1, SEPIN RST, CS1, CS2, SIN, SCLK CTRL1, SEPIN Applies RST, CS1, CS2, SIN, SCLK, pins specified options. CVIN: VDD1 SYNIN: VDD1 XtalIN (when external clock input used), 2fsc 4fsc: VDD1 XtalIN, XtalOUT oscillator pins (2fsc: NTSC) XtalIN, XtalOUT oscillator pins (4fsc: NTSC) XtalIN, XtalOUT oscillator pins (2fsc: PAL-M) XtalIN, XtalOUT oscillator pins (4fsc: PAL-M) OSCIN, OSCOUT oscillator pins oscillator) 7.159 14.318 7.151 14.302 Conditions VDD1 VDD1 1.27 VDD1 VDD1 VDD1 VDD1 VDD1 Unit Vp-p Vp-p Vp-p
Input high level voltage
Input level voltage
Pull-up resistance Composite video input voltage Input voltage
Note: Extreme care must used prevent noise when XtalIN used clock input mode.
Electrical Characteristics +70°C, unless otherwise specified, with VDD1
Parameter Input leakage current Output leakage current Output high level voltage Output level voltage Input current Symbol Ileak1 Ileak2 VOH1 VOL1 IDD1 IDD2 VCBL VCBH VRSL VRSH CVIN CVOUT LN21, SYNCJDG, CPDT, SEPOUT: VDD1 -1.0 LN21, SYNCJDG, CPDT, SEPOUT: VDD1 RST, CS1, CS2, SIN, SCLK, CTRL1, SEPIN: VDD1 CTRL1, OSCIN: VSS1 VDD1: outputs open, crystal: 7.159 MHz, VDD2: VDD2 When sync level CVOUT: VDD1, VDD2 When sync level CVOUT: VDD1, VDD2 When sync level CVOUT: VDD1, VDD2 When sync level CVOUT: VDD1, VDD2 When sync level CVOUT: VDD1, VDD2 When sync level CVOUT: VDD1, VDD2 When sync level CVOUT: VDD1, VDD2 When sync level CVOUT: VDD1, VDD2 When sync level CVOUT: VDD1, VDD2 When sync level CVOUT: VDD1, VDD2 When sync level CVOUT: VDD1, VDD2 When sync level CVOUT: VDD1, VDD2 0.69 0.89 1.28 1.47 0.97 1.16 1.60 1.79 1.44 1.63 1.96 2.16 0.81 1.01 1.40 1.59 1.09 1.28 1.72 1.91 1.56 1.75 2.08 2.28 0.98 1.13 1.52 1.71 1.21 1.40 1.84 2.03 1.68 1.87 2.20 2.40 Conditions Unit
Operating current drain
Sync level
Pedestal level
Color burst level
Color burst high level
Background color level
Background color high level
Continued next page. 5213-3/16
LC74725, 74725M
Continued from preceding page.
Parameter Border level Symbol VBK0 VBK1 VCHA Conditions When sync level CVOUT: VDD1, VDD2 When sync level CVOUT: VDD1, VDD2 When sync level CVOUT: VDD1, VDD2 When sync level CVOUT: VDD1, VDD2 When sync level CVOUT: VDD1, VDD2 When sync level CVOUT: VDD1, VDD2 1.43 1.61 2.01 2.18 2.57 2.76 1.55 1.73 2.13 2.30 2.69 2.88 1.67 1.85 2.25 2.42 2.81 3.00 Unit
Border level
Character level
Timing Characteristics +70°C, VDD1
Parameter write (See Figure Minimum input pulse width (SCLK) (CS1) (CS1) (SIN) (CS1) (SIN) tword tCKCY Minimum input pulse width tCKL tCKH Data setup time Output delay time tICK tCKO SCLK (the period when high) time write bits data data write time Symbol Conditions Unit
Data setup time
Data hold time
One-word write time
read (See Figure n-channel open-drain circuit.) SCLK SCLK SCLK SCLK CPDT
Note: Follows timing CMOS output circuit type.
Figure Serial Data Input Timing
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LC74725, 74725M
Note: CPDT goes high-impedance state when high.
Figure Serial Output Test Conditions (N-Channel Open-Drain Circuit)
Note: signal output from SYNCJDG when SEL0 high. LN21 outputs even field when MOD0 low, both fields when MOD0 high.
Figure LN21 Output Timing
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LC74725, 74725M
Note: When closed caption character data extracted NTSC-TV mode (MOD0 high), control microprocessor determine whether current field field even field checking signal level output SYNCJDG (when SEL0 high) point detects rise LN21 signal.
Figure LC74725/M Decoder Microprocessor) Caption Data Transfer Technique (This basic usage mode these LSIs.)
Caption data transfer data output buffer synchronized with falling edge pulse output from LN21. Therefore, following software processing required decoder microprocessor) does detect fall LN21.
When MOD0 low, since data output data buffer once (during even field) single frame, decoder microprocessor) must perform transfer control operation least twice frame (about ms). When transfer control operation performed twice same frame, second CPDT bits output data zeros. Therefore, microprocessor must determine that data next frame been transferred output buffer this case. Note: LC74725 hardware will transfer data output buffer while low. Therefore decoder microprocessor) must restore from level high level after completing data transfer control cycle. This transfer technique (technique cannot used NTSC-TV mode, i.e., when MOD0 high.
Figure LC74725/M Decoder Microprocessor) Caption Data Transfer Technique (When port detect fall LN21 cannot allocated decoder Microprocessor).)
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LC74725, 74725M System Block Diagram
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LC74725, 74725M Display Control Commands Display control commands have 8-bit format transferred using serial input function. Commands consist command identification code first byte command data following bytes. following commands supported. COMMAND0: Display memory (VRAM) write address setup command COMMAND1: Display character data write command COMMAND2: Vertical display start position vertical character size setup command COMMAND3: Horizontal display start position horizontal character size setup command COMMAND4: Display control setup command COMMAND5: Display control setup command
Display Control Command Table
First byte Command Command identification code COMMAND0 write address COMMAND1 Write character COMMAND2 vertical display start position vertical character size COMMAND3 horizontal display start position horizontal character size COMMAND4 Display control COMMAND5 Synchronizing signal control Data Second byte Data
Once written, command identification code first byte stored until next first byte written. However, when display character data write command (COMMAND1) written, LC74725/M locks into display character data write mode, another first byte cannot written. When high level input pin, LC74725/M COMMAND0 (display memory write address setup mode). COMMAND0 (Display memory write address setup command) First byte
Register content Register name State Display memory address hexadecimal) Command identification code display memory write address. Function Note
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LC74725, 74725M Second byte
Register content Register name State Display memory column address hexadecimal) Function Second byte identification Note
COMMAND1 (Display character data write setup command) First byte
Register content Register name State Command identification code display character data write. Function Note When this command input, LC74725/M locks into display character data write mode until goes high.
Second byte
Register content Register name State Character code hexadecimal) Character attribute Character attribute Function Note
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LC74725, 74725M COMMAND2 (Vertical display start position vertical character size setup command) First byte
Register content Register name VS20 VS10 State First line vertical character size Second line vertical character size Command identification code vertical display start position vertical character size. Function Note
Second byte
Register content Register name (MSB) State vertical display start position bits VP5. weight Function Second byte identification Crystal oscillator frequency: 2fsc Crystal oscillator frequency: 4fsc vertical display start position then: 2nVPn) horizontal synchronization pulse period
Note
(LSB)
COMMAND3 (Horizontal display start position horizontal character size setup command) First byte
Register content Register name State First line horizontal character size Correction: Correction: Border specification when horizontal double character size used Second line horizontal character size Command identification code horizontal display start position horizontal character size. Function Note
HS20 HS10
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LC74725, 74725M Second byte
Register content Register name (MSB) State horizontal start position then: 2nHPn)
Function Second byte identification oscillator used clock. crystal oscillator used clock.
Note
Selects clock used horizontal character display.
Period oscillator connected OSCIN/OSCOUT operating mode.
horizontal display start position bits HP5. weight 2Tc.
(LSB)
COMMAND4 (Display control setup command) First byte
Register content Register name TSTMOD State Reset registers turn display off. Erase display (set hexadecimal) stop crystal oscillator oscillator circuits. Stop crystal oscillator oscillator circuits. Normal operating mode Test mode This must zero. erase operation requires about executed DSPOFF state.) Valid when character display external synchronization mode. Reset occurs when low, reset cleared when goes high. Command identification code Display control setup Function Note
RAMERS
OSCSTP
SYSRST
Second byte
Register content Register name State Blinking Reverse (character reversing) Reverse (character reversing) Character display Character display Function Second byte identification Border level (VBK0) Border level (VBK1) Interlaced (262.5H field) Noninterlaced (263H field) Border Border Blinking period: about Blinking period: about Blinking Switches blinking period. When blinking specified reversed characters, blinking will between normal character reversed character display. Switches border level Switches between interlaced noninterlaced Note
DSPON
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LC74725, 74725M COMMAND5 (Display control setup command) First byte
Register content Register name State External synchronizing signal detection control: External synchronization Internal synchronization Blue background External synchronizing signal detection control: Background color present background color (only background level set) Green background Only valid internal synchronization mode Background color switching (Only valid NTSC mode) PAL-M mode, only blue available background color.) External synchronizing signal detection control. Determines when signal goes from detected undetected, from undetected detected. Switches between external internal synchronization Command identification code Synchronizing signal control settings Function Note
Second byte
Register content Register name State Normal output CVIN CVOUT fixed pedestal level. Even field line data extraction (VCR) Both even field line data extraction (NTSC-TV) Internal separation used. Internal separation used. NTSC PAL-M External synchronizing signal detection output signal signal Switches CVOUT. Switches line data extraction operation. Switches separation usage. Switches between generation NTSC PAL-M signals. Switches SYNCJDG (pin output. Function Second byte identification Note
MOD0
CTL3
CTL2
SEL0
Note: register states zero when LC74725/M reset with pin.
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LC74725, 74725M Display Screen Structure display consists lines characters each thus characters displayed. Enlarging size characters reduces number characters that displayed under characters. Display memory addresses specified decimal) column decimal) addresses. Display Screen Structure (display memory addresses)
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LC74725, 74725M Composite Video Signal Output Level (internally generated level)
CVOUT Output Level Waveform (VDD2 5.00
Output level VCHA: Character VRSH: Background color high VCBH: Color burst high VRSL: Background color VBK1: Border VBK0: Border VPD: VSN: Pedestal VCBL: Color burst Sync VDD2 5.00 Output voltage 2.69 2.08 1.72 1.56 2.13 1.55 1.40 1.09 0.81 Output voltage 2.88 2.28 1.91 1.75 2.30 1.73 1.59 1.28 1.01
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LC74725, 74725M Application Circuit Examples (Connected Y/C1 chip) External system clock input
Note: Values listed reference values.
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LC74725, 74725M Crystal oscillator clock generation
Note: Values listed reference values.
products described contained herein intended surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment like, failure which directly indirectly cause injury, death property loss. Anyone purchasing products described contained herein above-mentioned shall: Accept full responsibility indemnify defend SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees, jointly severally, against claims litigation damages, cost expenses associated with such use: impose responsibility fault negligence which cited such claim litigation SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees jointly severally. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties. This catalog provides information December, 1997. Specifications information herein subject change without notice. 5213-16/16
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