High Speed PROGRAMMABLE GAIN AMPLIFIER DIGITALLY PROGRAMMABLE GAI

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High Speed PROGRAMMABLE GAIN AMPLIFIER DIGITALLY PROGRAMMABLE GAI

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PGA102
High Speed PROGRAMMABLE GAIN AMPLIFIER
DIGITALLY PROGRAMMABLE GAIN: GAIN ERROR: 0.025% FAST SETTLING: 2.8µs 0.01% 16-PIN PLASTIC CERAMIC
DESCRIPTION
PGA102 high speed, digitally programmablegain amplifier. CMOS/TTL-compatible inputs select gains 100V/V. Each gain independent input terminal, providing input multiplexer function. On-chip metal film gain-set resistors laser-trimmed provide excellent gain accuracy. High speed input circuitry allows multiplexing high speed signals. PGA102 available 16-pin plastic ceramic packages. Commercial, industrial military temperature range models available.
APPLICATIONS
DATA ACQUISITION AMPLIFIER FIXED-GAIN AMPLIFIER AUTOMATIC GAIN SCALING
1.33k Common Force 1.2k 1.2k 10.8k
10.8k
PGA102
Common Sense
10.8k
VIN1
Gain Adj. VIN2
VOUT
Gain Adj. VIN3
Gain/Channel Select -VCC +VCC X100 Select Offset Adjust
Logic Ground Select
International Airport Industrial Park Mailing Address: 11400 Tucson, 85734 Street Address: 6730 Tucson Blvd. Tucson, 85706 Tel: (520) 746-1111 Twx: 910-952-1111 Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
1985 Burr-Brown Corporation
PDS-579C
Printed U.S.A. September, 1993
PGA102
SBOS142
SPECIFICATIONS
ELECTRICAL
+25°C, ±VCC 15VDC unless otherwise specified. PGA102AG PARAMETER GAIN Inaccuracy(1) CONDITIONS ±0.007 ±0.015 ±0.02 ±0.4 0.001 0.002 0.003 ±12.5 0.01 2000 ±200 ±0.5 ±500 ±200 ±200 ±0.02 ±0.03 ±0.05 0.003 0.005 0.01 PGA102BG, ±0.003 ±0.01 ±0.015 ±100 ±250 ±100 ±100 ±0.01 ±0.02 ±0.025 PGA102KP UNITS
Temperature
Nonlinearity
VOUT
±0.05 ±0.06
ppm/°C ppm/°C ppm/°C
RATED OUTPUT Voltage Current Short Circuit Current Output Resistance Load Capacitance INPUT OFFSET VOLTAGE Initial(2)
Stable Operation ±18V +25°C
Temperature
±1500 ±600 ±600
µV/°C µV/°C µV/°C µV/V µV/V µV/V
Supply Voltage
INPUT BIAS CURRENT Initial Over Temperature ANALOG INPUT CHARACTERISTICS Voltage Range Resistance Capacitance INPUT NOISE Voltage Noise
Linear Operation
Voltage Noise Density
Current Noise Current Noise Density
0.1Hz 10Hz 1Hz, 10Hz, 100Hz, 1kHz, 0.1Hz 10Hz 10Hz 100Hz 1kHz Small Signal, VOUT ±10V, VOUT ±10V Step,
0.99 0.43 1500
µVp-p µVp-p µVp-p nV/Hz nV/Hz nV/Hz nV/Hz nV/Hz nV/Hz nV/Hz nV/Hz nV/Hz nV/Hz nV/Hz nV/Hz pAp-p pA/Hz pA/Hz pA/Hz pA/Hz V/µs
DYNAMIC RESPONSE ±3dB Bandwidth
Full Power Bandwidth Slew Rate
PGA102
SPECIFICATIONS (CONT)
ELECTRICAL
+25°C, ±VCC 15VDC unless otherwise specified. PGA102AG PARAMETER CONDITIONS PGA102BG PGA102KP UNITS
DYNAMIC RESPONSE (CONT) Settling Time (0.1%) VOUT Step, Settling Time (0.01%) VOUT Step, Overload Recovery Overdrive, Time, 0.1% (see Performance Curve) CROSSTALK 60Hz DIGITAL INPUT CHARACTERISTICS Input "Low" Threshold Input "Low" Current Input "High" Threshold Input "High" Current Logic Threshold Control Switching Time(4) POWER SUPPLY Rated Voltage Voltage Range Quiescent Current ±10V Both Channels ±10V Both Channels
-155 -144
VIL(3) VIH(3) VLTC Between Channels VLTC+2 -VCC ±2.4
VLTC+0.8
°C/W
VOUT External Load, VOUT ±10V
±3.3 ±5.3
TEMPERATURE RANGE Specification, Grade Grades Grade Operating Storage Thermal Resistance
+125 +150 +125
+125
Specification same grade. NOTES: Gain inaccuracy percent error between actual ideal gain selected. externally adjusted zero gains 100. Offset voltage adjusted channel. Adjustment affects temperature drift approximately ±0.3µV/°C each 100µV offset adjusted. Voltage logic threshold control pin, VLTC, adjusts threshold "Low" "High" logic levels. Total time settle equals switching time plus settling time newly selected gain.
information provided herein believed reliable; however, BURR-BROWN assumes responsibility inaccuracies omissions. BURR-BROWN assumes responsibility this information, such information shall entirely user's risk. Prices specifications subject change without notice. patent rights licenses circuits described herein implied granted third party. BURR-BROWN does authorize warrant BURR-BROWN product life support devices and/or systems.
PGA102
CONFIGURATION
View
Select X100 Select Logic Threshold Control Common Force Common Sense VIN1 (X1) VIN2 (X10) VIN3 (X100)
+VCC VOUT NC(1) -VCC Offset Adjust Offset Adjust Gain Adjust (X10) Gain Adjust (X100)
NOTE: Internal Connection.
ABSOLUTE MAXIMUM RATINGS
Power Supply ±18V Input Voltage Range: Analog ±VCC Digital (VPIN 5.6V) +VCC Storage Temperature Range: Package -65°C +150°C Package -55°C +125°C Lead Temperature (soldering, 10s) +300°C Output Short Circuit Duration Continuous Common Junction Temperature: Package +175°C Package +110°C
PACKAGE INFORMATION
MODEL PGA102AG PGA102BG PGA102SG PGA102KP PACKAGE 16-Pin Hermetic 16-Pin Hermetic 16-Pin Hermetic 16-Pin Plastic PACKAGE DRAWING NUMBER(1)
NOTE: detailed drawing dimension table, please data sheet, Appendix Burr-Brown Data Book.
ORDERING INFORMATION
MODEL PGA102AG PGA102BG PGA102SG PGA102KP PACKAGE 16-Pin Hermetic 16-Pin Hermetic 16-Pin Hermetic 16-Pin Plastic TEMPERATURE RANGE -25°C +85°C -25°C +85°C -55°C +125°C +70°C
PGA102
TYPICAL PERFORMANCE CURVES
+25°C, ±VCC 15VDC unless otherwise noted.
GAIN ERROR TEMPERATURE .075 .005 .006 NONLINEARITY TEMPERATURE
Gain Error
.025
Nonlinearity
.004 .003 .002 .001
-.025 -.05
Temperature (°C)
Temperature (°C)
SETTLING TIME TEMPERATURE
SMALL SIGNAL FREQUENCY RESPONSE
Settling Time (µs)
Gain (dB)
Large Signal
Large Signal 100k Temperature (°C) Frequency (Hz)
SLEW RATE TEMPERATURE
SMALL SIGNAL STEP RESPONSE
Positive
Slew Rate (V/µs)
Output (mV)
Negative
=100
-100
Time (µs)
Temperature (°C)
PGA102
TYPICAL PERFORMANCE CURVES (CONT)
+25°C, ±VCC 15VDC unless otherwise noted.
LARGE SIGNAL STEP RESPONSE OVERLOAD RECOVERY INPUT OVERLOAD
Overload Recovery Time (µs)
Output
Time (µs)
Input Overload Voltage
INPUT VOLTAGE CURRENT NOISE FREQUENCY Voltage Noise
INPUT CROSSTALK FREQUENCY
Voltage Noise Density (nV/Hz)
Current Noise Density (pA/Hz)
Input Crosstalk (dB)
-100 -120 -140 -160 Frequency (Hz) 100k
Current Noise 100)
Frequency (Hz)
100k
POWER SUPPLY REJECTION FREQUENCY
Power Supply Rejection (dB)
QUIESCENT CURRENT TEMPERATURE ±15V
Quiescent Current (mA)
100k
Frequency (Hz)
Temperature (°C)
PGA102
APPLICATION INFORMATION
Figure shows basic connections required operation PGA102. Power supplies should bypassed with 0.1µF capacitors located close device pins. inputs each gain independent connected three separate signal sources. many applications, three inputs connected parallel form single input-see Figure Only input corresponding selected gain active, operating non-inverting amplifier. inactive inputs behave open circuits. input bias current inactive inputs negligible compared that selected input.
-VCC -VCC Optional Offset Trim 100k VIN1 VIN2 VIN3 Input Ground Output Ground +VCC
OFFSET ADJUSTMENT offset voltage each three input stages lasertrimmed. Many applications require further adjustment. optional trim circuit shown Figure used adjust offset voltage. This adjustment affects offset three gain channels. Since each gain setting require different adjustment potentiometer, this requires compromise. Often, offset voltage channel most important, adjustment optimized this channel only. Alternatively, Figure shows CMOS switch used select independent offset adjustment potentiometers each three channels. these offset adjustment techniques only null offset voltage PGA102. null offset produced signal source other system offsets this will increase temperature drift PGA102.
-15V +15V
0.1µF 0.1µF
Adjust VOUT channels.
PGA102
+15V 100k
Analog Ground Digital Ground
100k
CH1CH2CH3 4016 CMOS SWITCH
-VCC
INPUT GAIN VIN1 VIN2 VIN3 Invalid
X100
Logic "0": 0.8V Logic "1": +VCC Logic voltages referred
100k
FIGURE Basic Circuit Connections. DIGITAL INPUTS Gain selected digital input pins, "X10" "X100". threshold these logic inputs approximately 1.3V above voltage CMOS logic signals, connect logic ground. logic inputs latched. change logic inputs immediately selects gain. Switching time approximately 1µs. This does include time required analog output settle output value (see settling time specifications). Note that logic inputs allow four possible logic states-see Figure logic table. logic both inputs invalid code. This will damage device, analog output voltage will predictable while this code applied.
Offset Adjusts
FIGURE Independent Offset Adjustment Channels GAIN ADJUSTMENT Gain PGA102 accurately laser trimmed usually requires further adjustment. optional circuit Figure allows independent gain adjustment inputs.
PGA102
gain inputs changed adding external resistors internal feedback network shown Figures internal gain-set resistors trimmed precise ratios, exact values. internal resistor values within approximately ±30%
nominal values shown front page diagram. This makes external resistor values Figures subject variation-especially gains differing greatly from initial value.
VIN1 (X1) VIN2 (X10)
PGA102 VOUT
VIN1 (X1) VIN2 (X10)
PGA102 VOUT
VIN3 (X100)
VIN3 (X100)
RX10
RX100
100k
RX10
X100 Fine Adjust Fine Adjust
97.2k 10.8k GX10
RX100 Example:
108k 1.09k GX100
620k
RX10 8.64k RX100 107k gives gains
FIGURE Optional Fine Gain Adjustment.
FIGURE Connections Lower Gains.
VIN1 (X1) VIN2 (X10)
PGA102 VOUT
3.32k PGA102 Force
3.32k
VIN3 (X100)
RX10
RX100
OPA602 Sense
RX10
10.8k GX10
3.32k OPA602
3.32k
108k RX100 GX100 Example: RX10 1.08k RX100 1.08k gives gains
FIGURE Connections Higher Gains.
FIGURE High-Speed Instrumentation Amplifier.
PGA102
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgment, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Customers responsible their applications using components. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 2000, Texas Instruments Incorporated

High Speed PROGRAMMABLE GAIN AMPLIFIER DIGITALLY PROGRAMMABLE GAI

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