LC7874E Graphics Decorder Overview LC7874E CMOS that pr

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LC7874E Graphics Decorder Overview LC7874E CMOS that pr

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Ordering number EN5521
LC7874E
Graphics Decorder
Overview
LC7874E CMOS that provides signal processing needed compact disc graphics (CD-G) single chip. LC7874E accepts subcode signals output from player LC786X Series, LC7862XE Series, LC7863XE Series device, performs de-interleaving, error detection correction, graphic instruction processing, image processing.
microcomputer interface functions, allowing upgrading. Provides superimposition support. color signal output function. DRAM interface output sync signal output 3-state outputs.
Package Dimensions
unit:
Features
CD-G decoder configured using three-chip combination this LSI-the LC7874E-with external (64K bits) LC78010E digital encoder. Performs insertion protection subcode sync signals detection signal deinterleave error signals. crystal oscillators, NTSC PAL, with simple switchover means control pin. Connecting crystal resonator 14.31818 NTSC 17.734476 enables standard clock other necessary timings generated internally. Performs graphics instruction processing drawing functions, controls image display.
trademark SANYO ELECTRIC CO., LTD. SANYO's original format addresses controlled SANYO.
3159-QFP64E
[LC7874E]
SANYO: QIP64E
Specifications
Electrical Characteristics -30°C +85°C
Parameter Power supply voltage Symbol SFSY, SBSY, MUTE, Input voltage CE1, CE2, CE3, LINE, HRESET, VRESET, INIT, RESET, N/P, SON, XIN1, XIN2 SBCK, CDGM, RAS, CAS, Output voltage VOUT Topr Tstg ROUT0 GOUT0 BOUT0 HSYNC, CSYNC, BLANK, 4FSCO, EFLG, FSCO, XOUT1, XOUT2 Allowable power dissipation Operating temperature Storage temperature 25°C +125 Conditions Ratings Unit
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, JAPAN
13097HA(OT) 5521-1/22
LC7874E Allowable Operating Ranges -30°C +85°C
Parameter Power supply voltage Symbol VIH1 VIH2 Input high-level voltage VIH3 VIH4 VIH5 VIL1 Input low-level voltage VIL2 VIL3 Input frequency Input amplitude FSCIN1 FSCIN2 LINE, N/P, INIT, RESET DB3, HRESET, VRESET SFSY, SBSY, MUTE, LINE, N/P, INIT, RESET SFSY, SBSY, MUTE, DB3, CE3, HRESET, VRESET XIN1 XIN2 XIN1, XIN2 Conditions Ratings 14.31818 17.734476 0.3VDD 0.2VDD Unit Vp-p
Electrical Characteristics +85°C, unless otherwise specified
Parameter Symbol Conditions SFSY, SBSY, MUTE, Input high-level current IIH1 IIH2 Input low-level current IIL1 DB3, LINE, HRESET, VRESET, INIT, RESET, N/P, SFSY, SBSY, MUTE, DB3, LINE, HRESET, VRESET, INIT, RESET, N/P, SBCK, RAS, CAS, CDGM, ROUT0 GOUT0 BOUT0 Output high-level voltage FSCO, 4FSCO, HSYNC, CSYNC, BLANK, EFLG -0.5 SBCK, RAS, CAS, CDGM, ROUT0 GOUT0 BOUT0 Output low-level voltage FSCO, 4FSCO, HSYNC, CSYNC, BLANK, EFLG RAS, CAS, DB3, Output leakage current IOFF HSYNC, ROUT0 GOUT0 BOUT0 CSYNC, BLANK, FSCO, 4FSCO Built-in feedback resistance Clock frequency Operating current drain XIN1, XIN2 SBCK Ratings Unit
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LC7874E Timing Characteristics (Microcontroller Interface Timing) 25°C,
Parameter Symbol tDOH Conditions high pulse width pulse width Ratings Unit
Input minimum pulse width Data setup time Data hold time Data hold time wait time setup time hold time
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LC7874E Timing Characteristics (DRAM Access Timing) 25°C,
Parameter Random read/write cycle time Page mode cycle time precharge time pulse width pulse width (page mode) hold time hold time pulse width precharge time precharge time address setup time address hold time Column address setup time Column address hold time Read command setup time Read command hold time Read command hold time Write command setup time Write command hold time Write command pulse width Write data setup time Write data hold time setup time hold time precharge active time Symbol tRAS tRASP tRSH tCSH tCAS tCPN tASR tRAH tASC tCAH tRCS tRCH tRRH tWCS tWCH tCSR tCHR tRPC tRDS tRDH tREF (CAS before RAS) (CAS before RAS) (Referenced (Referenced toRAS) page mode) Conditions Ratings 18000 Unit
Read data setup time Read data hold time Refresh time
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LC7874E DRAM Read Cycle
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LC7874E DRAM Early Write Cycle
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LC7874E DRAM Page Mode Read Cycle
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LC7874E DRAM Page Mode Write Cycle
DRAM CAS-Before-RAS Refresh Cycle
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LC7874E Assignment
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LC7874E Functions
Symbol Name Polarity selection pins Positive Clock output Sync signal input Data input Sync signal input Power supply Enable input Data output Data input Clock input Data input Ground (GND) Color selection Graphic data discrimination output DRAM control input DRAM output DRAM output DRAM output DRAM output DRAM output DRAM output DRAM output DRAM output DRAM output DRAM output DRAM output DRAM output DRAM input/output DRAM input/output DRAM input/output DRAM input/output Blank signal output Composite sync output Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Function Selected LC7861N/67 LC7860K/63 Setting prohibited LC7868/62X/63X
SBCK SFSY SBSY MUTE CDGM BLANK CSYNC
Subcode read clock output Subcode frame sync signal input (MORE+ input) Subcode data input (MORE+ input) Subcode block sync signal input (MORE+ input) Digital power supply Serial input/output data control input (MORE+ input) Serial data output (Nch open-drain) Serial data input (MORE+ input) Serial data input/output clock input (MORE+ input) Control signal input invalidating subcode data (MORE+ input) Normal mode, Color output (built-in pull-down resistor) Goes high when graphics data input (can reset command control). Signal input setting DRAM connection high impedance (MORE+ input) DRAM address (A0) output DRAM address (A1) output DRAM address (A2) output DRAM address (A3) output DRAM address (A4) output DRAM address (A5) output DRAM address (A6) output DRAM address (A7) output
Negative DRAM column address strobe signal output Negative DRAM data write enable signal output Negative DRAM data read enable signal output Negative DRAM address strobe signal output Positive Positive Positive Positive Positive DRAM data (D0) input/output DRAM data (D1) input/output DRAM data (D2) input/output DRAM data (D3) input/output Video signal blanking period output
Negative Composite sync signal output
Continued next page.
5521-10/22
LC7874E
Continued from preceding page.
Symbol HSYNC ROUT3 ROUT2 ROUT1 ROUT0 4FSC0 FSC0 GOUT3 GOUT2 GOUT1 GOUT0 BOUT3 BOUT2 BOUT1 BOUT0 EFLG HRESET LINE VRESET INIT RESET XIN2 XOUT2 XIN1 XOUT1 Crystal oscillator connection pins Crystal oscillator connection pins Name Horizontal synchronization output data output data output data output data output Clock output Clock output data output data output data output data output data output data output data output data output Video output control input Sync signal control input Superimposition output Error status monitor output External horizontal synchronization input Line number selection External vertical synchronization input Initial input Reset input NTSC/PAL selection input Superimposition control Polarity Function
Negative Horizontal sync signal output Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Video signal data output Video signal data output Video signal data output Video signal data output clock output Subcarrier clock output NTSC: 14.31818 PAL: 17.734476 NTSC: 3.579545 PAL: 4.433619
Video signal data output Video signal data output Video signal data output Video signal data output Video signal data output Video signal data output Video signal data output Video signal data output Signal input setting video output high impedance (MORE+ input) Signal input setting sync signal output high impedance (MORE+ input) Superimposition control output Error status monitor signal output
Negative External horizontal synchronization timing control Line number selection input NTSC 263H, 262H 312H, 314H
Negative External vertical synchronization timing control Negative System initial signal input Negative System reset signal input Positive Positive NTSC crystal oscillator connection (4Fsc 14.31818 MHz) crystal oscillator connection (4Fsc 17.734476 MHz) NTSC/PAL selection input NTSC, Superimposition ON/OFF control input Superimposition
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LC7874E Block Diagram
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LC7874E CD-G Instructions contents instructions Book which supported LC7874E follows. ZERO mode (MODE ITEM LINE GRAPHICS mode (MODE ITEM INSTRUCTION (4): Write FONT INSTRUCTION (12): Write Scroll SCREEN GRAPHICS mode (MODE ITEM INSTRUCTION (1): Preset MEMORY INSTRUCTION (2): Preset BORDER INSTRUCTION (6): Write FONT FOREGROUND/BACKGROUND INSTRUCTION (20): scroll SCREEN with preset INSTRUCTION (24): scroll SCREEN with copy INSTRUCTION (30): Load CLUT color-0 color-7 INSTRUCTION (31): Load CLUT color-8 color-15 INSTRUCTION (38): EXCLUSIVE-OR FONT
Outline Functions Crystal clock oscillation: XIN1, XOUT1, XIN2, XOUT2, N/P, 4FSCO, FSCO XIN1 XOUT1 14.31818 (NTSC) crystal oscillator connection pins, XIN2 XOUT2 17.734476 (PAL) crystal oscillator connection pins. Both modes supported switching pin. 4FSCO outputs Xtal clock, FSCO outputs this clock divided functions each mode shown below.
XIN1, XOUT1 14.31818 XIN2, XOUT2 17.734476 system NTSC/M PAL/GBIDH 4FSCO 14.31818 17.734476 FSCO 3.579545 4.433619
Subcode interface: SBCK, SFSY, SBSY Control pins provides interfacing with following three modes. Driving mute high disables SBSY input SBCK output.
Mode LC7861N/67 interface LC7860K/63 interface LC78681/62X/63X interface
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LC7874E With LC7860K/63 interface, SBCK transmitted when SFSY confirmed approximately after falling edge SFSY detected. With other interfaces, SBCK transmitted when SFSY confirmed high SBSY approximately after rising edge SFSY detected. LC7860 interface [DSP names shown parentheses]
LC7861N/67 interface [DSP names shown parentheses]
LC78681/62X/63X Series interface Same (2), except that SBCK polarity shifted inversely (shifted rise SBCK). DRAM interface Interface pins: DB3, RAS, CAS, 4-bit DRAM connected externally. interface pins high impedance driving high. MPEG DRAM sharing possible. graphic monitor pin: CDGM CDGM goes high once LC7874E accepts CD-G instruction. power-on state, once CDGM goes high remains high. driven driving INIT transferring INIT command from microcontroller.
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LC7874E Display format
Video output: ROUT0 ROUT3, GOUT0 GOUT3, BOUT0 BOUT3 Error flag output: EFLG Error detection results monitored with EFLG pin.
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LC7874E Color output: When driven high, color bars output from video output pins. Details color bars shown below.
White Gray Yellow Cyan Green Magenta Blue BORDER (BLACK)
Drawing Functions (Graphic Functions) Operating modes (scan operation, display operation) NTSC mode Non-interlace clock System clock mode Non-interlace clock System clock PAL60 mode Non-interlace clock System clock Display functions Display resolution Image data area 16-color display
(262 lines) 2fsc: 7.15909 139.67 4fsc: 14.31818
(312 lines) 4fsc 2/5: 7.09379 140.97 4fsc: 17.734476
(262 lines) 4fsc 2/5: 7.09379 140.97 4fsc: 17.734476 dots 192H dots 216H Selection colors from 4096
Microcontroller Interface (CCB) Transfer format (for command transfer) Transfer format (example)
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LC7874E Display Control Command Table
First byte Command
Command identification code
Second byte INIT CH15 BGG3 CKG3 SCP2 CH14 BGG2 CKG2 MVMD SCP1 CH13 BGG1 CKG1 EXSN SCH5 SCP0 CH12 BGG0 CKG0 HVMK SCV4 SCH4 Data CH11 BGR3 BGB3 CKR3 CKB3 SCV3 SCH3 DISK /GPH CH10 BGR2 BGB2 CKR2 CKB2 TST2 SCV2 SCH2 LINE BGR1 BGB1 CKR1 CKB1 TST1 SCV1 SCH1 VRAM BGR0 BGB0 CKR0 CKB0 TST0 SCV0 SCH0
Register 00HEX (Various mode settings) Register 10HEX (Fine adjustment screen position) Register 20HEX (Channel ON/OFF) Register 30HEX (Channel ON/OFF) Register 40HEX (BGC settings) Register 50HEX (BGC setting) Register 60HEX (Chroma color settings) Register 70HEX (Chroma color setting) Register 80HEX output phase adjustment) Register 90HEX (External synchronization mode, test mode) Register A0HEX (Subtitle scroll: vertical) Register B0HEX (Subtitle scroll: horizontal) Register 01HEX (19-byte command input)
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LC7874E Description Commands Command transmission should performed LSB-first. Control item code 00HEX: Various mode settings Default: [01100000] Data VRAM/BG Display screen switchover setting VRAM contents displayed Background color displayed Data TV/LINE Graphic display mode setting graphic mode LINE graphic mode Data DISK/GPH Disk command acceptance control DISK command only accepted DISK command acceptance ignored, (Micro graphic command) only accepted Data Color screen output setting Graphic signal output Color signal output Data SCP0 output (pin control Data SCP1 Superimposition compare condition (valid only when
SCP1 SCP0 Comparison performed When border color black, high (display) parts whose color does match border color, (transparent) otherwise High parts whose color does match chroma color; otherwise Compare condition
Data SCP2 output (pin control When SCP0, SCP1 compare condition satisfied, setting full-screen (transparent) When SCP0, SCP1 compare condition satisfied, setting full-screen high (display) Data INIT Software reset setting Internal reset executed (normal) Internal reset executed (display screen becomes blue background screen) Control item code 10HEX: Fine adjustment screen position Default: [00000000] Data Data Data Data Data Data Data Data Horizontal fine adjustment screen position Specified two's complement with left positive direction (variable dots from center 2-dot units) Vertical fine adjustment screen position Specified two's complement with positive direction (variable dots from center 2-dot units)
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LC7874E Control item code 20HEX: Channel on/off setting Default: [00000011] Data on/off setting Data Data Channel Data Channel Data Data Data Data Control item code 30HEX: Channel on/off setting Default: [00000000] Data CH15 on/off setting Data Data CH10 Channel Data CH11 Channel Data CH12 Data CH13 Data CH14 Data CH15 Control item code 40HEX: color settings Default: [00000000] Data BCR0 color: setting kinds Data BCR1 Data BCR2 Data BCR3 Data BCG0 color: setting kinds Data BCG1 Data BCG2 Data BCG3 Control item code 50HEX: color setting Default: [00001010] Data BCB0 color: setting kinds Data BCB1 Data BCB2 Data BCB3 kinds each; selection color from 4096 Data data Fixed Control item code 60HEX: Chroma color settings Default: [00000000] Data CKR0 Chroma color: setting kinds Data CKR1 Data CKR2 Data CKR3 Data CKG0 Chroma color: setting kinds Data CKG1 Data CKG2 Data CKG3
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LC7874E Control item code 70HEX: Chroma color setting Default: [00000000] Data CKB0 Chroma color: setting kinds Data CKB1 Data CKB3 kinds each; selection color from 4096 Data data Fixed Control item code 80HEX: signal output/video signal output phase adjustment data setting Default: [00000000] Data signal output/video signal output phase adjustment data Data Data Data Data Data Fixed Data PAL60 PAL/PAL60 setting (valid only when PAL60 Data CSYSEL CSYNC output addressing (autonomous mode only) Equalization pulses used equalization pulses Control item code 90HEX: External synchronization control, test mode setting Default: [00000000] Data TST0 Test mode addressing (normally fixed low) Data TST1 Data TST2 Data Fixed Data HVMK HRESET, VRESET mask Mask used mask Data EXSN Sync signal rest control setting when using external clock (when Reset executed with HRESET (pin VRESET (pin signals Reset executed with VRESET (pin signal (HRESET signal unnecessary) Data MVMD Moving display area setting Movement display area only Border area included movement (only horizontal movement possible) Data CVSEL CSYNC output setting CSYNC output VSYNC output Control item code A0HEX: Superimposed text scroll amount, vertical setting Default: [00000000] Data SCV0 Upward scroll amount (font unit) setting (scroll amount: font units) Data SCV1 Screen display position scrolled vertically font unit Data SCV2 font unit: vertical dots (12H)) Data SCV3 Data SCV4 Data data Fixed
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LC7874E Control item code C0HEX: Superimposed text scroll amount, horizontal setting Default: [00000000] Data SCH0 Left scroll amount (font unit) setting (scroll amount: 49-font units) Data SCH1 Screen display position scrolled horizontally 1-font unit Data SCH2 (1-font unit: horizontal dots) Data SCH3 Data SCH4 Data SCH5 Data data Fixed Control item code 01HEX: 19-byte command input (MGC write) Transfer format
Address: F4HEX Control item: 01HEX sym0 sym19: subcode input Executed fall
Control item code 11HEX: 19-byte command input (pack data read) Transfer format
Address: F5HEX Data (check flags)
[PF1, PF0, QF1, QF0, DKMD, VBLK, EXEC, :LSB Data when next bytes guaranteed first data read. Note: Reading must completed within after output setting. Data EXEC Command status Command executing Command wait state Data VBLK output during vertical blanking (vertical retrace line) period Vertical retrace line period NTSC: PAL: Data DKMD Disk identification flag CD-G
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LC7874E Data Data Data Data error correction flag data error correction flag data error correction flag data error correction flag data
sym0, subcode input
Sample Application Circuit NTSC
products described contained herein intended surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment like, failure which directly indirectly cause injury, death property loss. Anyone purchasing products described contained herein above-mentioned shall: Accept full responsibility indemnify defend SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees, jointly severally, against claims litigation damages, cost expenses associated with such use: impose responsibility fault negligence which cited such claim litigation SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees jointly severally. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties. This catalog provides information January, 1997. Specifications information herein subject change without notice. 5521-22/22

LC7874E Graphics Decorder Overview LC7874E CMOS that pr

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