QUALITY SEMICONDUCTOR, INC. QuickSwitch® Products High-Speed CMOS

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QUALITY SEMICONDUCTOR, INC. QuickSwitch® Products High-Speed CMOS

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QS3ST253, QS3S253 ADVANCE INFORMATION
QUALITY SEMICONDUCTOR, INC.
QuickSwitch® Products High-Speed CMOS SynchroSwitchDual Mux/Demux With Optional Active Terminators (QS3ST253)
DESCRIPTION
QS3ST253 QS3S253 ADVANCE INFORMATION
FEATURES/BENEFITS
Enhanced channel with inherent diode Bidirectional signal flow Flow-through pinout Zero propagation delay, zero ground bounce banks Mux/Demux Port select synchronous clock Undershoot clamp diodes switch control pins Clock enable Asynchronous enable "Bus hold" terminators demux side Asynchronous option Break-before-make feature Available 20-pin QSOP Bus-hold eliminates floating lines reduces static power consumption QS3S253 non-bus-hold version QS3ST253 docking applications
QS3S253 QS3ST253 high speed CMOS dual multiplexer/demultiplexers. QS3ST253 active terminators (bus-hold circuits) demux side. Port selection connection, controlled signals, either asynchronous synchronous. synchronous mode, port port connection updated rising edge input clock CLK. Once port-to-port connection made, data flow bi-directional with typical 250ps propagation delay through switch. Clock Enable, over-riding Asynchronous Enable, Asynchronous Select controls provide additional design flexibility. bus-hold circuits QS3ST253 latch last data driven demux side, providing infinite hold time glitch-free signal transitions. Synchronous controls bus-hold ease timing constraints many high speed data mux/demux applications such bank interleaving. QS3S253 performs same function QS3ST253, does have terminators demux side. This facilitates 3.3V translation.
APPLICATIONS
Video, audio, graphics switching, muxing Hot-swapping, hot-docking Voltage translation 3.3V) QS3S253 only
Figure Functional Block Diagram
SEL0 SEL1 CLKEN SYNC
Control Logic
Bank
Bank
QS3ST253
MDSL-00135-01 JULY 1997
QUALITY SEMICONDUCTOR, INC.
QS3ST253, QS3S253 ADVANCE INFORMATION
Table Description
Name A0.D0 A1.D1 SEL0, SEL1 CLKEN OE0, SYNC Description Bank Demux Ports Bank Demux Ports Port Select Inputs Clock Clock Enable Output Enable Synchronous Enable
Figure Configuration (All Pins View) QSOP
SEL0 SEL1 CLKEN SYNC
Figure Control Logic
SEL0
BANK SWITCHES
DECODE LOGIC SWITCH CONTROL
CLKEN SYNC
SEL1
BANK SWITCHES
QUALITY SEMICONDUCTOR, INC.
MDSL-00135-01 JULY 1997
QS3ST253, QS3S253 ADVANCE INFORMATION Table Function Table
CONTROL INPUTS SYNC CLKEN SEL0 SEL1 Hold previous data (Switch OFF)
PORT STATUS Hold previous data(1) (Swich OFF) Hold previous connection(2) (Switch
Hold previous connection(2) (Switch
Hold previous data(3) Hold previous data(3) (Switch OFF) (Switch OFF)
Hold previous data(1) Hold previous data(1) (Switch OFF) (Switch OFF)
Notes: switches turned terminators (last value latches) hold previous data state. post connection changed inputs. contents "mux select register" unchanged previous connection unchanged. output (Mux port) data state will depend present data state input (Demux port). contents "mux select register" unchanged last value latch holds previous data state.
Table Absolute Maximum Ratings
Supply Voltage Ground -0.5V +7.0V Switch Voltage -0.5V +7.0V Input Voltage -0.5V +7.0V Input Voltage (for pulse width 20ns) -3.0V Output Current Max. Sink Current/Pin 120mA Maximum Power Dissipation 85°C 0.82 watts TSTG Storage Temperature -65°C +150°C
Note: ABSOLUTE MAXIMUM CONTINUOUS RATING those values beyond which damage device occur. Exposure these conditions conditions beyond those indicated rating adversely affect device reliability. Functional operation under absolute-maximum conditions implied.
Table Capacitance
25°C, MHz, VOUT Pins Control Inputs QuickSwitch Channels (Switch OFF) Demux QSOP Unit
Note: Capacitance guaranteed, production tested. total capacitance while switch please Section under "Input Switch Capacitance."
MDSL-00135-01 JULY 1997
QUALITY SEMICONDUCTOR, INC.
QS3ST253, QS3S253 ADVANCE INFORMATION Table Electrical Characteristics Over Operating Range
-40°C 85°C, 5.0V Symbol Parameter IBHL IBHH Input HIGH Voltage Input Voltage Input Leakage Current (Control Inputs) Test Conditions Guaranteed Logic HIGH Control Pins Guaranteed Logic Control Pins Typ(1) 0.01 0.01 Unit
Off-State Current (Hi-Z) Switch Resistance
Min., 0.0V, 30mA Min., 2.4V, 15mA Min. Switch Max. 0.8V 2.0V QS3S253 only
Input Hold Current(3,4) Input Current(5) Pass Voltage(6)
IOUT -5µA
Notes: Typical values indicate 5.0V 25°C. Measured voltage drop between A/B/C/D indicated current through switch. diagram explaining procedure measurement, please Section under Electrical Characteristics." guaranteed, production tested. IBHL Minimum sustaining `sink' current input 0.8V. This parameter signifies latching capability Bus-hold circuit logic state. IBHH Minimum sustaining `source' current input 2.0V. This parameter signifies latching capability Bus-hold circuit logic HIGH state. Magnitude input current specified under conditions: Input voltage This indicates input current under steady-state condition. Input voltage between 0.8V 2.0V (TTL input threshold range). This indicates maximum input current during transient condition. driver connected input must overcome this current requirement order switch logic state Bus-hold circuit. Pass voltage guaranteed, production tested.
Figure Typical Resistance 5.0V
(ohms)
(Volts)
QUALITY SEMICONDUCTOR, INC. MDSL-00135-01 JULY 1997
QS3ST253, QS3S253 ADVANCE INFORMATION Table Power Supply Characteristics Over Operating Range
-40°C 85°C, 5.0V Symbol ICCQ QCCD Parameter Quiescent Power Supply Current Power Supply Current Control Input HIGH(2) Dynamic Power Supply Current MHz(3) Test Conditions(1) Max., VCC, Max., 3.4V, Max., A/B/C/D Pins Open, Control Input Toggling Duty Cycle 0.25 Unit
Notes: conditions shown Min. Max., appropriate values specified under specifications. driven input (VIN 3.4V, control inputs only). A/B/C/D pins contribute ICC. This current applies control inputs only represents current required switch internal capacitance specified frequency. A/B/C/D inputs generate significant currents they transition. This parameter guaranteed, production tested.
Table Switching Characteristics Over Operating Range
-40°C 85°C, 5.0V CLOAD 50pF, RLOAD unless otherwise noted.
Symbol tPLH tPHL tSEC tHEC tCSO tASO tSCS tHCS tPZL, tPZH tPLZ, tPHZ
Description(1) Data Propagation Delays(2,3) A/B/C/D A/B/C/D Clock Enable Clock Setup Time Clock Enable Clock Hold Time Clock Switch Turn-on Delay(4) Asynchronous Select Switch Turn-on Delay(4) Clock Pulse Width (High) Clock Setup Time Clock Hold Time Asynchronous Enable Switch Turn-on Delay
Unit
QS3ST253, QS3S253 0.25
Asynchronous Enable Switch Turn-off Delay(2,4)
Notes: Test Circuit Waveforms. This parameter guaranteed, production tested. switch contributes propagation delay other than delay resistance switch load capacitance. time constant switch alone order 0.25ns 50pF. Since this time constant much smaller than rise/fall times typical driving signals, adds very little propagation delay system. Propagation delay switch when used system determined driving circuit driving side switch interaction with load driven side. Minimums guaranteed production tested.
MDSL-00135-01 JULY 1997
QUALITY SEMICONDUCTOR, INC.
QS3ST253, QS3S253 ADVANCE INFORMATION Figure Timing Waveforms: Synchronous Mode, Demux Function
Example: Port A/Port Port
SYNC
tSEC tHEC
CLKEN
tSCS tHCS tSCS tHCS
SEL0, SEL1
OE0,
tCSO
Port
DATA0
DATA1
tPLH, tPHL
DATA2
Port INVALID DATA
DATA0
DATA1
HOLD PREVIOUS DATA, DATA1
PLH, tPHL
tCSO
Port
INVALID DATA
DATA1 DATA2 HOLD PREVIOUS DATA, DATA2
QUALITY SEMICONDUCTOR, INC.
MDSL-00135-01 JULY 1997
QS3ST253, QS3S253 ADVANCE INFORMATION Figure Timing Waveforms: Synchronous Mode, Function
Example: Port A/Port Port
SYNC
tSEC tHEC
CLKEN
tSCS tHCS tSCS tHCS
SEL0
Port
DATA1
DATA2
Port
tCSO tPLH, tPHL tCSO
DATA3
DATA4
tPLH, tPHL
Port
INVALID DATA
DATA1
DATA2
DATA3
DATA4
MDSL-00135-01 JULY 1997
QUALITY SEMICONDUCTOR, INC.
QS3ST253, QS3S253 ADVANCE INFORMATION Figure Timing Waveforms: ASynchronous Mode, Function
Example: Port A/Port Port
SYNC
SEL0, SEL1
OE0,
Port
INVALID DATA
DATA1
tPLH, tPHL
DATA2
tPLH,
Port
INVALID DATA
DATA3
tASO
tPLZ, tPHZ
DATA3
tPZL, tPZH
Port
INVALID DATA
DATA1
DATA2
DATA3
QUALITY SEMICONDUCTOR, INC.
MDSL-00135-01 JULY 1997
QS3ST253, QS3S253 ADVANCE INFORMATION ACTIVE TERMINATOR 'BUS-HOLD' CIRCUIT
Active Terminator circuit, also known Bus-hold circuit, configured `weak latch' with positive feedback. When connected CMOS input port, Bus-hold circuit holds last logic state input when input `disconnected' from driver. When output device connected such input attempts logic level transition, will overdrive Bus-hold circuit. primary benefit Bus-hold circuit that prevents CMOS inputs from floating, situation which should avoided prevent spurious switching inputs unnecessary power dissipation. Bus-hold better solution than traditional approach using resistive termination prevent floating, because Bus-hold circuit does consume static power.
Figure Characteristics Bus-hold Circuit
Sinking Current
IBHL IBHH
IBHL
IBHH
Voltage
Sourcing Current
-500
Threshold Voltage 1.5V
Figure Shows input characteristics typical Bus-hold implementation. input characteristics resemble resistor. input voltage increased from volts, input `sink' current increases linearly. When threshold circuit reached (typically Volts), latch changes logic state positive feedback direction current reversed. input voltage further increased towards VCC, input `source' current begins decrease, reaching lowest level VCC.
MDSL-00135-01 JULY 1997
QUALITY SEMICONDUCTOR, INC.

QUALITY SEMICONDUCTOR, INC. QuickSwitch® Products High-Speed CMOS

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