Using Synplify Design Actel Radiation-Hardened FPGAs Actel's RadH

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Using Synplify Design Actel Radiation-Hardened FPGAs Actel's RadH

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Using Synplify Design Actel Radiation-Hardened FPGAs
Actel's RadHard RadTolerant FPGAs offer advantages applications commercial military satellites, deep space probes, types military high reliability equipment. Synplify version 5.31 later provides designers radiation-hardened FPGAs automatic means steering synthesis away from standard commercial sequential elements (flip-flops). Synplify automatically infers either C-C, TMR, TMR_CC implementations place normal flip-flops, instead post-processing netlist flip-flop substitution. This application note intended help designers understand design flow required when using Synplify design Actel's radiation-hardened FPGAs.
Techniques
your design then selectively override different portions. also control design technique apply register register basis. values "syn_radhardlevel" are: "none" standard design techniques "cc" implementation "tmr" implementation "tmr_cc" TMR_CC implementation
influence device's resistance (single event upset) effects using certain logic design techniques. default technique, using S-FFs, produces designs that most susceptible effects. Because devices have S-modules, S-FFs cannot implemented these devices. There resistant design techniques addition default) that used Actel devices with Synplicity. techniques are, order increasing resistance effects, CC-FFs triple voting. Synplicity also enables custom implementations. single design incorporate these design techniques.
Using CC-FFs
Actel recommends three techniques implementing logic sequential elements radiation-hardened FPGAs (C-C, TMR, TMR_CC). technique uses combinatorial cells with feedback (instead flip-flop latch primitives) implement storage. example, DFP1 (comprised combinational modules) would used place DF1. acronym triple-module-redundancy triple voting). register implementation technique; each register implemented three flip-flops latches) that "vote" determine state register. TMR_CC also triple-module-redundancy technique. Each voting register composed combinatorial cells with feedback (instead flip-flop latch primitives). Some techniques available appropriate Actel families. Please contact Actel technical support more information.
CC-FFs produce designs that more resistant effects than designs that S-FFs. 40MX devices CC-FFs default. CC-FFs cannot implemented 54SX devices this time. CC-FFs typically twice area resources S-FFs.
Using Triple Voting
Synplify provides attribute called "syn_radhardlevel" specify register implementation technique designs that Actel's radiation-hardened FPGAs. apply this attribute module, architecture, register output signal (inferred register VHDL). necessary, apply globally top-level module architecture
Triple voting, triple module redundancy (TMR), produces designs that most resistant effects. Instead single flip-flop, triple voting uses three flip-flops leading majority gate voting circuit. This way, flip-flop flipped wrong state, other override correct value propagated rest circuit. Because cost (three four times area times delay required S-FF implementations), triple voting usually implemented using S-FFs. However, implement triple voting using only CC-FFs Synplicity.
2000 Actel Corporation
Figure displays some examples register implementation described above after using "syn_radhardlevel" attribute.
dfpc
sum\[6\].u1
TMR_CC
Figure Logic Implementations Radiation-Hardened Register attribute only effective corresponding Actel Verilog (*.v) VHDL (*.vhd) macro file(s) design technique(s) included Source Files list your Synplify Project. first Actel file specified list determines default (global) design technique. Then "syn_radhardlevel" override your defaults register register basis sub-module level.
VHDL
library synplify; synplify.attributes.all; architecture isattribute syn_radhardlevel top: architecture "tmr_cc"; Other coding
"syn_radhardlevel" attribute different ways. following "syn_radhardlevel" examples describe design constraint, Verilog, VHDL file.
design example actual design. illustrates example flow Actel radiation-hardened design attribute "syn_radhardlevel." design written Verilog. source code files listed Appendix. design levels hierarchies, shown Figure page design requirements radiation hardened example design follows: Default (global) implementation registers must "tmr". Register "b1_int" "top" module must implemented "tmr_cc". registers "module_b" implemented "cc". module must
define_attribute {dataout[3:0]} syn_radhardlevel {"cc"}
module (clk, dataout, input clk; input input output dataout [3:0]; [3:0] dataout synthesis syn_radhardlevel="tmr" Other coding
registers "module_d" implemented "tmr_cc"
module
must
using Synplify attribute "syn_radhardlevel" conjunction with Actel macro files, Synplify enables design Actel's radiation-hardened FPGAs with little effort. However, allows precise control register implementation. only need focus controlling designs, controlling tool. easy clean flow helps reduce design cycle improve productivity.
module_a
module_d
module_b
module_c
Figure Example Hierarchy Design following steps complete design satisfy requirements: Bring "top.v" your favorite editor make following edit:
[15:0] a1_int, b1_int synthesis syn_radhardlevel="tmr_cc"
Note:
Step design requirement
Edit "module_b.v" following:
module module_b sub, clk, rst) /*synthesis syn_radhardlevel="cc"
Note:
Step design requirement
Edit "module_d.v" following:
module module_d sum, clk, rst) /*synthesis syn_radhardlevel="tmr_cc"
Note:
Step design requirement
Bring Synplify create project. Synplify "Set Device Options" window, select Actel device that RadHard RadTolerant. Actel Verilog macro files ("cc.v," "tmr.v," "tmr_cc.v") project, with "tmr.v" listed first file. Since three register implementations, three Verilog macro files need included project. With "tmr.v" listed first file, ensures that global register implementation "tmr" (requirement
Note:
design modules project. Click RUN. Click "Technology View" button confirm implementations.
Appendix This appendix lists five modules used Design Example section application note.
module sel_byte0, clk, sum_out, sum_carry, sub_out, sub_carry, shft_out, rst); input [15:0] input clk,rst,sel_byte0; output [7:0] sum_out, sub_out; output sum_carry, sub_carry; output [8:0] shft_out; wire [7:0] sum_out, sub_out; wire sum_carry, sub_carry; wire [8:0] sum_out_int, sub_out_int, shft_out_int; [15:0] a1_int, b1_int synthesis syn_radhardlevel="tmr_cc" [7:0] a_byte, b_byte; regsel_byte0_int; always (posedge posedge rst) begin (rst) begin a1_int b1_int sel_byte0_int else begin a1_int b1_int sel_byte0_int sel_byte0; always a1_int begin (sel_byte0_int) a_byte a1_int b_byte b1_int else begin a_byte a1_int b_byte b1_int b1_int sel_byte0_int) begin [7:0]; [7:0];
[15:8]; [15:8];
module_a (a_byte, b_byte, sub_out_int, shft_out, clk, rst); module_d (a_byte, b_byte, sum_out_int, clk, rst);
assign sum_out sum_out_int[7:0]; assign sum_carry sum_out_int[8]; assign sub_out sub_out_int[7:0]; assign sub_carry sub_out_int[8]; assign shft_out shft_out_int; endmodule
Using Synplify Design Actel Radiation-Hardened FPGAs
module module_a sub, shft, clk, rst); input [7:0] input clk, rst; output [8:0] sub, shft; module_b sub, clk, rst); module_c shft, clk, rst); endmodule
module module_b sub, clk, rst) /*synthesis syn_radhardlevel="cc" input [7:0] input clk, rst; output [8:0] sub; [8:0] sub; [7:0] a_int, b_int; always (posedge posedge rst) (rst) begin a_int b_int else begin a_int b_int a_int b_int; endmodule
module module_c shft, clk, rst); input [7:0] input clk, rst; output [8:0] shft; [8:0] shft; [7:0] a_int; always (posedge posedge rst) (rst) begin a_int shft else begin a_int shft a_int endmodule
module module_d sum, clk, rst) /*synthesis syn_radhardlevel="tmr_cc" input [7:0] input clk, rst; output [8:0] sum; [8:0] sum; [7:0] a_int, b_int; always (posedge posedge rst) (rst) begin a_int b_int else begin a_int b_int a_int b_int; endmodule
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Using Synplify Design Actel Radiation-Hardened FPGAs Actel's RadH

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