Preliminary Data Sheet 06.99 24901 Revision History: Previous Ver
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Quad ISDN 4B3T Echocanceller Digital Front DFE-T V2.1 24901 Version
Preliminary Data Sheet 06.99
24901 Revision History: Previous Version: Page Page previous current Version) Version) Subjects (major changes since last revision) Current Version: 06.99
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ABM®, AOP®, ARCOFI®, ARCOFI®-BA, ARCOFI®-SP, DigiTape®, EPIC®-1, EPIC®-S, ELIC®, FALC®54, FALC®56, FALC®-E1, FALC®-LH, IDEC®, IOM®, IOM®-1, IOM®-2, IPAT®-2, ISAC®-P, ISAC®-S, ISAC®-S ISAC®-P ITAC®, IWE®, MUSAC®-A, OCTAT®-P, QUAT®-S, SICAT®, SICOFI®, SICOFI®-2, SICOFI®-4, SICOFI®-4µC, SLICOFI® registered trademarks Infineon Technologies ACETM, ASMTM, ASPTM, POTSWIRETM, QuadFALCTM, SCOUTare trademarks Infineon Technologies Edition 06.99 Published Infineon Technologies Gr., 81541 Infineon Technologies i.Gr. 1999. Rights Reserved. Attention please! patents other rights third parties concerned, liability only assumed components, applications, processes circuits implemented within components assemblies. information describes type component shall considered assured characteristics. Terms delivery rights change design reserved. technical requirements components contain dangerous substances. information types question please contact your nearest Infineon Technologies Office. Infineon Technologies approved CECC manufacturer. Packing Please recycling operators known you. also help touch with your nearest sales office. agreement will take packing material back, sorted. must bear costs transport. packing material that returned unsorted which obliged accept, shall have invoice costs incurred. Components used life-support devices systems must expressly authorized such purpose! Critical components1 Infineon Technologies only used life-support devices systems2 with express written approval Infineon Technologies critical component component used life-support device system whose failure reasonably expected cause failure that life-support device system, affect safety effectiveness that device system. Life support devices systems intended implanted human body, support and/or maintain sustain human life. they fail, reasonable assume that health user endangered.
24901
Preface
This document describes interfaces, functions behavior QUAD ISDN 4B3T Echocanceller Digital Front (DFE-T V2.1). 24901 digital part twochip solution featuring four times ISDN basic rate access 144kbit/s. DFE-T V2.1 supersedes existing versions, DFE-T V1.1 DFE-T V1.2. corresponding Analog Front End, V2.1 (PEF 24902) described detail Data Sheet V1.1, Delta Sheet V1.2 Delta Sheet V2.1. Organization this Document This Preliminary Data Sheet divided into chapters. organized follows: Chapter Introduction Gives general description product family, lists features, presents some typical applications. Chapter Description Lists locations with associated signals, categorizes signals according function, describes signals. Chapter Functional Description Gives functional overview device, shows block diagram, specifies various interfaces describes provided U-transceiver functions. Chapter Operational Description Describes reset power-down behavior, illustrates activation deactivation procedures, shows device tested maintenance data retrieved. Chapter Monitor Commands Lists available Monitor Commands that applied. Chapter Register Description Lists register functions that addressable MON-12 protocol which behaves like serial microprocessor interface. Chapter Electrical Characteristics Denotes operating conditions gives exact interface timing. Chapter Package Outlines Chapter Appendix Standards Specifications
Preliminary Data Sheet
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Chapter Glossary Chapter Index
Related Documentation DFE-T V2.1 Product Overview 04.99 DFE-T V2.1 Delta Sheet 03.98 V1.1 Data Sheet 05.96 V1.2 Delta Sheet 06.97 V2.1 Delta Sheet 09.98
Your Comments welcome your comments this document continuously aiming improving documentation. Please send your remarks suggestions e-mail sc.docu_comments@infineon.com Please provide subject your e-mail: device name (DFE-T V2.1), device number (PEF 24901), device version (Version 2.1), body your e-mail: document type (Preliminary Data Sheet), issue date (06.99) document revision number
Preliminary Data Sheet
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Table Contents
Page
Preface 3.3.1 3.3.2 3.3.3 3.3.4 3.6.1 3.6.2 3.6.3 3.6.4 3.6.5 3.6.6 3.6.7 3.6.8 3.6.9 3.6.10 3.6.11 3.6.12 3.6.12.1 3.6.12.2 3.6.12.3 Introduction Features Logic Symbol System Integration Operational Overview Descriptions Diagram Definitions Functions Pinning Changes from DFE-T V1.2 DFE-T V2.1 Functional Description Functional Overview Block Diagram IOM®-2 Interface IOM®-2 Interface Frame Structure IOM®-2 Command/ Indicate Channel IOM®-2 Monitor Channel MON-12 Protocol 3-11 Interface Analog Front 3-13 General Purpose I/Os 3-16 U-Transceiver Functions 3-17 4B3T Frame Structure 3-17 Maintenance Channel 3-20 Exchanging Transparent Messages 3-22 Coding from Binary Ternary Data 3-24 Decoding from Ternary Binary Data 3-25 Monitoring Code Violations 3-25 Scrambler Descrambler 3-26 4B3T Signal Elements 3-27 Awake Protocol 3-30 Codes 3-32 State Machine Notation 3-34 Mode State Diagram 3-35 State Machine Inputs 3-38 State Machine Outputs 3-40 State Description 3-41 Clock Generation 3-44 Operational Description Reset Power Down
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Table Contents 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 4.4.1 4.4.1.1 4.4.1.2 4.4.1.3 4.4.2 4.4.3 4.4.4 4.4.4.1 4.4.4.2 4.4.4.3 4.4.4.4 4.4.4.5 4.4.4.6 4.4.4.7 4.4.4.8 4.4.5 4.4.5.1 4.4.6 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.2.9
Page
Layer Activation/ Deactivation Procedures Complete Activation Initiated Exchange Complete Activation Initiated Complete Activation Initiated Exchange with Repeater Complete Activation Initiated Terminal with Repeater Deactivation Activation Loop#1 Activation Loop#1A 4-10 Activation Loop#2 4-11 Maintenance Test Functions 4-12 Test Loopbacks 4-12 Analog Loopback (No.1) 4-13 Loopback No.2 4-13 Available Loopbacks Register 4-14 Block Error Counter 4-16 Error Rate Counter 4-16 System Measurements 4-17 Send Single Pulses Test Mode (SSP) 4-17 Data Through Mode (DT) 4-17 Master Reset Mode 4-17 Pulse Mask Measurement 4-18 Power Spectral-Density Measurement 4-18 Return-Loss Measurement 4-18 Quiet Mode Measurement 4-18 Insertion Loss Measurement 4-18 Retrieving Data 4-19 Reading/Writing Coefficient Values 4-21 Boundary Scan 4-23 Monitor Commands Register Description Register Summary Detailed Register Description LP_SEL Line Port Selection Register OPMODE Operation Mode Register M-Bit Read M-Bit Write Register TEST Test Register LOOP Loopback Register Block Error Counter Register 6-10 BERC Error Rate Counter Register 6-11 Registers 6-12
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Table Contents 7.4.1 7.4.2 7.4.3 7.4.4 7.6.1 7.6.2
Page
Electrical Characteristics Absolute Maximum Ratings Operating Range Characteristics Characteristics Reset Timing IOM®-2 Interface Timing Interface Analog Front Boundary Scan Timing Capacitances Power Supply Supply Voltage Power Consumption Package Outlines Appendix Standards Specifications Glossary 10-1 Index 11-1
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List Figures Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 3-10 Figure 3-11 Figure 3-12 Figure 3-13 Figure 3-14 Figure 3-15 Figure 3-16 Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 4-10 Figure 4-11 Figure 4-12 Figure 4-13 Figure Figure Figure Figure Figure
Page
DFE-T/ Generation Chip Logic Symbol 16-Line Card Application with DELPHI Solution 16-Line Card Application with ELIC®/ IDEC® Solution Connecting AFE/DFE-T Chip Sets Recommended Clocking Scheme More Than DFE-T/AFE Chip Sets Configuration used) Data Flow Diagram (DFE-T V2.1 AFE). DFE-T V2.1 Block Diagram Clock Supply Data Exchange between Master Slave Multiplexed Frame Structure IOM®-2 Interface Handshake Protocol with 2-Byte Monitor Message/Response Abortion Monitor Channel Transmission Monitor Access with Enabled 3-10 Interface Analog Front 3-13 Frame Structure SDX/SDR 3-14 M-Bit Access MRD, Register Pair. 3-22 M-Bit Access Timing 3-23 Awake Procedure initiated 3-30 Awake Procedure initiated 3-30 State Diagram Example 3-34 State Diagram 3-35 Maximum Tolerable Input Jitter 15.36MHz Clock 3-44 Activation Initiated Exchange Activation Initiated Activation with Repeater Initiated Activation with Repeater Initiated Deactivation (Always Initiated Exchange) Activation Loop#1 Activation Loop#1A (Repeater) 4-10 Activation Loop#2 4-11 Test Loopbacks 4-12 Loopback No.2 4-13 Loopbacks Featured Register LOOP 4-15 Data Transfer Synchronization Handshake Signals 4-19 Provided Registers Access Coefficient Data 4-21 DFE-T V2.1 Register Input/Output Waveform Tests. Reset Timing IOM®-2 Interface Timing (Double Clock Mode) Dynamic Input Output Requirements Analog Interface.
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Boundary Scan Timing.
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List Tables Table Table Table Table Table Table Table Table Table Table Table Table 3-10 Table 3-11 Table 3-12 Table Table Table Table Table Table Table Table Table Table Table Table Table
Page
Definitions Functions Pinning Changes IOM®-2 Data Rates Assignments IOM® Channels Time-Slots SDX/SDR Line Ports 3-14 Coding 4B3T Data Pulse (AOUT/BOUT) 3-15 Frame Structure Downstream Transmission 3-18 Frame Structure Upstream Transmission 3-19 Coding Table 3-24 4B3T Decoding Table 3-25 Coding 4B3T Signal Elements 3-27 4B3T Signal Elements 3-28 Command Indicate Codes 3-32 Differences LT-SM DFE-T V1.2 3-36 Timers 3-39 Boundary Scan Cells. 4-23 Controller Instructions: 4-25 MON-8 Commands MON-8 Indications MON-0 Commands MON-0 Indications Register Reference Table IOM®-2 Dynamic Input Characteristics IOM®-2 Dynamic Output Characteristics Dynamic Input Characteristics Dynamic Output Characteristics Boundary Scan Dynamic Timing Requirements Power Consumption.
Preliminary Data Sheet
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Introduction
Introduction
Quad ISDN 4B3T Echocanceller Digital Front (DFE-T) digital part optimized two-chip solution featuring ISDN basic rate access 144kbit/s. 24901 designed provide conjunction with Quad ISDN Echocanceller Analog Front (PEF 24902 V2.1) full duplex data transmission U-reference point according Guideline 220, ETSI ITU-T I.430 standards. DFE-T generation been completely reengineered guarantee availability well proved DFE-T/AFE solution over year 2000. 24901 V2.1 downwards compatible functionally equivalent DFE-T V1.x. Thus, line card manufacturers make most advanced process technology without need change their current design (besides changeover 3.3V power supply). software changes required DFE-T V2.1 deployed existing DFE-T V1.x solutions. Some features provided such transparent message exchange enhanced monitoring test functions. data rate programmable from 1Mbit/s 4Mbit/s.
15.36MHz
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output input pins throughout compatible although 24901 processed advanced 3.3V CMOS technology. power down state with very power consumption featured. 24901 comes P-MQFP-64 package.
Preliminary Data Sheet
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Quad ISDN 4B3T Echocanceller Digital Front DFE-T V2.1
24901
Version
CMOS
Features
U-Interface Digital part two-chip solution featuring full duplex data transmission reception over twowire metallic subscriber loops providing ISDN basic rate access kbit/s Conforms P-MQFP-64 (1991) ETSI V1.3.1 (1998) ITU-T I.430 (1995) 4B3T-block code 120-kHz symbol rate Subscriber loop length without repeater: wire wire mode kbit/s maintenance channel transmission data loopback commands, detected transmission errors transparent messages Activation/ deactivation controller Adaptive echo cancellation equalization Automatic gain control polarity adaption Clock recovery (frame synchronization) Transmission error counters line monitoring Remote local control test loops System Interface IOM®-2 interface with programmable data rates Mbit/s Mbit/s) relay driver pins port addressable Monitor command status pins port accessible Monitor channel
Type 24901
Preliminary Data Sheet
Package P-MQFP-64
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Introduction Other Features Software compatible 24901 V1.2 Inputs outputs compatible DOUT (open drain) accepts pull-up 3.3V Advanced power CMOS technology (digital: 0.35µ process) Sophisticated power management restricted power mode +3.3V ±0.3V Power Supply Extended temperature range 40.to 85°C) available Boundary-Scan, JTAG IEEE 1149.1
Add-On Features Differences with Respect DFE-T V1.2 +3.3V instead power supply Exchange transparent messages Maintenance channel MON-0 commands LT-RP mode supported DOUT configurable either open drain push-pull (tristate) output Monitor Time-Out (MTO) procedure Error Rate measurement port Additional digital local loops codes 'LTD' 'HI' more supported code mnemonics adapted 2B1Q notation consistency reasons coding been retained unchanged State machine notation aligned that 2B1Q consistency reasons MON-12 class features internal register access Coefficients retrievable MON-12 commands instead MON-8 commands Boundary-Scan instructions 'CLAMP' HIGHZ supported version ('SSP' omitted since this function dedicated reserved) JTAG Boundary-Scan with dedicated reset line TRST (replaces power-on reset functionality)
Preliminary Data Sheet
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Introduction
Logic Symbol
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Preliminary Data Sheet
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Introduction
System Integration
This paragraph shows DFE-T V2.1 integrated systems using other Infineon ISDN devices. 24901 V2.1 optimized following applications: Digital Line Cards Central Office Digital Line Cards Access Networks mode only) applications mode only) Figure Figure illustrate line card solutions with various Infineon line card controllers. DELPHI (PEB 20570) supersedes ELIC® (PEB 20550) will feature HDLC controllers on-chip.
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Preliminary Data Sheet
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Introduction
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Figure shows channel line card application realized AFE/ DFE-T chip sets: generates synchronized 15.36MHz clock provides master clock CL15 other devices. internal first synchronizes 15.36 master clock onto reference clock either 2048 kHz. second deactivated. 15.36 master clock applied CL15. CL15 configured input clamped either VSS. XOUT left open CLOCK shall tied GND.
Preliminary Data Sheet
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Introduction
15.36MHz
2048kHz Reference Cock
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DFE-T devices supplied first CL15 with synchronized 15.36MHz clock. IOM®-2 channels DFE-T devices assigned programmed slot pins. Starting from channel 0/4/8/12 always four subsequent channels occupied. Alternatively clocking scheme shown Figure applied more than devices clocked (e.g. 16-channel line card application). Instead supply with master clock CL15, here 15.36MHz master clock input XIN. Thereby CL15 configured output passes 15.36MHz clock attached DFE-T. clock chain extended same another AFE/DFE-T chip sets 16-channel line card application realized with just single crystal. Note that 15.36MHz clock inverted once input output CL15. This duty cycle recovered again.
Preliminary Data Sheet
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Introduction
15.36MHz
2048kHz Reference Cock
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Introduction
Operational Overview
DFE-T V2.1 operates always mode. System Interface Configurations following parameters system interface configurable: Open Drain/ Push-Pull Mode Configured open drain output DOUT floating pull-up resistor required. push-pull mode output high impedance outside active time slots. IOM®-2 Channel Assignment IOM®-2 channels always assigned blocks four.
SLOT1
SLOT0
Assigned IOM®-2 Channels
IOM®-2 Data Rates
Frequency [kHz] 2048 3072 4096 6144 8192
Data Rate [kBit/s] 1024 1536 2048 3072 4096
IOM®-2 Channels
Remarks
Burst Mode
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Introduction Send Single Pulses Test Mode test mode 'Send Single Pulses' pulses spaced transmitted lines. test mode activated SSP= '1'. test function well stimulated C/I= besides fact that selection impacts line ports while selection impacts only chosen line. Data Through Mode test mode 'Data Through' U-transceiver forced enter 'Transparent' state issue independent wake-up protocol. test mode activated '1'. test function well stimulated C/I= besides fact that selection impacts line ports while selection impacts only chosen line.
Preliminary Data Sheet
1-10
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Descriptions
Descriptions
Diagram
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Descriptions
Definitions Functions
Definitions Functions Symbol Input Output Function
Table
IOM®-2 Interface Frame Synchronization Clock (8kHz) start first B1-channel time-slot marked, expected least periods. Data Clock clock rate ranges from 2048 8192kHz (1024 4096kBit/s) Data input IOM®-2 data synchronous clock Data output IOM®-2 data synchronous clock
DOUT
(OD/ PuP)
Mode Selection Pins Reset triggers asynchronous reset, Schmitt trigger input '1'= inactive '0'= active IOM®-2 Channel Slot Selection assigns IOM®-2 channels blocks SLOT1, '00'= IOM®-2 channels '01'= IOM®-2 channels '10'= IOM®-2 channels '11'= IOM®-2 channels SLOT1 (PD) IOM®-2 Channel Slot Selection assigns IOM®-2 channels blocks internal pulldown resistor (160k)
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Descriptions Table Definitions Functions Symbol Input Output (PD) Function Monitor Channel Time-Out activated Monitor channel reset every 12ms, internal pulldown resistor (160k) '1'= enables 12ms time-out '0'= disables 12ms time-out (PD) Push Pull Mode push pull mode actively driven during occupied time slot soon 1.FSC received after reset), outside active time slots DOUT high impedance (tristate), internal pulldown resistor (160k) '1'= configures DOUT push/pull output '0'= configures DOUT open drain output Send Single Pulses (SSP) Test Mode '1'= pulses issued line ports intervals '0'= deactivated, clamp used
Note: This function corresponds selection C/I= besides fact that selection impacts line ports while selection impacts only chosen line
Data Through (DT) Test Mode enables/disables test mode '1'= test mode enabled, U-transceiver forced line ports enter 'Transparent' state '0'= test mode disabled
Note: This function corresponds selection C/I= besides fact that selection impacts line ports while selection impacts only chosen line
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Descriptions Table Definitions Functions Symbol Input Output Function
Interface Analog Front CL15 PDM0 15.36MHz Master Clock Input Pulse Density Modulated Receive Data Line Port pulse density modulated stream from 24902 Quad that output from second-order sigma-delta Pulse Density Modulated Receive Data Line Port pulse density modulated stream from 24902 Quad that output from second-order sigma-delta Pulse Density Modulated Receive Data Line Port pulse density modulated stream from 24902 Quad that output from second-order sigma-delta Pulse Density Modulated Receive Data Line Port pulse density modulated stream from 24902 Quad that output from second-order sigma-delta Serial Data Receive Line interface signal from PEB24902 Quad that transports level detect information wake-up recognition lines
PDM1
PDM2
PDM3
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Descriptions Table Definitions Functions Symbol Input Output Function Serial Data Transmit Line interface PEB24902 Quad transmit control data. Transmission based clock CL15 (15.36 Mbit/s). each line port following bits exchanged: TD0, TD1: Transmit data RANGE: Range select LOOP: Analog loopback switch PDOW: Power down/power Synchronization information
Relay Driver/ Status Pins Relay Driver Pins Line Port addressable MON-8 command IOM®-2 channel 0/4/8/12. logic values positions A,B,C, MON-8 command 'SETD' determine output setting. Default value after pin-reset low. C/I-code reset does affect current status. Relay Driver Pins Line Port addressable MON-8 command IOM®-2 channel 1/5/9/13. logic values positions A,B,C, MON-8 command 'SETD' determine output setting. Default value after pin-reset low. C/I-code reset does affect current status. Relay Driver Pins Line Port addressable MON-8 command IOM®-2 channel 2/6/10/14. logic values positions A,B,C, MON-8 command 'SETD' determine output setting. Default value after pin-reset low. C/I-code reset does affect current status.
Preliminary Data Sheet
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Descriptions Table Definitions Functions Symbol Input Output Function Relay Driver Pins Line Port addressable MON-8 command IOM®-2 channel 3/7/11/15. logic values positions A,B,C, MON-8 command 'SETD' determine output setting. Default value after pin-reset low. C/I-code reset does affect current status. Status Line Port change status passed IOM®-2 channel 0/4/8/12 MON-8 message 'AST' positions Connect either used. Status Line Port change status passed IOM®-2 channel 1/5/9/13 MON-8 message 'AST' positions Connect either used. Status Line Port change status passed IOM®-2 channel 2/6/10/14 MON-8 message 'AST' positions Connect either used. Status Line Port3 change status passed IOM®-2 channel 3/7/11/15 MON-8 message 'AST' positions Connect either used.
ST00 ST01
ST10 ST11
ST20 ST21
ST30 ST31
Test Pins CLS0 CLS1 CLS2 120kHz Transmit Baud Clock Port used monitoring test purposes 120kHz Transmit Baud Clock Port used monitoring test purposes 120kHz Transmit Baud Clock Port used monitoring test purposes
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Descriptions Table Definitions Functions Symbol CLS3 Input Output Function 120kHz Transmit Baud Clock Port used monitoring test purposes Test available user. Connect GND.
JTAG Boundary Scan TRST (PU) (PU) (PU) Test Clock Test Mode Select internal pullup resistor (160k) Test Data Input internal pullup resistor (160k) Test Data Output JTAG Boundary Scan Disable resets controller state machine (asynchronous reset), active internal pullup (160k) '1'= reset inactive '0'= reset active Power Supply Pins
PuP: Open Drain Push Pull Internal Pull Down Internal Pull
3.3V ±0.3V supply voltage ground
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Descriptions
Pinning Changes from DFE-T V1.2 DFE-T V2.1
Pinning Changes V2.1 V1.2 N.C. SLOT2 Comment activates Monitor Time-Out procedure provided IEC-Q additional push-pull mode eases interface adaption, SLOT2 used V1.2 renamed V1.x LT-RP mode neither supported V2.1 dedicated 'Send Single Pulses' test mode dedicated 'Data Through' test mode power-on-reset replaced dedicated reset line
Table
N.C. TRST
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Functional Description
Functional Description
Functional Overview
functional overview DFE-T V2.1 given Figure 3-1. Besides signal processing frame formatting blocks 24901 features on-chip activation/ deactivation controller programmable general purpose pins control test relays power feeding circuits. application specific core services four lines cuts chip size minimum.
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Functional Description
Block Diagram
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Functional Description
IOM®-2 Interface
IOM®-2 interface four-wire serial interface providing symmetrical full-duplex communication link layer-1 layer-2 backplane devices. transports user data, control/programming status information dedicated time multiplexed channels. structure used follows D-channel structure ISDN. ISDN-user data rate kbit/s U-interface transmitted transparently both directions IOM®) over interface.
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Frame Sync Signal signal delimiting frames. This signal used determine start frame. data clocked Data Clock (DCL) which operates twice data rate. data clock square wave signal with duty cycle ratio typically 1:1. Incoming data sampled falling edge DCL-clock. Data carried over Data Upstream (DD) Data Downstream (DU) signals. upstream downstream directions always defined with respect exchange: Downstream refers information flowing from exchange subscriber, upstream defined vice versa. output line operating either open drain push-pull output. Both modes selected signal "PUP". open drain mode external pull-up resistor required. absence pull-up resistor automatically recognized (i.e. push-pull detection).
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Functional Description Within FSC-period, transmitted, corresponding DCLfrequencies ranging from 2048 8192 kHz. following table shows possible operating frequencies IOM®-2-interface. Table IOM®-2 Data Rates Data Rate [kBit/s] 1024 1536 2048 3072 4096 IOM®-2 Channels Burst Mode Remarks
Frequency [kHz] 2048 3072 4096 6144 8192
3.3.1
IOM®-2 Interface Frame Structure
typical IOM®-2 line card application comprises DCL-frequency 4096 with nominal rate 2048 kbit/s. Therefore eight channels available, each consisting basic frame with nominal data rate kbit/s. downstream data (DD) transferred signal DIN, upstream data (DU) signal DOUT. IOM®-2 channel assignment programmable strapping (SLOT1,0). basic IOM®-2 frame clocking structure consists
channel bits
Monitor
Command Indicate
64-kbit/s channels monitor channel transferring maintenance information between layer-1 layer-2 devices bits 16-kbit/s D-channel Four command indication (C/I) bits controlling layer-1 functions (activation/ deactivation additional control functions) layer-2 controller bits handling monitor channel
Preliminary Data Sheet
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Functional Description
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Multiplexed Frame Structure IOM®-2 Interface
3.3.2
IOM®-2 Command/ Indicate Channel
Command/Indication (C/I) channel carries real-time control status information between DFE-T V2.1 layer-1 control device. code must detected consecutive IOM®-2 frames considered valid (double last look criterion). indication issued permanently DFE-T V2.1 DOUT until indication needs forwarded. code wide located positions 27-30 each time-slot. listing explanation U-transceiver codes found page 3-32.
3.3.3
IOM®-2 Monitor Channel
Monitor channel represents second method initiating reading U-transceiver specific information. Features monitor channel supplementary command/indicate channel. Unlike command/indicate channel with emphasis status control, monitor channel provides access internal bits (maintenance, overhead) test functions (local loop-backs, block error counter self-test). Besides known MON-8 commands classes, MON-0 MON-12 introduced DFE-T V2.1: MON-0 Class Like 2B1Q version MON-0 messages allow user transfer transparent
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Functional Description messages across U-interface. MON-12 Class MON-12 commands DFE-T V2.1 provides ability address parts device internal register thus address functions that have been added with version 2.1. MON-12 commands always prioritized processed first other Monitor commands outstanding. Chapter 3.3.4 details. This means that Monitor commands split into three categories. Each category derives name from first nibble bits) byte long message. These are: MON-12 MON-0 MON-8 (Internal Register Map) (Transparent Channel) (Local Functions)
order list above corresponds priority attributed each category. MON12 commands always processed first. MON-0 messages will transmitted before MON-8 messages case several messages initiated simultaneously. various MON-0 MON-8-commands discussed detail chapter "Monitor Commands" page 5-1. Structure structure Monitor channel wide, located position every time-slot. Monitor commands/messages sent to/from U-transceiver always bytes long. Transmission multiple monitor bytes specified IOM®-2 (see next section "Handshake Procedure" details). handshake control multiple byte transfers, monitor read "MR", monitor transmit "MX", every time-slot used. Verification double last-look criterion implemented monitor channel. monitor message that received consecutively after change been detected identical message that received before message will aborted. Handshake Procedure IOM®-2 provides sophisticated handshake procedure transfer monitor messages. handshake control bits, assigned each IOM®-2 frame DOUT). monitor transmit (MX) indicates when byte been issued monitor channel (active low). transmitter postpones transmitting next information until correct reception been confirmed. correct reception will confirmed setting monitor read (MR) low.
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Functional Description monitor channel full duplex operates pseudo-asynchronous base, i.e. while data transfer takes place synchronized frame synchronization, flow monitor data controlled MX-bits. Monitor data will transmitted repeatedly until reception acknowledged. Figure illustrates monitor transfer maximum speed. transmission 2-byte monitor command followed 2-byte response requires minimum frames (reception frames transmission frames 1.875 ms). case controller able confirm receipt first response byte frame immediately following MX-transition DOUT from high (i.e. frame byte saved frames frames). Transmission reception monitor messages performed simultaneously U-transceiver. procedure depicted Figure would possible Utransceiver transmit monitor data frames (excluding EOM-indication) receive monitor data from frame onwards.
1/2: 1/2:
Monitor message byte Monitor response byte
Figure Idle State
Handshake Protocol with 2-Byte Monitor Message/Response
After bits have been held inactive (i.e. high) more successive IOM®-frames, channel considered idle this direction.
Preliminary Data Sheet
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Functional Description Standard Transmission Procedure first byte monitor data placed external controller line DFE-T V2.1 activated (low; frame DFE-T V2.1 reads data monitor channel acknowledges setting MR-bit DOUT active transmitted bytes identical received frames (frame because data already read compared while MX-bit activated). second byte monitor data placed controller MX-bit inactive single IOM®-frame. This performed time convenient controller. DFE-T V2.1 reads data byte monitor channel after rising edge been detected. frame immediately following MX-transition activeto-inactive, MR-bit DOUT inactive. MR-transition inactive-to-active exactly IOM®-frame later regarded acknowledgment external controller (frame 4-5). acknowledgment DFE-T V2.1 will always sent IOM®-frames after activation data byte. After both monitor data bytes have been transferred DFE-T V2.1, controller transmits "End Message" (EOM) setting MX-bit inactive more IOM®-frames (frame 5-6). frame following transition MX-bit from active inactive, DFE-T V2.1 sets MR-bit inactive case step detects EOM, keeps MR-bit inactive (frame transmission monitor command controller complete. DFE-T V2.1 requested return answer will commence with response soon possible. case "monitor time out" function enabled have postpone answer until after internal reset (see section Monitor Procedure Time-out details). Figure illustrates case where response sent immediately. procedure response similar that described points except transmission direction. assumed that controller does latch monitor data. this reason additional frame will required acknowledgment. Transmission monitor byte will started DFE-T V2.1 frame immediately following acknowledgment first byte. U-transceiver does delay monitor transfer.
Preliminary Data Sheet
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Functional Description Transmission Abortion detected after first monitor bytes, received bytes identical first received frames, transmission will aborted through receiver setting MR-bit inactive more IOM®-2-frames. controller reacts with EOM. This situation illustrated Figure 3-6.
Figure
Abortion Monitor Channel Transmission
MONITOR Procedure Time-Out (MTO) DFE-T V2.1 offers internal reset (monitor procedure "Time-out") monitor routine. This reset function transfers monitor channel into idle state high) thereby resolving possible lock-up situations. therefore used systems where microprocessor capable detecting solving hang-up situations monitor procedure. reset procedure started intervals. order avoid loss transmitted received data DFE-T V2.1 commences monitor transfer only when enough time available before next reset will initiated. this case transmission postponed until after reset. Once message been issued IOM®-2, transfer needs completed before next reset. this accomplished, message lost without notice. this reason control software should able transfer monitor messages quickly possible. Signal "MTO" enables MTO-function, signal "MTO" disables
Preliminary Data Sheet
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Functional Description With MTO-function enabled, monitor routine reset every 12ms. Every reset sets both handshake bits DOUT idle state high) thereby preventing lock-up situations. reset synchronously. With MTO-function disabled internal resets performed. this case external controller must prevent lock-up situations monitor channel.
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Figure
Monitor Access with Enabled
Note that there relationship reset timing U-frame, since superframe exists 2B1Q line code. DFE-T V2.1 operates Transmitter with Enabled transmitter reset 12ms intervals shown figure above. case transmission monitor message been completed before transmitter reset, complete message will lost. message that been lost interruption monitor reset will retransmitted. prevent this loss monitor messages, DFE-T V2.1 will only commence monitor transmission more than IOM®-2 frames will available transmission before next reset occurs. ensure correct transmission receiver must delay receive procedure more than following value: 2-byte transmission: max. speed frames max. controller (receive) delay frames DFE-T V2.1 operates Receiver with Enabled receiver reset 12ms intervals shown figure above. case reception monitor message been completed before receiver reset, complete message lost because generation abort request guaranteed.
Preliminary Data Sheet
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Functional Description prevent this loss monitor messages DFE-T V2.1 will only commence monitor reception (i.e. acknowledge received byte) more than IOM®-2 frames will available reception before next reset occurs. Reception thus does start there less than (=16x IOM®-2 frames) time left. ensure correct reception, transmitter must delay receive procedure more than following value: 2-byte reception: max. speed frames max. controller (transmit) delay frames
3.3.4
MON-12 Protocol
MON-12 commands feature direct access device internal register Monitor channel. This means that although DFE-T V2.1 features microcontroller interface internal register functions directly addressed MON-12 commands. MON-12 read request command must first acknowledged DFE-T V2.1 before subsequent read request triggered. case failure condition DFE-T V2.1 repeats last outstanding MON-12 answer. MON-12 commands prioritized over other classes. U-interface functions addressed then value register LP_SEL determines register bank channel that referred result desired line port number must programmed first register LP_SEL before U-interface register accessed. this reason MON-12 commands issued simultaneously different IOM®-2 channels, must issued consecutively they address U-interface functions. registers that addressable MON-12 commands please refer register Chapter page 6-4. MON-12 commands following format: MON-12 write command comprises bytes, first byte contains MON-12 header, second byte register address, third byte register value.
Byte 1100 MON-12 Byte AAAA AAAA Register Address Byte DDDD DDDD Register Value
MON-12 read request command comprises bytes, first byte contains MON-12 header, second byte register address data that requested.
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Functional Description
Byte 1100 MON-12 Byte AAAA AAAA Register Address
After read request DFE-T V2.1 reacts with 3-byte message. MON-12 read answer comprises bytes, first byte contains MON-12 header, second byte register address, third byte register value.
Byte 1100 MON-12 Byte AAAA AAAA Register Address Byte DDDD DDDD Register Value
Preliminary Data Sheet
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Functional Description
Interface Analog Front
interface 24902 V2.1 6-wire interface (see Figure 3-8). transmit receive data exchanged well control information start-up procedure means time division multiplexing. transmit data, power-up/down information, range function analog loopback requests transferred. level status information received line ports. PDM0.PDM3 output data from transferred DFE-T V2.1. timing signals based 15.36MHz master clock which provided AFE.
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Interface Analog Front
available bits (related 15.36 clock) SDR/SDX during period divided into time-slots. time-slots bits long reserved data transmission, time-slot bits long used synchronization purposes. DFE-T V2.1 uses four them, time-slots Table shows assignment IOM®-2 channels time-slots SDX/SDR assignment time-slots line ports.
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Functional Description
Table
Assignments Channels Time-Slots SDX/SDR Line Ports Time-Slot Line Port
IOM®-2 Channel 0/4/8/12 1/5/9/13 2/6/10/14 3/7/11/15
status synchronized SDX. Each time-slot carries corresponding during last bits slot.
Figure
Frame Structure SDX/SDR
data interpreted follows: NOP: no-operation-bit none control bits (PDOW, RANGE LOOP) shall changed. values control bits assigned line port latched. states control bits ignored, they should reduce digital cross-talk analog signals. NOPQ least control bits shall changed. this case control bits transmitted with their current values. PDOW: PDOW '1', assigned line port switched power-down. Otherwise switched power-up.
RANGE: RANGE activates range function, otherwise range function deactivated. "Range function activated" refers high input levels.
Preliminary Data Sheet
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Functional Description LOOP: "0": LOOP activates loop function, i.e. loop closed. Otherwise line port normal operation. First time-slots with transmission data. synchronization allocation SDX, SDR. Reserved bit. Reserved bits currently defined shall '0'. Some these bits used test purposes assigned function later versions.
4B3T data coded with bits TD1, TD0:
Table
Coding 4B3T Data Pulse (AOUT/BOUT)
4B3T Data Pulse
data interpreted follows: level detect information communicated DFE-T V2.1 SDR. signal amplitude reaches wake-up level, toggles with signal frequency. input signal U-interface below wake-up level, tied either high. First time-slots with transmission data. synchronization allocation SDX, SDR.
Preliminary Data Sheet
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Functional Description
General Purpose I/Os
DFE-T V2.1 features general purpose pins line port. This transparent control test relays power feeding circuits possible IOM®-2 Monitor channel. Four pins outputs, inputs. Setting Relay Driver Pins Four relay driver output pins (where denotes line port specifies pin) available line port. logic state four relay driver outputs which assigned same line port single MON-8 command, called 'SETD'. value latched long other SETD command with different relay driver settings received. state relay driver pins affected software reset (C/I= RES). state relay driver pins after hardware reset ,,low". Reading Status Pins Each line port owns status pins (where 0,1, denotes line port specifies pin) whose logical value reported associated Monitor channel. signal change status pins ST1.4 causes automatically issue two-byte MON-8 message 'AST' whose least significant bits reflect status STij. However, this automatic mechanism only enabled again, previous status message been transferred acknowledged correctly according Monitor channel handshake protocol. takes DFE-Q V1.2 least IOM®-2 frames (1ms) transmit 2-byte MON-8 message. Thus, repeated changes within periods shorter than IOM®-2 frames will overwrite status register information. this reason only value last recent status change will reported. Note that MON-8 transfer time depends also reaction time (acknowledge MR-bit) DFE-Q counterpart. Besides this automatic report DFE-T V2.1 will issue status Monitor message 'AST' upon MON-8 request 'RST' STij pins have tied either GND, they used.
Preliminary Data Sheet
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Functional Description
U-Transceiver Functions
4B3T U-interface performs full duplex data transmission reception Ureference point according ETSI 220. applies 4B3T block code together with adaptive echo cancelling equalization. Transmission performance shall such that meets ETSI test loops with margin. U-interface designed data transmission twisted pair wires local telephone loops with ISDN basic rate access user rate kbit/s. following information transmitted over twisted pair: Bidirectional: data channels Symbol clock, kbit/s Transmission rate Frame block clock Activation From side: Power feeding Deactivation Remote control test loops From side: Indication monitored code violations U-interface transmission ranges wires diameter wires achieved without additional signal regeneration loop. transmission ranges doubled inserting repeater signal regeneration.
3.6.1
4B3T Frame Structure
frames transmitted across U-interface, each consisting symbols: scrambled coded data symbols: Barker code both symbol frame synchronization (not scrambled) symbol: Ternary maintenance symbol (not scrambled) user data symbols split into four equally structured groups. Each group ternary symbols, resp. bits) contains user data IOM®-2 frames same order 2D). Different syncwords used each direction: Downstream from Upstream from side transmitted Barker code begins symbols after received Barker code vice versa. After successful synchronization, resynchronization will occur syncword detected expected position consecutive frames.
Preliminary Data Sheet 3-17 06.99
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Functional Description U-transceiver synchronized, detects syncword four times consecutively within period
Table D1/2 D7/8 D1/2
Frame Structure Downstream Transmission D1/2 D3/4 D3/4 D3/4 D5/6 D5/6 D5/6 D7/8 D7/8
Ternary data IOM-2 frames Maintenance symbol Syncword
Preliminary Data Sheet
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Functional Description
Table U1/2 U1/2
Frame Structure Upstream Transmission U1/2 U3/4 U3/4 U3/4 U5/6 U5/6 U5/6 U7/8 U7/8 U7/8
Ternary data IOM-2 frames Maintenance symbol Syncword
Preliminary Data Sheet
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Functional Description
3.6.2
Maintenance Channel
4B3T frame structure provides 1kbit/s M(aintenance)-channel transfer remote loopback commands, error indications transparent messages. Loopback Commands station uses M-channel request remote loopbacks. Loopback commands coded with series symbols. continuous series '+0' requests loopback activation repeater continuous series requests loopback activation continuous series requests deactivation loopback station reacts soon pattern been detected consecutive symbols. Error Indications U-transceiver reports line code violations M-channel exchange setting M-Bit polarity. Transparent Messages either direction possible transmit transparent messages M-channel. Transparent messages have priority override loopback commands line code violations. user make sure that during activation able recognize loopback command that there conflict simultaneous transparent channel. polarity represents logic '0', polarity represents logic '1'. interpretation M-Bit symbols depending direction (up-, downstream) summarized below:
Loopback Commands symbol sequence given below shall received least times before loopback command approved valid '+0.'= '++.'= '00.'= '0'= '+'= '-'= loopback activation regenerator) loopback activation loopback deactivation logic loop request logic loop request logic
Transparent Channel Messages
Preliminary Data Sheet
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Functional Description
Transmission Error Detection Report '+'= '0'= '0'= '+'= '-'= code violation detected idle code logic code violation logic detected code violation logic
Transparent Channel Message
Preliminary Data Sheet
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Functional Description
3.6.3
Exchanging Transparent Messages
4B3T U-transceiver provides register pair direct access transparent channel. Access registers provided turn Monitor channel IOM®-2 interface. Therefore MON-0 messages were defined, MON-0 'MRD' MON-0 'MWR'. Register contains last eight received M-bits, register stores M-bit data that serialized sent with next eight outgoing U-frames (see Figure 3-10).
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Figure 3-10 M-Bit Access MRD, Register Pair Transparent channel mode enabled MTRANS OPMODE register using MON-12 protocol. soon OPMODE.MTRANS been Utransceiver starts with next incoming U-frame shift M-bit data into register. Simultaneously starting with value- content register inserted M-bit positions next outgoing U-frame. case register preloaded before, zero plus polarity sent default. same applies register reloaded time again.
Preliminary Data Sheet 3-22 06.99
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Functional Description Once eight M-bits have been stacked (every 8ms) content been shifted out, MON-0 message sent. That every autonomous MON-0 message will issued which contains last eight received M-bit data. periodic transmission MON-0 messages allows align MON-0 write commands transmit direction. Figure 3-11 access timing (MON Monitor channel transmit register, Monitor channel receive register).
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Figure 3-11 M-Bit Access Timing
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Functional Description
3.6.4
Coding from Binary Ternary Data
Each block binary data encoded into ternary symbols using block code according Table 3-6. number next column used, given right hand side each block. left hand signal elements table (both ternary binary) transmitted first.
Table
Coding Table
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Functional Description
3.6.5
Decoding from Ternary Binary Data
Decoding done reverse manner coding. received blocks ternary symbols converted into blocks bits. decoding algorithm given Table 3-7. encoding table left hand symbol each block (both binary ternary) first right hand last. ternary block received, decoded binary This pattern usually occurs only during deactivation. Table 4B3T Decoding Table 7HUQDU\ %ORFN %LQDU\ %ORFN
3.6.6
Monitoring Code Violations
running digital monitor (RDSM) computes running digital from received ternary symbols adding polarity received user data -1). each block, running digital supposed reflect number next column Table "MMS Coding Table" page 3-24.
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Functional Description code violation occurred running digital less than more than four ternary block, ternary block (three user symbols with zero polarity) found received data. ternary block error found, running digital retains current value. counter value greater than beginning next ternary block, value less, one. after code violation been detected, RDSM synchronizes itself within period depending received data pattern. Note there some transmission errors which cause code violation.
3.6.7
Scrambler
Scrambler Descrambler
binary transmit data from IOM®-2 interface scrambled with polynomial bits, before sent 4B3T coder. scrambling algorithm ensures that sequences permanent binary transmitted. scrambler polynomial mode mode with analog loop closed
scrambler polynomial mode with open analog loop Descrambler received data (after decoding from ternary binary) multiplied with polynomial bits order recover original data before forwarded IOM®-2 interface. descrambler itself synchronized after symbols. descrambler polynomial mode with open analog loop
descrambler polynomial mode with analog loop closed
Preliminary Data Sheet
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Functional Description
3.6.8
4B3T Signal Elements
control monitoring purposes activation/deactivation progress following signal elements defined 220. Encoding Scheme table below describes characteristics defined 4B3T signal elements.
Table
Coding 4B3T Signal Elements 'RZQVWUHDP IURP times ternary tone Frequency: Period: 2.13 U2A: Binary continuous before scrambling. frame, ternary instead Barker code Binary continuous before scrambling. Frame (Transmitting Barker code) U4H: Binary continuous before scrambling with duration Frame (Transmitting Barker code) Binary data from digital interface. Frame (Transmitting Barker code) Ternary continuous frame, signal level
8SVWUHDP IURP U1W: times ternary tone Frequency: Period: 2.13 U1A: Binary continuous before scrambling. frame, ternary instead Barker code Binary continuous before scrambling. Frame (Transmitting Barker code) Binary continuous before scrambling. Frame (Transmitting Barker code) Binary data from digital interface. Frame (Transmitting Barker code) Ternary continuous frame, signal level
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Functional Description Detection DFE-T V2.1 detects signal element continuous binary data found descrambler output after subsequent U-frames. Thus these signal elements detected valid after recognized finds subsequent binary data stream. recognized finds complete frame with continuous zero level. significance signal element given Table 3-9.
Significance 4B3T Signal Elements Table lists defined 4B3T signal elements that exchanged across Ureference point course activation deactivation process.
Table
4B3T Signal Elements signal deactivation signal that used both directions. Downstream, requests deactivate. Upstream, acknowledges that deactivated. Awake awake acknowledge signal XSVWUHDP (7.5kHz) used awake procedure U-interface. Awake awake acknowledge signal GRZQVWUHDP (7.5kHz) used awake procedure U-interface. sends enable echo canceller adapt coefficients. Barker code other enabled synchronize. detection used criterion synchronization. M-channel used transfer loop commands. similar without framing information. While synchronizes received signal, sends enable echo canceller adapt coefficients, sends Barker code prevent from synchronizing still asynchronous signal. proceeding synchronization, U-frame jump from time time. detected far-end
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Functional Description Table 4B3T Signal Elements When synchronized, sends Barker code synchronize itself. indicates additionally that terminal equipment activated. Upon receiving indicates synchronized state 'UAI' layer-2. Usually during activation, signal detected because activated first changes before being detected. M-channel used transfer code error indications kbit/s transparent data. indicates that whole link synchronous both directions. detecting requests establish fully transparent connection. M-channel used transfer code error indications kbit/s transparent data. requires 'Transparent' state. detecting stops sending signal informs S-transceiver layer-2 device IOM®-2 interface. M-channel used transfer loop commands kbit/s transparent data. transports operational data channels. M-channel used transfer loop commands kbit/s transparent data. transports operational data channels. M-channel used transfer code error indications kbit/s transparent data. DFE-T V2.1 sends periodically single pulses spaced U-interface. test mode used pulse mask measurements.
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Functional Description
3.6.9
Awake Protocol
awake process signals defined 'U1W' 'U2W'. Depending call direction (up-, downstream) interpreted awake acknowledge signals (see figures below).
Figure 3-12 Awake Procedure initiated
INFO 2.133 INFO 2.133 INFO
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Figure 3-13 Awake Procedure initiated
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Functional Description Acting Calling Station After sending awake signal, awaking device waits acknowledge. After awake signal repeated, acknowledge been recognized. acknowledge signal been recognized, DFE-T V2.1 waits possible repetition case previous coincidence awake signals). repetition detected, DFE-T V2.1 starts transmitting with delay such repetition detected, DFE-T V2.1 interprets awake signal behaves like device awoken far-end. Acknowledging Wake-Up Call DFE-T V2.1 detects awake signal acknowledge signal sent out. Afterwards DFE-T V2.1 waits possible repetition awake signal case acknowledge signal been recognized). repetition found, awoken DFE-T V2.1 starts sending after from detecting awake signal. repeated awake signal found, procedure awoken DFE-T V2.1 starts again.
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Functional Description
3.6.10
Codes
Control/Indicate (C/I) channel used control operational status DFE-T V2.1 issue corresponding indications. Table 3-10 presents defined codes (former code names DFE-T V1.2 given brackets). command indication will recognized valid after been detected successive IOM® frames (double last-look criterion). Indications strictly state orientated. Refer state diagram following section commands indications applicable various states. Table 3-10
Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Command Indicate Codes
LT-Mode DOUT DEAC(DA) (HI) (RSYU) UAI(RDS) AR(ARU) AI(AIU) DI(DIU) (LTD) DT(TEST) AR(ARN) ARL2(AR2) ARL1A(AR4) DC(DID)
ARL2
ARL1A
Activation Indication Activation Request Activation Request Local Loop Activation Request Loop Activation Request Loop
Deactivation Indication. Deactivation Request Reset Resynchronization Indication Send-Single-Pulses
Preliminary Data Sheet
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Functional Description Deactivation Confirmation Data Through Mode Activation Indication
DEAC Deactivation Accepted
Preliminary Data Sheet
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Functional Description
3.6.11
State Machine Notation
following state diagram describes actions/reactions resulting from command detected signal resulting from various operating modes. states with inputs outputs interpreted shown below:
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Figure 3-14 State Diagram Example Each state more transitions other states. These transitions depend certain conditions which noted next transition lines. These conditions only possibility leave state. more conditions have fulfilled together, they into parentheses with operator (&). more than condition leads same transition, they into parentheses with operator (|). meaning condition inverted operator (/). Only described states transitions exist. some transitions, internal timer started. start timer indicated ('x' timer number). Transitions that caused timer expired labelled TxE. Some conditions lead same target state. reduce number lines complexity figures, state named "ANY STATE" acts behalf state. state machine designed cope with ISDN devices with IOM®-2 standard interfaces. Undefined situations excluded. case involved devices will enter defined conditions soon line deactivated.
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Functional Description
3.6.12
Mode State Diagram
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Figure 3-15 State Diagram
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Functional Description
Table 3-11
Differences LT-SM DFE-T V1.2 Change V2.1 split into states Reset State Test State renamed state 'Pending Deactivation' renamed state 'Deactivated' Comment simplifies implementation
V1.2 State/ Signal 'Maintenance' State State 'Deactivating' State 'Deac. Acknowledge'
consistency reasons 2B1Q
State renamed state 'Start Awak. 'Alerting' State renamed state 'Awake Signal 'Wait U1W' Sent' State 'Sending Awake Ack.' State 'Ack. Sent/ Received' State Synch. TE?' State 'Link Synch.' renamed state 'Acknowledge U1W' renamed state 'Awake' renamed state 'Line Active' renamed state 'Pend. Transparent' renamed state 'Transparent' transition condition PFOFF& support type power /ARL doesn't exist controller interface more
State 'Data Transmission' State
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Functional Description Table 3-11 Differences LT-SM DFE-T V1.2 Change V2.1 RSYU TEST ARL2 ARL1A DEAC Comment consistency 2B1Q coding
V1.2 State/ Signal Renamed codes
codes Timer variables introduced
codes 'LTD' 'HI' were function corresponds that omitted more 'RES' available Name Duration 0.5ms 1.0ms 7.0ms 12.0ms
Preliminary Data Sheet
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Functional Description
3.6.12.1 State Machine Inputs
C/I-Commands Activation Request U-transceiver requested enter power-up state start activation procedure sending wake-up signal U2W. Activation Request Local Loop-back U-Transceiver gets reset requested operate analog loopback. activation procedure started. other C/I-channel input, high causes analog loop opened Msymbol zero. Activation Request Loop U-Transceiver requested enter power-up state start activation procedure sending wake-up signal U2W. loop request signalled Maintenance channel continuous plus polarity M-symbol. Activation Request Loop Repeater U-Transceiver requested enter power-up state start activation procedure sending wake-up signal U2W. loop request signalled Maintenance channel series alternating plus zero polarity M-symbol. Deactivation Request U-transceiver requested start deactivation procedure. Deactivation Confirmation informs U-transceiver that upstream unit also deactivated. U-transceiver ready receive awake signals. Upon Utransceiver enters power-down mode. Reset Unconditional command which resets stored settings U-transceiver; line signal will sent out. Send Single Pulses Unconditional command which requests transmission single pulses with period 1ms. Data Through Test Mode Unconditional command which causes U-transceiver transit transparent state issue independent wake-up protocol. farend transceiver needs connected. case far-end transceiver present assumed same condition.
ARL2
ARL1A
Preliminary Data Sheet
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Functional Description Pins Pin-Reset Corresponds code 'RES' besides fact that selection impacts line ports while selection impacts only chosen line. C/I-message DEAC will issued. Pin-Send Single Pulses Corresponds code 'SSP' besides fact that selection impacts line ports while selection impacts only chosen line. C/I-message DEAC will issued.
U-Interface Events detected recognized after complete frame with continuous zero level. detected U-transceiver detects continuous binary data found descrambler output after subsequent U-frames. detected after detected description Awake signal (U1W) detected Awake signal (U2W) been sent Timer ended, started timer expired
Timers
start timers indicated TxS, expiry TxE. following table shows which timers used.
Table 3-12 Timer
Timers Function code recognition Defines duration Supervises repetition Supervises repetition State Deactivated Pend. Transparent Awake Alerting, Wait
Duration (ms)
12.0
Preliminary Data Sheet
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Functional Description
3.6.12.2 State Machine Outputs
Below signals indications summarized that issued IOM®-2 (C/Iindications) U-interface (predefined U-signals). Indications Activation Request code indicates that awake signal been received that start-up procedure progress. U-Activation Indication U-transceiver detected indicating that transmission line between U-interface stations synchronized. this point time block error counter (RDS) enabled. Activation Indication soon been detected U-transceiver issues 'AI' transits 'Transparent' state. 'AI' indicates that whole transmission line synchronized from Deactivation Accepted DEAC issued response DR-code informs upstream unit that U-transceiver deactivating transmission line downstream. Deactivation Indication informs upstream unit that U-transmission line deactivated. receiving 'DC' U-transceiver enters power-down state. transmitter disabled, awake signals detected. Resynchronization Indication informs that U-transceiver synchronous. issued Utransceiver fully activated state lost synchronization afterwards (transmission will interrupted).
DEAC
Signals U-Interface signals U2W, U2A, U4H, transmitted U-interface course activation/ deactivation. They defined detail Table "4B3T Signal Elements" page 3-28. Single Pulses U-transceiver sends periodically single pulses spaced e.g. pulse mask measurements.
Preliminary Data Sheet
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Functional Description
3.6.12.3 State Description
this section each state described with inputs, outputs function. C/I-channel output transmitted signal elements already specified state diagram. Below they only referred within state there more than them specified. this case, C/I-channel output transmitted signal element depend given inputs. Acknowledge receipt awake signal U-transceiver responds with transmission U2W. user data DOUT clamped high. Alerting receipt ARL, ARL2 ARL1A C/I-channel U-transceiver powered sending awake signal U2W. user data DOUT clamped high. Awake awaking U-transceiver received acknowledge signal. being awoken U-transceiver sent acknowledge. both cases U-transceiver waits possible repetition time-out. user data DOUT clamped high prevent that wrong data transmit D-channel during activation. Deactivated Deactivated state signal transmitted U-interface. U-transceiver ready enter power-down state. user data DOUT clamped high. Line Active After recognition U-interface synchronized both directions. That 1.152 subsequent bits have been transferred received without error. Utransceiver transits 'Transparent' state soon signals presence signal case analog loop U-transceiver leaves this state again immediately. subsequent U-frames Barker-code detected expected position, U-transceiver issues C/I-channel until resynchronized. criteria resynchronization that Barker-code been detected same position subsequent frames. block error counter (RDS) coefficient adaptation enabled until deactivation performed.
Preliminary Data Sheet 3-41 06.99
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Functional Description Pending Deactivation U-transceiver deactivates U-interface sending waits turn signal enter 'Deactivated' state. Timer ensures that code DEAC recognized exchange. user data DOUT clamped high. Pending Transparent whole transmission system from synchronized both directions transmission. Signal sent until expiry timer requires establish transparent link synchronization been lost U-transceiver issues C/I-channel until resynchronized again. Power Down receipt 'DC' channel U-transceiver enters power-down state. power-down mode power consuming parts device which required wake-up detection switched off. U-transceiver waits either activation request (AR, ARL, ARL2, ARL1A) from exchange wake-up signal from Reset Reset state entered unconditional command pin-RES. stored coefficients erased. U-transceiver leaves Reset state pin-RES inactive ('1') code applied. U-transceiver does react receipt wake-up signal. user data DOUT clamped high. Synchronizing After successful awake procedure, U-transceiver looks signals synchronize receiver. user data DOUT clamped high. Test Test mode entered unconditional command pin-SSP. Test state left inactive ('0') code applied. Single pulses spaced sent U-line. U-transceiver does react receipt wake-up signal. user data DOUT clamped high.
Preliminary Data Sheet
3-42
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Functional Description Transparent transmission line fully activated. User data exchanged U4/U5. Transparent state also entered case loop-back exchange informed code that transparent state been reached. block error counter (RDS) adaptation receiver coefficients enabled even sent. synchronization been lost U-transceiver issues C/I-channel until resynchronized again. Wait transparent state been reached, U-Transceiver exchange waits ensure that whole link already transparent before indicated code exchange. synchronization been lost U-transceiver issues C/I-channel until resynchronized again. user data DOUT clamped high. Wait U-transceiver awaking U-interface waits acknowledge time-out (12ms) after sending awake signal. user data DOUT clamped high.
Preliminary Data Sheet
3-43
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Functional Description
Clock Generation
15.36MHz master clock generated crystal oscillator connected V2.1. case differs from 8kHz reference clock integrated crystal based phase locked loop (PLL) provided retain system synchronization. AFE-PLL accepts either 8kHz 2048kHz system clock. supplies DFE-T V2.1 with synchronized 15.36MHz clock CL15. Below clock characteristics summarized: Master clock nominal frequency: Max. freq. phase wander within period: Jitter (peak-to-peak): 15.36 0.85 )LJXUH
Max. Difference phase deviations Master clock FSC:
Jitter 15.36 master clock passed U-interface without change. Hence, Figure 3-16 reflects maximum tolerable input jitter given 220.
(15.36 MHz)
jitter frequency (Hz)
60000
Figure 3-16 Maximum Tolerable Input Jitter 15.36MHz Clock
Preliminary Data Sheet
3-44
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Operational Description
Operational Description
scope this section describe DFE-T V2.1 works behaves system environment. Activation/ deactivation control procedures exemplary given programmers reference.
Reset
There different ways apply reset, either hardware reset setting software reset applying 'C/I= RES' Hardware Reset hardware reset affects design components takes effect immediately (asynchronous reset style). clock signal other than master clock shall required reset execution. Software Reset software reset triggered 'C/I= RES' only effect addressed line port. remaining line ports, system interface, relay driver/ status pins global functions affected. clock signal must provided code processing. 'RES' resets receiver activation/deactivation state machine. Transmission stopped. unconditional command therefore applicable state.
Power Down
Each building block DFE-T V2.1 optimized with respect power consumption support power down mode. chapter 7.6.2 page specified max. power consumption. DFE-T V2.1 goes power down mode U-transceiver state 'Power Down' There events that awake DFE-T V2.1 again from power down mode, when wake tone (U1W) been detected when codes ARL, ARL2 ARL1A applied Regarding DFE-T V2.1 power down mode means that clock turned other digital circuits (excluding IOM®-2 interface) power down mode
Preliminary Data Sheet 06.99
24901
Operational Description timing signals delivered (CLS0, CLS3) Regarding connected power down mode means that signal sent U-interface only functions that necessary detect wake conditions kept active transmit path, receive path auxiliary functions analog line port switched power consuming mode when power down function activated. This implies following: ADC, relevant output tied GND. output buffer; outputs AOUTx/ BOUTx tied GND. internal voltage reference switched off. range loop functions deactivated.
Preliminary Data Sheet
06.99
24901
Operational Description
Layer Activation/ Deactivation Procedures
This chapter illustrates interactions during activation deactivation between station. activation initiated either stations involved. deactivation procedure initiated only exchange. status transmission line classified seven activation/deactivation states (also referred number activation/ deactivation procedures following sides): Activation States: Line awake Each individual line being awoken, synchronized, data transmission possible Synchronization downstream Synchronization always done downstream first, whole line synchronize exchange Synchronization upstream Because delay differs from line line, synchronization necessary Synchronized layer-1 units link told exchange that synchronization been finished Transparent State: activated state, user data transmitted from exchange vice versa. Deactivation States: Deactivation done steps each individual line separately. Deactivation request downstream Deactivation acknowledge upstream transmission link totally deactivated thereafter. exchange control information partially state oriented U-interface. Some signal elements given long other information transferred, other signal elements have distinct durations.
Preliminary Data Sheet
06.99
24901
Operational Description
4.3.1
Complete Activation Initiated Exchange
8yyr VUhprvr 8yyr
actbyLT_4b3t.emf
Figure
Activation Initiated Exchange
06.99
Preliminary Data Sheet
24901
Operational Description
4.3.2
Complete Activation Initiated
8yyr VUhprvr 8yyr
actbyNT_4b3t.emf
Figure
Activation Initiated
06.99
Preliminary Data Sheet
24901
Operational Description
4.3.3
Complete Activation Initiated Exchange with Repeater
TUhprvr
VUhprvr
VUhprvr
VUhprvr
8yyr
actwithLTRP_4b3t.emf
Figure
Activation with Repeater Initiated
06.99
Preliminary Data Sheet
24901
Operational Description
4.3.4
Complete Activation Initiated Terminal with Repeater
TUhprvr
VUhprvr
VUhprvr
VUhprvr
8yyr
actwithNTRP_4b3t.emf
Figure
Activation with Repeater Initiated
06.99
Preliminary Data Sheet
24901
Operational Description
4.3.5
Deactivation
9@68
9@68
8yyr
VUhprvr
VUhprvr
VUhprvr
8yyr
deac_4b3t.emf
Figure
Deactivation (Always Initiated Exchange)
06.99
Preliminary Data Sheet
24901
Operational Description
4.3.6
Activation Loop#1
8yyr
VUhprvr
8yyr
act_loop1_4b3t.emf
Figure
Activation Loop#1
06.99
Preliminary Data Sheet
24901
Operational Description
4.3.7
Activation Loop#1A
evtl.
TUhprvr
VUhprvr
VUhprvr
VUhprvr
8yyr
Srrhr
act_loop1a_4b3t.emf
Figure
Activation Loop#1A (Repeater)
4-10 06.99
Preliminary Data Sheet
24901
Operational Description
4.3.8
Activation Loop#2
6SG!
8yyr
VUhprvr
8yyr
act_loop2_4b3t.emf
Figure
Activation Loop#2
4-11 06.99
Preliminary Data Sheet
24901
Operational Description
Maintenance Test Functions
This chapter summarizes features provided U-transceiver support maintenance functions system measurements. They classified into three main groups: maintenance functions close open test loopbacks features facilitating recognition transmission errors test modes required system measurements next four sections describe these maintenance functions used applications.
4.4.1
Test Loopbacks
Four different loopbacks defined maintenance purposes order facilitate location defect systems. position each loopback illustrated Figure Remote control exchange featured. When test loop closed channels looped back data from other line ignored. There separate loops single channels.
S-BUS Loop S-Transceiver
IOM®-2
Loop U-Transceiver
IOM®-2
Loop U-Transceiver U-Transceiver Loop U-Transceiver
IOM®-2
Loop Layer-1 Controller U-Transceiver
IOM®-2
Repeater (optional)
Exchange
IOM®-2
Loop Layer-1 Controller U-Transceiver
loop.emf
Figure
Test Loopbacks
test loops transparent loops. line signal still transmitted although analog loop closed. Nevertheless receives this signal synchronizes distinguish between line signals sent from during loop loop
Preliminary Data Sheet 4-12 06.99
24901
Operational Description signals sent during normal operation. Loopback no.1 closed DFE-T V2.1 itself, whereas loopback no.2 remote controlled code 'ARL1A' 'ARL2' closed Loopback no.3 supported since DFE-T V2.1 operates only mode.
4.4.1.1
Analog Loopback (No.1)
analog loop no.1 closed DFE-T V2.1 close U-interface possible. signal from line driver back directly input. like short-circuit between pins AOUT well between BOUT BIN. input signal from hybrid ignored this mode. analog loop mode controlled IOM®2 C/I-channel code 'ARL'. request LT-repeater close analog loop no.1A, code 'ARL1A' must applied DFE-T V2.1. will send turn alternating plus zero polarity within subsequent frames M-channel
4.4.1.2
Loopback No.2
Loopback controlled exchange. transparent which means that bits that looped back also passed S-bus. DFE-T V2.1 features remote control loop no.2 channel. code 'ARL2' requests close loop, 'AR' 'DR' requests open loop again.
Repeater S-Bus Loop Loop
NTC-T U-Transceiver Loop
ITS09867
Figure 4-10 Loopback No.2
Preliminary Data Sheet
4-13
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Operational Description DFE-T V2.1 translates received codes into following pattern sequence M-channel U-interface: continuous polarity closes loopback no.2 after consecutive pulses with plus polarity been received M-channel continuous polarity closes loopback no.2 after consecutive zeros been received Mchannel deactivation request. During normal transmission without loops, M-symbol zero minus. loopback comprises both B-channels D-channel. closed close S-transceiver possible. U-transceiver passes request S-transceiver issuing C/I-code "Transparent" state C/I-code other states.
4.4.1.3
Available Loopbacks Register
Besides remote loopback stimulation local analog loopback (C/I= ARL) DFE-T V2.1 features digital local loopbacks internal register set. loopbacks that additionally available with internal LOOP register shown Figure 4-11. They activated regardless current activation status using MON-12 protocol have direct effect. LOOP register configured whether digital looback closed only and/or ISDN-BA channels whether loopback closed towards IOM®-2 interface towards U-Interface. default loopbacks transparent mode. transparent mode data both passed looped back. non-transparent mode data forwarded substituted (idle code). Besides loopbacks system interface further digital loopback, Framer/ Deframer loopback featured. allows test digital functions 4B3T Utransceiver besides signal processing blocks.
Preliminary Data Sheet
4-14
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Operational Description
/223/% /223/% /223/%%' /2238,20
/223/% /223/% /223/%%' /2238,20
')(7
/D\HU &RQWUROOHU
8hpryyr Uvvt Srpr @hyvr #7"U 9rpqr Tphiyr Ahvt TpXq #7"U Tphiyr Ahvt
)LOWHU
8yyr Drshpr
/223'/%
')(7
/D\HU &RQWUROOHU
8hpryyr Uvvt Srpr @hyvr #7"U 9rpqr Tphiyr Ahvt TpXq #7"U Tphiyr Ahvt
)LOWHU
8yyr Drshpr
loopreg.vsd
Figure 4-11 Loopbacks Featured Register LOOP
Preliminary Data Sheet 4-15 06.99
24901
Operational Description
4.4.2
Block Error Counter
DFE-T V2.1 provides block error counter channel. This feature allows comfortable surveillance transmission quality U-interface. block error given U-frame with least code violation been detected (near-end block error) positive M-symbol been received from (farend block error). transmits positive M-symbol upstream code error been detected within frame (position upstream U-frame from LT). current status block error counter retrieved MON-8 command 'RDS'. Upon reception 'RDS' counter value issued with corresponding MON8 message. block error counter read automatically reset. counter also automatically reset course deactivation procedure. enabled again count code violations from moment code 'UAI' written into C/I-channel indicating that U-line sychronized state 'Line Active'). counter does overflow stops maximum value (255). Note that each counted frame with detected code violation causes about binary errors average. error rate 10-7 both directions results detected frame errors within 1000 frame error detected transmitted M-symbol).
4.4.3
Error Rate Counter
error rate monitoring DFE-T V2.1 features 16-bit Error Rate counter (BERC) line. measurement performed channel. Prerequisite that loop addressed line port been closed before side M-channel. measurement initiated control bits TEST register. soon function enabled zeros sent selected channels incoming ones counted until function been disabled again user.
Preliminary Data Sheet
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Operational Description
4.4.4
System Measurements
DFE-T V2.1 features dedicated test modes enable ease system measurements. these test modes used conduct most frequently needed system measurements described following sections.
4.4.4.1
Send Single Pulses Test Mode (SSP)
send-single-pulses test mode, U-transceiver transmits U-interface pulses spaced options exist selecting "Send-Single-Pulses" (SSP) mode:
hardware selection: software selection: Pin-SSP= code= (0101B)
Both methods fully equivalent besides fact that selection impacts line ports while selection impacts only chosen line. SSP-test mode required pulse mask measurements.
4.4.4.2
Data Through Mode (DT)
selected data-through mode forces DFE-T V2.1 directly into "Transparent" state. This possible from state state diagram. Data-Through option (DT) provides possibility transmit standard scrambled U-signal even U-interface wake-up protocol possible. This feature interest counter station connected supply wake-up protocol signals. with SSP-mode, options available.
hardware selection: software selection: Pin-DT= code= (0110B)
Note that hardware selection offers option initiate further actions C/I-code (e.g. simultaneous stimulation analog loop-back 'ARL'). DT-mode required power spectral density total power measurements.
4.4.4.3
Master Reset Mode
master-reset mode characterizes mode where U-transceiver does transmit signals. chip "Reset" state. echo canceller equalizer coefficients reset. seen from state diagram, activation possible device "Reset" state. measurements methods recommended order transfer U-transceiver into master-reset mode:
hardware selection: software selection: Pin-RES= C/I-code= (0001B)
Preliminary Data Sheet
4-17
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Operational Description Both alternatives fully compatible besides fact that selection channel selective. master-reset test mode used return-loss measurements.
4.4.4.4
Pulse Mask Measurement
Pulse mask defined Guideline ETSI U-interface terminated with U-transceiver "Send-Single-Pulses" mode (C/I 'SSP' Pin-SSP '1') Measurements done using oscilloscope
4.4.4.5
Power Spectral-Density Measurement
defined Guideline ETSI U-interface terminated with U-transceiver "Data-Through" mode (C/I 'DT' Pin-DT= '1') measurements spectrum analyzer employed
4.4.4.6
Return-Loss Measurement
Return loss defined Guideline ETSI U-transceiver "Reset" state (C/I 'RES' Pin-RES= '0') Measure complex impedance from Calculate return loss with formula: RL(dB) 20log (abs((Z 150) -150)))
4.4.4.7
Quiet Mode Measurement
Quite mode defined Guideline ETSI U-transceiver "Reset" state (C/I 'RES' Pin-RES= '0') Trigger exit criteria have realized externally
4.4.4.8
Insertion Loss Measurement
Insertion loss defined Guideline ETSI U-transceiver "Data-Through" mode (C/I 'DT' Pin-DT= '1') Trigger exit criteria have realized externally
Preliminary Data Sheet
4-18
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Operational Description
4.4.5
Retrieving Data
Beyond test maintenance features described previous sections, DFET V2.1 permits access specific data. Access provided MON-12 protocol. data transfer between external device synchronized handshake signals, 'DATA_REQ' 'DATA_ACK'. following text technical term 'read' stands process sending read request Monitor channel using MON-12 protocol. Data Exchange Handshake Signals handshake signal DATA_REQ accommodated position register DSP_DREQ, handshake signal DATA_ACK position register DSP_DACK.
')(7 &RUH
+DQGVKDNH &RQWURO
,QWHUIDFH &RQWUROOHU '287
'63B'$&.
'63B'5(4
dsp_acs1.vsd
Figure 4-12 Data Transfer Synchronization Handshake Signals Significance DATA_REQ DATA_REQ external device able control data exchange adapt data rate needs. During read access layer-1 controller indicates with active DSP_REQ signal (='1') that requests data. DATA_REQ signals that layer-1 controller busy.
Preliminary Data Sheet
4-19
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Operational Description Significance DATA_ACK Signal DATA_ACK controlled DSP. During read access informs external controller DATA_ACK that data Read Registers (DSP_RD1.3) been updated. active DATA_ACK '1') signals that busy. Below single steps handshake protocol course read access given. Read direction (DSP Layer-1 controller): Layer-1 controller polls DATA_ACK Layer-1 controller signals readiness read access DATA_REQ= signals with DATA_ACK= that DSP_RD1.3 registers have been loaded Layer-1 controller reads Read Registers, DSP_RD1.3 subsequent read accesses this procedure repeated
Preliminary Data Sheet
4-20
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Operational Description
4.4.5.1
Reading Coefficient Values
means DSP_RD1.3 registers possible read coefficient values. coefficient subsets various filter banks addressable 3-bit DAT_TYP field register DSP_CR2. Below accessible coefficient clusters listed: '100' '110' '001' '011' Coefficient Coefficient Coefficient Coefficient
Figure 4-13 shows register structure that provided access coefficient values.
')(7 &RUH
+DQG VKDNH
'63B'5(4 '63B'$&.
'63B5'
'63B&5
'63B&5
'63B5' '63B5'
&RQWUROOHU
dsp_acs2_ds.emf
Figure 4-13 Provided Registers Access Coefficient Data
Preliminary Data Sheet
4-21
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Operational Description read coefficient data following programming sequence must carried Select addressed line port CH_SEL register DSP_CR1 register DSP_CR1. Thereby coefficients freezed. Program Control Register No.2, DSP_CR2 follows: Select proper coefficient type DATA_TYP (e.g. coefficient set= '100') same coefficient repeatedly read DSP_TYP must another value then reset again desired coefficient type. This required reset internal counters. COM_MOD enable handshake mechanism Trigger read procedure setting DATA_RW '01' register DSP_CR2. Read DSP_RD1.3 registers using either handshake procedure described chapter before.
Preliminary Data Sheet
4-22
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Operational Description
4.4.6
Boundary Scan
DFE-T V2.1 provides boundary scan support cost effective board testing. consists Complete boundary scan signals (pins) according IEEE 1149.1 specification Test Access Port controller (TAP) Five dedicated pins (TCK, TMS, TDI, TDO, TRST) Pins TRST, provided with internal pullup resistor 32-bit IDCODE register TRST tied resets Boundary Scan Controller Instructions CLAMP HIGHZ were added, instruction removed V2.1
Boundary Scan pins except power supply pins, "Not Connected" pins pins TDI, TDO, TCK, TMS, TRST included boundary scan chain. Depending functionality one, three boundary scan cells provided. Table Boundary Scan Cells. Number Boundary Scan Cells Usage input output, enable input, output, enable
Type Input Output
When controller appropriate mode data shifted into boundary scan pins TDI/TDO using 6.25 clock TCK. pins included following sequence boundary scan chain:
Boundary Scan Number
Number
Name
Type
Number Scan Cells
CLS3 SLOT0
V2.1 provided with BScan cell (N.C.)
Preliminary Data Sheet
4-23
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Operational Description Boundary Scan Number
Preliminary Data Sheet
Number
Name
Type
Number Scan Cells
06.99
CLS2 SLOT1 CLS0 ST00 ST01 ST10 ST11 ST20 ST21 CLS1 ST30 ST31
4-24
24901
Operational Description Boundary Scan Number Number Name Type Number Scan Cells
DOUT PDM0 PDM1 PDM2 PDM3 CL15
Controller Test Access Port (TAP) controller implements state machine defined JTAG standard IEEE 1149.1. Transitions cause controller perform state change. Before operation controller reset TRST. According IEEE 1149 standard instructions executable. instructions 'CLAMP' 'HIGHZ' were added. Instruction 'SSP' more supported since function identical that pin.
Table Code 0000 0001 0010 0011 0100
Controller Instructions: Instruction EXTEST INTEST SAMPLE/PRELOAD IDCODE CLAMP Function External testing Internal testing Snap-shot testing Reading code Reading outputs
Preliminary Data Sheet
4-25
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Operational Description Code 0101 11XX Instruction HIGHZ BYPASS Function Z-State boundary scan output pins Bypass operation
EXTEST used examine board interconnections. When controller state "update DR", output pins updated with falling edge TCK. When entered state "capture levels input pins latched with rising edge TCK. in/out shifting scan vectors typically done using instruction SAMPLE/PRELOAD. INTEST supports internal chip testing. When controller state "update DR", inputs updated internally with falling edge TCK. When entered state "capture levels outputs latched with rising edge TCK. in/out shifting scan vectors typically done using instruction SAMPLE/PRELOAD. 0001 (INTEST) default value instruction register. SAMPLE/PRELOAD provides snap-shot level during normal operation used preload (TDI) shift (TDO) boundary scan with test vector. Both activities transparent system functionality. IDCODE Register 32-bit identification register serially read TDO. contains version number bits), device code bits) manufacturer code bits). fixed "1". Version 0001 Device Code 0000 0000 0110 0111 Manufacturer Code 0000 1000 Output
Note: state "test logic reset" code "0011" loaded into instruction code register.
CLAMP allows state signals included boundary scan driven from 24901 determined from boundary scan register while bypass register selected serial path between TDO. These output signals driven from DFE-T V2.1 will change while CLAMP selected.
Preliminary Data Sheet 4-26 06.99
24901
Operational Description
HIGHZ sets output pins included boundary scan path into high impedance state. this state, in-circuit test system drive signals onto connections normally driven DFE-T V2.1 outputs without incurring risk damage DFE-T V2.1. BYPASS, entering shifted after clock cycle, e.g. skip testing selected printed circuit board.
Preliminary Data Sheet
4-27
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Monitor Commands
Monitor Commands
This chapter summarizes Monitor commands messages that available 4B3T U-Transceiver application. Please refer section "IOM®-2 Monitor Channel" page detailed description Monitor handshake procedure. Besides existing MON-8 commands classes, MON-0 MON-12 introduced. MON-0 commands/messages provide access 1kbit/s transparent channel 4B3T frame. MON-12 commands allow address functions that available with 4B3T register map. Defined MON-8 Commands Chip identification, echocanceller coefficients block error counter readout with two-byte MON-8 commands given Table 5-1. Each command executed after having been transferred proper handshake procedure. MON-8 commands have highest priority.
Table
Code (Hex)
MON-8 Commands
Read Identification requests U-Transceiver issue code Read Reset Block Error Counter Function
')(7 Specific MON-8 Functions
DCBA)
SETD
Relay Driver Pins DiA, DiB, DiC, port status output pins this MON-8 command, Binary: 1000 0001 0111 DCBA Read Request Status Pins this MON-8 command information current status general purpose input pins retrieved, port status pins provided
indications summarized Table 5-2. messages "Answer Identification", "Answer Block Error Counter Read Request" "Answer 'RST' Request" two-byte messages.
Preliminary Data Sheet
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24901
Monitor Commands
Table
Code (Hex)
MON-8 Indications
ARDS Answer Identification DFE-T V2.1 replies code. Answer Block Error Counter Read Request monitor byte contains 8-bit counter value 'XX' Function
ARDS
')(7 Specific MON-8 Functions
00S1S0)
Answer 'RST' Request also issued without request change either STi0, STi1 pin, Binary: 1000 1000 0000 00S1S0
Preliminary Data Sheet
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Monitor Commands Defined MON-0 Commands Following systematics 2B1Q MON-0 commands messages used exchange transparent messages 4B3T Maintenance-channel. With MON-0 command 'MWR' 8-bit message transferred DFE-T V2.1. DFE-T V2.1 then inserts data 1kbit/s transparent channel. station stores received bits until 8-bit word complete sends autonomous MON-0 message 'MRD' which carries received information. usage transparent channel must enabled first 'MTRANS' register OPMODE. This done single MON-12 write command. MON-0 commands have highest priority (1st MON-12). more details access synchronization issues please refer chapter "IOM®-2 Monitor Channel" page 3-5.
Table
Code (Hex)
MON-0 Commands
Send Transparent Message data 'XX' sent Transparent channel (M-Bit) across U-interface Function
Table
Code (Hex)
MON-0 Indications
Receive Transparent Message data 'XX' that received across U-interface Transparent channel (M-Bit) output Function
Preliminary Data Sheet
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Register Description
Register Description
this section complete register described that provided with MON12 protocol. protocol details please refer page 3-11. register address arrangement given Figure 6-1. U-interface registers provided line port. register LP_SEL determined which register bank that which line port number addressed. LP_SEL adds offset value current address. offset value latched long register LP_SEL overwritten again. access registers 8-bit wide address must '1'.
/3B6(/ 5HVHUYHG
%(5&
Pssr
/3B6(/
5HJLVWHUV 5HJLVWHUV 5HJLVWHU %DQNV
2302'( 8B&6
'63B&6
regmap_cust.emf
Figure
DFE-T V2.1 Register
Preliminary Data Sheet
06.99
24901
Register Description
Register Summary
WR/RD WR/RD*
LP_SEL
U-Interface Registers
OPMODE TEST LOOP BERC
TRANS
WR/RD*
M-Bit data last received U-frames M-Bit data next transmit U-frames
TRANS U/IOM
LBBD
WR/RD* WR/RD*
Block Error Counter Value BERC Counter Value (Bit 15-8) BERC Counter Value (Bit 7-0)
Registers
DSP_CR1 DSP_CR2 DSP_DREQ DSP_DACK DSP_RD1 DSP_RD2 DSP_RD3 DATA_TYP WR/RD* WR/RD* Coefficient Data CH_SEL
DATA_RW DATA _REQ DATA _ACK
Coefficient Data Coefficient Data Reserved
read-back function test
Preliminary Data Sheet
06.99
24901
Register Description
Table
Register Reference Table Address Reset Value Comment Page
Name Access
U-Interface Registers LP_SEL Line Port Selection Reg. line port selected default Opmode Register mode, channel controlled IOM®-2 M-Bit Read Register value meaningful after activation M-Bit Write Register appropriate value must loaded TEST Register test modes disabled
OPMODE
TEST LOOP
LOOP Register transparent loop mode set, local loops deactivated Running Digital Counter Counter Value 6-10 6-11
BERC
0000H
Registers DSP_CR1 DSP_CR2 DSP_ DREQ DSP_ DACK DSP_RD 91H-93H
Control Register functions enabled Control Register normal operation mode Data Request Register
6-12 6-12 6-14
Data Acknowl. Register 6-15 Read Registers 6-16
06.99
Preliminary Data Sheet
24901
Register Description
6.2.1
Detailed Register Description LP_SEL Line Port Selection Register
Line Port Selection register selects register bank that associated with addressed line port. line port specific register operations line port specific registers indicated last column register summary performed line port that addressed value LP_SEL. LP_SEL Reset value: read/write Address:
LN2,1
Line Port Number Line port addressed following command Line port addressed following command Line port addressed following command Line port addressed following command
Preliminary Data Sheet
06.99
24901
Register Description
U-Interface Registers
6.2.2
OPMODE Operation Mode Register
Operation Mode register determines operating mode DFE-T V2.1. OPMODE Reset value:
TRANS
read*)/write
Address:
MODE1
MODE0
MTRANS Enable/Disable Transparent Channel (see "Exchanging Transparent Messages" page 3-22) Transparent Channel disabled M-channel transports only loop (LT-> code violation information (NT-> LT), data exchanged Transparent Channel enabled transparent messages exchanged across 1kbit/s Mchannel using MON-0 commands messages
MODE
Operation Mode Setting mode
Preliminary Data Sheet
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24901
Register Description
6.2.3
M-Bit Read
M-Bit Read register contains data last received eight M-bits. Data shifted into register soon transmission line transparent. combination with register possible exchange transparent messages across Uinterface. value output IOM®-2 MON-0 message each time 8-bit word been stacked register. autonomous MON-0 message used synchronize MON-0 'MWR' command transmission opposite direction. Reset value: read Address:
data last received U-frames
Received transparent channel messages interpreted follows '0'= '+'= '-'= mapped logic loop requested mapped logic loop requested simultaneously mapped logic
Preliminary Data Sheet
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24901
Register Description
6.2.4
M-Bit Write Register
M-Bit Write register allows transmit transparent messages across U-interface. data that written register sent next subsequent U-frames. After U-frames zeros sent register reloaded again time. MON-0 command 'MWR' provided which allows overwrite register value. periodic MON-0 'MRD' messages synchronize transmission MON-0 'MWR' commands. Note that transparent messages have priority override loopback commands. Reset value: write Address:
data next transmit U-frames
data mapped following symbol values mapped symbol loopback requested mapped symbol loopback requested same time mapped symbol
Preliminary Data Sheet
06.99
24901
Register Description
6.2.5
TEST Test Register
Test register sets U-transceiver desired test mode. Note that test modes 'Data Through' 'Send Single Pulses' activated channel strapping. TEST Reset value: read*)/write Address:
Error Rate Measurement Function allows measure B1-, D-channel Transparent state, prerequisite: closed loopback side continuous series zeros sent Error Rate (BERC) counter disabled Reserved Reserved Error Rate counter (BERC) enabled, starts measurement B1-, D-channel, zeros sent channel
Preliminary Data Sheet
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24901
Register Description
6.2.6
LOOP Loopback Register
Loop register controls local digital loopbacks DFE-T V2.1. analog loopback (No. remote loopbacks closed codes. loopback configurations that available LOOP register also Chapter 4.4.1 page 4-12. LOOP Reset value: TRAN IOM® LBBD read*)/write Address:
Close Framer/Deframer loopback Framer/Deframer loopback open Framer/Deframer loopback closed
TRANS
Transparent/ Non-Transparent Loopback transparent mode data both passed looped back whereas non-transparent mode data forwarded substituted '1's (idle code) just looped back
Note: effect analog loopback since 'ARL' operates always transparent mode
transparent mode non-transparent mode '1's sent IOM®-2 interface corresponding time-slot
U/IOM®
Switch that selects whether looback LB1, LBBD closed towards IOM®-2 LB1, LB2, LBBD loops closed towards IOM® LB1, LB2, LBBD loops closed towards
LBBD
Close complete loop (B1, near system interface direction towards loop closed determined 'U/IOM®'
Preliminary Data Sheet
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Register Description complete loopback open complete loopback closed
Close loop near system interface direction towards loop closed determined 'U/IOM®' loopback open loopback closed
Close loop near system interface direction towards loop closed determined 'U/IOM®' loopback open loopback closed
6.2.7
Block Error Counter Register
Block Error Counter register 'RDS' monitors counts code violations nearend far-end side. counter stops does overflow. register read line deactivated block error counter automatically reset '0'. register value requested either MON-8 command 'RDS' directly addressed using MON-12 protocol. Reset value: read Address:
Block Error Counter Value
Preliminary Data Sheet
6-10
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Register Description
6.2.8
BERC Error Rate Counter Register
Error Rate Counter register contains number errors that occurred during period TEST.BER active. register read automatically reset BERC Reset value: 0000H read Address: 08/09H
Error Rate Counter Value
Error Rate Counter Value
Preliminary Data Sheet
6-11
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Register Description
6.2.9
Registers
DSP_CR Control Registers Control register operational function core controlled. With Control register data type access direction determined data exchange between external controller. DSP_CR1 Reset value: CH_SEL read*)/write Address:
CH_SEL
Channel Selection selects addressed line port subsequent data transfers assigned selected line port selects line port selects line port selects line port selects line port
Disable adjust freeze coefficients line port selective command: takes only effect selected line port CH_SEL inactive disables coefficient update
Preliminary Data Sheet
6-12
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Register Description DSP_CR2 Reset value: DATA_TYP read*)/write Address:
DATA_RW
DATA_
Data Access Type '100' '110' '001' '011' coefficients coefficients coefficients coefficients
DATA_
Read Data disabled read data reserved
Preliminary Data Sheet
6-13
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Register Description DSP_DREQ Data Request Register Data Request register contains handshake signal 'DATA_REQ' communication between external microcontroller. DATA_REQ controlled external controller signals when layer-1 controller requests data. DSP_DREQ Reset value: DATA _REQ write Address:
DATA_
Data Request External controller busy inactive indicates that layer-1 controller read data requests data
Preliminary Data Sheet
6-14
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Register Description DSP_DACK Data Acknowledge Register Data Acknowledge register contains handshake signal 'DATA_ACK' communication between external microcontroller. DATA_ACK controlled signals whether busy ready data access. DSP_DACK Reset value: DATA _ACK read Address:
DATA_
Data Acknowledge DATA register value been updated busy
Preliminary Data Sheet
6-15
06.99
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Register Description DSP_RD Read Registers Read Data registers contain data that have been requested external controller. data type determined setting DSP_CR2 register. DSP_RD1 Reset value: read Address:
Coefficient Data DSP_RD2 Reset value: read Address:
Coefficient Data DSP_RD3 Reset value: read Address:
Reserved
Coefficient Data
Preliminary Data Sheet
6-16
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Electrical Characteristics
Parameter
Electrical Characteristics
Absolute Maximum Ratings
Symbol Limit Values (max. Unit
Ambient temperature under bias Storage temperature supply voltage
Input/Output voltage with respect ground
Tstg
Maximum current lines connected Imax backplane when DFE-T V2.1 without power supply; 3.3V external signal level robustness1) HBM:
VESD,HBM
2000
According MIL-Std 883D, method 3015.7 Ass. Standard EOS/ESD-5.1-1993.
Note: Stresses above those listed here cause permanent damage device. Exposure absolute maximum rating conditions extended periods affect device reliability.
Parameter
Operating Range
Symbol Limit Values min. max. Unit Test Condition
Ambient temperature Supply voltage Ground
Note: operating range, functions given circuit description fulfilled.
Parameter
Characteristics
Symbol Limit Values min. max.
Unit Notes
Input voltage Input high voltage
Preliminary Data Sheet
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Electrical Characteristics Parameter Output voltage Output high voltage Avg. power supply current Symbol Limit Values min. max. 0.45 Unit Notes
(AV)
4.096 Clock 15.36
Input leakage current
other
pins floating;
Output leakage current
VOUT
Apply DOUT Apply pins that appear list note
listed characteristics ensured over operating range integrated circuit. Typical characteristics specify mean values expected over production spread. otherwise specified, typical characteristics apply given supply voltage.
Preliminary Data Sheet
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Electrical Characteristics
Characteristics
Inputs driven logical 0.45 logical '0'. Timing measurements made logical logical '0'. testing input/output waveforms shown Figure 7-1.
Test Points
Device Under Test
AC_char.vsd
Figure
Input/Output Waveform Tests
7.4.1
Reset Timing
Symbol Limit Values min. max.
executed 400µs after active phase 15.36MHz clock applied master reset
Parameter Active Period
Unit
Remark
tRES
tRES
Figure
Reset Timing
Preliminary Data Sheet
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Electrical Characteristics 7.4.2 IOM®-2 Interface Timing
dynamic characteristics IOM®-2-interface given Figure 7-3. case period signals stated time reference will other cases (low) (high) thresholds used reference.
Figure Table
Parameter
IOM®-2 Interface Timing (Double Clock Mode) IOM®-2 Dynamic Input Characteristics
Symbol min. Limit Values typ. max. Unit
rise/fall time period pulse width, high rise/fall setup time hold time advance
twFH
xTDCL xTDCL
TDCL
Preliminary Data Sheet
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Electrical Characteristics
Parameter Symbol min. Limit Values typ. max. Unit
pulse width, high Superframe pulse width, high setup time hold time
twFH twFL twFH twFL
TDCL TDCL
<twH
Table
Parameter
IOM®-2 Dynamic Output Characteristics
Symbol min. Limit Values typ. max. Unit Test Condition
Data delay clock Data delay frame
tdDC tdDF
<100 <150
Notes:1) point time which output data will valid referred rising edges either (tdDF (tdDC rising edge signal appearing last (normally DCL) shall reference.
Preliminary Data Sheet
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Electrical Characteristics
7.4.3
Interface Analog Front
CL15
Figure
Dynamic Input Output Requirements Analog Interface Dynamic Input Characteristics Signal CL15 CL15 PDM0.3 PDM0.3 Symbol Limit Values min. typ. max. Unit
Table Parameter Clock period Pulse width high/ Data setup Data hold
Table Parameter
Dynamic Output Characteristics Signal Symbol Limit Values min. typ. max. Unit
data delay
Preliminary Data Sheet
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Electrical Characteristics
7.4.4
Boundary Scan Timing
Figure
Boundary Scan Timing Boundary Scan Dynamic Timing Requirements Symbol min. tTCP tTCPL tTCPH tMSS tMSH tDIS tDIH tDOD Limit Values max. Unit
Table Parameter
test clock period test clock period test clock period high set-up time hold time from set-up time hold time from valid delay from
Preliminary Data Sheet
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Electrical Characteristics
Parameter
Capacitances
Symbol Limit Values min. max. Unit Notes
Clock input capacitance
CXIN
pins, which under test, connected
Input capacitance Output capacitance
COUT
7.6.1
Power Supply Supply Voltage
+3.3V ±0.3V
7.6.2
Power Consumption
measurements with random 2B+D data active states, 3.3V (0°C 70°C) Table
Mode Power-up Channels Power-down
Power Consumption
Typ. values Max. values Unit Test conditions open outputs, inputs /VSS open outputs, inputs /VSS
Preliminary Data Sheet
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Package Outlines
Package Outlines
P-MQFP-64 (Plastic Metric Quad Flat Package)
Sorts Packing Package outlines tubes, trays etc. contained Data Book "Package Information". Surface Mounted Device Preliminary Data Sheet
Dimensions 06.99
GPM05247
24901
Appendix Standards Specifications
Appendix Standards Specifications
table below lists relevant standards concerning transmission performance DFE-T V2.1 claims comply with.
2UJDQL]DWLRQ ETSI European Telecommunications Standards Institute
9DOLG
'RFXPHQW V1.3.1 (1998-11), formerly called ETR080 Transmission Multiplexing (TM); Integrated Services Digital Network (ISDN) basic rate access; Digital transmission system metallic local lines Spezifikation ISDNSchnittstelle Schicht ISDN Aktivierung/ Deaktivierung Basisanschlusses Schicht Euro-ISDN Aktivierung/ Deaktivierung Basisanschlusses Schicht
Fernmeledetechnisches Zentralamt
08/91 11/87 04/90
Preliminary Data Sheet
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Glossary
Glossary
Analog digital Analog digital converter Automatic gain control Differential U-interface input American National Standardization Institute Differential U-interface output 64-kbit/s voice data transmission channel Differential U-interface input Differential U-interface output Command/Indicate (channel) 16-kbit/s data control trans
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