Preliminary DDR400 Data Sheet Addendum Jan. 2003, V0.9 Latency Cl
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HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum Jan. 2003, V0.9
Latency Clock Frequency
Latency Maximum Operating Frequency (MHz) DDR400B DDR400A
Double data rate architecture: data transfers clock cycle Bidirectional data strobe (DQS) transmitted received with data, used capturing data receiver edge-aligned with data reads center-aligned with data writes Differential clock inputs Four internal banks concurrent operation
Data mask (DM) write data aligns transitions with transitions Commands entered each positive edge; data data mask referenced both edges Burst Lengths: Latency: (1.5), 2.5, Auto Precharge option each burst access Auto Refresh Self Refresh Modes 7.8ms Maximum Average Periodic Refresh Interval refresh) 2.5V (SSTL_2 compatible) VDDQ 2.6V 0.1V 2.6V 0.1V TSOP66 package
Description
256Mb SDRAM high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. internally configured quad-bank DRAM. 256Mb SDRAM uses double-data-rate architecture achieve high-speed operation. double data rate architecture essentially prefetch architecture with interface designed transfer data words clock cycle pins. single read write access 256Mb SDRAM effectively consists single 2n-bit wide, clock cycle data transfer internal DRAM core corresponding n-bit wide, onehalf-clock-cycle data transfers pins. bidirectional data strobe (DQS) transmitted externally, along with data, data capture receiver. strobe transmitted SDRAM during Reads memory controller during Writes. edge-aligned with data Reads center-aligned with data Writes. 256Mb SDRAM operates from differential clock crossing going HIGH going referred positive edge CK). Commands (address control signals) registered every positive edge Input data registered both edges DQS, output data referenced both edges DQS, well both edges Read write accesses SDRAM burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration Active command, which then followed Read Write command. address bits registered coincident with Active command used select bank accessed. address bits registered coinci2003-01-10, V0.9
dent with Read Write command used select bank starting column location burst access. SDRAM provides programmable Read Write burst lengths locations. Auto Precharge function enabled provide self-timed precharge that initiated burst access. with standard SDRAMs, pipelined, multibank architecture SDRAMs allows concurrent operation, thereby providing high effective bandwidth hiding precharge activation time. auto refresh mode provided along with power-saving power-down mode. inputs compatible with JEDEC Standard SSTL_2. outputs SSTL_2, Class compatible. Note: functionality described timing specifications included this data sheet Enabled mode operation.
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HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Ordering Information
Part Numbera Org. CAS-RCD-RP Clock CAS-RCD-RP Clock CAS-RCD-RP Clock Speed Latencies (MHz) Latencies (MHz) Latencies (MHz) 3-3-3 2.5-3-3 2-3-3 Package
HYB25D256800BT(L)-5A HYB25D256160BT(L)-5A HYB25D256800BT(L)-5 HYB25D256160BT(L)-5
DDR400A TSOP-II
DDR400B
HYB: designator memory components 25D: DDR-I SDRAMs Vddq=2.5V 256: 256Mb density 400/800/160: Product variations revision C/T: Package type FBGA TSOP power version (optional) these components specifically selected IDD6 Self Refresh currents speed grade table
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2003-01-10, V0.9
HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Configuration (TSOP66)
VDDQ VSSQ VDDQ VSSQ VDDQ A10/AP
VDDQ VSSQ VDDQ VSSQ VDDQ A10/AP
VDDQ VSSQ VDDQ VSSQ VDDQ LDQS A10/AP
16Mb 32Mb 64Mb
DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 VDDQ VSSQ UDQS VREF
VSSQ VDDQ VSSQ VDDQ VSSQ VREF
VSSQ VDDQ VSSQ VDDQ VSSQ VREF
2003-01-10, V0.9
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HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Input/Output Functional Description
Symbol Type Input Function Clock: differential clock inputs. address control input signals sampled crossing positive edge negative edge Output (read) data referenced crossings (both directions crossing). Clock Enable: HIGH activates, deactivates, internal clock signals device input buffers output drivers. Taking provides Precharge Power-Down Self Refresh operation (all banks idle), Active Power-Down (row Active bank). synchronous power down entry exit, self refresh entry. asynchronous self refresh exit. must maintained high throughout read write accesses. Input buffers, excluding disabled during power-down. Input buffers, excluding CKE, disabled during self refresh. Chip Select: commands masked when registered HIGH. provides external bank selection systems with multiple banks. considered part command code. standard pinout includes pin. Command Inputs: RAS, (along with define command being entered. Input Data Mask: input mask signal write data. Input data masked when sampled HIGH coincident with that input data during Write access. sampled both edges DQS. Although pins input only, loading matches loading. Bank Address Inputs: define which bank Active, Read, Write Precharge command being applied. also determines mode register extended mode register accessed during EMRS cycle. Address Inputs: Provide address Active commands, column address Auto Precharge Read/Write commands, select location memory array respective bank. sampled during Precharge command determine whether Precharge applies bank (A10 LOW) banks (A10 HIGH). only bank precharged, bank selected BA0, BA1. address inputs also provide op-code during Mode Register command. Data Input/Output: Data bus. Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered write data. Used capture write data. Connect: internal electrical connection present. Supply Supply Supply Supply Supply Power Supply: 2.6V 0.1V. Ground Power Supply: 2.6V 0.1V. Ground SSTL_2 reference voltage: (VDDQ
Input
RAS, CAS,
Input Input
Input
BA0,
Input
Input
VDDQ VSSQ VREF
Input/Output Input/Output
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2003-01-10, V0.9
HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Block Diagram (32Mb
Control Logic
Command Decode
Bank1 Row-Address Bank0 Row-Address Latch Decoder
Bank2
Bank3
Mode Registers
8192
Read Latch
Refresh Counter
Generator
Sense Amplifiers Bank Control Logic
8192
Drivers
Bank0 Memory Array (8192 512x
Data
Address Register
COL0 Gating Mask Logic
(x16)
Column Decoder Column-Address Counter/Latch COL0
Data COL0
Note: This Functional Block Diagram intended facilitate user understanding operation device; does represent actual circuit implementation. Note: unidirectional signal (input only), internally loaded match load bidirectional signals.
2003-01-10, V0.9
Receivers
A0-A12, BA0,
Write FIFO Drivers
Input Register Mask
DQ0-DQ7,
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HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Block Diagram (16Mb
Command Decode
Control Logic
Bank1 Row-Address Bank0 Row-Address Latch Decoder
Bank2
Bank3
Mode Registers
8192
Read Latch
Refresh Counter
Generator
Sense Amplifiers Bank Control Logic
8192
Drivers
Bank0 Memory Array (8192 256x
Data
Address Register
COL0 Gating Mask Logic
(x32)
Column Decoder Column-Address Counter/Latch COL0
Data COL0
Note: This Functional Block Diagram intended facilitate user understanding operation device; does represent actual circuit implementation. Note: unidirectional signals (input only), internally loaded match load bidirectional UDQS LDQS signals.
Receivers
A0-A11, BA0,
Write FIFO Drivers
Input Register Mask
DQ0-DQ15, LDQS, UDQS
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2003-01-10, V0.9
HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Functional Description
256Mb SDRAM high-speed CMOS, dynamic random-access memory containing 268, 435, bits. 256Mb SDRAM internally configured quad-bank DRAM. 256Mb SDRAM uses double-data-rate architecture achieve high-speed operation. doubledata-rate architecture essentially prefetch architecture, with interface designed transfer data words clock cycle pins. single read write access 256Mb SDRAM consists single 2n-bit wide, clock cycle data transfer internal DRAM core corresponding n-bit wide, one-half clock cycle data transfers pins. Read write accesses SDRAM burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration Active command, which then followed Read Write command. address bits registered coincident with Active command used select bank accessed (BA0, select bank; A0-A12 select row). address bits registered coincident with Read Write command used select starting column location burst access. Prior normal operation, SDRAM must initialized. following sections provide detailed information covering device initialization, register definition, command descriptions device operation. Initialization SDRAMs must powered initialized predefined manner. Operational procedures other than those specified result undefined operation. following criteria must met: power sequencing specified during power power down given following criteria: VDDQ driven from single power converter output meets specification VREF tracks VDDQ/2 following relationship must followed: VDDQ driven after with such that VDDQ driven after with VDDQ such that VDDQ 0.3V VREF driven after with VDDQ such that VREF VDDQ 0.3V outputs High-Z state, where they remain until driven normal operation read access). After power supply reference voltages stable, clock stable, SDRAM requires 200ms delay prior applying executable command. Once 200ms delay been satisfied, Deselect command should applied, should brought HIGH. Following command, Precharge command should applied. Next Mode Register command should issued Extended Mode Register, enable DLL, then Mode Register command should issued Mode Register, reset DLL, program operating parameters. clock cycles required between reset executable command. During cycles clock locking, Deselect command must applied. After clock cycles, Precharge command should applied, placing device "all banks idle" state. Once idle state, AUTO REFRESH cycles must performed. Additionally, Mode Register command Mode Register, with reset deactivated (i.e. program operating parameters without resetting DLL) must performed. Following these cycles, SDRAM ready normal operation.
2003-01-10, V0.9
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HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Register Definition
Mode Register Mode Register used define specific mode operation SDRAM. This definition includes selection burst length, burst type, latency, operating mode. Mode Register programmed Mode Register command (with retains stored information until programmed again device loses power (except which self-clearing). Mode Register bits A0-A2 specify burst length, specifies type burst (sequential interleaved), A4-A6 specify latency, A7-A12 specify operating mode. Mode Register must loaded when banks idle, controller must wait specified time before initiating subsequent operation. Violating either these requirements results unspecified operation. Burst Length Read write accesses SDRAM burst oriented, with burst length being programmable. burst length determines maximum number column locations that accessed given Read Write command. Burst lengths locations available both sequential interleaved burst types. Reserved states should used, unknown operation incompatibility with future versions result. When Read Write command issued, block columns equal burst length effectively selected. accesses that burst take place within this block, meaning that burst wraps within block boundary reached. block uniquely selected A1-Ai when burst length two, A2-Ai when burst length four A3-Ai when burst length eight (where most significant column address given configuration). remaining (least significant) address bit(s) (are) used select starting location within block. programmed burst length applies both Read Write bursts.
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HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Mode Register Operation
Address Mode Register
Operating Mode
Latency
Burst Length
Valid Valid
Operating Mode Normal operation reset Normal operation Reset Reserved Reserved Burst Type Sequential Interleave
Latency
Latency Reserved Reserved (optional) Reserved (optional) Reserved
Burst Length
Burst Length Reserved Reserved Reserved Reserved Reserved
must select Mode Register (vs. Extended Mode Register).
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HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Burst Definition
Starting Column Address Burst Length Type Sequential 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Type Interleaved 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Order Accesses Within Burst
Notes: burst length two, A1-Ai selects two-data-element block; selects first access within block. burst length four, A2-Ai selects four-data-element block; A0-A1 selects first access within block. burst length eight, A3-Ai selects eight-data- element block; A0-A2 selects first access within block. Whenever boundary block reached within given sequence above, following access wraps within block. Burst Type Accesses within given burst programmed either sequential interleaved; this referred burst type selected ordering accesses within burst determined burst length, burst type starting column address, shown Burst Definition page Read Latency Read latency, latency, delay, clock cycles, between registration Read command availability first burst output data. latency programmed clocks. latency optional feature this device. Read command registered clock edge latency clocks, data available nominally coincident with clock edge Reserved states should used unknown operation incompatibility with future versions result.
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HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Operating Mode normal operating mode selected issuing Mode Register Command with bits A7-A12 zero, bits A0-A6 desired values. reset initiated issuing Mode Register command with bits A9-A12 each zero, one, bits A0-A6 desired values. Mode Register command issued reset should always followed Mode Register command select normal operating mode. other combinations values A7-A12 reserved future and/or test modes. Test modes reserved states should used unknown operation incompatibility with future versions result. Required Latencies
Latency
Command Read CL=2
Latency 2.5,
Command Read CL=2.5
Shown with nominal tAC, tDQSCK, tDQSQ.
Don't Care
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HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Extended Mode Register
Extended Mode Register controls functions beyond those controlled Mode Register; these additional functions include enable/disable, output drive strength selection (optional). These functions controlled bits shown Extended Mode Register Definition. Extended Mode Register programmed Mode Register command (with retains stored information until programmed again device loses power. Extended Mode Register must loaded when banks idle, controller must wait specified time before initiating subsequent operation. Violating either these requirements result unspecified operation. Enable/Disable must enabled normal operation. enable required during power initialization, upon returning normal operation after having disabled purpose debug evaluation. automatically disabled when entering self refresh operation automatically re-enabled upon exit self refresh operation. time enabled, clock cycles must occur before Read command issued. This reason clock cycles must occur before issuing Read Write command upon exit self refresh operation. Output Drive Strength normal drive strength outputs specified SSTL_2, Class addition this design version supports weak driver mode lighter load and/or point-to-point environments which activated during mode register set. curves normal weak drive strength included this document.
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2003-01-10, V0.9
HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Extended Mode Register Definition
Address Extended Mode Register
Operating Mode
Drive Strength
Valid Operating Mode Normal Operation other states Reserved Normal Weak Drive Strength
must must select Extended Mode Register (vs. base Mode Register) Enable Disable
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HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Commands
CommandsDeselect Deselect function prevents commands from being executed SDRAM. SDRAM effectively deselected. Operations already progress affected. Operation (NOP) Operation (NOP) command used perform SDRAM. This prevents unwanted commands from being registered during idle wait states. Operations already progress affected. Mode Register mode registers loaded inputs A0-A12, BA1. mode register descriptions Register Definition section. Mode Register command only issued when banks idle bursts progress. subsequent executable command cannot issued until tMRD met. Active Active command used open activate) particular bank subsequent access. value BA0, inputs selects bank, address provided inputs A0-A12 selects row. This remains active open) accesses until Precharge Read Write with Auto Precharge) issued that bank. Precharge Read Write with Auto Precharge) command must issued completed before opening different same bank. Read Read command used initiate burst read access active (open) row. value BA0, inputs selects bank, address provided inputs A0-Ai, (where don't care] x16, don't care] selects starting column location. value input determines whether Auto Precharge used. Auto Precharge selected, being accessed precharged Read burst; Auto Precharge selected, remains open subsequent accesses. Write Write command used initiate burst write access active (open) row. value BA0, inputs selects bank, address provided inputs A0-Ai, (where don't care] where selects starting column location. value input determines whether Auto Precharge used. Auto Precharge selected, being accessed precharged Write burst; Auto Precharge selected, remains open subsequent accesses. Input data appearing written memory array subject input logic level appearing coincident with data. given signal registered low, corresponding data written memory; signal registered high, corresponding data inputs ignored, Write executed that byte/column location. Precharge Precharge command used deactivate (close) open particular bank open row(s) banks. bank(s) will available subsequent access specified time (tRP) after Precharge command issued. Input determines whether banks precharged, case where only bank precharged, inputs BA0, select bank. Otherwise BA0, treated "Don't Care." Once bank been precharged, idle state must activated prior
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2003-01-10, V0.9
HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Read Write commands being issued that bank. precharge command treated there open that bank, previously open already process precharging. Auto Precharge Auto Precharge feature which performs same individual-bank precharge functions described above, without requiring explicit command. This accomplished using enable Auto Precharge conjunction with specific Read Write command. precharge bank/row that addressed with Read Write command automatically performed upon completion Read Write burst. Auto Precharge nonpersistent that either enabled disabled each individual Read Write command. Auto Precharge ensures that precharge initiated earliest valid stage within burst. user must issue another command same bank until precharge (tRP) completed. This determined explicit Precharge command issued earliest possible time, described each burst type Operation section this data sheet. Burst Terminate Burst Terminate command used truncate read bursts (with Auto Precharge disabled). most recently registered Read command prior Burst Terminate command truncated, shown Operation section this data sheet. Auto Refresh Auto Refresh used during normal operation SDRAM analogous Before (CBR) Refresh previous DRAM types. This command nonpersistent, must issued each time refresh required. refresh addressing generated internal refresh controller. This makes address bits "Don't Care" during Auto Refresh command. 256Mb SDRAM requires Auto Refresh cycles average periodic interval (maximum). allow improved efficiency scheduling switching between tasks, some flexibility absolute refresh interval provided. maximum eight Auto Refresh commands posted system, meaning that maximum absolute interval between Auto Refresh command next Auto Refresh command (70.2ms). This maximum absolute interval short enough allow updates internal SDRAM restricted Auto Refresh cycles, without allowing much drift between updates. Self Refresh Self Refresh command used retain data SDRAM, even rest system powered down. When self refresh mode, SDRAM retains data without external clocking. Self Refresh command initiated Auto Refresh command coincident with transitioning low. automatically disabled upon entering Self Refresh, automatically enabled upon exiting Self Refresh (200 clock cycles must then occur before Read command issued). Input signals except (low) "Don't Care" during Self Refresh operation. procedure exiting self refresh requires sequence commands. (and must stable prior returning high. Once high, SDRAM must have commands issued tXSNR because time required completion internal refresh progress. simple algorithm meeting both refresh requirements apply NOPs clock cycles before applying other command.
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HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Truth Table Commands
Name (Function) Deselect (Nop) Operation (Nop) Active (Select Bank Activate Row) Read (Select Bank Column, Start Read Burst) Write (Select Bank Column, Start Write Burst) Burst Terminate Precharge (Deactivate Bank Banks) Auto Refresh Self Refresh (Enter Self Refresh Mode) Mode Register Address Bank/Row Bank/Col Bank/Col Code Op-Code Read Write Notes
HIGH commands shown except Self Refresh. BA0, select either Base Extended Mode Register (BA0 selects Mode Register; selects Extended Mode Register; other combinations BA0-BA1 reserved; A0-A12 provide op-code written selected Mode Register.) BA0-BA1 provide bank address A0-A12 provide address. BA0, provide bank address; A0-Ai provide column address (where 8for x16, x4); HIGH enables Auto Precharge feature (nonpersistent), disables Auto Precharge feature. LOW: BA0, determine which bank precharged. HIGH: banks precharged BA0, "Don't Care." This command AUTO REFRESH HIGH; Self Refresh LOW. Internal refresh counter controls bank addressing; inputs I/Os "Don't Care" except CKE. Applies only read bursts with Auto Precharge disabled; this command undefined (and should used) read bursts with Auto Precharge enabled write bursts Deselect functionally interchangeable.
Truth Table Operation
Name (Function) Write Enable Write Inhibit Used mask write data; provided coincident with corresponding data. Valid Notes
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2003-01-10, V0.9
HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Truth Table Clock Enable (CKE)
CKEn logic state clock edge state previous clock edge. Current state state SDRAM immediately prior clock edge COMMAND command registered clock edge ACTION result COMMAND states sequences shown illegal reserved.
Current State Previous Cycle CKEn Current Cycle Command Action Notes
Self Refresh Self Refresh Power Down Power Down Banks Idle Banks Idle Bank(s) Active
Deselect Deselect Deselect AUTO REFRESH Deselect "Truth Table Current State Bank Command Bank (Same Bank)" page
Maintain Self-Refresh Exit Self-Refresh Maintain Power-Down Exit Power-Down Precharge Power-Down Entry Self Refresh Entry Active Power-Down Entry
Deselect commands should issued clock edges occurring during Self Refresh Exit (tXSNR) period. minimum clock cycles needed before applying read command allow lock input clock.
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HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Truth Table Current State Bank Command Bank (Same Bank)
Current State Idle Active Read (Auto Precharge Disabled) Command Deselect Operation Active AUTO REFRESH MODE REGISTER Read Write Precharge Read Precharge BURST TERMINATE Read Write Precharge Select column start Read burst Select column start Write burst Deactivate bank(s) Select column start Read burst Truncate Read burst, start Precharge BURST TERMINATE Select column start Read burst Select column start Write burst Truncate Write burst, start Precharge Action NOP. Continue previous operation NOP. Continue previous operation Select activate Notes 1-6, 1-6, 1-6, 1-6, 1-6, 1-6, 1-6, 1-6, 1-6,
Write (Auto Precharge Disabled)
This table applies when HIGH HIGH (see Truth Table Clock Enable (CKE) after tXSNR tXSRD been previous state self refresh). This table bank-specific, except where noted, i.e., current state specific bank commands shown those allowed issued that bank when that state. Exceptions covered notes below. Current state definitions: Idle: bank been precharged, been met. Active: bank been activated, tRCD been met. data bursts/accesses register accesses progress. Read: Read burst been initiated, with Auto Precharge disabled, terminated been terminated. Write: Write burst been initiated, with Auto Precharge disabled, terminated been terminated. following states must interrupted command issued same bank. Precharging: Starts with registration Precharge command ends when met. Once met, bank idle state. Activating: Starts with registration Active command ends when tRCD met. Once tRCD met, bank "row active" state. Read w/Auto Precharge Enabled: Starts with registration Read command with Auto Precharge enabled ends when been met. Once met, bank idle state. Write w/Auto Precharge Enabled: Starts with registration Write command with Auto Precharge enabled ends when been met. Once met, bank idle state. Deselect commands, allowable commands other bank should issued clock edge occurring during these states. Allowable commands other bank determined current state according Truth Table following states must interrupted executable command; Deselect commands must applied each positive clock edge during these states. Refreshing: Starts with registration Auto Refresh command ends when tRFC met. Once tRFC met, SDRAM "all banks idle" state. Accessing Mode Register: Starts with registration Mode Register command ends when tMRD been met. Once tMRD met, SDRAM "all banks idle" state. Precharging All: Starts with registration Precharge command ends when met. Once met, banks idle state. states sequences shown illegal reserved. bank-specific; requires that banks idle. bank-specific; all/any banks precharged, all/any must valid state precharging. bank-specific; BURST TERMINATE affects most recent Read burst, regardless bank. Reads Writes listed Command/Action column include Reads Writes with Auto Precharge enabled Reads Writes with Auto Precharge disabled. Requires appropriate masking. 2003-01-10, V0.9
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HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Truth Table Current State Bank Command Bank (Different bank)
Current State Idle Activating, Active, Precharging Read (Auto Precharge Disabled) Write (Auto Precharge Disabled) Read (With Auto Precharge) Write (With Auto Precharge) Command Deselect Operation Command Otherwise Allowed Bank Active Read Write Precharge Active Read Precharge Active Read Write Precharge Active Read Write Precharge Active Read Write Precharge Select activate Select column start Read burst Select column start Write burst Select activate Select column start Read burst Select column start Write burst Select activate Select column start Read burst Select column start Write burst Select activate Select column start Read burst Select activate Select column start Read burst Select column start Write burst Action NOP/continue previous operation NOP/continue previous operation Notes 1-7,10 1-7,9,10 1-7,10 1-7,10
This table applies when HIGH HIGH (see Truth Table Clock Enable (CKE) after tXSNR tXSRD been previous state self refresh). This table describes alternate bank operation, except where noted, i.e., current state bank commands shown those allowed issued bank (assuming that bank such state that given command allowable). Exceptions covered notes below. Current state definitions: Idle: bank been precharged, been met. Active: bank been activated, tRCD been met. data bursts/accesses register accesses progress. Read: Read burst been initiated, with Auto Precharge disabled, terminated been terminated. Write: Write burst been initiated, with Auto Precharge disabled, terminated been terminated. Read with Auto Precharge Enabled: note Write with Auto Precharge Enabled: note AUTO REFRESH Mode Register commands only issued when banks idle. BURST TERMINATE command cannot issued another bank; applies bank represented current state only. states sequences shown illegal reserved. Reads Writes listed Command/Action column include Reads Writes with Auto Precharge enabled Reads Writes with Auto Precharge disabled. Requires appropriate masking. Write command applied after completion data output. Concurrent Auto Precharge: This device supports "Concurrent Auto Precharge". When read with auto precharge write with auto precharge enabled command follow other banks long that command does interrupt read write data transfer other limitations apply (e.g. contention between READ data WRITE data must avoided). mimimum delay from read write command with auto precharge enable, command different banks summarized table
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HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Truth Table Concurrent Auto Precharge
From Command
Command (different bank) Read Read w/AP
Minimum Delay with Concurrent Auto Precharge Support (BL/2) tWTR BL/2 BL/2 (rounded up)+ BL/2
Units
WRITE w/AP
Write Write w/AP Precharge Activate Read Read w/AP
Read w/AP
Write Write w/AP Precharge Activate
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2003-01-10, V0.9
HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Simplified State Diagram
Power Applied Power
Precharge PREALL
Self Refresh REFS REFSX
EMRS
Idle
REFA
Auto Refresh
CKEL CKEH
Active Power Down CKEH CKEL
Precharge Power Down
Write Write Write
Active
Burst Stop Read
Read Read Read
Write Read Write
Read
Read
Precharge PREALL Automatic Sequence Command Sequence
PREALL Precharge Banks Mode Register EMRS Extended Mode Register REFS Enter Self Refresh REFSX Exit Self Refresh REFA Auto Refresh
CKEL Enter Power Down CKEH Exit Power Down Active Write Write with Autoprecharge Read Read with Autoprecharge Precharge
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HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Operating Conditions Absolute Maximum Ratings
Symbol VIN, VOUT VDDQ TSTG IOUT Parameter Voltage pins relative Voltage Inputs relative Voltage supply relative Voltage VDDQ supply relative Operating Temperature (Ambient) Storage Temperature (Plastic) Power Dissipation Short Circuit Output Current Rating Units
-0.5 VDDQ+ -0.5 +3.6 -0.5 +3.6 -0.5 +3.6
+150
Note: Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
Input Output Capacitances
Parameter Input Capacitance: Delta Input Capacitance Input Capacitance: other input-only pins Delta Input Capacitance: other input-only pins Input/Output Capacitance: DQS, Delta Input/Output Capacitance DQS, Package TSOP TSOP TSOP TSOP TSOP TSOP Symbol CdI1 CdI2 CdIO Min. Max. 0.25 Units Notes
These values guaranteed design tested sample base only. VDDQ 2.6V 0.1V, 100MHz, 25°C, VOUT (DC) VDDQ/2, VOUT (Peak Peak) 0.2V. Unused pins tied ground inputs grouped with pins reflecting fact that they matched loading facilitate trace matching board level
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2003-01-10, V0.9
HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Electrical Characteristics Operating Conditions
(0°C 70°C; VDDQ 2.6V 0.1V, 2.6V 0.1V
Symbol VDDQ Supply Voltage Supply Voltage Parameter 2.50 2.50 VDDQ /2-50mV VREF 0.04 VREF 0.15 2.70 2.70 VDDQ /2+50mV VREF 0.04 VDDQ VREF 0.15 VDDQ VDDQ Units Notes
VSS, VSSQ Supply Voltage, Supply Voltage VREF VIH(DC) VIL(DC) VIN(DC) VID(DC) VIRatio Reference Voltage Termination Voltage (System) Input High (Logic1) Voltage Input (Logic0) Voltage Input Voltage Level, Inputs Input Differential Voltage, Inputs VI-Matching Pullup Current Pulldown Current Input Leakage Current. input (All other pins under test Output Leakage Current (DQs disabled; Vout VDDQ Output High Current, Normal Strength Driver (VOUT 1.95 Output Current, Normal Strength Driver (VOUT 0.35
0.36 0.71
16.2
16.2
This voltage supplied DRAM inclusive noise 10MHz. DRAM does generate noise that exceeds ±150mV above 10MHz does meet full functionality with ±150mV above 10MHz DRAM that generated DRAM itself. noise above 10MHz DRAM generated from other source than DRAM itself exceed voltage range 2.6V ±100mV. tolerances data sheet additive. Inputs recognized valid until VREF stabilizes. VREF expected equal VDDQ transmitting device, track variations level
same. Peak-to-peak noise VREF exceed value. applied directly device. system supply signal termination resistors, expected equal VREF, must track variations level VREF. magnitude difference between input level input level ration pullup current pulldown current specified same temperature voltage, over entire temperature voltage range, device drain source voltage from 0.25 1.0V. given output, represents maximum difference between pullup pulldown drivers process variation.
2003-01-10, V0.9
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HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Specification Conditions
VDDQ 2.5V 0.2V; 2.5V 0.2V)
Param eter/C ondition typ. OperatingC urrent: onebank; active/ precharge; x4/x8 andD Sinputs changingonceper clock cycle; address andcontrol inputs changingonceevery clock cycles OperatingC urrent: onebank; active/read/precharge; burst length4; Refer tothefollow pagefor detailedtest conditions. x4/x8 266A typ. typ. 400A/B typ. otes Unit
typ.
PrechargePow er-Dow StandbyC urrent: banks idle; er-dow ode; CKE<= VILM
PrechargeFloatingStandbyC urrent: VIHM banks idle; CKE>= VIHM address andother control inputs changingonceper clock cycle, SandDM PrechargeQ StandbyC uiet urrent: >=VIHM banks idle; CKE>= VIHM address andother control inputs stable >=VIHM VILM VIN=VREFfor andD
ActivePow StandbyC er-D urrent: onebank active; er-dow ode; CKE<= VILM VIN=VR SandD
ActiveStandbyC urrent: onebank active; >=VIHM x4/x8 CKE>= VIHM tRC=tRASM andD inputs changingtw clock cycle; address andcontrol inputs changing onceper clock cycle OperatingC urrent: onebank active; BL2; reads; continuous burst; x4/x8 address andcontrol inputs changingonceper clock cycle; 50%of dataoutputs changingonevery clock edge; 200and 266(A), CL3for andD 400; OperatingC urrent: onebank active; Burst rites; continuous x4/x8 burst; address andcontrol inputs changingonceper clock cycle; 50%of dataoutputs changingonevery clock edge; CL2for 200andDD 266(A), CL3for andD R400
urrent: tRC=tRFCM distributedrefresh Auto-RefreshC
standardversion efreshC urrent: <=0.2V; external clock Self-R
1.25
1.30
lowpow version 1.20 1.25 1.20 1.25 1.20 1.25 1.20 1.25 OperatingC urrent: four bank; four bank interleavingw burst length4; Refer tothefollow pagefor detailedtest conditions. x4/x8
specifications aretestedafter thedeviceis properly initializedandm easured 100M 133M 266(A) and166M R333 200, Input slewrate=1V/ns. Enables on-chiprefreshandaddress counters Test conditionfor typical values 2.5V,Ta=25°C test conditionfor umvalues: test 2.7V,Ta=10°C axim
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2003-01-10, V0.9
HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Detailed test conditions SDRAM IDD1 IDD7
IDD1 Operating current bank operation
Only bank accessed with tRC(min) Burst Mode, Address Control inputs edge changing once clock cycle. lout Timing patterns DDR200 (100Mhz, CL=2) CL=2, BL=4, tRCD tCK, tRAS Setup: Read repeat same timing with random address changing data changing every burst DDR266A (133Mhz, CL=2) CL=2, BL=4, tRCD tCK, tCK, tRAS Setup: Read repeat same timing with random address changing data changing every burst DDR333 (166Mhz, CL=2.5) CL=2.5, BL=4, tRCD tCK, tCK, tRAS Setup: Read repeat same timing with random address changing data changing every burst 3.Legend A=Activate, R=Read, W=Write, P=Precharge, N=NOP
IDD7 Operating current: Four bank operation
Four banks being interleaved with tRC(min) Burst Mode, Address Control inputs edge changing. lout Timing patterns DDR200 (100Mhz, CL=2) CL=2, BL=4, tRRD tCK, tRCD= tCK, Read with autoprecharge Setup: Read repeat same timing with random address changing data changing every burst DDR266A (133Mhz, CL=2) CL=2, BL=4, tRRD tCK, tRCD Setup: Read repeat same timing with random address changing data changing every burst DDR333 (166Mhz, CL=2.5) CL=2.5, BL=4, tRRD tCK, tRCD Setup: Read repeat same timing with random address changing data changing every burst 3.Legend A=Activate, R=Read, W=Write, P=Precharge, N=NOP
2003-01-10, V0.9
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HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Characteristics
(Notes apply following Tables: Electrical Characteristics Operating Conditions, Operating Conditions, Specifications Conditions, Electrical Characteristics Timing.) voltages referenced VSS. Tests timing, IDD, electrical, characteristics, conducted nominal reference/supply voltage levels, related specifications device operation guaranteed full voltage range specified. figure below represents timing reference load used defining relevant timing parameters part. intended either precise representation typical system environment depiction actual load presented production tester. System designers will IBIS other simulation tools correlate timing reference load system environment. Manufacturers will correlate their production test conditions (generally coaxial transmission line terminated tester electronics). timing tests swing 1.5V test environment, input timing still referenced VREF crossing point CK), parameter specifications guaranteed specified input levels under normal conditions. minimum slew rate input signals 1V/ns range between VIL(AC) VIH(AC). input level specifications defined SSTL_2 Standard (i.e. receiver effectively switches result signal crossing input level, remains that state long signal does ring back above (below) input (HIGH) level) System Characteristics like Setup Holdtime Derating Slew Rate, Delta Rise/Fall Derating,DDR SDRAM Slew Rate Standards, Overshoot Undershoot specification Clamp characteristics latest JEDEC specification components
Output Load Circuit Diagram Timing Reference Load Output (VOUT) Timing Reference Point
30pF
Operating Conditions
VDDQ 2.6V 0.1V; 2.6V 0.1V)
Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) Parameter/Condition Input High (Logic Voltage, DQS, Signals Input (Logic Voltage, DQS, Signals Input Differential Voltage, Inputs Input Closing Point Voltage, Inputs VREF 0.31 VREF 0.31 VDDQ Unit Notes
0.5*VDDQ 0.5*VDDQ
Input slew rate 1V/ns. Inputs recognized valid until VREF stabilizes. magnitude difference between input level input level value expected equal 0.5*VDDQ transmitting device must track variations level same.
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2003-01-10, V0.9
HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Electrical Characteristics Timing Absolute Specifications
VDDQ 2.6V 0.1V; 2.6V 0.1V) (Part
DDR400A Min. output access time from CK/CK -0.5 -0.55 0.45 0.45 Max. +0.5 +0.55 0.55 0.55 DDR400B Min. -0.5 -0.55 0.45 0.45 Max. +0.5 +0.55 0.55 0.55 +0.65 -0.65 0.72 +0.65 1.28 +0.4 +0.5 tHP-tQHS 0.35 0.60 0.40 0.25 0.60 70,000 0.40 0.60 70,000 0.60
Symbol
Parameter
Unit
Notes
1-4,10 1-4, 1-4, 1-4, 1-4, 1-4,
tDQSCK output access time from CK/CK tIPW tDIPW tDQSS tDQSQ tQHS input hold time input setup time Control Addr. input pulse width (each input) input pulse width (each input) Data-out high-impedence time from CK/CK Data-out low-impedence time from CK/CK Write command latching transition DQS-DQ skew (DQS associated signals) Data hold skew factor output hold time from Clock cycle time high-level width low-level width Clock Half Period
(tCL, tCH) 0.40 0.40 1.75 +0.65 -0.65 0.72 +0.65 1.28 +0.4 +0.5 tHP-tQHS 0.35 0.40 0.25 fast slew rate fast slew rate 0.40
(tCL, tCH) 0.40 0.40 1.75
tDQSL,H input (high) pulse width (write cycle) tDSS tDSH tMRD falling edge setup time (write cycle) falling edge hold time from (write cycle) Mode register command cycle time
tWPRES Write preamble setup time tWPST tWPRE tRPRE tRPST tRAS tRFC Write postamble Write preamble Address control input setup time Address control input hold time Read preamble Read postamble Active Precharge command Active Active/Auto-refresh command period Auto-refresh Active/Auto-refresh command period
2-4, 10,11
2003-01-10, V0.9
Page
HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Electrical Characteristics Timing Absolute Specifications
VDDQ 2.6V 0.1V; 2.6V 0.1V) (Part
DDR400A Min. tRCD tRAP tRRD tDAL tWTR tXSNR tXSRD tREFI Active Read Write delay Precharge command period Active Autoprecharge delay Active bank Active bank command Write recovery time Auto precharge write recovery precharge time Internal write read command delay Exit self-refresh non-read command Exit self-refresh read command Average Periodic Refresh Interval (8192 refresh commands 64ms refresh period) Max. DDR400B Min. Max. 1-4,9 1-4,
Symbol
Parameter
Unit
Notes
Input slew rate 1V/ns DDR400 CK/CK input reference level (for timing reference CK/CK) point which cross: input reference level signals other than CK/CK, VREF. CK/CK slew rate V/ns Inputs recognized valid until VREF stabilizes. Output timing reference level, measured timing reference point indicated Characteristics (Note VTT. transitions occur same access time windows valid data transitions. These parameters referred specific voltage level, specify when device longer driving (HZ), begins driving (LZ). maximum limit this parameter device limit. device operates with greater value this parameter, system performance (bus turnaround) degrades accordingly. specific requirement that valid (HIGH, LOW, some point valid transition) before this edge. valid transition defined monotonic meeting input slew rate specifications device. When writes were previously progress bus, will transitioning from Hi-Z logic LOW. previous write progress, could HIGH, LOW, transitioning from HIGH this time, depending tDQSS. maximum eight Autorefresh commands posted given SDRAM device. each terms, already integer, round next highest integer. equal actual system clock cycle time. These parameters guarantee device timing, they necessarilty tested each device Fast slew rate V/ns slow slew rate V/ns 1V/ns command/address slew rate >1.0 V/ns, measured between VOH(ac) VOL(ac)
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2003-01-10, V0.9
HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Electrical Characteristics Timing DDR400 Applicable Specifications Expressed Clock Cycles VDDQ 2.6V 0.1V; 2.6V 0.1V,
DDR400A/B Symbol tMRD tWPRE tRAS tRFC tRCD tRRD tDAL tWTR tXSNR tXSRD Parameter Mode register command cycle time Write preamble Active Precharge command Active Active/Auto-refresh command period Auto-refresh Active/Auto-refresh command period Active Read Write delay Precharge command period Active bank Active bank command Write recovery time Auto precharge write recovery precharge time Internal write read command delay Exit self-refresh non-read command Exit self-refresh read command 0.25 16000 1-54 Units Notes
Input slew rate 1V/ns CK/CK input reference level (for timing reference CK/CK) point which cross: input reference level signals other than CK/CK, VREF. Inputs recognized valid until VREF stabilizes. Output timing reference level, measured timing reference point indicated Characteristics (Note VTT. transitions occur same access time windows valid data transitions. These parameters referred specific voltage level, specify when device longer driving (HZ), begins driving (LZ).
2003-01-10, V0.9
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