T-SMINTI Edition 2001-11-09 Published Infineon Technologies St.-M
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T-SMINTI
Edition 2001-11-09 Published Infineon Technologies St.-Martin-Strasse D-81541 Germany
Infineon Technologies 2001. Rights Reserved.
Attention please! information herein given describe certain components shall considered warranted characteristics. Terms delivery rights technical change reserved. hereby disclaim warranties, including limited warranties non-infringement, regarding circuits, descriptions charts stated herein. Infineon Technologies approved CECC manufacturer. Information further information technology, delivery terms conditions prices please contact your nearest Infineon Technologies Office Germany Infineon Technologies Representatives worldwide (see address list). Warnings technical requirements components contain dangerous substances. information types question please contact your nearest Infineon Technologies Office. Infineon Technologies Components only used life-support devices systems with express written approval Infineon Technologies, failure such components reasonably expected cause failure that life-support device system, affect safety effectiveness that device system. Life support devices systems intended implanted human body, support and/or maintain sustain and/or protect human life. they fail, reasonable assume that health user other persons endangered.
T-SMINTI
82902 Revision History: Previous Version: Page 2001-11-09 Preliminary Data Sheet 06.01 Subjects (major changes since last revision)
Table Additional C/I-command Figure Chapter 2.4.7.4 Chapter 3.2.3 Chapter Chapter 4.9.4 Chapter Chapter Chapter 4.9.8 Chapter 4.9.4 Chapter Chapter Framer Deframer Loopback (DLB) more supported
Reset value MASKU (not 00h) Reset value FW-Version Restriction LOOP.LB1, LBBD Transparent state Input Leakage Current AIN, BIN: max. 30µA Reduced power consumption
questions technology, delivery prices please contact Infineon Technologies Offices Germany Infineon Technologies Companies Representatives worldwide: webpage http://www.infineon.com
82902
Table Contents 1.6.1 2.1.1 2.1.1.1 2.1.2 2.1.3 2.3.1 2.3.2 2.3.2.1 2.3.2.2 2.3.3 2.3.3.1 2.3.3.2 2.3.3.3 2.3.3.4 2.3.3.5 2.3.3.6 2.3.4 2.3.5 2.3.5.1 2.3.5.2 2.3.5.3 2.3.5.4 2.3.5.5 2.3.6 2.4.1 2.4.2 2.4.3 2.4.4 2.4.4.1
Data Sheet
Page
Overview References Features Supported Configuration Block Diagram Definitions Functions Specific Pins Test Modes System Integration Functional Description Microcontroller Interfaces Serial Control Interface (SCI) Programming Sequences Parallel Microcontroller Interface Microcontroller Clock Generation Reset Generation IOM-2 Interface IOM,-2 Functional Description IOM,-2 Handler Controller Data Access (CDA) Serial Data Strobe Signal IOM,-2 Monitor Channel Handshake Procedure Error Treatment MONITOR Channel Programming Master Device MONITOR Channel Programming Slave Device Monitor Time-Out Procedure MONITOR Interrupt Logic Channel Handling D-Channel Access Control Application Examples D-Channel Access Control Handling Stop/Go Handling D-Channel Arbitration State Machine D-Channel Arbiter Activation/Deactivation IOM®-2 Interface U-Transceiver 4B3T Frame Structure Maintenance Channel Coding from Binary Ternary Data Decoding from Ternary Binary Data Monitoring Code Violations
2001-11-09
82902
Table Contents 2.4.4.2 2.4.5 2.4.6 2.4.7 2.4.7.1 2.4.7.2 2.4.7.3 2.4.7.4 2.4.7.5 2.4.7.6 2.4.8 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.5.5.1 2.5.5.2 2.5.5.3 2.5.6 2.5.7 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 3.2.1 3.2.2 3.2.2.1 3.2.2.2 3.2.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5
Data Sheet
Page
Block Error Counter (RDS Error Counter) Scrambler Descrambler Command/Indication Codes State Machine Activation Deactivation State Machine Notation Awake Protocol State Machine (IEC-T NTC-T Compatible) Inputs U-Transceiver Outputs U-Transceiver NT-States U-Transceiver Interrupt Structure S-Transceiver Line Coding, Frame Structure Channels, Multiframing Data Transfer between IOM,-2 Loopback Control S-Transceiver State Machine Codes State Machine Mode State Machine LT-S Mode S-Transceiver Enable Disable Interrupt Structure S-Transceiver
Operational Description Layer Activation/Deactivation Generation 4B3T Signal Elements Complete Activation Initiated Exchange Complete Activation Initiated Complete Activation Initiated Complete Deactivation Loop Layer Loopbacks Analog Loop-Back S-Transceiver Loopback No.2 Complete Loopback Loopback No.2 Single Channel Loopbacks Local Loopbacks Featured LOOP Register External Circuitry Power Supply Blocking Recommendation U-Transceiver S-Transceiver Oscillator Circuitry General
2001-11-09
82902
Table Contents 4.3.1 4.3.2 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.5.6 4.5.7 4.5.8 4.5.9 4.6.1 4.6.2 4.6.3 4.6.4 4.6.5 4.6.6 4.7.1 4.7.2 4.7.3 4.7.4 4.7.5 4.7.6 4.7.7 4.7.8 4.7.9 4.7.10 4.7.11
Data Sheet
Page
Register Description Address Space Interrupts Register Summary Reset U-Transceiver Functions During Deactivation with C/I-Code RESET Mode Register Evaluation Timing Detailed Registers MODEH Mode Register IOM-2 CIR0 Command/Indication Receive CIX0 Command/Indication Transmit CIR1 Command/Indication Receive CIX1 Command/Indication Transmit Detailed S-Transceiver Registers S_CONF0 S-Transceiver Configuration Register S_CONF2 S-Transmitter Configuration Register S_STA S-Transceiver Status Register S_CMD S-Transceiver Command Register SQRR S/Q-Channel Receive Register SQXR- S/Q-Channel Transmit Register ISTAS Interrupt Status Register S-Transceiver MASKS Mask S-Transceiver Interrupt S_MODE S-Transceiver Mode Interrupt General Configuration Registers ISTA Interrupt Status Register MASK Mask Register MODE1 Mode1 Register MODE2 Mode2 Register Identification Register SRES Software Reset Register Detailed IOM®-2 Handler Registers CDAxy Controller Data Access Register XXX_TSDPxy Time Slot Data Port Selection CHxy CDAx_CR Control Register Controller Data Access CH1x S_CR Control Register S-Transceiver Data CI_CR Control Register Data MON_CR Control Register Monitor Data SDS1_CR Control Register Serial Data Strobe SDS2_CR Control Register Serial Data Strobe IOM_CR Control Register Data MCDA Monitoring Bits Synchronous Transfer Interrupt
2001-11-09
82902
Table Contents 4.7.12 4.7.13 4.8.1 4.8.2 4.8.3 4.8.4 4.8.5 4.8.6 4.9.1 4.9.2 4.9.3 4.9.4 4.9.5 4.9.6 4.9.7 4.9.8 5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 7.1.1 7.1.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5
Data Sheet
Page
ASTI Acknowledge Synchronous Transfer Interrupt MSTI Mask Synchronous Transfer Interrupt Detailed MONITOR Handler Registers MONITOR Receive Channel MONITOR Transmit Channel MOSR MONITOR Interrupt Status Register MOCR MONITOR Control Register MSTA MONITOR Status Register MCONF MONITOR Configuration Register Detailed U-Transceiver Registers OPMODE Operation Mode Register UCIR Code Read Register UCIW Code Write Register LOOP Loopback Register Block Error Counter Register ISTAU Interrupt Status Register U-Interface MASKU Mask Register U-Interface FW_VERSION Electrical Characteristics Absolute Maximum Ratings Characteristics Capacitances Power Consumption Supply Voltages Characteristics IOM®-2 Interface Serial Interface Parallel Interface Reset Undervoltage Detection Characteristics
Package Outlines Appendix: Differences between T-SMINT,I Pinning Definitions Functions U-Transceiver U-Interface Conformity U-Transceiver State Machines Command/Indication Codes Interrupt Structure Register Summary U-Transceiver
2001-11-09
82902
Table Contents Page
External Circuitry Index
Data Sheet
2001-11-09
82902
List Figures Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
Data Sheet
Page
Configuration Block Diagram Application Example T-SMINT®I: High Feature Intelligent Control Interface Control IOM,-2 Interface Serial Control Interface Timing Serial Command Structure. Direct/Indirect Register Address Mode Reset Generation T-SMINT,I IOM-2 Frame Structure T-SMINT,I Architecture IOM,-2 Handler Data Access CDAx0 CDAx1 register pairs Examples Data Access CDAxy Registers. Data Access when Looping from Data Access when Shifting (DD) Example Monitoring Data Interrupt Structure Synchronous Data Transfer Examples Synchronous Transfer Interrupt Control with STIxy enabled Data Strobe Signal Generation MONITOR Channel Protocol (IOM®-2) Monitor Channel, Transmission Abort requested Receiver. Monitor Channel, Transmission Abort requested Transmitter. Monitor Channel, Normal Transmission MONITOR Interrupt Structure Interrupt Structure. D-Channel Arbitration: with HDLC Direct Access D-Channel Arbitration: with HDLC Access Structure Last Octet Structure Last Octet State Machine D-Channel Arbiter (Simplified View). Deactivation IOM®-2 Clocks State Diagram Example Awake Procedure initiated Awake Procedure initiated State Machine (IEC-T/NTC-T Compatible). Interrupt Structure U-Transceiver -Interface Line Code Frame Structure Reference Points (ITU I.430). S-Transceiver Control State Diagram Notation State Machine Mode
2001-11-09
82902
List Figures Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
Page
State Machine LT-S Mode Interrupt Structure S-Transceiver. Activation Initiated Exchange Activation Initiated Activation Initiated Complete Deactivation. Loop Test Loopbacks External Loop S/T-Interface Complete Loopback Options NT-Mode Loopbacks Featured Register LOOP Power Supply Blocking External Circuitry U-Transceiver with External Hybrid External Circuitry S-Interface Transmitter External Circuitry S-Interface Receiver Crystal Oscillator Address Space. T-SMINT,I Interrupt Status Registers Maximum Sinusoidal Ripple Supply Voltage Input/Output Waveform Tests. IOM®-2 Interface Synchronization Timing IOM®-2 Interface Frame Synchronization Timing Serial Control Interface Microprocessor Read Cycle. Microprocessor Write Cycle Multiplexed Address Timing. Non-Multiplexed Address Timing Microprocessor Read Timing Microprocessor Write Cycle Non-Multiplexed Address Timing Reset Input Signal Undervoltage Control Timing NTC-Q Compatible State Machine Q-SMINT,I: 2B1Q Simplified State Machine Q-SMINT,I: 2B1Q IEC-T/NTC-T Compatible State Machine T-SMINT,I: 4B3T. Interrupt Structure U-Transceiver Q-SMINT,I: 2B1Q Interrupt Structure U-Transceiver T-SMINT,I: 4B3T. External Circuitry T-SMINT,I
Data Sheet
2001-11-09
82902
List Tables Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table
Page
Products Generation Definitions Functions States. Interface Selection T-SMINT,I. Header Byte Code Operation Modes MCLK Frequencies Reset Source Selection Examples Synchronous Transfer Interrupts Transmit Direction Receive Direction. T-SMINT,I Configuration Settings Intelligent Applications Frame Structure Downstream Transmission Frame Structure Upstream Transmission Coding Table 4B3T Decoding Table Active States Codes Differences former NT-SM IEC-T/NTC-T Timers Symbol Output Signal Output State Test C/I-Code Output. S/Q-Bit Position Identification Multi-Frame Structure 4B3T Signal Elements Generation 4B3T Signal Elements. S/T-Interface Signals U-Transformer Parameters S-Transformer Parameters Crystal Parameters Reset U-Transceiver Functions During Deactivation with C/I-Code RESET Mode Register with Immediate Evaluation Execution. Maximum Input Currents S-Transceiver Characteristics U-Transceiver Characteristics Capacitances Reset Input Signal Characteristics. Parameters UVD/POR Circuit Design Number States.
Data Sheet
2001-11-09
82902
Overview
Overview
82902 offers U-transceiver, S-transceiver interface. microcontroller interface provides access both transceivers well interface. However, opposed bigger brother does have HDLC controller. Main target applications intelligent applications where HDLC controller(s) (are) provided microcontroller. example such microcontroller Infineon UTAH chip which features four flexible HDLC controllers. Table Page summarizes generation products.
Table
Products Generation 80902 T-SMINT®O 81902 T-SMINT®IX P-MQFP-64 P-TQFP-64 U+S+HDLC+ 82902 T-SMINT®I P-MQFP-64 P-TQFP-64
Package Register access Access MCLK, watchdog timer, SDS, BCL, Dchannel arbitration, access manipulation etc. provided HDLC controller mode available
P-MQFP-44
parallel parallel
(only)
Data Sheet
2001-11-09
82902
Overview
References
080, Transmission Multiplexing; ISDN basic rate access; Digital transmission system metallic local lines, ETSI, November 1998 Technische Richtlinie, Spezifikation ISDN Schnittstelle Schicht Deutsche Telecom August 1991 0284/96 Technische Spezifikation Intelligenter (iNT) Funktionen eines Terminaladapters 2a/b (ohne Internverkehr), Deutsche Telekom 2001 Draft, ISDN; Basic User Network Interface (UNI), ETSI, November 1996 T1.605-1991, ISDN-Basic Access Interface Reference Points (Layer Specification), ANSI, 1991 I.430, ISDN User-Network Interfaces: Layer Recommendations, ITU, November 1988 IEC-T, ISDN Echocancellation Circuit, 20901 (IEC 20902 (IEC TA), preliminary Target Specification 11.88, Siemens 1988 SBCX, Interface Circuit Extended, 2081 V3.4, User's Manual 11.96, Siemens 1996 NTC-T, Network Termination Controller (4B3T), 8090 V1.1, Data Sheet 06.98, Siemens 1998 INTC-Q, Intelligent Network Termination Controller (2B1Q), 8191 V1.1, Data Sheet 10.97, Siemens 1997 Q-SMINTO, 2B1Q Second Gen. Modular ISDN (Ordinary), 80912 Q-SMINTIX, 2B1Q Second Gen. Modular ISDN (Intelligent eXended), 81912 Q-SMINTI, 2B1Q Second Gen. Modular ISDN (Intelligent), 82912 V1.3, Data Sheets 03.01, Infineon 2001 Interface Reference Guide, Siemens 03.91 SCOUT-S(X), Siemens Codec with S/T-Transceiver, 2138x V1.1, Preliminary Data Sheet 08.98, Infineon Technologies 1999 PITA, Interface Telephony/Data Applications V0.3, SICAN GmbH, September1997 Dual Channel SLICOFI-2, HV-SLIC; DUSLIC; PEB3265, 4265, 4266; Data Sheet DS2, Infineon Technologies, July 2000.
[10] [11]
[12] [13] [14] [15]
Data Sheet
2001-11-09
T-SMINT®I 4B3T Second Gen. Modular ISDN (Intelligent)
82902
Version
CMOS
Features
Features known from 8090 U-transceiver S-transceiver chip U-interface (4B3T) conform ETSI [2]: Meets transmission requirements ETSI loops with margin S/T-interface conform ETSI [4], ANSI Supports point-to-point configurations Meets exceeds transmission requirements Access Monitor channels Power-on reset Undervoltage Detection with external components robustness Features
P-MQFP-64-1,-2
P-TQFP-64-1
Conforms 'Technische Spezifikation Intelligenter (iNT) Funktionen eines Terminaladapters 2a/b' Deutsche Telekom Perfectly suited high-end intelligent that require multiple HDLC controllers compatible with (2nd Generation) Parallel serial µP-interface Siemens/Intel non-multiplexed (direct indirect addressing (SCOUT)) Siemens/Intel multiplexed Motorola programmable MCLK (can disabled) (SCOUT)
Type 82902 82902
Data Sheet
Package P-MQFP-64 P-TQFP-64
2001-11-09
82902
Overview Enhanced interface Timeslot access manipulation (SCOUT) output; programmable flexible strobes SDS1/2, e.g. active during several timeslots. Optional: registers read written Monitor channel concept External Awake (EAW) Optional: Implementation S-transceiver statemachine software Power Down reset states (e.g. S-transceiver) individual circuits Automatic D-channel arbitration between S-bus external HDLC controller Priority setting (8/10) off-chip HDLC controller Vref according external capacitor removed Inputs accept 3.3V (open drain) accepts pull-up 3.3V1) Lowest power consumption power CMOS technology (0.35µ) Newly optimized power libraries High output swing S-line interface leads minimized power consumption Single Volt power supply
Supported
integrated hybrid provided Therefore, external hybrid always required, which consists only additional resistors compared integrated hybrid, allows more flexibility board design. On-chip HDLC controller Auxiliary interface (capacitive receiver coupling suited S-feeding) NT-Star with star point IOM®-2 (already supported NTC-T). access S2-5 channels. Access only channel Scout-S. selection betweeen transparent non-auto mode provided.
Pull-ups must avoided. so-called 'hot-electron-effect' would lead long term degradation.
Data Sheet
2001-11-09
82902
Overview
Configuration
VDDa_SX VSSa_SX
/VDDDET VDDa_SR VSSa_SR
T-SMINT 82902
XOUT BOUT VDDa_UX VSSa_UX AOUT
VSSD VDDD SCLK /EAW MCLK /ACT
pin_2.vsd
Figure
Configuration
Data Sheet
SDS1 VDDD VSSD /INT
VSSa_UR VDDa_UR /RST /RSTO SDS2
2001-11-09
82902
Overview
Block Diagram
XOUT
VDDDET
RSTO
Clock Generation
POR/UVD
AOUT BOUT
S-Transceiver U-Tansceiver
D-Channel Arbitration
Factory Tests
IOM-2 Interface
Interface (e.g. Multiplexed Mode)
SDS1 SDS2
AD0-AD7
MCLK
block diagram.vsd
Figure
Block Diagram
Data Sheet
2001-11-09
82902
Overview
Definitions Functions
Definitions Functions Symbol
VDDa_UR
Table
Type
Function Supply voltage U-Receiver (3.3 Analog ground U-Receiver Supply voltage U-Transmitter (3.3 Analog ground U-Transmitter Supply voltage S-Receiver (3.3 Analog ground S-Receiver Supply voltage S-Transmitter (3.3 Analog ground S-Transmitter Supply voltage digital circuits (3.3 Ground digital circuits Supply voltage digital circuits (3.3 Ground digital circuits Frame Sync: 8-kHz frame synchronization signal Data Clock: interface clock signal (double clock): 1.536 Clock: clock identical data rate (768 kHz) Data Downstream: Data interface Data Upstream: Data interface
VSSa_UR VDDa_UX
VSSa_UX VDDa_SR
VSSa_SR VDDa_SX
VSSa_SX VDDD
VSSD VDDD
VSSD
Data Sheet
2001-11-09
82902
Overview Table Definitions Functions (cont'd) Symbol SDS1 Type Function Serial Data Strobe1: Programmable strobe signal time slot and/or D-channel indication Serial Data Strobe2: Programmable strobe signal time slot and/or D-channel indication Chip Select: level indicates microcontroller access Serial Clock: Clock signal interface serial interface selected Multiplexed Mode: Address/data Address/data line parallel interface selected Non-Multiplexed Mode: Data Data line parallel interface selected Serial Data Receive: Receive data line interface serial interface selected Multiplexed Mode: Address/data Address/data line parallel interface selected Non-Multiplexed Mode: Data Data line parallel interface selected
SDS2
SCLK
Data Sheet
2001-11-09
82902
Overview Table Definitions Functions (cont'd) Symbol Type OD/O Function Serial Data Transmit: Transmit data line interface serial interface selected Multiplexed Mode: Address/data Address/data line parallel interface selected Non-Multiplexed Mode: Data Data line parallel interface selected Multiplexed Mode: Address/data Transfers addresses from microcontroller data between microcontroller Non-Multiplexed Mode: Data bus. Transfers data between microcontroller (data lines D0-D4). Non-Multiplexed Mode: Address transfers addresses from microcontroller indirect address mode only valid. Multiplexed Mode used multiplexed mode. this case A0-A6 should directly connected VDD. Read Indicates read access registers (Intel mode). Data Strobe rising edge marks valid read write operation (Motorola mode).
Data Sheet
2001-11-09
82902
Overview Table Definitions Functions (cont'd) Symbol Type Function Write Indicates write access registers (Intel mode). Read/Write HIGH identifies valid host access read operation identifies valid host access write operation (Motorola mode). Address Latch Enable address external address/data (multiplexed type only) latched with falling edge ALE. also selects microcontroller interface type (multiplexed multiplexed). Reset: active reset input. Schmitt-Trigger input with hysteresis typical 360mV. used. Reset Output: active reset output. Interrupt Request: becomes active requests interrupt. Microcontroller Clock: Clock output microcontroller External Awake: level during power down activates clock generation i.e. interface provides FSC, read write access.1)
RSTO
MCLK
S-Bus Transmitter Output (positive) S-Bus Transmitter Output (negative) S-Bus Receiver Input
Data Sheet
2001-11-09
82902
Overview Table Definitions Functions (cont'd) Symbol XOUT Type Function S-Bus Receiver Input Crystal Connected 15.36 crystal Crystal Connected 15.36 crystal Differential U-interface Output Differential U-interface Output Differential U-interface Input Differential U-interface Input Detection: This selects detection active ('0') reset pulses generated RSTO whether deactivated ('1') external reset applied RST. Activation LED. Indicates activation status Stransceiver. directly drive (4mA). Test Used factory device test. 'VSS' Test Used factory device test. 'VSS' Reserved These pins reserved future use. connect.
AOUT BOUT
VDDDET
This function different that defined Ref. [13]
Data Sheet
2001-11-09
82902
Overview Input Output (Push-Pull) Output (Open Drain)
1.6.1
Specific Pins Test Modes
connected display four different states (off, slow flashing, fast flashing, on). displays activation status S-transceiver according Table programmable bits (LED1 LED2 register MODE2). Table States U_Deactivated U_Activated S_Activated
fast flashing
slow flashing
Note: denotes duty cycle 'high' 'low'. with: U_Deactivated: 'Deactivated State' defined Chapter 2.4.7.6. U_Activated: 'SBC Synchronizing', 'Wait Info U4H', `Transparent` defined Chapter 2.4.7.6. S-Activated: 'Activated State' defined Chapter 2.5.5.2. Note: Optionally, drive second with inverse polarity (connect this additional 3.3V only). Test Modes test patterns S-interface Single Pulses`, Continuous Pulses`) U-interface (`Data Through`, `Send Single Pulses`,) invoked codes (TM1, TM2, SSP). Setting SRES.RES_U forces U-transceiver into test mode `Quiet Mode` (QM), i.e. U-transceiver hardware reset.
Data Sheet
2001-11-09
82902
Overview
System Integration
DC/DC Converter IDCC PEB2023
Interface
T-SMINTI PEF82902
Interface
POTS Interface
SLIC SLICOFI SLIC
IOM-2
Core HDLC IOM-2
UTAH
USB/ V.24
V.24 Interface
HENTappl.vsd
Figure
Application Example T-SMINT®I: High Feature Intelligent
U-transceiver, S-transceiver channels controlled monitored via: parallel serial microprocessor interface Access on-chip registers interface Address/Data format Activation/Deactivation control S-transceiver interface handler Monitor channel master transparent interface used D-channel arbitration between S-transceiver off-chip HDLC controllers.
Data Sheet
2001-11-09
82902
Overview
C/I0 C/I1
Register
Interface
IOM-2 Slave e.g. SLICOFI-2
iommaster.vsd
Figure
Control Interface
Alternatively, controlled Interface Access on-chip registers Monitor channel with Header/Address/Data format (Device Monitor slave) Activation/Deactivation control S-transceiver channels transparent interface used D-channel arbitration between S-transceiver off-chip HDLC controllers.
Data Sheet
2001-11-09
82902
Overview
C/I1
C/I0
Register
IOM-2 Master e.g. UTAH
iomslave.vsd
Figure
Control Interface
Data Sheet
2001-11-09
82902
Functional Description
Functional Description
Microcontroller Interfaces
supports either serial parallel microcontroller interface. applications where controller connected microcontroller interface, register programming done MONITOR channel from master device. such applications operates slave mode (refer corresponding chapter MONITOR handler). interface selections done pinstrapping. possible interface selections listed Table selection pins evaluated when reset input released. levels stated tables following defined: 'High':dynamic value which must 'High' when level evaluated VDD, VSS:static 'High' 'Low' level (tied VDD, VSS)
Table PINS (R/W) (DS)
Interface Selection Serial /Parallel Interface PINS Interface Type/Mode Motorola Siemens/Intel Non-Mux Siemens/Intel Serial Control Interface(SCI) MONITOR Channel (Slave Mode)
'High' 'High'
Parallel Serial
`High' 'High'
edge
Note: selected interface mode which does require pins (e.g. address pins) unused pins must tied VDD. microcontroller interface also consists microcontroller clock generation MCLK, interrupt request INT, reset input reset output RSTO. interrupt request (open drain output) becomes active requests interrupt.
2.1.1
Serial Control Interface (SCI)
serial control interface (SCI) compatible interface Motorola Siemens C510 family microcontrollers. consists lines: SCLK, SDX, Data transferred lines rate given SCLK. falling edge indicates beginning
Data Sheet 2001-11-09
82902
Functional Description serial access registers. latches incoming data rising edge SCLK shifts falling edge SCLK. Each access must terminated rising edge Data transferred groups bits with first. mode selected 'open drain' 'push-pull' programming MODE2.PPSDX. Figure shows timing byte read/write access serial control interface.
Data Sheet
2001-11-09
82902
Functional Description
Write Access
SCLK Header Command/Address Data
write
Read Access
SCLK Header Command/Address
read Data
SCI_TIM.VSD
Figure
Serial Control Interface Timing
Data Sheet
2001-11-09
82902
Functional Description
2.1.1.1
Programming Sequences
basic structure read/write access registers serial control interface shown Figure
write sequence:
header
write
byte byte
address (command)
write data
read sequence:
header
read
byte
address (command)
byte
read data
Figure
Serial Command Structure
programming sequence starts with transfer header byte. header byte specifies different programming sequences allowing flexible optimized access individual functional blocks possible sequences listed Table described after that.
Table Header Byte
Header Byte Code Sequence Adr-Data-Adr-Data Adr-Data-Data-Data Sequence Type non-interleaved interleaved Read-/Write-only non-interleaved interleaved Address Range 00H-7FH Access Address Range 00H-7FH
Header 40H: Non-interleaved A-D-A-D Sequences non-interleaved A-D-A-D sequences give direct read/write access address range 00H-7FH have length. this mode connected
Data Sheet
2001-11-09
82902
Functional Description together allowing data transmission line. Example read/write access with header 40H:
header wradr wrdata rdadr rddata rdadr rddata wradr wrdata
Header 48H: Interleaved A-D-A-D Sequences interleaved A-D-A-D sequences give direct read/write access address range 00H-7FH have length. This mode allows time optimized access registers interleaving data SDR. Example read/write access with header 48H:
header wradr wrdata rdadr rdadr rddata wradr rddata wrdata
Header 43H: Read-/Write- only A-D-D-D Sequence Generally, used register access address range 20H-7DH. sequence have length terminated rising edge Example write access with header 43H: Example read access with header 43H:
header rdadr rddata
(rdadr)
header
wradr
wrdata
(wradr)
wrdata
(wradr)
wrdata
(wradr)
wrdata
(wradr)
wrdata
(wradr)
wrdata
(wradr)
wrdata
(wradr)
rddata
(rdadr)
rddata
(rdadr)
rddata
(rdadr)
rddata
(rdadr)
rddata
(rdadr)
rddata
(rdadr)
Header 41H: Non-interleaved A-D-D-D Sequence This sequence (header 41H) allows front A-D-D-D write access noninterleaved A-D-A-D read access. Generally, used register access address range 20H-7DH.The termination condition read access reception wradr. sequence have length terminated rising edge
Data Sheet
2001-11-09
82902
Functional Description Example read/write access with header 41H:
header rdadr rddata rdadr rddata wradr wrdata
(wradr)
wrdata
(wradr)
wrdata
(wradr)
Header 49H: Interleaved A-D-D-D Sequence This sequence (header 49H) allows front A-D-D-D write access interleaved A-D-A-D read access. Generally, used register access address range 20H-7DH.The termination condition read access reception wradr. sequence have length terminated rising edge Example read/write access with header 49H:
header rdadr rdadr rddata wradr rddata wrdata
(wradr)
wrdata
(wradr)
wrdata
(wradr)
2.1.2
Parallel Microcontroller Interface
8-bit parallel microcontroller interface with address decoding chip allows easy fast microcontroller access. parallel interface provides three types busses which selected ALE. operation modes with corresponding control pins listed Table
Table
Operation Modes Edge Control Pins R/W,
Mode Motorola Siemens/Intel non-multiplexed Siemens/Intel multiplexed
occurrence edge ALE, either positive negative, time during operation immediately selects interface type (3). return other interface types possible only hardware reset issued. Note: selected interface mode which does require pins (e.g. address pins) unused pins must tied VDD. read/write access registers done multiplexed nonmultiplexed mode. non-multiplexed mode register address must applied address (A0A6) data access data (D0-D7).
Data Sheet 2001-11-09
82902
Functional Description multiplexed mode address address (AD0-AD7) latched before read/write access address/data performed. provides different ways address register contents which selected with AMOD MODE2 register. address mode after reset indirect address mode (AMOD '0'). Reprogramming into direct address mode (AMOD '1') take place indirect address mode. Figure illustrates both register addressing modes. Direct address mode (AMOD '1'): register address read written directly described above. Indirect address mode (AMOD '0'): non-muxed: only address (A0) muxed: only address-data (AD0) gets evaluated address virtual ADDRESS (0H) virtual DATA (1H) register. Every access target register consists write access (muxed non-muxed) ADDRESS store target address, well read access (muxed non-muxed) from DATA read from target register write access (muxed non-muxed) DATA write target register
Direct Address Mode AMOD Data
Indirect Address Mode AMOD (default) Data
DATA ADDRESS
regacces.vsd
Figure
Direct/Indirect Register Address Mode
Data Sheet
2001-11-09
82902
Functional Description
2.1.3
Microcontroller Clock Generation
microcontroller clock derived from unregulated 15.36 clock from oscillator provided MCLK. Five clock rates selectable programmable prescaler which controlled bits MODE1.MCLK MODE1.CDS corresponding following table. Table MODE1. MCLK Bits MCLK Frequencies MCLK frequency with MODE1.CDS 3.84 0.96 7.68 disabled MCLK frequency with MODE1.CDS 7.68 1.92 15.36 disabled
clock rate changed after becomes inactive.
Reset Generation
Figure shows organization reset generation
Data Sheet
2001-11-09
82902
Functional Description
RSS1
C/I0 Code Change (Exchange Awake)
125µs 250µs
RSS2,1 RSTO
RSS2,1 open
Watchdog
125µs
Deactivation Delay
Software Reset Register (SRES)
Reset MODE1 Register
VDDDET
RES_CI
Reset Functional Block
POR/UVD
RES_HDLC RES_S
RES_U
VDDDET
Internal Reset Registers
RESETGEN.VSD
Figure
Reset Generation
Reset Source Selection internal reset sources code change Watchdog timer output active reset RSTO. These reset sources selected with RSS2,1 bits MODE1 register according Table
'OR'-gates shall illustrate symbolic way, that 'source active' 'source active' forwarded. real polarity different sources considered.
Data Sheet
2001-11-09
82902
Functional Description internal reset sources MODE1 register reset value. Table RSS2
Reset Source Selection RSS1 -C/I Code Change -Watchdog Timer -/RSTO disabled high impedance) POR/UVD1)
POR/UVD enabled/disabled VDDDET
Code Change (Exchange Awake) change downstream channel (C/I0) generates reset pulse Watchdog Timer After selection watchdog timer (RSS '11') internal timer reset started. During every time period microcontroller program WTC1- WTC2 bits following sequence reset restart watchdog timer: WTC1 WTC2
Otherwise timer expires WOV-interrupt (ISTA Register) together with reset pulse RSTO generated. Deactivation watchdog timer only possible with hardware reset (including expiration watchdog timer). SCOUT-S, watchdog timer clocked with clocks works only internal clocks active. Hence, power consumption minimized state power down. Software Reset Register (SRES) Several main functional blocks reset separately software setting corresponding SRES register. This equivalent hardware reset corresponding functional block. reset state activated long '1'.
Data Sheet
2001-11-09
82902
Functional Description External Reset Input input external reset applied forcing reset state. This external reset signal additionally RSTO output. After release external reset, wait min. before starts read write access (see Table 37). Reset Ouput VDDDET active, then deactivation reset output RSTO delayed tDEACT (see Table 38). Reset Generation on-chip reset generator based Power-On Reset (POR) Under Voltage Detection (UVD) circuit (see Table 38). POR/UVD requires external components. POR/UVD circuit disabled VDDDET. requirements ramp-up during power-on reset described Chapter 5.6.5. Clocks Data Lines During Reset During reset data clock (DCL), clock (BCL), microcontroller clock1) (MCLK) frame synchronization (FSC) keep running. During reset high; with exception output code from U-Transceiver channel 'DR' 0000 (Value after reset register UCIR '00H') output code from S-Transceiver channel 'TIM' 0000.
during Power-On/UVD Reset, microcontroller clock MCLK running, starts running soon timer tDEAC started.
Data Sheet
2001-11-09
82902
Functional Description
IOM-2 Interface
supports interface terminal mode (DCL=1.536 MHz) according Reference Guide [12].
2.3.1
Functional Description
interface consists four lines: FSC, DCL, optionally BCL. rising edge indicates start frame. clock signals synchronize data transfer both data lines twice rate, rate equal rate. bits shifted with rising edge first clock cycle sampled falling edge second clock cycle. With bits shifted with rising edge sampled with falling edge single clock cycle. interface enabled/disabled with DIS_IOM IOM_CR registerThe signal frame sync signal. number timeslots receive transmit lines determined frequency clock BCL), with 1.536 (BCL=768 kHz) clock channels consisting timeslots each available. IOM®-2 Frame Structure frame structure data ports (DU,DD) with clock 1.536 BCL=768 kHz) disabled (IOM_CR.TIC_DIS) shown Figure
macro_19
Figure
IOM-2 Frame Structure
Data Sheet
2001-11-09
82902
Functional Description frame composed three channels: Channel contains 144-kbit/s user signaling data MONITOR programming channel (MON0) command/indication channel (CI0) control programming e.g. U-transceiver. Channel contains 64-kbit/s intercommunication channels (IC), MONITOR programming channel (MON1) command/indication channel (CI1) control programming e.g. S-transceiver. Channel used D-channel access mechanism (TlC-bus, bit). Additionally, channel supports further channels.
2.3.2
Handler
handler offers great flexibility handling data transfer between different functional units voice/data devices connected interface. Additionally provides microcontroller access time slots interface four controller data access registers (CDA). data functional units S-transceiver Controller data access (CDA) configured programming time slot data port selection registers (TSDP). With bits (Time Slot Selection) data functional units assigned each time slots frame. With (Data Port Selection) output each functional unit assigned respectively. input assigned vice versa. With control registers (CR) access data functional units controlled setting corresponding control bits (EN, SWAP). handler also provides access transceiver MONITOR channel channels (CI0,CI1) (TIC)
access these channels controlled registers S_CR, CI_CR MON_CR. interface with Serial Data Strobes (SDS1,2) controlled control registers IOM_CR, SDS1_CR SDS2_CR. following Figure shows architecture handler.
Data Sheet
2001-11-09
82902
Functional Description
BCL/SCLK
SDS1
IOM-2 Handler
SDS1/2_CR IOM_CR IOM-2 Interface (EN,
(EN, TLEN, TSS)
Data
SDS2
D/B1/B2 Data C/I0 Data
Monitor Data
Controller Data Access (CDA)
Architecture Handler
Data C/I0 Data C/I1 Data
Registers
CDA10 CDA11 CDA20 CDA21 (TSDP, DPS, SWAP, TBM, MCDA, STI) CDA_TSDPxy CDA_CRx MCDA MSTI ASTI
Control Data Access
Control Monitor Data
Disable
Control C/I1 Data
Control Transceiver Data Access (TSS, DPS,
MON_CR IOM_CR CI_CR
Transceiver Data (TR=U/S)
S_TSDP_B1 S_TSDP_B2 S_CR
TR_B1_X TR_B2_X TR_D_X TR_B1_R TR_B2_R TR_D_R
represents transceiver
Handler
C/I0 Data
C/I1
21150_0 Microcontroller Interface
Data Sheet
Figure
2001-11-09
82902
Functional Description
2.3.2.1
Controller Data Access (CDA)
four controller data access registers (CDA10, CDA11, CDA20, CDA21) provide microcontroller access time slots more: looping four independent channels from vice versa over four registers shifting switching independent channels another independent channels both data ports (DU, DD). Between reading writing data manipulated (processed with algorithm) microcontroller. this case switching function performed. monitoring four time slots interface simultaneously microcontroller read write access each channel access principle, which identical channel register pairs CDA10/11 CDA20/21, illustrated Figure index variables used following description prefix 'CDA_' from register names been omitted simplification. each four CDAxy data registers TSDPxy register assigned which time slot data port determined. With (Time Slot Selection) bits time slot from 0.11 selected. With (Data Port Selection) output CDAxy register assigned respectively. time slot data port output CDAxy always defined TSDPxy register. input CDAxy depends SWAP control registers CRx. SWAP (swap disabled) time slot data port input output CDAxy register defined TSDPxy register. SWAP (swap enabled) input port time slot CDAx0 defined TSDP register CDAx1 input port time slot CDAx1 defined TSDP register CDAx0. input definition time slot data port CDAx0 thus swapped CDAx1 CDAx1 swapped CDAx0. output timeslots affected SWAP. input output every CDAxy register enabled disabled setting corresponding (-able) control register CDAx_CR. input register disabled output value register retained. Usually input output functional unit (transceiver, register) programmed timeslot (e.g. B-channel transmission upstream direction S-transceiver writes data onto U-transceiver reads data from monitoring data such cases register programmed described below under "Monitoring Data". Besides that none timeslots must assigned more than input output functional unit.
Data Sheet
2001-11-09
82902
Functional Description
Control Register CDA_CRx
Time Slot Selection (TSS)
Enable output (EN_O0) input (EN_I0) Input Swap (SWAP) input (EN_I1)
Enable output (EN_O1)
CDA_TSDPx0
Time Slot Selection (TSS)
CDAx0
CDAx1
Data Port Selection (DPS)
0.11
IOM_HAND.FM4
Figure
Data Access CDAx0 CDAx1 register pairs
Looping Shifting Data Figure gives examples typical configurations with above explained control configuration possibilities with bits TSS, DPS, SWAP registers TSDPxy CDAx_CR: looping time slot data from vice versa (SWAP '0') shifting data from both transmission directions (SWAP '1') switching data from looping from switching looping from programmed TSDP10, TSDP11, TSDP20 TSDP21.
Data Sheet
2001-11-09
Data Port Selection (DPS)
CDA_TSDPx1
82902
Functional Description
Looping Data
CDA10
CDA11
CDA20
CDA21
.TSS: .DPS .SWAP Shifting Data
CDA10
CDA11
CDA20
CDA21
.TSS: .DPS .SWAP Switching Data
CDA10
CDA11
CDA20
CDA21
.TSS: .DPS .SWAP Figure
Examples Data Access CDAxy Registers
Looping Data Shifting (Switching) Data Switching Looping Data
Data Sheet
2001-11-09
82902
Functional Description Figure shows timing looping from CDAxy register. read CDAxy register from written frame later Figure shows timing shifting data from DU(DD). Figure 15a) shifting done frame because didn't succeed directly another a+2). Figure 15b) shifting done from frame following frame. This case when time slots succeed other a+1) smaller than looping shifting data accessed controller between synchronous transfer interrupt (STI) status overflow interrupt (STOV). STOV explained section 'Synchronous Transfer'. there controller intervention looping shifting done autonomously.
CDAxy
STOV
access required
Figure
Data Access when Looping from
Data Sheet
2001-11-09
82902
Functional Description
Shifting within frame (a,b: 0.11 a+2)
(DD)
CDAxy
STOV
Shifting next frame (a,b: 0.11
(DD)
CDAxy
STOV
access required
Figure
Data Access when Shifting (DD)
Data Sheet
2001-11-09
82902
Functional Description Monitoring Data Figure gives example monitoring time slots each simultaneously. monitoring and/or channel registers with even numbers (CDA10, CDA20) assigned time slots with even numbers TS(2n) channel registers with numbers (CDA11, CDA21) assigned time slots with numbers TS(2n+1). user take care this restriction programming appropriate time slots. This mode only valid blocks (e.g. both transceivers) programmed these timeslots communicating However, only block programmed this timeslot timeslots CDAx0 CDAx1 programmed completely independently.
Monitoring Data EN_O: CDA_CR1. EN_I: DPS: TSS: TS(2n) TS(2n+1)
CDA10 CDA20
CDA11 CDA21
TSS: TS(2n) DPS: CDA_CR2. EN_I: EN_O:
TS(2n+1)
Figure
Example Monitoring Data
Monitoring Monitoring (TS11) handled special case. monitored with registers CDAx0 setting EN_TBM (Enable Monitoring) control registers CRx. TSDPx0 must monitoring from
Data Sheet
2001-11-09
82902
Functional Description monitoring from this possible monitor (TS11) numbered D-channel (TS3) simultaneously Synchronous Transfer While looping, shifting switching data accessed controller between synchronous transfer interrupt (STI) synchronous transfer overflow interrupt (STOV). microcontroller access each CDAxy registers synchronized means four programmable synchronous transfer interrupts (STIxy)1) synchronous transfer overflow interrupts (STOVxy)2) register. Depending corresponding TSDPxy register STIxy generated (for DPS='0') (for DPS='1') clock after selected time slot (CDA_TSDPxy.TSS). clock equivalent clocks. following description index used refer different interrupt pairs (STI/STOV) four interrupt pairs (STI10/STOV10, STI11/ STOV11, STI20/STOV20, STI21/STOV21). STOVxy0 related STIxy0 only generated STIxy0 enabled acknowledged. However, STIxy0 masked, STOVxy0 generated other STIxy1 which enabled acknowledged. Table gives some examples that. assumed that STOV interrupt only generated because interrupt acknowledged before. example only STIxy0 enabled thus STIxy0 only generated. enabled, interrupt will generated even STOV enabled (example example STIxy0 enabled generated corresponding STOVxy0 disabled. STIxy1 disabled STOVxy1 enabled, therefore STOVxy1 generated STIxy0. example additionally corresponding STOVxy0 enabled, STOVxy0 STOVxy1 both generated STIxy0. example additionally STIxy1 enabled with result that STOVxy0 only generated STIxy0 STOVxy1 only generated STIxy1. Compared previous example STOVxy0 disabled example STOVxy0 generated STOVxy1 only generated STIxy1 STIxy0.
order enable interrupts input corresponding register enabled. This also valid only synchronous write access wanted. enabling output alone does effect interrupt. order enable STOV interrupts output corresponding register enabled. This also valid only synchronous read access wanted. enabling input alone does effect interrupt.
Data Sheet
2001-11-09
82902
Functional Description
Table
Examples Synchronous Transfer Interrupts Enabled Interrupts (Register MSTI) Generated Interrupts (Register STI) STOV Example Example Example Example Example Example Example
STOV
Compared example example third STOVxy2 enabled thus STOVxy2 generated additionally both STIxy0 STIxy1. STOV interrupt generated stimulating interrupts acknowledged. STIxy must acknowledged setting ACKxy ASTI register clock (for DPS='0') clocks (for DPS='1') before time slot which selected appropriate STIxy. interrupt structure synchronous transfer shown Figure
Data Sheet
2001-11-09
82902
Functional Description
MASK Figure
ISTA
STOV21 STOV20 STOV11 STOV10 STI21 STI20 STI11 STI10 MSTI
STOV21 STOV20 STOV11 STOV10 STI21 STI20 STI11 STI10
ACK21 ACK20 ACK11 ACK10 ASTI
Interrupt Structure Synchronous Data Transfer
Figure shows some examples based timeslot structure. Figure shows which point time STOV interrupt generated specific timeslot. Figure identical example above, figure corresponds example figure shows example
Data Sheet
2001-11-09
82902
Functional Description
interrupt generated STOV interrupt generated acknowledged interrupt
Interrupts data access time slot after reset), MSTI.STI10 MSTI.STOV10 enabled CDA_TDSPxy.TSS: MSTI.STIxy: MSTI.STOVxy: TS11 TS10 TS11
TS11
Interrupts data access time slot after reset), STOV interrupt used flag "last possible access"; MSTI.STI10 MSTI.STOV20 enabled CDA_TDSPxy.TSS: MSTI.STIxy: MSTI.STOVxy: TS11 TS10 TS11
TS11
Interrupts data access time slot after reset), MSTI.STI10, MSTI.STOV10, MSTI.STI11 MSTI.STOV11 enabled CDA_TDSPxy.TSS: MSTI.STIxy: MSTI.STOVxy: TS11 TS10 TS11
TS11
Interrupts data access time slot after reset), STOV20 interrupt used flag "last possible access", STOV10 interrupt used flag "CDA access failed"; MSTI.STI10, MSTI.STOV10 MSTI.STOV20 enabled CDA_TDSPxy.TSS: MSTI.STIxy: MSTI.STOVxy: TS11 TS10 TS11
TS11
sti_stov.vsd
Figure
Examples Synchronous Transfer Interrupt Control with STIxy enabled
Data Sheet
2001-11-09
82902
Functional Description
2.3.2.2
Serial Data Strobe Signal
time slot oriented standard devices interface, provides independent data strobe signals SDS1 SDS2. strobe signals generated with every 8-kHz-frame controlled registers SDS1/2_CR. programming bits three enable bits (ENS_TSS, ENS_TSS+1, ENS_TSS+3) data strobe generated time slots TS+1 TS+3 (bit7,6) combinations them. data strobes TS+1 always bits long (bit7 bit0) whereas data strobe TS+3 always bits long (bit7, bit6).
DD,DU
MON0
MON1
TS10 TS11
SDS1,2 (Example1) SDS1,2 (Example2) SDS1,2 (Example3)
Example
ENS_TSS ENS_TSS+1 ENS_TSS+3 ENS_TSS ENS_TSS+1 ENS_TSS+3 ENS_TSS ENS_TSS+1 ENS_TSS+3
'0H' '5H' '0H'
Example
Example
strobe.vsd
Figure
Data Strobe Signal Generation
Data Sheet
2001-11-09
82902
Functional Description Figure shows three examples generation strobe signal. example active during channel whereas second example during MON1. third example shows strobe signal 2B+D channels which used e.g. IDSL (144 kbit/s) transmission.
2.3.3
Monitor Channel
MONITOR channel utilized information exchange between other devices MONITOR channel. MONTIOR channel data controlled bits MONITOR control register (MON_CR). transmission MONITOR data channels selected setting MONITOR channel selection bits (MCS) MONITOR control register (MON_CR). same register selects between output respectively with EN_MON MONITOR data enabled/disabled. default value MONITOR channel (MON0) enabled transmission MONITOR channel used following applications (refer also master device program control other devices (e.g. 2161) attached which therefore, need microcontroller interface. slave device programmed controlled from master device (e.g. UTAH). This used applications where microcontroller connected directly MONITOR channel operates according Reference Guide [12]. Note: contrast NTC-T, does neither issue react Monitor commands (MON0,1,2,8). Instead, operated slave mode must programmed MONITOR channel concept (see Chapter 2.3.3.4), which provides full register access. Monitor time procedure available. Reporting performed interrupts.
2.3.3.1
Handshake Procedure
MONITOR channel operates asynchronous basis. While data transfers take place synchronized frame sync, flow data controlled handshake procedure using MONITOR Channel Receive (MR) MONITOR Channel Transmit (MX) bits. Data placed onto MONITOR channel activated. This data will transmitted once 8-kHz frame until transfer acknowledged bit.
Data Sheet
2001-11-09
82902
Functional Description MONITOR channel protocol described following section Figure shall illustrate this. relevant control status bits transmission reception listed Table Table Table Control/ Status Control Status Transmit Direction Register MOCR MOSR MSTA Table Control/ Status Control Status Function Control Transmit Interrupt (MDA, MAB, MER) Enable Data Acknowledged Data Abort Transmission Active
Receive Direction Register MOCR MOSR Function Control Receive Interrupt (MDR) Enable Data Received Reception
Data Sheet
2001-11-09
82902
Functional Description
Transmitter
Receiver
ITD10032
Int. DATA1
DATA1 DATA1 DATA1 DATA1 DATA2 DATA2 DATA2 DATA2
Int. (=ADR)
Int. (=DATA1)
Int. DATA2
Int. (=DATA2)
Int.
Int.
Figure
MONITOR Channel Protocol (IOM®-2)
Before starting transmission, microprocessor should verify that transmitter inactive, i.e. that possible previous transmission been terminated. This indicated MONITOR Channel Active status bit. After having written MONITOR Data Transmit (MOX) register, microprocessor sets MONITOR Transmit Control '1'. This enables active (0), indicating presence valid MONITOR data (contents MOX) corresponding frame. result, receiving device stores MONITOR byte MONITOR Receive register generates interrupt status. Alerted interrupt, microprocessor reads MONITOR Receive (MOR) register. When ready accept data (e.g. based value MOR, which point-to-multipoint application might address destination device), sets control enable receiver store succeeding MONITOR channel bytes acknowledge them according MONITOR channel protocol. addition,
Data Sheet
2001-11-09
82902
Functional Description enables other MONITOR channel interrupts setting MONITOR Interrupt Enable (MIE) '1'. result, first MONITOR byte acknowledged receiving device setting '0'. This causes MONITOR Data Acknowledge interrupt status transmitter. MONITOR data byte written microprocessor MOX. still active state. transmitter indicates byte MONITOR channel returning active after sending once inactive state. result, receiver stores MONITOR byte generates interrupt status. When microprocessor read register, receiver acknowledges data returning active after sending once inactive state. This turn causes transmitter generate interrupt status. This "MDA interrupt write data interrupt read data interrupt" handshake repeated long transmitter data send. Note that MONITOR channel protocol imposes maximum reaction times microprocessor. When last byte been acknowledged receiver (MDA interrupt status), microprocessor sets MONITOR Transmit Control '0'. This enforces inactive ('1') state bit. frames inactive signifies message. Thus, MONITOR Channel Reception interrupt status generated receiver when received inactive state consecutive frames. result, microprocessor sets control which turn enforces inactive state bit. This marks transmission, making MONITOR Channel Active return '0'. During transmission process, possible receiver transmission aborted sending inactive value consecutive frames. This effected microprocessor writing control '0'. aborted transmission indicated MONITOR Channel Data Abort interrupt status transmitter. MONITOR transfer protocol rules summarized following section pair inactive state more consecutive frames indicates idle state transmission. start transmission initiated transmitter setting enabling internal control. receiver acknowledges received first byte setting control enabling internal control. internal control indicates acknowledges byte slot toggling from active inactive state frame. frames with MR-bit inactive indicate receiver request abort. transmitter delay transmission sequence sending same byte continuously. that case MX-bit remains active frame following first byte occurrence. Delaying transmission sequence only possible while receiver MR-bit transmitter MX-bit active.
Data Sheet
2001-11-09
82902
Functional Description Since double last-look criterion implemented receiver able receive slot data least twice consecutive frames), receiver waits acknowledge reception identical bytes successive frames. control this handshake procedure collision detection mechanism implemented transmitter. This done making collision check transmitted MONITOR data bit. Monitor data will transmitted repeatedly until reception acknowledged transmission time-out timer expires. frames with inactive state indicates message (EOM). Transmission reception monitor messages performed simultaneously. This feature used device send back response before transmission from controller completed (the device does wait from controller).
2.3.3.2
Error Treatment
case device does detect identical monitor messages successive frames, transmission aborted. Instead device will wait until identical bytes received succession. transmission aborted device error handshaking occurs collision MONITOR data occurs transmission time-out timer expires reception aborted device error handshaking occurs abort request from opposite device occurs MX/MR Treatment Error Case master mode MX/MR bits under control microcontroller through MRC, respectively. abort indicated interrupt interrupt, respectively. slave mode MX/MR bits under control device. abort always indicated setting MX/MR inactive more frames. controller must react with EOM. Figure shows example abort requested receiver, Figure shows example abort requested transmitter Figure shows example successful transmission.
Data Sheet
2001-11-09
82902
Functional Description
Frame (DU) (DD)
Abort Request from Receiver
mon_rec-abort.vsd
Figure
Monitor Channel, Transmission Abort requested Receiver
Frame (DU) (DD)
Abort Request from Transmitter
mon_tx-abort.vsd
Figure
Monitor Channel, Transmission Abort requested Transmitter
Frame (DU) (DD)
mon_norm.vsd
Figure
Data Sheet
Monitor Channel, Normal Transmission
2001-11-09
82902
Functional Description
2.3.3.3
MONITOR Channel Programming Master Device
master mode selected default microcontroller interfaces selected. monitor data written microcontroller register transmitted DD(DU) line programmed/controlled device e.g. ARCOFIBA 2161. transfer commands channel regulated handshake protocol mechanism with
2.3.3.4
MONITOR Channel Programming Slave Device
MONITOR slave mode selected pinstrapping microcontroller interface pins according Table programming data required device received MONITOR time slot transferred register. transfer commands channel regulated handshake protocol mechanism with which described previous Chapter 2.3.3.1. first byte MONITOR message must contain higher nibble MONITOR channel address code which '1000' lower nibble distinguishes between programming command identification command. Identification Command order able identify unambiguously different hardware designs software, following identification command used: byte value byte value
responds this identification sequence sending identification sequence: byte value byte value <IDENT>
DESIGN
DESIGN: code, specific each device order identify differences operation (see Identification Register" Page 139). This identification sequence usually done once, when connected first time. This function used that software distinguish between different possible hardware configurations. However this sequence compulsory. Programming Sequence programming sequence characterized being sent lower nibble received address code. data structure after this first byte equivalent structure serial control interface described chapter Chapter 2.1.1.
Data Sheet 2001-11-09
82902
Functional Description
byte value byte value byte value byte value (nth byte value
Header Byte Command/ Register Address Data Data
registers read back when setting '1'. responds sending specific address byte (81h) followed requested data. Note: Application Hint: allowed disable MR-control programming device same time! First, MX-control must disabled, then wait Reception before MR-control disabled. Otherwise, does recognize Reception.
2.3.3.5
Monitor Time-Out Procedure
prevent lock-up situations MONITOR transmission time-out procedure enabled setting time-out (TOUT) MONITOR configuration register (MCONF). internal timer always started when transmitter must wait reply addressed device transmit data from microcontroller. After frames without reply timer expires transmission will aborted with (End Message) command setting consecutive frames.
2.3.3.6
MONITOR Interrupt Logic
Figure shows interrupt structure MONITOR handler. MONITOR Data Receive interrupt status enable bits, MONITOR Receive interrupt Enable (MRE) Control (MRC). MONITOR channel Reception MER, MONITOR channel Data Acknowledged MONITOR channel Data Abort interrupt status bits have common enable MONITOR Interrupt Enable MIE. prevents occurrence status, including when first byte packet received. When "0", interrupt status generated only first byte receive packet. When both "1", always generated received MONITOR bytes marked 1-to-0 transition stored. Additionally, enables control handshake according MONITOR channel protocol.
Data Sheet
2001-11-09
82902
Functional Description
MASK
ISTA MOCR MOSR
Figure
MONITOR Interrupt Structure
2.3.4
Channel Handling
Command/Indication channel carries real-time status information between another device connected C/I0 channel lies channel access arbitrated access protocol. this case arbitration done channel C/I0 channel accessed register CIR0 (received C/I0 data from register CIX0 (transmitted C/I0 data DU). C/I0 code four bits long. receive direction, code from layer-1 continuously monitored, with interrupt being generated time change occurs (ISTA.CIC). C/I0 only: code must found consecutive frames considered valid trigger code change interrupt status (double last look criterion). transmit direction, code written CIX0 continuously transmitted C/I0. second channel (called C/I1) lies channel used convey real time status information on-chip S-transceiver external device. C/I1 channel consists four bits each direction. width changed from setting CIX1.CICW.
Data Sheet
2001-11-09
82902
Functional Description 4-bit mode 6-bits written whereby higher bits must 6-bits read whereby only LSBs used comparison interrupt generation (i.e. higher bits ignored). C/I1 channel accessed registers CIR1 CIX1. connection CIR1 CIX1 respectively, selected setting CI_CR.DPS_CI1. change received C/I1 code indicated interrupt status without double last look criterion. Interrupt Logic Figure shows interrupt structure. corresponding status bits CIC0 CIC1 read CIR0 register. CIC1 individually disabled clearing enable CI1E CIX1 register. this case occurrence code change CIR1 will displayed CIC1 until corresponding enable been one. Bits CIC0 CIC1 cleared read CIR0. interrupt status indicated every time valid code loaded CIR0 CIR1. CIR0 buffered with FIFO size two. second code change occurs received channel before first been read, immediately after reading CIR0 interrupt will generated code will stored CIR0. several consecutive codes detected, only first last code obtained first second register read, respectively. CIR1 FIFO available. actual code received channel always stored CIR1.
MASK
ISTA
CI1E CIX1
CIC0 CIC1 CIR0
Figure Interrupt Structure
Data Sheet
2001-11-09
82902
Functional Description
2.3.5
D-Channel Access Control
upstream D-channel arbitrated between S-bus external HDLC controllers (S/G, BAC, bits) according Reference Guide1). Further implementation INTC-Q possible, priority HDLC-controllers connected which particularly useful together with UTAH.
2.3.5.1
Application Examples D-Channel Access Control
Figure Figure show different scenarios local D-channel arbitration between S-bus microcontroller.
E-Bit
Arbitr.
Prio
IOM-2
access BAC-Bit S/G-bit IOM-2. generally required only local D-channel source.
HDLC HDLC HDLC HDLC
e.g. UTAH; MPC860
IOM-2
Figure
D-Channel Arbitration: with HDLC Direct Access
A/B-bit supported U-transceiver
Data Sheet
2001-11-09
82902
Functional Description
E-Bit
Arbitr.
Prio
CIX0 CIR0
Channel Handler
IOM-2
HDLC HDLC HDLC HDLC
IOM-2
e.g. MC68302
access BAC, TBA-Bit S/G-bit TIC-Bus Handler must poll until S/G=0, then transmit D-channel
Figure
D-Channel Arbitration: with HDLC Access
2.3.5.2
Handling
implemented organize access C/I0-channel Dchannel from D-channels HDLC controllers. arbitration mechanism must activated setting MODEH.DIM2-0=00x. arbitration mechanism implemented last octet channel interface (see Figure 28). access request either generated software access C/I0-channel CIX0 register) external D-channel HDLC controller (transmission HDLC frame D-channel). software access request effected setting register CIX0 (resulting case access request Accessed-bit (bit last octet Figure checked status "bus free", which indicated logical '1'. free, transmits individual address programmed CIX0 register (CIX0.TBA2-0). While being transmitted address compared with value read back sent read back because access external device with lower TAD, withdraws immediately from bus, i.e. remaining bits transmitted. occupied device which sends reads back address error-free. more than device attempt seize simultaneously, with lowest address values wins. This will BAC=0 starts D-channel transmission same frame.
Data Sheet 2001-11-09
82902
Functional Description
MON1
MON0
ITD02575.vsd
TIC-BUS Address (TAD Accessed ("1" TIC-BUS Access)
Figure
Structure Last Octet
When seized identified other devices occupied Accessed-bit state until access request withdrawn. After successful access, automatically into lower priority class, that access cannot performed until status "bus free" indicated successive frames. none devices connected interface request access channels, address will present. device with this address will therefore have access, default, C/I0 channels. Note: (CIX0 register) should reset when access more requested, grant other devices access C/I0 channels.
2.3.5.3
Stop/Go Handling
availability channel indicated "Stop/Go" (S/G) last octet channel (Figure 29). arbitration mechanism must activated setting MODEH.DIM2-0=0x1. stop Stop/Go available other layer-2 devices connected interface determine they access channel upstream direction.
Data Sheet
2001-11-09
82902
Functional Description
MON1
Stop/Go
Available/Blocked
ITD09693.vsd
Figure
Structure Last Octet
2.3.5.4
D-Channel Arbitration
intelligent applications (selected register S_MODE.MODE2-0) share upstream D-channel with more D-channel controllers interface with connected interface. S-transceiver incorporates elaborate state machine D-channel priority handling (Chapter 2.3.5.5). access D-channel similar arbitration mechanism interface (writing D-bits, reading back E-bits) performed D-channel sources this equal fair access guaranteed D-channel sources both interface interface. access upstream D-channel handled HDLC controllers E-bit connected terminals (E-bits inverted block terminals Furthermore, more than HDLC source requesting D-channel access mechanism used (see Chapter 2.3.5.2). arbiter permanently counts "1s" upstream D-channel necessary number "1s" counted HDLC controller requests upstream D-channel access (BAC arbiter allows this D-channel controller immediate access blocks other (E-bits inverted). Similar S-interface priority D-channel access configured (S_CMD.DPRIO). configuration settings intelligent applications summarized Table
Data Sheet
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Functional Description
Table
Configuration Settings Intelligent Applications Configuration Setting S-Transceiver Mode Register: S_MODE.MODE0 state machine) S_MODE.MODE0 (LT-S state machine) S_MODE.MODE1 S_MODE.MODE2
Functional Configuration Block Description Layer Select Intelligent mode
Layer
Enable evaluation
D-channel Mode Register: MODEH.DIM2-0
Note: mode selection S_MODE register MODE1/2 bits used select intelligent mode, MODE0 selects LT-S state machine. With configuration settings shown above intelligent applications provides equal access D-channel terminals connected S-interface D-channel sources
2.3.5.5
State Machine D-Channel Arbiter
Figure gives simplified view state machine D-channel arbiter. number D-channel corresponds BAC-bit number depends configuration settings (selected priority condition previous transmission, i.e. abort seen respectively) last transmission successful respectively).
Data Sheet
2001-11-09
82902
Functional Description
RST=0, A/B=0, Mode=0xx
State
(CNT D=0) [BAC (BAC READY 1)2)
(BAC=1 DCI=0) d.c. ACCESS (BAC=0 DCI=1)
d.c. d.c. LOCAL ACCESS Transmit Stop Flag
Setting causes Setting causes
D-Channel_Arbitration.vsd
LOCAL ACCESS Wait Start Flag
Figure
State Machine D-Channel Arbiter (Simplified View)1)
Local D-Channel Controller Transmits Upstream initial state ('Ready' state) neither local D-channel sources terminals connected S-bus transmit D-channel. S-transceiver thus receives line) transmits line). access will then established according following procedure: Local D-channel source verifies that (currently access). Local D-channel source issues address verifies that controller with higher priority requests transmission (TIC access must always performed even other D-channel sources connected Local D-channel source issues block other sources announce D-channel access. S-transceiver pulls ZERO ('Local Access' state) soon (see note) allow sending D-channel data from entitled source.
S-transceiver reset SRES.RES_S disabled S_CONF0.DIS_TR '1', then D-channel arbiter state Ready (S/G '1'), too. evaluation HDLC disabled this case; otherwise, HDLC able send data.
Data Sheet
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Functional Description S-transceiver transmits inverted echo channel bits) S-bus block connected S-bus terminals Local D-channel source commences with data transmission long receives "0". After D-channel data transmission completed controller sets ONE. S-transceiver transmits non-inverted echo S-transceiver pulls ('Ready' state) block D-channel controller
Note: right after D-data transmission D-channel arbiter goes state 'Ready' local D-channel source wants transmit again, then happen that leading start flag written into D-channel before D-channel source recognizes that pulled stops transmission. order prevent unintended transitions state 'S-Access', additional condition introduced. soon D-channel source start transmission again occupied). This allows equal access D-channel sources interface. Terminal Transmits D-Channel Data Upstream initial state identical that described last paragraph. When connected S-bus terminals needs transmit D-channel, access established according following procedure: S-transceiver recognizes that D-channel S-bus active '0'. S-transceiver transfers S-bus D-channel data transparently through upstream bus.
2.3.6
Activation/Deactivation IOM®-2 Interface
deactivation procedure interface shown Figure After detecting code (Deactivation Indication) responds transmitting (Deactivation Confirmation) during subsequent frames stops timing signals after fourth frame. clocks stop C/I-code channel
Data Sheet
2001-11-09
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Functional Description
DOUT
Interface deactivated
Detail Fig.b
Interface deactivated
ITD10292
Figure
Deactivation IOM®-2 Clocks
Conditions Power-Down none following conditions true, interface switched off, reducing power consumption minimum. S-transceiver state 'Deactivated' Signal INFO0 S-interface Uk0-transceiver state 'Deactivated' (either interface IOM_CR.SPU) External External Awake MODE 1.CFS Stop correct place frame. must during power down (stop falling edge DCL) (see Figure 31).
deactivated reactivated following methods: Pulling line low: directly interface interface with "Software Power (IOM_CR:SPU bit) Pulling `External Awake` Setting `Configuration Select` MODE1:CFS Level detection S-interface
Data Sheet 2001-11-09
82902
Functional Description Activation from U-interface
U-Transceiver
statemachine U-Transceiver compatible state machine 8090 documentation [9], includes some minor changes simplification compliance Ref. [1]. U-transceiver configured controlled registers described Chapter U-transceiver always channel
2.4.1
4B3T Frame Structure
4B3T U-interface performs full duplex data transmission reception Ureference point according ETSI 220. applies 4B3T block code together with adaptive echo cancelling equalization. Transmission performance shall such, that meets ETSI test loops with margin. U-interface designed data transmission twisted pair wires local telephone loops, with basic access ISDN user rate kbit/s. following information transmitted over twisted pair: Bidirectional: data channels Symbol clock Frame Activation kbit/s Transparent Channel symbol), (not implemented) From side: Power feeding Deactivation Remote control test loops symbol) From side: Indication monitored code violations symbol) Performance Requirements according (August 1991): U-interface, following transmission ranges achieved without additional signal regeneration loop (bit error rate 10-7): with noise: wires diameter wires without noise: wires diameter wires Note: Typical attenuation wires diameter about 7dB/km contrast ETSI wires with about 8dB/km. transmission ranges doubled inserting repeater signal regeneration.
Data Sheet
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Functional Description Performance requirements according ETSI met, too. frames transmitted U-interface, each consisting symbols: scrambled coded data symbols: Barker code both symbol frame synchronization (not scrambled) symbol: Ternary maintenance symbol (not scrambled) user data symbols split into four equally structured groups. Each group ternary symbols, resp. bits) contains user data IOM®-2 frames same order 2D). Different syncwords used each direction: Downstream from Upstream from +++---+--+- -+--+---+++
side, transmitted Barker code begins symbols after received Barker code vice versa. Ternary data IOM®-2 frames Maintenance symbol Syncword
Data Sheet
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Functional Description Table D1/2 D7/8 D1/2 Frame Structure Downstream Transmission D1/2 D3/4 D3/4 D3/4 D5/6 D5/6 D5/6 D7/8 D7/8
Data Sheet
2001-11-09
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Functional Description
Table U1/2 U1/2
Frame Structure Upstream Transmission U1/2 U3/4 U3/4 U3/4 U5/6 U5/6 U5/6 U7/8 U7/8 U7/8
Ternary data IOM®-2 frames Maintenance symbol Syncword
Data Sheet
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Functional Description
2.4.2
Maintenance Channel
4B3T frame structure provides kbit/s M(aintenance)-channel transfer remote loopback commands error indications. Loopback Commands station uses M-channel request remote loopbacks. Loopback commands coded with series symbols. continuous series requests loopback activation continuous series requests deactivation loopback station reacts soon pattern been detected consecutive symbols. Error Indications U-transceiver reports line code violations M-channel exchange setting M-Bit polarity. Transparent Messages exchange Transparent Messages Transparent Channel supported
2.4.3
Coding from Binary Ternary Data
Each block binary data coded into ternary symbols block code according Table number next column used, given right hand side each block. left hand signal elements table (both ternary binary) transmitted first.
Table
Coding Table
Data Sheet
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Functional Description Table Coding Table
2.4.4
Decoding from Ternary Binary Data
Decoding done reverse manner coding. received blocks ternary symbols converted into blocks bits. decoding algorithm given Table encoding table, left hand symbol each block (both binary ternary) first right hand last. ternary block received, decoded binary This pattern usually occurs only during deactivation.
Table
Data Sheet
4B3T Decoding Table Ternary Block
Binary Block
2001-11-09
82902
Functional Description Table 4B3T Decoding Table
2.4.4.1
Monitoring Code Violations
running digital monitor (RDSM) computes running digital from received ternary symbols adding polarity received user data -1). each block, running digital supposed reflect number next column Table code violation occurred running digital less than more than four ternary block, ternary block (three user symbols with zero polarity) found received data. ternary block error found, running digital retains current value. counter value greater than beginning next ternary block, value less, one. after code violation been detected, RDSM synchronizes itself within period depending received data pattern. Note there some transmission errors which cause code violation.
2.4.4.2
Block Error Counter (RDS Error Counter)
provides block error counter. This feature allows monitoring transmission quality U-interface. side block error given, U-frame with least code violation been detected (near-end block error). following frame transmits positive M-symbol upstream. side block error given, U-frame with least code violation been detected (near-end block error) positive M-symbol been received from (far-end block error). current status block error counter retrieved system interface. When block error counter read (register RDS), automatically reset. counter enabled states listed Table reset other states. counter saturated maximum value (255). Table Active States Sychronizing Wait INFO Transparent
Data Sheet
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Functional Description Note that every frame with detected code violation causes about binary errors average. error rate 10-7 both directions equivalent detected frame errors within 1000 frame error detected transmitted M-symbol).
2.4.5
Scrambler
Scrambler Descrambler
binary transmit data from IOM®-2 interface scrambled with polynomial bits, before sent 4B3T coder. scrambler polynomial is:: Descrambler received data (after decoding from ternary binary) multiplied with polynomial bits order recover original data before forwarded IOM®-2 interface.The descrambler self synchronized after symbols. descrambler polynomial is::
scrambling descrambling process controlled fully Hence, influence taken user.
2.4.6
Command/Indication Codes
Both commands indications depend data direction. Table presents defined codes. command indication will recognized valid after been detected successive IOM®-2 frames (double last-look criterion). Note: Unconditional C/I-commands must applied least IOM®-2 frames reliable recognition U-transceiver. Indications strictly state orientated. Refer state diagrams following sections commands indications applicable various states. Table Code 0000 0001 0010 Codes
Data Sheet
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Functional Description 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
reserved1)
code `1010` must input U-transceiver.
Activation Indication Activation Indication Loop Activation Request Activation Request Local Loop Data Through Mode Deactivation Confirmation
Deactivation Indication. Deactivation Request Disable Reset Resynchronization Indication Send-Single-Pulses Timing Request
2.4.7 2.4.7.1
State Machine Activation Deactivation State Machine Notation
following state diagram describes actions/reactions resulting from command detected signal resulting from various operating modes. states with inputs outputs interpreted shown below:
Data Sheet
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Functional Description
Transmitted U-Signal State Name Channel Indication (DOUT)
SM_expl.emf
Figure
State Diagram Example
Each state more transitions other states. These transitions depend certain conditions which noted next transition lines. These conditions only possibility leave state. more conditions have fulfilled together, they into parentheses with operator (&). more than condition leads same transition, they into parentheses with operator (|). meaning condition inverted operator (/). Only described states transitions exist. some transitions, internal timer started. start timer indicated ('x' timer number). Transitions that caused timer expired labelled TxE. Some conditions lead same target state. reduce number lines complexity figures, state named "ANY STATE" acts behalf state. state machines designed cope with ISDN devices with IOM®-2 standard interfaces. Undefined situations excluded. case, involved devices will enter defined conditions soon line deactivated.
2.4.7.2
Awake Protocol
awake process signals defined' U1W' 'U2W'. Depending call direction (up-, downstream) interpreted awake acknowledge signals (see figures below).
Data Sheet
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Functional Description
INFO 2.133 INFO
INFO 2.133
ITD06385.vsd
INFO
Figure
Awake Procedure initiated
INFO 2.133 INFO
INFO 2.133 INFO
ITD06386.v
Figure
Awake Procedure initiated
Acting Calling Station After sending awake signal, awaking U-transceiver waits acknowledge. After awake signal repeated, acknowledge been recognized. acknowledge signal been recognized, U-transceiver waits possible repetition case previous coincidence awake signals). repetition detected, U-transceiver starts transmitting with delay such repetition detected, U-transceiver interprets awake signal behaves like device awoken end.
Data Sheet
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Functional Description Acknowledging Wake-Up Call deactivated device detects awake signal acknowledge signal sent out. After that, U-transceiver waits possible repetition awake signal case acknowledge hasn't been recognized). repetition found, awoken U-transceiver starts sending after from detecting awake signal. repeated awake signal found, procedure awoken U-transceiver starts again.
Data Sheet
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Functional Description
2.4.7.3
State Machine (IEC-T NTC-T Compatible)
Awaked Start Awaking Awake Signal Sent T13S T13E Ack. Sent Received T05E) T12S Synchronizing T05S Synchronizing T12E) T05S Pend. Deactivation Test STATE Reset T13S Sending Awake-Ack. T13S T05S T05S T05E Deactivating Deactivated
Wait Info
Transparent Loss Framing
NT_SM_4B3T_cust.emf
Figure
State Machine (IEC-T/NTC-T Compatible)
Note: test modes `Data Through` (DT) `Send Single Pulses` (SSP) invoked codes 'DT' 'SSP' according Table Setting SRES.RES_U forces U-transceiver into test mode `Quiet Mode` (QM), i.e. U-transceiver hardware reset.
Data Sheet 2001-11-09
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Functional Description
Table
Differences former NT-SM IEC-T/NTC-T Change Comment simplifies implementation
State/ Signal
State 'Deact. split into states Request Rec.' 'Pend. Deactivation 'Reset' State 'Test' State State 'Loss Framing' inserted, results different behavior state 'Transparent', return normal transmission possible after detection inserted renamed state 'Deactivated' renamed state 'Transparent' Name Duration
compliance ETSI 080, corresponds state NT1.10
C/I-code State 'Power Down' State 'Data Transmission' Timer variables introduced
consistency reasons 2B1Q
Table
2.4.7.4
Inputs U-Transceiver
C/I-Commands Activation Indication downstream device issues this indication announce that layer available. U-transceiver turn informs side transmitting Activation Request U-transceiver requested start activation process already done) sending wake-up signal U1W. Deactivation Indication This indication used during deactivation procedure inform Utransceiver that enter 'Deactivated' (power-down) state. Data Through Test Mode This unconditional command used test purposes only forces Utransceiver into state 'Transparent'.
Data Sheet
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Functional Description Disable This unconditional command forces U-transceiver state 'Test', where transmits further action initiated. Reset Unconditional command which resets U-transceiver. Send Single Pulses Unconditional command which requests transmission single pulses U-interface. Timing U-transceiver requested enter state 'IOM Awaked'.
U-Interface Events detected recognized after symbols (1ms) with zero level row. Detection last detected U-transceiver detects continuous binary found after descrambling least subsequent U-frames. detected after detected recognized, U-transceiver detects subsequent binary after descrambling. Awake signal (U2W) detected Awake signal (U1W) been sent Loss Framing U-interface Timer ended, started timer expired
Timers
start timers indicated TxS, expiry TxE. following table shows which timers used.
Table Timer
Timers Duration (ms) Function code recognition Supervises repetition State Pend. Deactivation, Deactivating Start Awaking
Data Sheet
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Functional Description Table Timer Timers (cont'd) Duration (ms) Function Prevents U-transceiver state Synchronizing from immediate transition state 'Pend. Deactivation' detected Supervises repetition State Synchronizing
Ack. sent received Sending awake-ack.
2.4.7.5
Outputs U-Transceiver
Below signals indications summarized that issued IOM®-2 (C/I indications) U-interface (predefined U-signals). Indications Activation Indication U-transceiver established transparency transmission. downstream device requested establish layer-1 functionality. Activation Indication Loop-back U-transceiver established transparency transmission. downstream device requested establish loopback Activation Request downstream device requested start activation procedure. Activation Request Loop-back U-transceiver detected loop-back command M-channel established transparency transmission direction IOM® Uinterface. downstream device requested start activation procedure establish loopback Deactivation Confirmation Idle code IOM®-2 interface. Deactivation Request U-transceiver detected deactivation request command from LTside complete deactivation. downstream device requested start deactivation procedure. Resynchronizing Indication informs downstream device that U-transceiver synchronous.
Data Sheet
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Functional Description Signals U-Interface signals U1W, U1A, transmitted U-interface.They defined Table Signals IOM®-2 Data (B+B+D) '1's states besides states listed Table Dependence Outputs M-symbol output states with valid M-symbol output value according Table
Table Error
Symbol Output detected detected
Symbol Output
Table Input
Signal Output State Test C/I-Code applied other except C/I-Code 'DI'
Signal Output
Table
C/I-Code Output Synchronizing Wait Info Transparent
Loopback Command received received
2.4.7.6
NT-States
this section each state described with function. Acknowledge Sent Receive After having sent awake signal, U-transceiver received acknowledge wake tone. being awoken U-transceiver sent acknowledge. both cases U-transceiver waits possible repetition time-out.
Data Sheet
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Functional Description Awake Signal Sent sent awake signal waits response. does react time timer expires repeats wake-up call. Deactivated Only "Deactivated" state device enter power-down mode. Deactivating State Deactivating assures that C/I-channel code issued four times before entering 'Deactivated' state. IOM® Awaked U-transceiver deactivated, enter power-down mode. Loss Framing This state entered loss framing (LOF). signal transmitted U-interface. receiver-reset performed Note that there return 'Transparent' state that been possible before former IEC-T based state machine. Pending Deactivation U-transceiver received U-transceiver remains least 0.5ms this state before accepts Synchronizing synchronized indicates this AR/ARL towards downstream device. waits acknowledge 'AI' from downstream device. Sending Awake-Ack. receipt awake signal U-transceiver responds with transmission U1W. Start Awaking receipt C/I-channel U-transceiver sends awake signal start activation.
Data Sheet
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Functional Description Synchronizing After successful awake procedure U-transceiver trains receiver coefficients until able detect signals Reset state 'Reset' software-reset performed. Test State "Test" entered when unconditional commands C/I=SSP applied. test signal issued long active C/I=SSP applied. Transparent transmission line fully activated. User data transparently exchanged U4/U5. Transparent state entered case loopback downstream device informed code that transparent state been reached Note that contrast former IEC-T state machine there resynchronization mechanism. Once loss framing (LOF) been detected deactivation initiated. Wait Info synchronized waits permission (U4H) 'Transparent' state.
2.4.8
U-Transceiver Interrupt Structure
U-Interrupt Status register (ISTAU) contains interrupt sources UTransceiver (Figure 36). Each source masked setting corresponding U-Interrupt Mask register (MASKU) '1'. Such masked interrupt status bits indicated when ISTAU read generate interrupt request. ISTAU register cleared read access. interrupt sources ISTAU register (UCIR, RDS, 1ms) need evaluated. When time interrupt source generates interrupt, further interrupts collected. Reading ISTAU register clears interrupts before even masked. interrupts, which flagged after remain active. After ISTAU read access, next unmasked interrupt will generate next interrupt time After possible reprogram MASKU register, that interrupts, which arrived between accessible.
Data Sheet
2001-11-09
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Functional Description
UCIR
ISTAU
MASKU
ISTA
MASK
intstruct_4b3t.emf
Figure
Interrupt Structure U-Transceiver
Data Sheet
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Functional Description
S-Transceiver
S-Transceiver offers LT-S mode state machines described User's Manual V3.4 [8]. S-transceiver lies channel (default) configured controlled registers described Chapter 4.5. state machine mode (default) LT-S mode register programming. mode (S-transceiver mode, U-transceiver disabled) supported.
2.5.1
Line Coding, Frame Structure
Line Coding following figure illustrates line code. binary represented line signal. Binary ZEROs coded with alternating positive negative pulses with exceptions: required frame structure code violation indicated consecutive pulses same polarity. These pulses adjacent separated binary ONEs. configurations binary ZERO always overwrites binary ONE.
code violation
Figure
-Interface Line Code
Frame Structure Each frame consists bits nominal rate kbit/s. user data (B1+B2+D) frame structure applies data rate kbit/s (see Figure 37). direction frame transmitted with offset. details framing rules please refer I.430 section 6.3. following figure illustrates standard frame structure both directions with framing maintenance bits.
Data Sheet
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Functional Description
Figure
Frame Structure Reference Points (ITU I.430) Framing D.C. Balancing D-Channel Data D-Channel Echo Auxiliary Framing B1-Channel Data B2-Channel Data Activation S-Channel Data Multiframing (0b) identifies frame (always positive pulse, always code violation) (0b) number binary ZEROs sent after last Signaling data specified user received E-bit equal transmitted D-bit section I.430 User data User data (0b) INFO transmitted (1b) INFO transmitted channel data (see note below) (1b) Start multi-frame
Note: I.430 standard specifies optional use.
Data Sheet
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Functional Description
2.5.2
Channels, Multiframing
According recommendation I.430 multi-frame provides extra layer-1 capacity TE-to-NT direction through extra channel between (Qchannel). bits defined bits position. NT-to-TE direction S-channel bits used information transmission. Q-channels accessed reading/writing bits channel registers (SQRR, SQXR). Table shows positions within multi-frame. Table S/Q-Bit Position Identification Multi-Frame Structure NT-to-TE NT-to-TE Position ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO NT-to-TE TE-to-NT Position ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO
Frame Number
S-transceiver starts multiframing SQXR1.MFEN set. After multi-frame synchronization been established data will inserted upstream position each frame,
Data Sheet
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Functional Description data will inserted downstream position each frame (see Table 24). Access S2-S5-channel supported. Interrupt Handling Multi-Framing trigger microcontroller multi-frame access interrupt generated once multi-frame (SQW) received Q-channel have changed (SQC). both cases microcontroller access multiframe within duration multiframe ms). start multiframe synchronized external signal.
2.5.3
Data Transfer between
state (Activated) internal layer-1 statemachine disabled XINF register S_CMD programmed '011' bits transferred transparently from interface vice versa. other states '1's transmitted interface. Note: intelligent intelligent LT-S mode D-channel access blocked D-channel handler.
2.5.4
Loopback
commands close analog loop close S-interface possible. ETSI refers this loop under 'loopback ETSI requires, that channels have same propagation delay when being looped back. D-channel Echo bin. during analog loopback (i.e. loopback loop transparent. Note: After C/I-code been recognized S-transceiver, zeros looped back D-channels (DU) four frames.
2.5.5
Control S-Transceiver State Machine
S-transceiver activation/ deactivation controlled internal statemachine C/I-channel software interface directly. default state internal layer-1 statemachine S-transceiver used. setting L1SW S_CONF0 register internal statemachine disabled layer-1 transmit commands, which normally generated internal statemachine written directly into S_CMD register received status read from S_STA register, respectively. S-transceiver layer-1 control flow shown Figure
Data Sheet
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Functional Description
Disable internal Statemachine (S_CONF.L1SW)
Command
IOM-2
Indication
Layer-1 State Machine
Transmit Command Register INFO Transmitter Transmitter (S_CMD) Receive Status Register INFO Receiver Receiver (S_STA)
Layer-1 Control
C-Interface
macro_14
Figure
S-Transceiver Control
state diagram notation given Figure information contained state diagrams are: state name Signal received from line interface (INFO) Signal transmitted line interface (INFO) code received (commands) code transmitted (indications) transition criteria
transition criteria grouped into: commands Signals received from line interface (INFOs) Reset
Data Sheet
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Functional Description
IOM-2 Interface code
Ind. Cmd. tate
Unconditional Transition
Interface INFO
macro_17.vsd
Figure
State Diagram Notation
seen from transition criteria, combinations multiple conditions possible well. stands logical combination. indicates logical combination. Test Signals Single Pulses (TM1) pulse with width period frame with alternating polarity. Continuous Pulses (TM2) Continuous pulses with pulse width period. Note: test signals invoked codes `TM1` `TM2` according Chapter 2.5.5.1. External Layer-1 Statemachine Instead using integrated layer-1 statemachine also possible implement layer-1 statemachine completely software. internal layer-1 statemachine disabled setting L1SW S_CONF0 register '1'. transmitter completely under control microcontroller register S_CMD. status receiver stored register S_STA evaluated microcontroller. This register updated continuously. masked interrupt generated change register contents. interrupt cleared after read access this register. Reset States After active signal reset S-transceiver state machine reset state.
Data Sheet 2001-11-09
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Functional Description Codes Reset State reset state code 0000 (TIM) issued. This state entered either after hardware reset (RST) with code RES. Codes Deactivated State S-transceiver state `Deactivated` receives code 0000 (TIM) issued until expiration timer. Otherwise, code 1111 (DI) issued.
2.5.5.1
Codes
table below presents defined C/I0 codes. command needs applied continuously until desired action been initiated. Indications strictly state orientated. Refer state diagrams following sections commands indications applicable various states.
LT-S Code
Data Sheet
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Functional Description Receive Infos INFO detected Level detected (signal different INFO detected INFO other than INFO
Transmit Infos INFO INFO INFO Send Single Pulses (TM1). Send Continuous Pulses (TM2).
Data Sheet
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Functional Description
2.5.5.2
State Machine Mode
Reset State ARD1) ARD1)
Test Mode State
Pend. Deact. (i0*16ms)+32ms
Wait
Deactivated ARD1) (i0*8ms)
Detected ARD1)
Pend. Lost Framing Lost Framing i3*ARD i3*ARD1) i3*AID2) AID2) ARD1) AID2) i3*AID2) ARD1)
Wait
Activated
statem_nt_s.vsd
Figure
State Machine Mode
Note: State 'Test Mode' entered from state except from state 'Test Mode' itself, i.e. C/I-code 'TMi' must followed C/I-code 'TMj' directly.
Data Sheet
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Functional Description Deactivated S-transceiver transmitting. There signal detected S/T-interface, activation command received channel. Activation possible from interface from interface. Detected INFO detected S/T-interface, translated "Activation Request" indication channel. S-transceiver waiting command, which normally indicates that transmission line upstream synchronized. Pending Activation result command, INFO sent S/T-interface. INFO received. case command, loop closed. wait INFO received, INFO continues transmitted while S-transceiver waits "switch-through" command from device upstream. Activated INFO sent S/T-interface result "switch through" command AID: D-channels transparent. command AIL, loop closed. Lost Framing This state reached when transceiver lost synchronism state activated. Lost Framing receiving command which usually indicates that synchronization been lost transmission line, S-transceiver transmits INFO Pending Deactivation This state triggered deactivation request unstable state. Indication (state wait DR") issued transceiver when: either INFO0 received duration internal timer expires.
Data Sheet
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Functional Description wait Final state after deactivation request. S-transceiver remains this state until issued. Unconditional States Test Mode Send Single Pulses Test Mode Send Continuous Pulses Commands
Command Deactivation Request Reset
Abbr.
Code 0000 0001
Remark Deactivation Request. Initiates complete deactivation transmitting INFO Reset state machine. Transmission Info0. reaction incoming infos. unconditional command. Send Single Pulses. Send Continuous Pulses. Receiver synchronous Activation Request. This command used start activation. Activation request loop. transceiver requested operate analog loop-back close S/T-interface. Activation Indication. Synchronous receiver, i.e. activation completed.
Send Single Pulses Send Continuous Pulses Receiver Synchronous Activation Request Activation Request Loop Activation Indication
0010 0011 0100 1000 1010
1100
Data Sheet
2001-11-09
82902
Functional Description Command Activation Indication Loop Deactivation Confirmation Abbr. Code 1110 1111 Remark Activation Indication Loop Deactivation Confirmation. Transfers transceiver into deactivated state which activated from terminal (detection INFO enabled). Remark Interim indication during deactivation procedure. Receiver synchronous. INFO received from terminal. Activation proceeds. Illegal code violation received. This function enabled S_CONF0.EN_ICV. Synchronous receiver, i.e. activation completed. Timer expired INFO received duration after deactivation request.
Indication Timing Receiver Synchronous Activation Request Illegal Code Ciolation Activation Indication Deactivation Indication
Abbr.
Code 0000 0100 1000 1011 1100 1111
Data Sheet
2001-11-09
82902
Functional Description
2.5.5.3
State Machine LT-S Mode
Reset State ARD1)
Pend. Deact. (i0*16ms)+32ms
Test Mode State
Wait Deactivated (i0*8ms)+ARD1) Pend. Act.
Lost Framing
Activated
statem_lts_s.vsd
Figure
State Machine LT-S Mode
Note: State 'Test Mode' entered from state except from state 'Test Mode' itself, i.e. C/I-code 'TMi' must followed C/I-code 'TMj 'directly.
Data Sheet
2001-11-09
82902
Functional Description deactivated S-transceiver transmitting. There signal detected S/T-interface, activation command received channel. Activation possible from interface from interface. pending activation result INFO detected line command, S-transceiver begins transmitting INFO waits reception INFO timer supervise reception INFO implemented software. case command, loop closed. activated Normal state where INFO transmitted S/T-interface. transceiver remains this state long neither deactivation test mode requested, receiver looses synchronism. When receiver synchronism lost, INFO sent automatically. After reception INFO transmitter keeps sending INFO lost framing This state reached when S-transceiver lost synchronism state activated. pending deactivation This state triggered deactivation request unstable state: indication (state wait DR.") issued S-transceiver when: either INFO0 received duration internal timer expires. wait Final state after deactivation request. transceiver remains this state until issued. Unconditional States Test mode Single alternating pulses sent S/T-interface.
Data Sheet
2001-11-09
82902
Functional Description Test mode Continuous alternating pulses sent S/T-interface.
Command Deactivation Request
Abbr.
Code 0000
Remark Deactivation Request. Initiates complete deactivation transmitting INFO Reset state machine. Transmission Info0. reaction incoming infos. unconditional command. Send Single Pulses. Send Continuous Pulses. Activation Request. This command used start activation. Activation request loop. transceiver requested operate analog loop-back close S/T-interface. Deactivation Confirmation. Transfers transceiver into deactivated state which activated from terminal (detection INFO enabled). Remark Interim indication during activation procedure Receiver synchronous INFO received from terminal. Activation proceeds. Illegal code violation received. This function enabled S_CONF0.EN_ICV. Synchronous receiver, i.e. activation completed. Timer expired INFO received duration after deactivation request
Reset
0001
Send Single Pulses Send Continuous Pulses Activation Request Activation Request Loop Deactivation Confirmation
0010 0011 1000 1010
1111
Indication Timing Receiver Synchronous Activation Request Illegal Code Ciolation Activation Indication Deactivation Indication
Abbr.
Code 0000 0100 1000 1011 1100 1111
Data Sheet
2001-11-09
82902
Functional Description
2.5.6
S-Transceiver Enable Disable
layer-1 part S-transceiver enabled/disabled with bits S_CONF0.DIS_TR S_CONF2.DIS_TX. DIS_TX='1' transmit buffers disabled. receiver will monitor incoming data this configuration. default transmitter disabled (DIS_TX '1'). transceiver disabled (DIS_TR '1', DIS_TX don't care) layer-1 functions disabled including level detection circuit receiver. this case power consumption S-transceiver reduced minimum.
Data Sheet
2001-11-09
82902
Functional Description
2.5.7
Interrupt Structure S-Transceiver
Level Detect
S_STA
RINF FECV FSYN
SQRR
MSYN MFEN SQR1 SQR2 SQR3 SQR4
SQXR
MFEN SQX1 SQX2 SQX3 SQX4
ISTAS
MASKS
ISTA
MASK
Reserved
interr.vsd
Figure
Interrupt Structure S-Transceiver
Data Sheet
2001-11-09
82902
Operational Description
3.1.1
Operational Description
Layer Activation/Deactivation Generation 4B3T Signal Elements
control monitoring purposes activation/deactivation progress following signal elements defined 220. Table 4B3T Signal Elements signal deactivation signal that used both directions. Downstream, requests deactivate. Upstream, acknowledges that deactivated.
U1W, Awake awake acknowledge signal used awake procedure U-interface. sends enable echo canceller adapt coefficients. Barker code other enabled synchronize. detection used criterion synchronization. M-channel used transfer loop commands. While NT-RP synchronizing received signal, LT-RP sends enable echo canceller adapt coefficients, sending Barker code inhibits synchronize still asynchronous signal. proceeding synchronization, U-frame jump from time time. detected end. similar without framing information. While synchronizes received signal, sends enable echo canceller adapt coefficients, sends Barker code prevent from synchronizing still asynchronous signal. proceeding synchronization, U-frame jump from time time. detected far-end When synchronized, sends Barker code synchronize itself. indicates additionally that terminal equipment activated. Upon receiving indicates synchronized state 'UAI' layer-2. Usually during activation, signal detected because activated first changes before being detected. M-channel used transfer code error indications kbit/s transparent data.
Data Sheet 2001-11-09
82902
Operational Description Table 4B3T Signal Elements (cont'd) indicates that whole link synchronous both directions. detecting requests establish fully transparent connection. M-channel used transfer code error indications kbit/s transparent data. requires 'Transparent' state. detecting stops sending signal informs S-transceiver layer-2 device system interface. M-channel used transfer loop commands kbit/s transparent data. transports operational data channels. M-channel used transfer loop commands kbit/s transparent data. transports operational data channels. M-channel used transfer code error indications kbit/s transparent data. T-SMINTI sends periodically single pulses once millisecond U-interface. test mode used pulse mask measurements. Loss frame, generated flywheel Generation 4B3T Signal Elements symbols (ternary) sync word (tern ary) (tern ary) binary data before scram bling
Table
Upstream Downstream
Resulting tone Frequency: Duration: 2.13 when sending wakeup tone finished, signal ternary sent scrambled binary data scrambled binary data scrambled binary data
times +++++ ++---- ----
Data Sheet
2001-11-09
82902
Operational Description Table Generation 4B3T Signal Elements (cont'd) Duration: (warranted state machine) Binary data from digital interface Ternary continuous single pulses
once "+", times (repeatedl
Table
S/T-Interface Signals Signals from INFO INFO signal. continuous signal with following pattern: Positive ZERO, negative ZERO, ONEs.
Signals from INFO signal.
INFO
Frame with bits D-echo channels binary ZERO. binary ZERO. bits according normal coding rules. INFO Synchronized frames with operational data D-channels.
INFO
Frames with operational data D-echo channels. binary ONE.
Data Sheet
2001-11-09
82902
Operational Description
3.1.2
Complete Activation Initiated Exchange
S/T-Reference Point
U-Reference Point
INFO INFO
INFO INFO INFO AR8/10 SBCX-X IPAC-X DFE-T
actbyLT_TSMINT.vsd
Figure
Activation Initiated Exchange
Note: starts issuing signal before starts issuing U1A. This chronological order displayed clarification.
Data Sheet
2001-11-09
82902
Operational Description
3.1.3
Complete Activation Initiated
S/T-Reference Point
U-Reference Point
AR8/10
INFO INFO
INFO
INFO INFO INFO
INFO
SBCX-X IPAC-X DFE-T
actbyTE_TSMINT.vsd
Figure
Activation Initiated
Note: starts issuing signal before starts issuing U1A. This chronological order displayed clarification.
Data Sheet
2001-11-09
82902
Operational Description
3.1.4
Complete Activation Initiated
S/T-Reference Point
U-Reference Point
INFO INFO
INFO INFO
INFO
8/10 SBCX-X IPAC-X
DFE-T
actbyNT_TSMINT.vsd
Figure
Activation Initiated
Note: starts issuing signal before starts issuing U1A. This chronological order displayed clarification.
Data Sheet
2001-11-09
82902
Operational Description
3.1.5
Complete Deactivation
S/T-Reference Point
U-Reference Point
INFO INFO
INFO INFO SBCX-X IPAC-X
DEAC
DFE-T
deac_TSMINT.vsd
Figure
Complete Deactivation
Data Sheet
2001-11-09
82902
Operational Description
3.1.6
Loop
AR8/10
S/T-Reference Point INFO INFO
U-Reference Point
2B+D (M-Bit= 2B+D (M-Bit=
2B+D
SBCX-X IPAC-X
DFE-T
act_loop2_TSMINT.vsd
Figure
Loop
Note: Closing/resolving loop provoke S-transceiver resynchronize. this case, following C/I-codes exchanged immediately reception AIL/AI, respectively: 'RSY', 'AI', 'AIL'/'AI'.
Data Sheet
2001-11-09
82902
Operational Description
Layer Loopbacks
Test loopbacks specified national PTTs order facilitate location defect systems. Four different loopbacks defined. position each loopback illustrated Figure
S-BUS Loop S-Transceiver
IOM®-2
Loop U-Transceiver
IOM®-2
Loop U-Transceiver U-Transceiver Loop U-Transceiver
IOM®-2
Loop Layer-1 Cont
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