80902 Version Wired Edition 2001-11-12 Published Infineon Te

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

80902 Version Wired Edition 2001-11-12 Published Infineon Te

Datasheet Thumbnail

Top Searches for this datasheet

80902 Version
Wired
Edition 2001-11-12 Published Infineon Technologies St.-Martin-Strasse D-81541 Germany Infineon Technologies 2001. Rights Reserved. Attention please! information herein given describe certain components shall considered warranted characteristics. Terms delivery rights technical change reserved. hereby disclaim warranties, including limited warranties non-infringement, regarding circuits, descriptions charts stated herein. Infineon Technologies approved CECC manufacturer. Information further information technology, delivery terms conditions prices please contact your nearest Infineon Technologies Office Germany Infineon Technologies Representatives worldwide (see address list). Warnings technical requirements components contain dangerous substances. information types question please contact your nearest Infineon Technologies Office. Infineon Technologies Components only used life-support devices systems with express written approval Infineon Technologies, failure such components reasonably expected cause failure that life-support device system, affect safety effectiveness that device system. Life support devices systems intended implanted human body, support and/or maintain sustain and/or protect human life. they fail, reasonable assume that health user other persons endangered.
80902 Version
Wired
80902 Revision History: Previous Version: Page 2001-11-12 Preliminary Data Sheet 06.01 Subjects (major changes since last revision)
Table Additional C/I-command Figure Chapter 2.3.7.4 Chapter Chapter Input Leakage Current AIN, BIN: max. 30µA Reduced power consumption
questions technology, delivery prices please contact Infineon Technologies Offices Germany Infineon Technologies Companies Representatives worldwide: webpage http://www.infineon.com
80902
Table Contents 1.6.1 2.2.1 2.3.1 2.3.2 2.3.3 2.3.4 2.3.4.1 2.3.5 2.3.6 2.3.7 2.3.7.1 2.3.7.2 2.3.7.3 2.3.7.4 2.3.7.5 2.3.7.6 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.5.1 3.1.1 3.1.2 3.1.3 3.1.4
Data Sheet
Page
Overview References Features Supported Configuration Block Diagram Definitions Functions Specific Pins Test Modes System Integration Functional Description Reset Generation IOM-2 Interface IOM,-2 Functional Description U-Transceiver 4B3T Frame Structure Maintenance Channel Coding from Binary Ternary Data Decoding from Ternary Binary Data Monitoring Code Violations Scrambler Descrambler Command/Indication Codes State Machine Activation Deactivation State Machine Notation Awake Protocol State Machine (IEC-T NTC-T Compatible) Inputs U-Transceiver Outputs U-Transceiver NT-States S-Transceiver Line Coding, Frame Structure Channels, Multiframing Data Transfer between IOM,-2 Loopback State Machine State Machine Mode Operational Description Layer Activation/Deactivation Generation 4B3T Signal Elements Complete Activation Initiated Exchange Complete Activation Initiated Deactivation
2001-11-12
80902
Table Contents 3.1.5 3.2.1 3.2.1.1 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 4.6.1 4.6.2 4.6.3 6.1.1 6.1.2 6.2.1 6.2.2 6.2.3
Page
Activation Procedures with Loopback Layer Loopbacks Loopback No.2 Complete Loopback External Circuitry Power Supply Blocking Recommendation U-Transceiver S-Transceiver Oscillator Circuitry General Electrical Characteristics Absolute Maximum Ratings Characteristics Capacitances Power Consumption Supply Voltages Characteristics IOM-2 Interface Reset Undervoltage Detection Characteristics
Package Outlines Appendix: Differences between T-SMINT,O Pinning Definitions Functions U-Transceiver U-Interface Conformity U-Transceiver State Machines Command/Indication Codes External Circuitry
Index
Data Sheet
2001-11-12
80902
List Figures Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
Page
Configuration Block Diagram Application Example T-SMINT,O: Standard IOM-2 Frame Structure T-SMINT,O State Diagram Example Awake Procedure initiated Awake Procedure initiated State Machine (IEC-T/NTC-T Compatible). -Interface Line Code Frame Structure Reference Points (ITU I.430). State Diagram Notation State Machine Mode Activation Initiated Exchange Activation Initiated Deactivation (always Initiated Activation Loopback Test Loopbacks Power Supply Blocking External Circuitry U-Transceiver with External Hybrid External Circuitry S-Interface Transmitter External Circuitry S-Interface Receiver Crystal Oscillator Maximum Sinusoidal Ripple Supply Voltage Input/Output Waveform Tests. IOM®-2 Interface Synchronization Timing IOM-2 Interface Frame Synchronization Timing Reset Input Signal Undervoltage Control Timing NTC-Q Compatible State Machine Q-SMINT,O: 2B1Q IEC-T/NTC-T Compatible State Machine T-SMINT,O: 4B3T External Circuitry T-SMINT,O
Data Sheet
2001-11-12
80902
List Tables Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table
Page
Products Generation Definitions Functions States. LP2I States Test Modes Frame Structure Downstream Transmission Frame Structure Upstream Transmission Coding Table 4B3T Decoding Table Codes Differences former NT-SM IEC-T/NTC-T Timers Active States Symbol Output Signal Output State Test C/I-Code Output. 4B3T Signal Elements Generation 4B3T Signal Elements. S/T-Interface Signals U-Transformer Parameters S-Transformer Parameters Crystal Parameters Maximum Input Currents S-Transceiver Characteristics U-Transceiver Characteristics Capacitances Reset Input Signal Characteristics. Parameters UVD/POR Circuit Definitions Functions States. Related Documents U-Interface. Codes Dimensions External Components.
Data Sheet
2001-11-12
80902
Overview
Overview
80902 offers features known from 8090 hence replace latter applications. Table Page summarizes generation products.
Table
Products Generation 80902 T-SMINT®O 81902 T-SMINT®IX P-MQFP-64 P-TQFP-64 U+S+HDLC+ 82902 T-SMINT®I P-MQFP-64 P-TQFP-64
Package Register access Access MCLK, watchdog timer, SDS, BCL, Dchannel arbitration, access manipulation etc. provided HDLC controller mode available
P-MQFP-44
parallel parallel
(only)
Data Sheet
2001-11-12
80902
Overview
References
080, Transmission Multiplexing; ISDN basic rate access; Digital transmission system metallic local lines, ETSI, November 1998 Technische Richtlinie, Spezifikation ISDN Schnittstelle Schicht Deutsche Telecom August 1991 0284/96 Technische Spezifikation Intelligenter (iNT) Funktionen eines Terminaladapters 2a/b (ohne Internverkehr), Deutsche Telekom 2001 Draft, ISDN; Basic User Network Interface (UNI), ETSI, November 1996 T1.605-1991, ISDN-Basic Access Interface Reference Points (Layer Specification), ANSI, 1991 I.430, ISDN User-Network Interfaces: Layer Recommendations, ITU, November 1988 IEC-T, ISDN Echocancellation Circuit, 20901 (IEC 20902 (IEC TA), preliminary Target Specification 11.88, Siemens 1988 SBCX, Interface Circuit Extended, 2081 V3.4, User's Manual 11.96, Siemens 1996 NTC-T, Network Termination Controller (4B3T), 8090 V1.1, Data Sheet 06.98, Siemens 1998 INTC-Q, Intelligent Network Termination Controller (2B1Q), 8191 V1.1, Data Sheet 10.97, Siemens 1997 Q-SMINTO, 2B1Q Second Gen. Modular ISDN (Ordinary), 80912 Q-SMINTIX, 2B1Q Second Gen. Modular ISDN (Intelligent eXended), 81912 Q-SMINTI, 2B1Q Second Gen. Modular ISDN (Intelligent), 82912 V1.3, Data Sheets 03.01, Infineon 2001 Interface Reference Guide, Siemens 03.91 SCOUT-S(X), Siemens Codec with S/T-Transceiver, 2138x V1.1, Preliminary Data Sheet 08.98, Infineon Technologies 1999 PITA, Interface Telephony/Data Applications V0.3, SICAN GmbH, September1997 Dual Channel SLICOFI-2, HV-SLIC; DUSLIC; PEB3265, 4265, 4266; Data Sheet DS2, Infineon Technologies, July 2000.
[10] [11]
[12] [13] [14] [15]
Data Sheet
2001-11-12
4B3T Second Gen. Modular ISDN (Ordinary) T-SMINT®O
80902
Version
CMOS
Features
Features known from 8090 Single chip solution including S-transceiver Perfectly suited ISDN Fully automatic activation deactivation U-interface (4B3T) conform ETSI [2]: Meets transmission requirements ETSI P-MQFP-44-2 loops with margin S/T-interface conform ETSI [4], ANSI Supports point-to-point configurations Meets exceeds transmission requirements Optional interface eases chip testing evaluation Power-on reset Undervoltage Detection with external components robustness
Type 80902
Data Sheet
Package P-MQFP-44
2001-11-12
80902
Overview Features Optional transformers with non-negligible resistance corresponding line sidePin Vref according external capacitor removed Inputs accept 3.3V (open drain) accepts pull-up 3.3V1) compatible with (2nd Generation) LEDs indicating Loopback activation status Lowest power consumption power CMOS technology (0.35µ) Newly optimized power libraries High output swing S-line interface leads minimized power consumption Single Volt power supply 185mW (NTC-T: 233mW) power consumption with random data over ETSI Loop 15mW typical power consumption power down NTC-T; NTC-Q: 28mW)
Supported
integrated hybrid provided Therefore, external hybrid always required, which consists only additional resistors compared integrated hybrid, allows more flexibility board design. Auxiliary interface (capacitive receiver coupling suited S-feeding) NT-Star with star point IOM®-2 (already supported NTC-T).
Pull-ups must avoided. so-called 'hot-electron-effect' would lead long term degradation.
Data Sheet
2001-11-12
80902
Overview
Configuration
VDDa_SX VSSa_SX
/LP2I
/VDDDET VDDa_SR VSSa_SR XOUT BOUT VDDa_UX VSSa_UX AOUT
VSSD VDDD
T-SMINTO 80902
/ACT
VSSa_UR VDDa_UR
/RSTO VDDD
VSSD
/RST
pin_2.vsd
Figure
Configuration
Data Sheet
2001-11-12
80902
Overview
Block Diagram
XOUT
VDDDET
RSTO
Clock Generation
POR/UVD
AOUT BOUT
S-Transceiver U-Tansceiver
Factory Test Test Modes
LP2I
IOM-2 Interface
Transceiver Control
block diagram.vsd
Figure
Block Diagram
Data Sheet
2001-11-12
80902
Overview
Definitions Functions
Table
Definitions Functions Symbol
VDDa_UR
Type
Function Supply voltage U-Receiver (3.3 Analog ground U-Receiver Supply voltage U-Transmitter (3.3 Analog ground U-Transmitter Supply voltage S-Receiver (3.3 Analog ground S-Receiver Supply voltage S-Transmitter (3.3 Analog ground S-Transmitter Supply voltage digital circuits (3.3 Ground digital circuits Supply voltage digital circuits (3.3 Ground digital circuits Frame Sync: 8-kHz frame synchronization signal Data Clock: interface clock signal (double clock): Loopback indication: directly drive (4mA). Loopback closed Loopback closed. Data Downstream: Data interface
VSSa_UR VDDa_UX
VSSa_UX VDDa_SR
VSSa_SR VDDa_SX
VSSa_SX VDDD
VSSD VDDD
VSSD
LP2I
Data Sheet
2001-11-12
80902
Overview Table Definitions Functions (cont'd) Symbol Type Function Data Upstream: Data interface Disable FSC, DCL, high FSC, DCL, push-pull mode S-interface: passive S-bus (fixed timing) point-to-point extended passive S-bus (adaptive timing) Reset: active reset input. Schmitt-Trigger input with hysteresis typical 360mV. used. Reset Output: active reset output. Test Mode Selects test pattern (see Page 10). Test Mode Selects test pattern (see Page 10). Test Mode Selects test pattern (see Page 10). S-Bus Transmitter Output (positive) S-Bus Transmitter Output (negative) S-Bus Receiver Input S-Bus Receiver Input Crystal Connected 15.36 crystal Crystal Connected 15.36 crystal
(PU)
RSTO
XOUT
Data Sheet
2001-11-12
80902
Overview Table Definitions Functions (cont'd) Symbol AOUT BOUT
VDDDET
Type
Function Differential U-interface Output Differential U-interface Output Differential U-interface Input Differential U-interface Input Detection: This selects detection active ('0') reset pulses generated RSTO whether deactivated ('1') external reset applied RST. Activation LED. Indicates activation status Stransceiver. directly drive (4mA). Test Used factory device test. 'VSS' Test Used factory device test. 'VSS'
10,11, 16,17, 26,38
Internal pull-up resistor (typ. 100µA) Input Output (Push-Pull) Output (Open Drain)
1.6.1
Specific Pins Test Modes
Pins ACT, LP2I connected display four different states (off, slow flashing, fast flashing, on). displays activation status S-transceiver according Table
Data Sheet
2001-11-12
80902
Overview Table States U_Deactivated U_Activated S_Activated
fast flashing
slow flashing
Note: denotes duty cycle 'high' 'low'. with: U_Deactivated: 'Deactivated State' defined Chapter 2.3.7.6. U_Activated: 'SBC Synchronizing', 'Wait Info U4H', `Transparent` defined Chapter 2.3.7.6. S-Activated: 'Activated State' defined Chapter 2.4.5.1. Note: Optionally, drive second with inverse polarity (connect this additional 3.3V only). Another connected LP2I indicate active Loopback according Table Table LP2I LP2I States Loopback command -channel received loopback command loopback deactivation after loopback command. Loopback command been received. Complete analog loop being closed S-interface.
Test Modes Different test patterns S-interface generated pins TM0-2 according Table Table
Data Sheet
Test Modes
U-transceiver
S-transceiver
Reserved future use. Normal operation this version. Normal operation kHz1) Continuous Pulses kHz2) Single Pulses
2001-11-12
80902
Overview Table
Test Modes (cont'd) U-transceiver Data Through3) Send Single Pulses Quiet Mode5) normal operation
S-transceiver Normal operation
S-transceiver transmits pulses with alternating polarity rate resulting envelope. S-transceiver transmits pulses with alternating polarity rate resulting envelope. Forces U-transceiver into state 'Transparent' where transmits signal Forces U-transceiver into state 'Test' send single pulses. pulses issued intervals have duration 8.33 U-transceiver hardware reset.
System Integration
provides functionality without microcontroller being necessary. Special selections done strapping (DIO, BUS, TM0-2). device interface. Interface serves only monitoring debugging purposes. regarded window internal
Data Sheet
2001-11-12
80902
Overview
DC/DC-Converter IDCC PEB2023
Interface
Interface
T-SMINTO PEF80902
IOM-2
LEDs
Strap Mode Selection
Loop Ind. Activation Status
Disable Selection Test Pattern Selection
NT1_appl.vsd
Figure
Application Example Standard
Data Sheet
2001-11-12
80902
Functional Description
Functional Description
Reset Generation
External Reset Input input external reset applied forcing reset state. This external reset signal additionally RSTO output. Reset Ouput VDDDET active, then deactivation reset output RSTO delayed tDEACT (see Table 28). Reset Generation on-chip reset generator based Power-On Reset (POR) Under Voltage Detection (UVD) circuit (see Table 28). POR/UVD requires external components. POR/UVD circuit disabled VDDDET. requirements ramp-up during power-on reset described Chapter 4.6.3. Clocks Data Lines During Reset During reset data clock (DCL) frame synchronization (FSC) keep running. During reset high; with exception output code from U-Transceiver 'DR' 0000 output code from S-Transceiver 'TIM' 0000.
Data Sheet
2001-11-12
80902
Functional Description
IOM-2 Interface
interface always operates mode according Reference Guide [12].
2.2.1
Functional Description
interface consists four lines: FSC, DCL, rising edge indicates start frame. clock signal synchronizes data transfer both data lines twice rate. bits shifted with rising edge first clock cycle. Note: possible write data into interface enabled/disabled with DIO. signal frame sync signal. number timeslots transmit line determined frequency clock with clock channel consisting timeslots available. IOM®-2 Frame Structure frame structure data ports (DU,DD) with clock shown Figure
macro_19_QSMINTO
Figure
IOM-2 Frame Structure
frame composed channel: Channel contains 144-kbit/s user signaling data MONITOR programming channel (not available command/indication channel (CI0) control e.g. U-transceiver.
Data Sheet 2001-11-12
80902
Functional Description
U-Transceiver
statemachine U-Transceiver compatible state machine 8090 documentation [9], includes some minor changes simplification compliance Ref. [1]. Basic configurations selected strapping
2.3.1
4B3T Frame Structure
4B3T U-interface performs full duplex data transmission reception Ureference point according ETSI 220. applies 4B3T block code together with adaptive echo cancelling equalization. Transmission performance shall such, that meets ETSI test loops with margin. U-interface designed data transmission twisted pair wires local telephone loops, with basic access ISDN user rate kbit/s. following information transmitted over twisted pair: Bidirectional: data channels Symbol clock Frame Activation kbit/s Transparent Channel symbol), (not implemented) From side: Power feeding Deactivation Remote control test loops symbol) From side: Indication monitored code violations symbol) Performance Requirements according (August 1991): U-interface, following transmission ranges achieved without additional signal regeneration loop (bit error rate 10-7): with noise: wires diameter wires without noise: wires diameter wires Note: Typical attenuation wires diameter about 7dB/km contrast ETSI wires with about 8dB/km. transmission ranges doubled inserting repeater signal regeneration. Performance requirements according ETSI met, too. frames transmitted U-interface, each consisting symbols: scrambled coded data
Data Sheet 2001-11-12
80902
Functional Description symbols: Barker code both symbol frame synchronization (not scrambled) symbol: Ternary maintenance symbol (not scrambled) user data symbols split into four equally structured groups. Each group ternary symbols, resp. bits) contains user data IOM®-2 frames same order 2D). Different syncwords used each direction: Downstream from Upstream from +++---+--+- -+--+---+++
side, transmitted Barker code begins symbols after received Barker code vice versa. Table D1/2 D7/8 D1/2 Frame Structure Downstream Transmission D1/2 D3/4 D3/4 D3/4 D5/6 D5/6 D5/6 D7/8 D7/8
Data Sheet
2001-11-12
80902
Functional Description Ternary data IOM®-2 frames Maintenance symbol Syncword
Data Sheet
2001-11-12
80902
Functional Description
Table U1/2 U1/2
Frame Structure Upstream Transmission U1/2 U3/4 U3/4 U3/4 U5/6 U5/6 U5/6 U7/8 U7/8 U7/8
Ternary data IOM®-2 frames Maintenance symbol Syncword
Data Sheet
2001-11-12
80902
Functional Description
2.3.2
Maintenance Channel
4B3T frame structure provides kbit/s M(aintenance)-channel transfer remote loopback commands error indications. Loopback Commands station uses M-channel request remote loopbacks. Loopback commands coded with series symbols. continuous series requests loopback activation continuous series requests deactivation loopback station reacts soon pattern been detected consecutive symbols. Error Indications U-transceiver reports line code violations M-channel exchange setting M-Bit polarity. Transparent Messages exchange Transparent Messages Transparent Channel supported T-SMINTO.
2.3.3
Coding from Binary Ternary Data
Each block binary data coded into ternary symbols block code according Table number next column used, given right hand side each block. left hand signal elements table (both ternary binary) transmitted first.
Table
Coding Table
Data Sheet
2001-11-12
80902
Functional Description Table Coding Table (cont'd)
2.3.4
Decoding from Ternary Binary Data
Decoding done reverse manner coding. received blocks ternary symbols converted into blocks bits. decoding algorithm given Table encoding table, left hand symbol each block (both binary ternary) first right hand last. ternary block received, decoded binary This pattern usually occurs only during deactivation.
Table
Data Sheet
4B3T Decoding Table Ternary Block
Binary Block
2001-11-12
80902
Functional Description Table 4B3T Decoding Table (cont'd)
2.3.4.1
Monitoring Code Violations
running digital monitor (RDSM) computes running digital from received ternary symbols adding polarity received user data -1). each block, running digital supposed reflect number next column Table code violation occurred running digital less than more than four ternary block, ternary block (three user symbols with zero polarity) found received data. ternary block error found, running digital retains current value. counter value greater than beginning next ternary block, value less, one. after code violation been detected, RDSM synchronizes itself within period depending received data pattern. Note there some transmission errors which cause code violation.
2.3.5
Scrambler
Scrambler Descrambler
binary transmit data from IOM®-2 interface scrambled with polynomial bits, before sent 4B3T coder. scrambler polynomial is:: Descrambler received data (after decoding from ternary binary) multiplied with polynomial bits order recover original data before forwarded IOM®-2 interface.The descrambler self synchronized after symbols. descrambler polynomial is::
scrambling descrambling process controlled fully T-SMINTO. Hence, influence taken user.
Data Sheet
2001-11-12
80902
Functional Description
2.3.6
Command/Indication Codes
Both commands indications depend data direction. Table presents defined codes. command indication will recognized valid after been detected successive IOM®-2 frames (double last-look criterion). Indications strictly state orientated. Refer state diagrams following sections commands indications applicable various states. Table Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Codes reserved
code `1010` must input U-transceiver.
Activation Indication Activation Indication Loop Activation Request Activation Request Local Loop Data Through Mode
Deactivation Indication. Deactivation Request Disable Reset Resynchronization Indication
2001-11-12
Data Sheet
80902
Functional Description Deactivation Confirmation Send-Single-Pulses Timing Request
2.3.7 2.3.7.1
State Machine Activation Deactivation State Machine Notation
following state diagram describes actions/reactions resulting from command detected signal resulting from various operating modes. states with inputs outputs interpreted shown below:
Transmitted U-Signal State Name Channel Indication (DOUT)
SM_expl.emf
Figure
State Diagram Example
Each state more transitions other states. These transitions depend certain conditions which noted next transition lines. These conditions only possibility leave state. more conditions have fulfilled together, they into parentheses with operator (&). more than condition leads same transition, they into parentheses with operator (|). meaning condition inverted operator (/). Only described states transitions exist. some transitions, internal timer started. start timer indicated ('x' timer number). Transitions that caused timer expired labelled TxE. Some conditions lead same target state. reduce number lines complexity figures, state named "ANY STATE" acts behalf state.
Data Sheet
2001-11-12
80902
Functional Description state machines designed cope with ISDN devices with IOM®-2 standard interfaces. Undefined situations excluded. case, involved devices will enter defined conditions soon line deactivated.
2.3.7.2
Awake Protocol
awake process signals defined' U1W' 'U2W'. Depending call direction (up-, downstream) interpreted awake acknowledge signals (see figures below).
INFO 2.133 INFO
INFO 2.133
ITD06385.vsd
INFO
Figure
Awake Procedure initiated
INFO 2.133 INFO
INFO 2.133 INFO
ITD06386.v
Figure
Awake Procedure initiated
Data Sheet
2001-11-12
80902
Functional Description Acting Calling Station After sending awake signal, awaking U-transceiver waits acknowledge. After awake signal repeated, acknowledge been recognized. acknowledge signal been recognized, U-transceiver waits possible repetition case previous coincidence awake signals). repetition detected, U-transceiver starts transmitting with delay such repetition detected, U-transceiver interprets awake signal behaves like device awoken end. Acknowledging Wake-Up Call deactivated device detects awake signal acknowledge signal sent out. After that, U-transceiver waits possible repetition awake signal case acknowledge hasn't been recognized). repetition found, awoken U-transceiver starts sending after from detecting awake signal. repeated awake signal found, procedure awoken U-transceiver starts again.
Data Sheet
2001-11-12
80902
Functional Description
2.3.7.3
State Machine (IEC-T NTC-T Compatible)
Awaked Start Awaking Awake Signal Sent T13S T13E Ack. Sent Received T05E) T12S Synchronizing T05S Synchronizing T12E) T05S Pend. Deactivation Test STATE Reset T13S Sending Awake-Ack. T13S T05S T05S T05E Deactivating Deactivated
Wait Info
Transparent Loss Framing
NT_SM_4B3T_cust.emf
Figure
State Machine (IEC-T/NTC-T Compatible)
Note: test modes 'Data Through` (DT), `Send Single Pulses` (SSP) `Quiet Mode` (QM) generated pins TM0-2 according Table
Data Sheet
2001-11-12
80902
Functional Description
Table
Differences former NT-SM IEC-T/NTC-T Change Comment simplifies implementation
State/ Signal
State 'Deact. split into states Request Rec.' 'Pend. Deactivation 'Reset' State 'Test' State State 'Loss Framing' inserted, results different behavior state 'Transparent', return normal transmission possible after detection inserted renamed state 'Deactivated' renamed state 'Transparent' Name Duration
compliance ETSI 080, corresponds state NT1.10
C/I-code State 'Power Down' State 'Data Transmission' Timer variables introduced
consistency reasons 2B1Q
Table
2.3.7.4
Inputs U-Transceiver
C/I-Commands Activation Indication downstream device issues this indication announce that layer available. U-transceiver turn informs side transmitting Activation Request U-transceiver requested start activation process already done) sending wake-up signal U1W. Deactivation Indication This indication used during deactivation procedure inform Utransceiver that enter 'Deactivated' (power-down) state. Data Through Test Mode This unconditional command used test purposes only forces Utransceiver into state 'Transparent'.
Data Sheet
2001-11-12
80902
Functional Description Disable This unconditional command forces U-transceiver state 'Test', where transmits further action initiated. Reset Unconditional command which resets U-transceiver. Send Single Pulses Unconditional command which requests transmission single pulses U-interface. Timing U-transceiver requested enter state 'IOM Awaked'.
U-Interface Events detected recognized after symbols (1ms) with zero level row. Detection last detected U-transceiver detects continuous binary found after descrambling least subsequent U-frames. detected after detected recognized, U-transceiver detects subsequent binary after descrambling. Awake signal (U2W) detected Awake signal (U1W) been sent Loss Framing U-interface Timer ended, started timer expired
Timers
start timers indicated TxS, expiry TxE. following table shows which timers used.
Table Timer
Timers Duration (ms) Function code recognition Supervises repetition State Pend. Deactivation, Deactivating Start Awaking
Data Sheet
2001-11-12
80902
Functional Description Table Timer Timers (cont'd) Duration (ms) Function Prevents U-transceiver state Synchronizing from immediate transition state 'Pend. Deactivation' detected Supervises repetition State Synchronizing
Ack. sent received Sending awake-ack.
2.3.7.5
Outputs U-Transceiver
Below signals indications summarized that issued IOM®-2 (C/I indications) U-interface (predefined U-signals). Indications Activation Indication U-transceiver established transparency transmission. downstream device requested establish layer-1 functionality. Activation Indication Loop-back U-transceiver established transparency transmission. downstream device requested establish loopback Activation Request downstream device requested start activation procedure. Activation Request Loop-back U-transceiver detected loop-back command M-channel established transparency transmission direction IOM® Uinterface. downstream device requested start activation procedure establish loopback Deactivation Confirmation Idle code IOM®-2 interface. Deactivation Request U-transceiver detected deactivation request command from LTside complete deactivation. downstream device requested start deactivation procedure. Resynchronizing Indication informs downstream device that U-transceiver synchronous.
Data Sheet
2001-11-12
80902
Functional Description Signals U-Interface signals U1W, U1A, transmitted U-interface.They defined Table Signals IOM®-2 Data (B+B+D) '1's states besides states listed Table
Table
Active States
Sychronizing Wait INFO Transparent Dependence Outputs M-symbol output states with valid M-symbol output value according Table
Table Error
Symbol Output detected detected
Symbol Output
Table Input
Signal Output State Test active other except C/I-Code 'DI'
Signal Output
Table
C/I-Code Output Synchronizing Wait Info Transparent
Loopback Command received received
2.3.7.6
NT-States
this section each state described with function.
Data Sheet
2001-11-12
80902
Functional Description Acknowledge Sent Receive After having sent awake signal, U-transceiver received acknowledge wake tone. being awoken U-transceiver sent acknowledge. both cases U-transceiver waits possible repetition time-out. Awake Signal Sent sent awake signal waits response. does react time timer expires repeats wake-up call. Deactivated Only "Deactivated" state device enter power-down mode. Deactivating State Deactivating assures that C/I-channel code issued four times before entering 'Deactivated' state. IOM® Awaked U-transceiver deactivated, enter power-down mode. Loss Framing This state entered loss framing (LOF). signal transmitted U-interface. receiver-reset performed Note that there return 'Transparent' state that been possible before former IEC-T based state machine. Pending Deactivation U-transceiver received U-transceiver remains least 0.5ms this state before accepts Synchronizing synchronized indicates this AR/ARL towards downstream device. waits acknowledge 'AI' from downstream device. Sending Awake-Ack. receipt awake signal U-transceiver responds with transmission U1W.
Data Sheet
2001-11-12
80902
Functional Description Start Awaking receipt C/I-channel U-transceiver sends awake signal start activation. Synchronizing After successful awake procedure U-transceiver trains receiver coefficients until able detect signals Reset state 'Reset' software-reset performed. Test State "Test" entered when unconditional commands TM2-0='SSP' applied. test signal issued long active C/I=SSP applied. Transparent transmission line fully activated. User data transparently exchanged U4/U5. Transparent state entered case loopback downstream device informed code that transparent state been reached Note that contrast former IEC-T state machine there resynchronization mechanism. Once loss framing (LOF) been detected deactivation initiated. Wait Info synchronized waits permission (U4H) 'Transparent' state.
Data Sheet
2001-11-12
80902
Functional Description
S-Transceiver
S-Transceiver offers state machine described User's Manual V3.4 [8]. S-transceiver basic configurations performed strapping.
2.4.1
Line Coding, Frame Structure
Line Coding following figure illustrates line code. binary represented line signal. Binary ZEROs coded with alternating positive negative pulses with exceptions: required frame structure code violation indicated consecutive pulses same polarity. These pulses adjacent separated binary ONEs. configurations binary ZERO always overwrites binary ONE.
code violation
Figure
-Interface Line Code
Frame Structure Each frame consists bits nominal rate kbit/s. user data (B1+B2+D) frame structure applies data rate kbit/s (see Figure direction frame transmitted with offset. details framing rules please refer I.430 section 6.3. following figure illustrates standard frame structure both directions with framing maintenance bits.
Data Sheet
2001-11-12
80902
Functional Description
Figure
Frame Structure Reference Points (ITU I.430) Framing D.C. Balancing D-Channel Data D-Channel Echo Auxiliary Framing B1-Channel Data B2-Channel Data Activation S-Channel Data Multiframing (0b) identifies frame (always positive pulse, always code violation) (0b) number binary ZEROs sent after last Signaling data specified user received E-bit equal transmitted D-bit section I.430 User data User data (0b) INFO transmitted (1b) INFO transmitted channel data (see note below) (1b) Start multi-frame
Note: I.430 standard specifies optional use.
2.4.2
Channels, Multiframing
channels supported.
Data Sheet
2001-11-12
80902
Functional Description
2.4.3
Data Transfer between
state (Activated) bits transferred transparently from interface vice versa. other states '1's transmitted interface.
2.4.4
Loopback
commands close analog loop close S-interface possible. ETSI refers this loop under 'loopback ETSI requires, that channels have same propagation delay when being looped back. D-channel Echo bin. during analog loopback (i.e. loopback loop transparent. Note: After C/I-code been recognized S-transceiver, zeros looped back D-channels (DU) four frames.
2.4.5
State Machine
state diagram notation given Figure information contained state diagrams are: state name Signal received from line interface (INFO) Signal transmitted line interface (INFO) code received (commands) code transmitted (indications) transition criteria
transition criteria grouped into: commands Signals received from line interface (INFOs) Reset
Data Sheet
2001-11-12
80902
Functional Description
IOM-2 Interface code
Ind. Cmd.
Unconditional Transition
Interface INFO
macro_17.vsd
Figure
State Diagram Notation
seen from transition criteria, combinations multiple conditions possible well. stands logical combination. indicates logical combination. Test Signals Single Pulses (TM1) pulse with width period frame with alternating polarity. Continuous Pulses (TM2) Continuous pulses with pulse width period. Note: test signals generated pins TM0-2 according Table Reset States After active signal reset S-transceiver state machine reset state. Codes Reset State reset state code 0000 (TIM) issued. This state entered after hardware reset (RST). Codes Deactivated State S-transceiver state `Deactivated` receives code 0000 (TIM) issued until expiration timer. Otherwise, code 1111 (DI) issued. Receive Infos
Data Sheet
INFO detected
2001-11-12
80902
Functional Description Level detected (signal different INFO detected INFO other than INFO
Transmit Infos INFO INFO INFO Send Single Pulses (TM1). Send Continuous Pulses (TM2).
Data Sheet
2001-11-12
80902
Functional Description
2.4.5.1
State Machine Mode
Reset State ARD1) ARD1)
Test Mode State
Pend. Deact. (i0*16ms)+32ms
Wait
Deactivated ARD1) (i0*8ms)
Detected ARD1)
Pend. Lost Framing Lost Framing i3*ARD i3*ARD1) i3*AID2) AID2) ARD1) AID2) i3*AID2) ARD1)
Wait
Activated
statem_nt_s.vsd
Figure
State Machine Mode
Note: setting Test Mode pins TM0-2 '010' '011': Continuous Pulses Single Pulses, S-transceiver starts sending corresponding test signal, state transition invoked.
Data Sheet 2001-11-12
80902
Functional Description Deactivated S-transceiver transmitting. There signal detected S/T-interface, activation command received channel. Activation possible from interface from interface. Detected INFO detected S/T-interface, translated "Activation Request" indication channel. S-transceiver waiting command, which normally indicates that transmission line upstream synchronized. Pending Activation result command, INFO sent S/T-interface. INFO received. case command, loop closed. wait INFO received, INFO continues transmitted while S-transceiver waits "switch-through" command from device upstream. Activated INFO sent S/T-interface result "switch through" command AID: D-channels transparent. command AIL, loop closed. Lost Framing This state reached when transceiver lost synchronism state activated. Lost Framing receiving command which usually indicates that synchronization been lost transmission line, S-transceiver transmits INFO Pending Deactivation This state triggered deactivation request unstable state. Indication (state wait DR") issued transceiver when: either INFO0 received duration internal timer expires.
Data Sheet
2001-11-12
80902
Functional Description wait Final state after deactivation request. S-transceiver remains this state until issued. Unconditional States Test Mode Send Single Pulses Test Mode Send Continuous Pulses Commands
Command Deactivation Request Reset
Abbr.
Code 0000 0001
Remark Deactivation Request. Initiates complete deactivation transmitting INFO Reset state machine. Transmission Info0. reaction incoming infos. unconditional command. Send Single Pulses. Send Continuous Pulses. Receiver synchronous Activation Request. This command used start activation. Activation request loop. transceiver requested operate analog loop-back close S/T-interface. Activation Indication. Synchronous receiver, i.e. activation completed.
Send Single Pulses Send Continuous Pulses Receiver Synchronous Activation Request Activation Request Loop Activation Indication
0010 0011 0100 1000 1010
1100
Data Sheet
2001-11-12
80902
Functional Description Command Activation Indication Loop Deactivation Confirmation Abbr. Code 1110 1111 Remark Activation Indication Loop Deactivation Confirmation. Transfers transceiver into deactivated state which activated from terminal (detection INFO enabled). Remark Interim indication during deactivation procedure. Receiver synchronous. INFO received from terminal. Activation proceeds. Illegal code violation received. This function enabled S_CONF0.EN_ICV. Synchronous receiver, i.e. activation completed. Timer expired INFO received duration after deactivation request.
Indication Timing Receiver Synchronous Activation Request Illegal Code Ciolation Activation Indication Deactivation Indication
Abbr.
Code 0000 0100 1000 1011 1100 1111
Data Sheet
2001-11-12
80902
Operational Description
3.1.1
Operational Description
Layer Activation/Deactivation Generation 4B3T Signal Elements
control monitoring purposes activation/deactivation progress following signal elements defined 220. Table 4B3T Signal Elements signal deactivation signal that used both directions. Downstream, requests deactivate. Upstream, acknowledges that deactivated.
U1W, Awake awake acknowledge signal used awake procedure U-interface. sends enable echo canceller adapt coefficients. Barker code other enabled synchronize. detection used criterion synchronization. M-channel used transfer loop commands. While NT-RP synchronizing received signal, LT-RP sends enable echo canceller adapt coefficients, sending Barker code inhibits synchronize still asynchronous signal. proceeding synchronization, U-frame jump from time time. detected end. similar without framing information. While synchronizes received signal, sends enable echo canceller adapt coefficients, sends Barker code prevent from synchronizing still asynchronous signal. proceeding synchronization, U-frame jump from time time. detected far-end When synchronized, sends Barker code synchronize itself. indicates additionally that terminal equipment activated. Upon receiving indicates synchronized state 'UAI' layer-2. Usually during activation, signal detected because activated first changes before being detected. M-channel used transfer code error indications kbit/s transparent data.
Data Sheet 2001-11-12
80902
Operational Description Table 4B3T Signal Elements (cont'd) indicates that whole link synchronous both directions. detecting requests establish fully transparent connection. M-channel used transfer code error indications kbit/s transparent data. requires 'Transparent' state. detecting stops sending signal informs S-transceiver layer-2 device system interface. M-channel used transfer loop commands kbit/s transparent data. transports operational data channels. M-channel used transfer loop commands kbit/s transparent data. transports operational data channels. M-channel used transfer code error indications kbit/s transparent data. T-SMINTO sends periodically single pulses once millisecond U-interface. test mode used pulse mask measurements. Loss frame, generated flywheel Generation 4B3T Signal Elements symbols (ternary) sync word (tern ary) (tern ary) binary data before scram bling
Table
Upstream Downstream
Resulting tone Frequency: Duration: 2.13 when sending wakeup tone finished, signal ternary sent scrambled binary data scrambled binary data scrambled binary data
times +++++ ++---- ----
Data Sheet
2001-11-12
80902
Operational Description Table Generation 4B3T Signal Elements (cont'd) Duration: (warranted state machine) Binary data from digital interface Ternary continuous single pulses
once "+", times (repeatedl
Table
S/T-Interface Signals Signals from INFO INFO signal. continuous signal with following pattern: Positive ZERO, negative ZERO, ONEs.
Signals from INFO signal.
INFO
Frame with bits D-echo channels binary ZERO. binary ZERO. bits according normal coding rules. INFO Synchronized frames with operational data D-channels.
INFO
Frames with operational data D-echo channels. binary ONE.
Data Sheet
2001-11-12
80902
Operational Description
3.1.2
Complete Activation Initiated Exchange
S/T-Reference Point
U-Reference Point
INFO INFO
INFO INFO
INFO AR8/10
SBCX-X IPAC-X
DFE-T
actbyLT_TSMINT.vsd
Figure
Activation Initiated Exchange
Note: starts issuing signal before starts issuing U1A. This chronological order displayed clarification.
Data Sheet
2001-11-12
80902
Operational Description
3.1.3
Complete Activation Initiated
S/T-Reference Point
U-Reference Point
AR8/10
INFO INFO
INFO
INFO INFO INFO
INFO
SBCX-X IPAC-X DFE-T
actbyTE_TSMINT.vsd
Figure
Activation Initiated
Note: starts issuing signal before starts issuing U1A. This chronological order displayed clarification.
Data Sheet
2001-11-12
80902
Operational Description
3.1.4
Deactivation
S/T-Reference Point
U-Reference Point
INFO INFO
INFO INFO
DEAC
SBCX-X IPAC-X
DFE-T
deac_TSMINT.vsd
Figure
Deactivation (always Initiated
Data Sheet
2001-11-12
80902
Operational Description
3.1.5
Activation Procedures with Loopback
AR8/10 S/T-Reference Point INFO INFO U-Reference Point
2B+D (M-Bit=
LP2I
2B+D (M-Bit=
LP2I
2B+D
SBCX-X IPAC-X
DFE-T
act_loop2_TSMINT.vsd
Figure
Activation Loopback
Note: Closing/resolving loop provoke S-transceiver resynchronize. this case, following C/I-codes exchanged immediately reception AIL/AI, respectively: 'RSY', 'AI', 'AIL'/'AI'.
Data Sheet
2001-11-12
80902
Operational Description
Layer Loopbacks
Test loopbacks specified national PTTs order facilitate location defect systems. Four different loopbacks defined. position each loopback illustrated Figure
S-BUS Loop S-Transceiver
IOM®-2
Loop U-Transceiver
IOM®-2
Loop U-Transceiver U-Transceiver Loop U-Transceiver
IOM®-2
Loop Layer-1 Controller U-Transceiver
IOM®-2
Repeater (optional)
Exchange
IOM-2
Loop Layer-1 Controller U-Transceiver
loop_2b1q.emf
Figure
Test Loopbacks
Loopbacks controlled exchange. Loopback controlled locally remote side. four loopback types transparent. This means bits that looped back will also passed onwards normal manner. Only data looped back internally processed; signals receive pins ignored. propagation delay actually looped channels data must identical loopbacks.
3.2.1
Loopback No.2
following loopback type belongs loopback-#2 category: complete loopback (B1,B2,D), downstream device Normally loopback controlled exchange. maintenance channel used this purpose.
3.2.1.1
Complete Loopback
When receiving request complete loopback, transceiver passes S-bus transceiver. This achieved issuing C/I-code "Transparent" state states different than "Transparent"
Data Sheet
2001-11-12
80902
Operational Description
3.3.1
External Circuitry Power Supply Blocking Recommendation
following blocking circuitry suggested.
VDDa_UR VDDa_UX VDDa_SR VDDa_SX VDDD VDDD 100nF
3.3V
100nF
100nF
100nF
100nF
100nF
VSSD VSSD VSSa_SX VSSa_SR VSSa_UX VSSa_UR
These capacitors should located near pins possible
blocking_caps_Smint.vsd
Figure
Power Supply Blocking
3.3.2
U-Transceiver
T-SMINTO connected twisted pair transformer. Figure shows recommended external circuitry with external hybrid. recommended protection circuitry displayed.
Data Sheet
2001-11-12
80902
Operational Description
AOUT
RCOMP
Loop
RCOMP
BOUT
extcirc_U_Q2_exthybrid.emf
Figure
External Circuitry U-Transceiver with External Hybrid
U-Transformer Parameters following table lists parameters typical U-transformers. Table U-Transformer Parameters Symbol Value Unit
U-Transformer Parameters U-Transformer ratio; Device side Line side Main inductanc windings line side
Leakage inductance windings line side Coupling capacitance between windings device side windings line side resistance windings device side resistance windings line side
Data Sheet
2001-11-12
80902
Operational Description Resistors External Hybrid 1.75 Resistors RCOMP Optional trafos with negligible resistance requires compensation resistors RCOMP depending (2RCOMP Compliance with Return Loss Measurements: (2RCOMP Rout Table ROUT Table 15nF Capacitor achieve optimum performance 15nF capacitor should MKT. Ceramic capacitor recommended. Tolerances 15nF: 10-20% 7.5mH:
3.3.3
S-Transceiver
order comply physical requirements recommendation I.430 considering national requirements concerning overvoltage protection electromagnetic compatibility (EMC), S-transceiver needs some additional circuitry.
Data Sheet
2001-11-12
80902
Operational Description S-Transformer Parameters following Table lists parameters typical S-transformer: Table S-Transformer Parameters Symbol Value typ. typ. typ. <100 typ. typ. Unit
Transformer Parameters Transformer ratio; Device side Line side Main inductance windings line side
Leakage inductance windings line side Coupling capacitance between windings device side windings line side resistance windings device side resistance windings line side Transmitter
transmitter requires external resistors Rstx order adjust output voltage pulse mask (nominal according I.430, tested with test mode "TM1") hand order meet output impedance minimum other hand tested with testmode 'Continuous Pulses') other hand. Note: resistance S-transformer must taken into account when dimensioning external resistors Rstx. transmit path contains additional components (e.g. choke), then resistance these additional components must taken into account, too.
Data Sheet
2001-11-12
80902
Operational Description
20.40
Point
extcirc_S.vsd
Figure Receiver
External Circuitry S-Interface Transmitter
receiver S-transceiver symmetrical. overall resistance recommended each receive path. preferable split resistance into resistors each line. This allows place high resistance between transformer diode protection circuit (required pass input impedance test I.430 300012-1). remaining resistance (1.8 protects Stransceiver itself from input current peaks.
Point
extcirc_S.vsd
Figure
Data Sheet
External Circuitry S-Interface Receiver
2001-11-12
80902
Operational Description
3.3.4
Oscillator Circuitry
Figure illustrates recommended oscillator circuit.
XOUT 15.36
Figure Table Parameter Frequency
Crystal Oscillator Crystal Parameters Symbol Limit Values 15.36 +/-60 fundamental Unit
Frequency calibration tolerance Load capacitance Max. resonance resistance Max. shunt capacitance Oscillator mode External Components Parasitics
load capacitance computed from external capacitances CLD, parasitic capacitances CPar (pin capacitances ground VDD) stray capacitance between XOUT: specific crystal total load capacitance predefined, equation must solved external capacitances CLD, which usually only variable determined circuit designer. Typical values capacitances connected crystal
3.3.5
General
power LEDs
Data Sheet 2001-11-12
80902
Electrical Characteristics
Electrical Characteristics
Absolute Maximum Ratings
Symbol Limit Values Unit
Parameter Ambient temperature under bias Storage temperature Maximum Voltage ground
TSTG
-0.3 (max. 5.5)
Maximum Voltage with respect
integrity (according EIA/JESD22-A114B (HBM)): Note: Stress above those listed here cause permanent damage device. Exposure absolute maximum ratings conditions extended periods affect device reliability. Line Overload Protection compliant tests according ANSI ESD-S 5.1-1993 (CDM), EIA/JESD22-A114B (HBM) Latch-up tests according JEDEC JESD78. From these tests following max. input currents derived (Table 23):
Table Test Latch-up
Maximum Input Currents Pulse Width -Current +/-200 Remarks repetitions repetitions, respectively
Data Sheet
2001-11-12
80902
Electrical Characteristics
Characteristics
VDD/VDDA VSS/VSSA Digital Pins except DD/DU ACT,LP2I MCLK DD/DU ACT,LP2I MCLK Parameter Input voltage Input high voltage Output voltage Output high voltage Output voltage Output high voltage (DD/DU push-pull) Input leakage current Input leakage current (internal pull-up) Analog Pins AIN, Input leakage current
Symbol Limit Values min. VOL1 VOH1 VOL2 VOH2 ILIPU 0.45 -0.3 max. 5.25 0.45
Unit
Test Condition
IOL1 IOH1 IOL2 IOH2
Output leakage current
Table SX1,2
S-Transceiver Characteristics Symbol Limit Values min. typ. max. 2.31 2.03 Unit Test Condition
Parameter Absolute value output pulse amplitude (VSX2 VSX1) S-Transmitter output impedance
SX1,2
2)3)
SR1,2 S-Receiver input impedance
Data Sheet
2001-11-12
80902
Electrical Characteristics
Requirement ITU-T I.430, chapter 8.5.1.1a): times except when transmitting binary zero, output impedance frequency range 2kHz MHz, shall exceed impedance indicated template Figure requirement applicable with applied sinusoidal voltage (r.m.s value)' Requirement ITU-T I.430, chapter 8.5.1.1b): 'When transmitting binary zero, output impedance shall Must external circuitry. Requirement ITU-T I.430, chapter 8.5.1.1b), Note: 'The output impedance limit shall apply nominal load impedance (resistive) output impedance each nominal load shall defined determining peak pulse amplitude loads equal nominal value 10%. peak amplitude shall defined amplitude midpoint pulse. limitation applies pulses both polarities.'
Table
U-Transceiver Characteristics Limit Values min. typ. max. peak Unit
Receive Path Signal (noise total harmonic distortion) 652) DC-level AD-output Threshold level detect (measured between with respect zero signal) Input impedance AIN/BIN Transmit Path Signal (noise total harmonic distortion) Common mode DC-level Offset between AOUT BOUT Absolute peak voltage single pulse measured between AOUT BOUT5) Output impedance AOUT/BOUT: Power-up Power-down
1.65 1.69 2.58
1.61 2.42
Test conditions: differential sine wave input AIN/BIN with long range (low, critical range). Versions 8x913 with enhanced performance U-interface tested with tightened limit values percentage "-values PDM-signal. Interpretation test conditions: noise total harmonic distortion, weighted with pass filter kHz, least below signal evenly distributed otherwise random sequence signal amplitude measured over period min. varies less than
Data Sheet
2001-11-12
80902
Electrical Characteristics
Capacitances
VSSA VSSD MHz, unmeasured pins grounded. Table Parameter Digital pads: Input Capacitance Capacitance Analog pads: Load Capacitance Capacitances Symbol Limit Values Unit min. CI/O max. AIN, Remarks
Power Consumption
Power Consumption VDD=3.3 VSS=0 Inputs VSS/VDD, connected, bin. zeros, output loads except SX1,2 Parameter Operational enabled, Limit Values min. typ. Power Down
Unit Test Condition
max. ETSI loop ETSI Loop (typical line)
S-bus.
Supply Voltages
VDDD VDDA maximum sinusoidal ripple specified following figure:
Data Sheet
2001-11-12
80902
Electrical Characteristics
(peak) Supply Voltage Ripple
Frequency
ITD04269.vsd
Frequency Ripple
Figure
Maximum Sinusoidal Ripple Supply Voltage
Data Sheet
2001-11-12
80902
Electrical Characteristics
Characteristics
Inputs driven logical logical "0". Timing measurements made logical logical "0". testing input/output waveforms shown Figure
Test Points
0.45
Device Under Test
CLoad=50
ITS00621.vsd
Figure
Input/Output Waveform Tests
Parameter Output Pins Fall time Rise time
Symbol
Limit values
Unit
Data Sheet
2001-11-12
80902
Electrical Characteristics
4.6.1
IOM-2 Interface
DU/DD (Output) DU/DD (Output) first last
Figure
IOM®-2 Interface Synchronization Timing
Figure
IOM-2 Interface Frame Synchronization Timing
Note: start reset period, frame jump occur. This results high time min. after this specific event.
Data Sheet
2001-11-12
80902
Electrical Characteristics Parameter IOM®-2 Interface period high Symbol Limit values 1875 1953 2035 1105 1105 Unit
Output data from high impedance active (FSC high other than first timeslot) Output data from active high impedance Output data delay from clock high cycle time
advance DCL, rise/fall Data rise/fall tristate)
Data Sheet
2001-11-12
80902
Electrical Characteristics
4.6.2
Table Parameter
Reset
Reset Input Signal Characteristics Symbol tRST Limit Values min. typ. max. Power assumed long enough oscillator correctly After Power Unit Test Conditions
Length active state
clock cycles
tRST
ITD09823.vsd
Figure
Reset Input Signal
Data Sheet
2001-11-12
80902
Electrical Characteristics
4.6.3
Undervoltage Detection Characteristics
VDET
VHYS
VDDmin
RSTO
tACT
tACT
tDEACT
tDEACT
VDDDET.VSD
Figure Table
Undervoltage Control Timing Parameters UVD/POR Circuit
VDD= VSS= Parameter Detection Threshold Hysteresis Max. rising/falling edge activation/ deactivation Max. rising power-on2) Min. operating voltage VDDmin
Symbol min. VDET VHys dVDD/dt
Limit Values typ. max. 2.92
Unit Test Condition V/µs
Data Sheet
2001-11-12
80902
Electrical Characteristics VDD= VSS= Parameter Delay activation RSTO Delay deactivation RSTO
Symbol min. tACT tDEACT
Limit Values typ. max.
Unit Test Condition
Detection Threshold VDET below specified supply voltage range analog digital parts T-SMINT Therefore, board designer must take into account that range voltages existing, where neither performance functionality T-SMINT® guaranteed, reset generated. integrated Power-On Reset T-SMINTO selected (VDDDET '0') supply voltage ramped from 3.3V then T-SMINTO kept reset during VDDmin VDET VHys. must ramped slowly that T-SMINTO leaves reset state after oscillator circuit already finished start-up. start-up time oscillator circuit typically range between 12ms.
Data Sheet
2001-11-12
80902
Package Outlines
Package Outlines
Plastic Package, P-MQFP-44 (Metric Quad Flat Package)
Data Sheet
2001-11-12
80902
Appendix: Differences between T-SMINT,O
Appendix: Differences between
Especially compatibility between allows single design both series with only some mounting differences. following chapter summarizes main differences between
have been designed compatible possible. However, some differences between them unavoidable different line codes 2B1Q 4B3T used data transmission line.
6.1.1
Pinning Definitions Functions
Definitions Functions 2B1Q Triple-Last-Look (TLL) Metallic Termination Input (MTI) Auto Activation (AUA) Cold Start Only (CSO) Power Status (primary) (PS1) Power Status (secondary) (PS2) 4B3T
Table MQFP-44
6.1.2
states (off, fast flashing, slow flashing, on), which displayed with ACT, slightly different (see Table 30). Table States 2B1Q fast flashing States 4B3T
Data Sheet
2001-11-12
80902
Appendix: Differences between T-SMINT,O Table States 2B1Q slow flashing States (cont'd) 4B3T
Note: denotes duty cycle 'high' 'low'.
6.2.1
U-Transceiver U-Interface Conformity
Related Documents U-Interface 2B1Q 4B3T conform annex conform annex compliant interruptions
Table
ETSI:
ANSI: T1.601-1998 (Revision ANSI T1.6011992) CNET: ST/LAA/ELR/DNP/ RC7355E FTZ-Richtlinie
conform required input decode logic conform conform required required required conform
Data Sheet
2001-11-12
80902
Appendix: Differences between T-SMINT,O
6.2.2
U-Transceiver State Machines
T14S
T14E T14S
Pending Timing
T14S
Deactivated
State C/I= 'SSP'
Test
Awaked
Reset State Pin-RST C/I= 'RES'
NT-AUTO
T1S, T11S
T11E T12S
Alerting
T12S
T11S
Alerting
T11E T12S
T1S, T11S
EC-Training
LSEC T12E LSUE
EC-Training
EC-Training
LSEC T12E
act=0 Wait
BBD1
EQ-Training
T20S
BBD0
SN3T act=0 Analog Loop Back
LSUE
T20E BBD0
Wait
dea=0 LSUE uoa=0 dea=0 LSUE uoa=0 dea=0 LSUE
SN3/SN3T act=1/0 Pend.Deact.
LSUE
dea=0
SN3/SN3T act=0 Synchronized
uoa=1
SN3/SN3T act=0 Synchronized AR/ARL
SN3/SN3T act=1 Wait AR/ARL
act=1 act=0
State C/I='DT'
act=1 SN3T Transparent AI/AIL
act=1
uoa=0 dea=0 LSUE
Pend Receive Res. T13S
/LOF T13E
SN3/SN3T act=0 Error act=0 AR/ARL
dea=0 uoa=0 LSUE
uoa=1
dea=1
SN3/SN3T act=1/0 Pend.Deact.
Receive Reset
Figure
NTC-Q Compatible State Machine 2B1Q
Data Sheet
2001-11-12
80902
Appendix: Differences between T-SMINT,O
Awaked Start Awaking Awake Signal Sent T13S T13E Ack. Sent Received T05E) T12S Synchronizing T12E) T05S Pend. Deactivation T05S Synchronizing Test STATE Reset T13S Sending Awake-Ack. T13S T05S T05S T05E Deactivating Deactivated
Wait Info
Transparent Loss Framing
NT_SM_4B3T_cust.emf
Figure
IEC-T/NTC-T Compatible State Machine 4B3T
Data Sheet
2001-11-12
80902
Appendix: Differences between T-SMINT,O
6.2.3
Table Code
Command/Indication Codes
Codes 2B1Q 4B3T
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Data Sheet
2001-11-12
80902
Appendix: Differences between T-SMINT,O
External Circuitry
external circuitry equivalent; however, some external components U-transceiver hybrid must dimensioned different 2B1Q 4B3T. information external circuitry preliminary changed future documents.
AOUT
RCOMP
RPTC
Loop
RCOMP
RPTC
BOUT
extcirc_U_Q2_exthybrid.emf
Figure
External Circuitry
Note: necessary protection circuitry displayed Figure Table Component Transformer: Ratio Main Inductivity Resistance Resistance Resistance Capacitor RPTC RComp
Data Sheet
Dimensions External Components 2B1Q 14.5 2RPTC 8RComp
4B3T 1:1.6 1.75 (2RCOMP
2001-11-12
80902
Index
Index
Package Outlines Configuration Definitions Functions Power Consumption Power Supply Blocking Power-On Reset
Absolute Maximum Ratings
Block Diagram
Codes U-Transceiver
Reset Generation Input Signal Characteristics Power-On Reset Under Voltage Detection
Characteristics Differences between T-SMINT
Channels Scrambler Descrambler S-Transceiver Functional Description State Machine, Supply Voltages System Integration
External Circuitry S-Transceiver U-Transceiver
Features
IOM®-2 Interface Characteristics Frame Structure Functional Description
Test Modes
U-Interface Hybrid Under Voltage Detection U-Transceiver 4B3T Frame Structure Functional Description State Machine
Layer Activation Deactivation Loopbacks Pins Line Overload Protection
Maintenance Channel
Oscillator Circuitry
Data Sheet
2001-11-12
Infineon goes Business Excellence
"Business excellence means intelligent approaches clearly defined processes, which both constantly under review ultimately lead good operating results. Better operating results business excellence mean less idleness wastefulness more professional success, more accurate information, better overview and, thereby, less frustration more satisfaction."
Ulrich Schumacher
http://www.infineon.com
Published Infineon Technologies

80902 Version Wired Edition 2001-11-12 Published Infineon Te

Top Searches for this datasheet

Other recent searches