SAA55xx Standard microcontrollers with On-Screen Display (OSD) Pr
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SAA55xx Standard microcontrollers with On-Screen Display (OSD)
Preliminary specification File under Integrated Circuits, IC02 1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
CONTENTS 10.1 10.2 10.3 11.1 11.2 11.3 11.4 12.1 12.2 12.3 12.4 14.1 15.1 15.2 15.3 16.1 17.1 FEATURES GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION Pinning description MICROCONTROLLER Microcontroller features MEMORY ORGANISATION Security bits program verify organisation Data memory memory Character feature bits External (auxiliary) memory POWER-ON RESET REDUCED POWER MODES Idle mode Power-down mode Standby mode FACILITY ports Port type Port alternate functions support INTERRUPT SYSTEM Interrupt enable structure Interrupt enable priority Interrupt vector address Level/edge interrupt TIMER/COUNTER WATCHDOG TIMER Watchdog Timer operation PULSE WIDTH MODULATORS control Tuning Pulse Width Modulator (TPWM) Software (SAD) I2C-BUS SERIAL I2C-bus port selection MEMORY INTERFACE Memory structure 17.2 17.3 17.4 18.1 18.2 18.3 18.4 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 19.10 19.11 19.12 19.13 19.14 22.1 23.1 23.2 23.3 27.1 27.2 27.3 27.4 Memory mapping Addressing memory Page clearing DATA CAPTURE
SAA55xx
Data Capture Features Broadcast service data detection acquisition acquisition DISPLAY Display features Display mode Display feature descriptions Character attribute coding Screen global controls Screen colour Text display control Display positioning Character Display synchronization Video/data switch (fast blanking) polarity Video/data switch adjustment brightness control Contrast reduction MEMORY MAPPED REGISTERS LIMITING VALUES CHARACTERISTICS I2C-bus characteristics QUALITY RELIABILITY Group Group Group APPLICATION INFORMATION ELECTROMAGNETIC COMPATIBILITY (EMC) GUIDELINES PACKAGE OUTLINE SOLDERING Introduction soldering through-hole mount packages Soldering dipping solder wave Manual soldering Suitability through-hole mount packages dipping wave soldering methods DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE PHILIPS COMPONENTS
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
FEATURES
SAA55xx
Single-chip microcontroller with integrated On-Screen Display (OSD) Versions available with integrated data capture Time Programmable (OTP) memory both program Read Only Memory (ROM) character sets Single power supply: tolerant digital inputs lines individual addressable controls Programmable push-pull, open-drain quasi-bidirectional port lines with sink <0.4 capability, direct drive Light Emitting Diode (LED) Single crystal oscillator microcontroller, data capture Power reduction modes: Idle Power-down Byte level I2C-bus with dual port compatibility throughout family Operating temperature: GENERAL DESCRIPTION
SAA55xx standard family microcontrollers derivative Philips industry-standard 80C51 microcontroller, intended central control mechanism television receiver. They provide control functions television system, OSD, some versions include integrated data capture display function. data capture hardware capability decoding displaying both 625-line World System Teletext (WST), Video Programming System (VPS) Wide Screen Signalling (WSS) information. same display hardware used both Teletext OSD, which means that display features available give greater flexibility differentiate set. SAA55xx standard family offers range functionality from non-text, 16-kbyte program 256-byte Random Access Memory (RAM), 10-page text version, 64-kbyte program 1.2-kbyte RAM.
QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT
Supply VDDX IDDP IDDC IDDC(id) IDDC(pd) IDDC(stb) IDDA IDDA(id) IDDA(pd) IDDA(stb) fxtal Tamb Tstg supply voltage (VDD VSS) periphery supply current core supply current Idle mode core supply current Power-down mode core supply current Standby mode core supply current analog supply current Idle mode analog supply current Power-down mode analog supply current Standby mode analog supply current crystal frequency operating ambient temperature storage temperature 0.76 5.11 0.87 0.45 0.95 6.50 1.20 +125
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
ORDERING INFORMATION PACKAGE(2) NAME SAA5500PS/nnnn SAA5501PS/nnnn SAA5502PS/nnnn SAA5503PS/nnnn SAA5520PS/nnnn SAA5521PS/nnnn SAA5522PS/nnnn SAA5523PS/nnnn SAA5551PS/nnnn SAA5552PS/nnnn SAA5553PS/nnnn Notes `nnnn' four digit number uniquely referencing microcontroller program mask. details LQFP100 package, please contact your local regional office availability. SDIP52 DESCRIPTION plastic shrink dual in-line package; leads (600 mil) VERSION SOT247-1 16-kbyte 32-kbyte 48-kbyte 64-kbyte 16-kbyte 32-kbyte 48-kbyte 64-kbyte 32-kbyte 48-kbyte 64-kbyte
SAA55xx
TYPE NUMBER(1)
256-byte 512-byte 256-byte 512-byte 256-byte 512-byte 750-byte 1-kbyte 750-byte 1-kbyte 1.2-kbyte
TEXT PAGES
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
BLOCK DIAGRAM
SAA55xx
handbook, full pagewidth
I2C-bus, general
CONTROL INTERFACE
64-KBYTE)
MICROPROCESSOR (80C51)
SRAM (256-BYTE)
DRAM 12-KBYTE)
MEMORY INTERFACE
CVBS DATA CAPTURE DISPLAY
CVBS
DATA CAPTURE TIMING
DISPLAY TIMING
GSA029
VSYNC HSYNC
Fig.1 Block diagram (top level architecture).
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
PINNING INFORMATION Pinning
SAA55xx
handbook, halfpage
P2.0/TPWM P2.1/PWM0 P2.2/PWM1 P2.3/PWM2 P2.4/PWM3 P2.5/PWM4 P2.6/PWM5 P2.7/PWM6 P3.0/ADC0
P1.5/SDA1 P1.4/SCL1 P1.7/SDA0 P1.6/SCL0 P1.3/T1 P1.2/INT0 P1.1/T0 P1.0/INT1 VDDP RESET XTALOUT XTALIN OSCGND
P3.1/ADC1 P3.2/ADC2 P3.3/ADC3 VSSC P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 VSSA CVBS0 CVBS1 SYNC_FILTER IREF
MBK951
SAA55xx
VDDC VSSP VSYNC HSYNC VDDA P3.4/PWM7 FRAME
Fig.2 SDIP52 configuration.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
SAA55xx
P2.0/TPWM
P2.6/PWM5
P2.5/PWM4
P2.4/PWM3
P2.3/PWM2
P2.2/PWM1
P2.1/PWM0
P1.5/SDA1
P1.7/SDA0
P1.4/SCL1
P1.6/SCL0
P1.2/INT0
handbook, full pagewidth
P2.7/PWM6 P3.0/ADC0 n.c. P3.1/ADC1 P3.2/ADC2 P3.3/ADC3 n.c. n.c. n.c.
P1.0/INT1 VDDP n.c. RESET n.c. XTALOUT XTALIN OSCGND n.c. n.c. n.c. n.c. n.c. VDDC VPE_2 n.c. VSSP P3.6 n.c. n.c. n.c. VSYNC P3.5 HSYNC n.c. n.c.
GSA001
P1.3/T1
P1.1/T0
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c. VSSC VSSP P0.5 n.c. n.c. P0.0 P0.1 P0.2 n.c. n.c. n.c. P0.3 n.c. P0.4 P3.7 n.c. n.c. P0.6 P0.7 VSSA CVBS0 CVBS1 n.c. SYNC_FILTER IREF n.c. n.c. n.c. n.c. n.c. FRAME P3.4/PWM7 VDDA n.c.
SAA55xx
Fig.3 LQFP100 configuration.
1999
n.c.
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
description SDIP52 LQFP100 packages SYMBOL SDIP52 P2.0/TPWM P2.1/PWM0 P2.2/PWM1 P2.3/PWM2 P2.4/PWM3 P2.5/PWM4 P2.6/PWM5 P2.7/PWM6 P3.0/ADC0 P3.1/ADC1 P3.2/ADC2 P3.3/ADC3 P3.4/PWM7 P3.5 P3.6 P3.7 VSSC P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 VSSA CVBS0 CVBS1 SYNC_FILTER IREF FRAME LQFP100 analog ground core ground TYPE DESCRIPTION
SAA55xx
Table
Port 8-bit programmable bidirectional port with alternative functions. P2.0/TPWM output 14-bit high precision P2.1/PWM0 P2.7/PWM6 outputs 6-bit PWMs
Port 8-bit programmable bidirectional port with alternative functions. P3.0/ADC0 P3.3/ADC3 inputs software facility P3.4/PWM7 output 6-bit PWM7. P3.5 P3.7 have alternative functions only available with LQFP100 package.
Port 8-bit programmable bidirectional port. P0.5 P0.6 have current sinking capability direct drive LEDs.
Composite video input. positive-going (peak-to-peak) input required; connected capacitor. CVBS sync filter input. This should connected VSSA capacitor. Reference current input analog circuits, connected VSSA resistor. De-interlace output synchronized with VSYNC pulse produce non-interlaced display adjustment vertical deflection circuits. programming voltage
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
SYMBOL SDIP52 LQFP100 TYPE DESCRIPTION
SAA55xx
Open-drain, active output which allows selective contrast reduction picture enhance mixed mode display. +3.3 analog power supply Pixel rate output BLUE colour information. Pixel rate output GREEN colour information. Pixel rate output colour information. Video/data switch push-pull output rate fast blanking. Schmitt triggered input TTL-level version horizontal sync pulse; polarity this pulse programmable register TXT1.H POLARITY. Schmitt triggered input TTL-level version vertical sync pulse; polarity this pulse programmable register TXT1.V POLARITY. periphery ground +3.3 core power supply crystal oscillator ground crystal oscillator input crystal oscillator output reset input HIGH least machine cycles oscillator periods) while oscillator running, device reset; this should connected VDDP capacitor. +3.3 periphery power supply Port 8-bit programmable bidirectional port with alternative functions. P1.0/INT1 external interrupt which triggered rising falling edge pulse. P1.1/T0 counter/Timer P1.2/INT0 external interrupt P1.3/T1 counter/Timer P1.6/SCL0 serial clock input I2C-bus P1.7/SDA0 serial data port I2C-bus. P1.4/SCL1 serial clock input I2C-bus. P1.5/SDA1 serial data port I2C-bus. programming voltage connected
VDDA HSYNC
VSYNC
VSSP VDDC OSCGND XTALIN XTALOUT RESET
VDDP P1.0/INT1 P1.1/T0 P1.2/INT0 P1.3/T1 P1.6/SCL0 P1.7/SDA0 P1.4/SCL1 P1.5/SDA1 VPE_2 n.c.
10,14,
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
MICROCONTROLLER MEMORY ORGANIZATION
SAA55xx
functionality microcontroller used this device described here with reference industry standard 80C51 microcontroller. full description functionality found "Handbook IC20, 80C51-Based 8-bit Microcontrollers". Microcontroller features
device capability maximum 64-kbyte Program 1.2-kbyte Data internally. Security bits program verify
80C51 microcontroller core standard instruction timing machine cycle Maximum 8-bit Program Maximum 1.2K 8-bit Auxiliary Interrupt Controller individual enable/disable with level priority 16-bit Timer/Counter registers Watchdog Timer Auxiliary page pointer 16-bit Data pointer Idle Power-down modes general lines Eight 6-bit Pulse Width Modulator (PWM) outputs control analog signals 14-bit Voltage Synthesis Tuner (VST) control 8-bit Analog-to-Digital Converter (ADC) with multiplexed inputs high current outputs directly driving LEDs I2C-bus byte level interface with dual ports.
SAA55xx devices have security bits allied with each section device, i.e. Program ROM, Character Packet ROM. security bits used prevent from being overwritten once programmed, also contents being verified once programmed. security bits one-time programmable cannot erased. SAA55xx memory security bits structured shown Fig.4. SAA55xx security bits shown Fig.5 production programmed devices shown Fig.6 production blank devices. organisation
internal Data organised into areas, Data memory Special Function Registers (SFRs) shown Fig.7. Data memory
Data memory 8-bit occupies address range when using indirect addressing when using direct addressing. SFRs occupy address range accessible using direct addressing only. lower bytes Data memory mapped shown Fig.8. lowest bytes grouped into banks registers, next bytes above register banks form block addressable memory space. upper bytes allocated special area functions.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
SAA55xx
handbook, full pagewidth MEMORY
SECURITY BITS INTERACTION
USER PROGRAMMING (ENABLE/DISABLE) VERIFY (ENABLE/DISABLE)
PROGRAM
USER (64K 8-BIT)
CHARACTER
USER PROGRAMMING (ENABLE/DISABLE)
VERIFY (ENABLE/DISABLE)
USER 12-BIT)
PACKET
USER PROGRAMMING (ENABLE/DISABLE)
VERIFY (ENABLE/DISABLE)
USER 8-BIT)
GSA030
Fig.4 Memory security structures.
handbook, full pagewidth MEMORY
SECURITY BITS
USER PROGRAMMING (ENABLE/DISABLE) VERIFY (ENABLE/DISABLE) ENABLED
PROGRAM
DISABLED
CHARACTER
DISABLED
ENABLED
PACKET
DISABLED
ENABLED
MBK954
Fig.5 Security bits production devices.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
SAA55xx
handbook, full pagewidth MEMORY
SECURITY BITS
USER PROGRAMMING (ENABLE/DISABLE) VERIFY (ENABLE/DISABLE) ENABLED
PROGRAM
ENABLED
CHARACTER
ENABLED
ENABLED
PACKET
ENABLED
ENABLED
MBK955
Fig.6 Security bits production blank devices.
handbook, halfpage
DATA MEMORY
SPECIAL FUNCTION REGISTERS
upper bytes lower bytes accessible direct indirect addressing
MBK956
accessible indirect addressing only
accessible direct addressing only
Fig.7 Internal Data memory.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
SAA55xx
handbook, halfpage
bit-addressable space (bit addresses 7FH) banks registers
MGM677
Fig.8 Lower bytes internal RAM.
1999
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Standard microcontrollers with On-Screen Display (OSD)
Special Function Register (SFR) space used port latches, timer, peripheral control, acquisition control, display control. These registers only accessed direct addressing. Sixteen addresses space both byte addressable. addressable SFRs those whose address ends summary address order shown Table description each bits shown Table which presents SFRs alphabetical order. Table memory NAMES DPL7 DPH7 GATE TL07 TL17 TH07 TH17 P0CFGA7 P0CFGB7 P1CFGA7 P1CFGB7 P2CFGA7 P2CFGB7 NOT3 DPL6 DPH6 TL06 TL16 TH06 TH16 P0CFGA6 P0CFGB6 P1CFGA6 P1CFGB6 P2CFGA6 P2CFGB6 EBUSY NOT2 DPL5 DPH5 TL05 TL15 TH05 TH15 P0CFGA5 P0CFGB5 P1CFGA5 P1CFGB5 P2CFGA5 P2CFGB5 NOT1 DPL4 DPH4 TL04 TL14 TH04 TH14 P0CFGA4 P0CFGB4 DC_COMP P1CFGA4 P1CFGB4 P2CFGA4 P2CFGB4 NOT0 DPL3 DPH3 GATE TL03 TL13 TH03 TH13 P0CFGA3 P0CFGB3 SAD3 P1CFGA3 P1CFGB3 P2CFGA3 P2CFGB3 LANG ENABLE DPL2 DPH2 TL02 TL12 TH02 TH12 P0CFGA2 P0CFGB2 SAD2 P1CFGA2 P1CFGB2 P2CFGA2 P2CFGB2 LAN2 DPL1 DPH1 TL01 TL11 TH01 TH11 P0CFGA1 P0CFGB1 SAD1 P1CFGA1 P1CFGB1 P2CFGA1 P2CFGB1 LAN1 DPL0 DPH0 TL00 TL10 TH00 TH10 P0CFGA0 P0CFGB0 SAD0 P1CFGA0 P1CFGB0 P2CFGA0 P2CFGB0 LAN0 RESET
PCON TCON TMOD P0CFGA P0CFGB SADB P1CFGA P1CFGB P2CFGA P2CFGB TXT18 TXT19 TXT20
Preliminary specification
SAA55xx
This text here white force landscape pages rotated correctly when browsing through Acrobat reader.This text here _white force landscape pages rotated correctly when browsing through Acrobat reader.This text here inThis text here white force landscape pages rotated correctly when browsing through Acrobat reader. white force landscape pages 1999 Philips Semiconductors NAMES TXT22 GPF7 WSS<13:11> ERROR POSN GPF6 PBUSY FORCE ACQ1 WSS13 DISPLAY 8-BIT REQ3 QUAD WIDTH ENABLE PES2 FORCE ACQ0 WSS12 AUTO FRAME REQ2 EAST/WEST GPF4 FORCE DISP1 WSS<3:0> ERROR WSS<7:4> ERROR WSS11 P3CFGA4 P3CFGB4 DISABLE HEADER ROLL REQ1 PRD4 DISABLE DOUBLE HEIGHT BOTTOM /TOP DISABLE SPANISH PORT FORCE DISP0 WSS3 WSS7 WSS<10:8> ERROR P3CFGA3 P3CFGB3 DISPLAY STATUS ONLY FULL FIELD REQ0 PRD3 MESH ENABLE TEXT TEXT DOUBLE HEIGHT RECEIVED GPF3 SCREEN COL2 WSS2 WSS6 WSS10 P3CFGA2 P3CFGB2 DISABLE FRAME FIELD POLARITY PRD2 MESH ENABLE TEXT TEXT RECEIVED PORT SCREEN COL1 WSS1 WSS5 WSS9 P3CFGA1 P3CFGB1 GPF1 GPF0 SCREEN COL0 WSS0 WSS4 WSS8 P3CFGA0 P3CFGB0 RESET
Standard microcontrollers with On-Screen Display (OSD)
TXT21 TXT17 WSS1 WSS2 WSS3
P3CFGA P3CFGB TXT0
TXT1 TXT2 TXT3 TXT4
BANK BANK ENABLE
POLARITY PRD1 TRANS ENABLE PICTURE PICTURE
POLARITY PRD0 SHADOW ENABLE PICTURE PICTURE CVBS1/ CVBS0
TXT5 TXT6 TXT7 TXT8 TXT9
BKGND BKGND BKGND BKGND STATUS (reserved) CURSOR FREEZE CURSOR FLICKER STOP CLEAR MEMORY
REVEAL (reserved)
Preliminary specification
SAA55xx
TXT10 TXT11
This text here white force landscape pages rotated correctly when browsing through Acrobat reader.This text here _white force landscape pages rotated correctly when browsing through Acrobat reader.This text here inThis text here white force landscape pages rotated correctly when browsing through Acrobat reader. white force landscape pages 1999 Philips Semiconductors NAMES TXT12 525/625 SYNC TPWE PW7E PW0E PW1E STAT4 DAT7 ADR6 PW3E PW4E PW5E PW6E ACC7 PW2E RECEIVED XRAMP7 STANDBY WKEY7 WDV7 SPANISH VER3 VER2 VER1 VER0 VIDEO SIGNAL QUALITY PAGE0 BLOCK0 PW7V0 PW0V0 PW1V0 DAT0 PW3V0 PW4V0 PW5V0 PW6V0 ACC0 PW2V0 SAD4 XRAMP0 (reserved) WKEY0 WDV0 RESET XXXX XX1X XXXX XXX0 Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
TXT14 TXT15 TDACL TDACH PWM7 PWM0 PWM1 S1CON S1STA
ENSI STAT3 DAT6 ADR5 ACC6
TD13 PW7V5 PW0V5 PW1V5 STAT2 DAT5 ADR4 PW3V5 PW4V5 PW5V5 PW6V5 ACC5 PW2V5
TD12 PW7V4 PW0V4 PW1V4 STAT1 DAT4 ADR3 PW3V4 PW4V4 PW5V4 PW6V4 ACC4 PW2V4 TEXT XRAMP4 WKEY4 WDV4
PAGE3 BLOCK3 TD11 PW7V3 PW0V3 PW1V3 STAT0 DAT3 ADR2 PW3V3 PW4V3 PW5V3 PW6V3 ACC3 PW2V3 SAD7 TEXT XRAMP3 WKEY3 WDV3
PAGE2 BLOCK2 TD10 PW7V2 PW0V2 PW1V2 DAT2 ADR1 PW3V2 PW4V2 PW5V2 PW6V2 ACC2 PW2V2 SAD6 8/30 XRAMP2 WKEY2 WDV2
PAGE1 BLOCK1 PW7V1 PW0V1 PW1V1 DAT1 ADR0 PW3V1 PW4V1 PW5V1 PW6V1 ACC1 PW2V1 SAD5 FASTEXT XRAMP1 (reserved) WKEY1 WDV1
S1DAT S1ADR PWM3 PWM4 PWM5 PWM6 PWM2 TXT13
PAGE DISPLAY CLEARING XRAMP6 WKEY6 WDV6 XRAMP5 WKEY5 WDV5
XRAMP ROMBK WDTKEY
SAA55xx
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
Table description Accumulator (ACC) ACC7 ACC0 Register Data Pointer High byte (DPH) DPH7 DPH0 Data Pointer byte (DPL) DPL7 DPL0 Interrupt Enable Register (IE) EBUSY Interrupt Priority Register (IP) PBUSY PES2 Port (P0) Port (P1) Port (P2) Port (P3) Port register connected external pins Port register connected external pins Port register connected external pins priority EBUSY interrupt priority interrupt priority interrupt priority Timer interrupt priority external interrupt priority Timer interrupt priority external interrupt register value accumulator value FUNCTION
SAA55xx
data pointer high byte, used with address auxiliary memory
data pointer byte, used with address auxiliary memory
disable interrupts (logic individual interrupt enable bits (logic enable BUSY interrupt enable I2C-bus interrupt enable Timer interrupt enable external interrupt enable Timer interrupt enable external interrupt
Port register connected external pins; only available with LQFP100 package
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
FUNCTION
SAA55xx
Port Configuration (P0CFGA) Port Configuration (P0CFGB) P0CFGA<7:0> P0CFGB<7:0> These registers used configure Port pins. example, configuration Port controlled setting both P0CFGA P0CFGB. P0CFGB<x>/P0CFGA<x>: P0.x open-drain configuration P0.x quasi-bidirectional configuration P0.x high-impedance configuration P0.x push-pull configuration Port Configuration (P1CFGA) Port Configuration (P1CFGB) P1CFGA<7:0> P1CFGB<7:0> These registers used configure Port pins. example, configuration Port controlled setting both P1CFGA P1CFGB. P1CFGB<x>/P1CFGA<x>: P1.x open-drain configuration P1.x quasi-bidirectional configuration P1.x high-impedance configuration P1.x push-pull configuration Port Configuration (P2CFGA) Port Configuration (P2CFGB) P2CFGA<7:0> P2CFGB<7:0> These registers used configure Port pins. example, configuration Port controlled setting both P2CFGA P2CFGB. P2CFGB<x>/P2CFGA<x>: P2.x open-drain configuration P2.x quasi-bidirectional configuration P2.x high-impedance configuration P2.x push-pull configuration Port Configuration (P3CFGA) Port Configuration (P3CFGB) P3CFGA<7:0> P3CFGB<7:0> These registers used configure Port pins. example, configuration Port controlled setting both P3CFGA P3CFGB. P3CFGB<x>/P3CFGA<x>: P3.x open-drain configuration P3.x quasi-bidirectional configuration P3.x high-impedance configuration P3.x push-pull configuration
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
Power Control Register (PCON) Program Status Word (PSW) carry auxiliary carry flag register bank selector bits RS<1:0>: Bank (00H 07H) Bank (08H 0FH) Bank (10H 17H) Bank (18H 1FH) overflow flag parity FUNCTION
SAA55xx
auxiliary disable bit, MOVX instructions access external data memory disable during internal access reduce radio frequency interference Watchdog Timer enable general purpose flag general purpose flag Power-down mode activation Idle mode activation
Pulse Width Modulator Control Register (PWM0) PW0E PW0V5 PW0V0 activate this take control respective port (logic pulse width modulator high time
Pulse Width Modulator Control Register (PWM1) PW1E PW1V5 PW1V0 activate this (logic pulse width modulator high time
Pulse Width Modulator Control Register (PWM2) PW2E PW2V5 PW2V0 activate this (logic pulse width modulator high time
Pulse Width Modulator Control Register (PWM3) PW3E PW3V5 PW3V0 activate this (logic pulse width modulator high time
Pulse Width Modulator Control Register (PWM4) PW4E PW4V5 PW4V0 activate this (logic pulse width modulator high time
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
Pulse Width Modulator Control Register (PWM5) PW5E PW5V5 PW5V0 activate this (logic pulse width modulator high time FUNCTION
SAA55xx
Pulse Width Modulator Control Register (PWM6) PW6E PW6V5 PW6V0 activate this (logic pulse width modulator high time
Pulse Width Modulator Control Register (PWM7) PW7E PW7V5 PW7V0 Bank (ROMBK) STANDBY standby activation activate this (logic pulse width modulator high time
I2C-bus Slave Address Register (S1ADR) ADR6 ADR0 I2C-bus Control Register (S1CON) clock rate bits; CR<2:0>: rate 3.75 rate rate rate rate 1.875 rate 37.5 rate rate ENSI enable I2C-bus interface (logic START flag. When this slave mode, hardware checks I2C-bus generates START condition free after becomes free. device operates master mode will generate repeated START condition. STOP flag. this master mode STOP condition generated. STOP condition detected I2C-bus clears this bit. This also slave mode order recover from error condition. this case STOP condition generated I2C-bus, hardware releases lines switches selected receiver mode. STOP flag cleared hardware. I2C-bus slave address which device will respond enable I2C-bus general call address (logic
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
FUNCTION
SAA55xx
Serial Interrupt flag. This flag interrupt request generated, after following events occur: START condition generated master mode slave address been received during general call address been received while S1ADR.GC data byte been received transmitted master mode (even arbitration lost) data byte been received transmitted selected slave STOP START condition received selected slave receiver transmitter. While flag set, remains serial transfer suspended. must reset software.
Assert Acknowledge flag. When this set, acknowledge returned after following conditions: slave address received General call address received (S1ADR.GC data byte received, while device programmed master receiver data byte received, while device selected slave receiver. When reset, acknowledge returned. Consequently, interrupt requested when address general call address received.
I2C-bus Data Register (S1DAT) DAT7 DAT0 I2C-bus Status Register (S1STA) STAT4 STAT0 Software Register (SAD) analog input voltage greater than voltage (logic input channel select bits; CH<1:0>: ADC3 ADC0 ADC1 ADC2 ST(1) SAD7 SAD4 initiate voltage comparison between input channel value MSBs input word I2C-bus interface status I2C-bus data
Software Control Register (SADB) DC_COMP SAD3 SAD0 Stack Pointer (SP) stack pointer value enable comparator mode (logic LSBs value
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
Timer/Counter Control Register (TCON) FUNCTION
SAA55xx
Timer overflow flag. hardware timer/counter overflow. Cleared hardware when processor vectors interrupt routine. Timer control bit. Set/cleared software turn timer/counter on/off. Timer overflow flag. hardware timer/counter overflow. Cleared hardware when processor vectors interrupt routine. Timer control bit. Set/cleared software turn timer/counter on/off. Interrupt Edge flag. Both edges generate flag. hardware when external interrupt edge detected. Cleared hardware when interrupt processed. Interrupt type control bit. Set/cleared software specify edge/LOW level triggered external interrupts. Interrupt Edge flag. hardware when external interrupt edge detected. Cleared hardware when interrupt processed. Interrupt type flag. Set/cleared software specify falling edge/LOW level triggered external interrupts.
14-bit Register (TDACH) TPWE TD13 14-bit Register (TDACL) Timer High byte (TH0) TH07 TH00 Timer High byte (TH1) TH17 TH10 Timer byte (TL0) TL07 TL00 Timer byte (TL1) TL17 TL10 LSBs Timer 16-bit counter LSBs Timer 16-bit counter MSBs Timer 16-bit counter MSBs Timer 16-bit counter LSBs 14-bit number output 14-bit activate this 14-bit (logic MSBs 14-bit number output 14-bit
Timer/Counter Mode Control (TMOD) GATE gating control Timer/Counter Counter/Timer selector mode control bits timer/counter M<1:0>: 8-bit timer 8-bit counter with divide-by-32 prescaler 16-bit time interval event counter 8-bit time interval event counter with automatic reload upon overflow; reload value stored stopped GATE Gating control Timer/Counter Counter/Timer selector
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
FUNCTION mode control bits timer/counter M<1:0>: 8-bit timer 8-bit counter with divide-by-32 prescaler 16-bit time interval event counter
SAA55xx
8-bit time interval event counter with automatic reload upon overflow; reload value stored 8-bit time interval event counter 8-bit time interval counter Text Register (TXT0) POSN DISPLAY AUTO FRAME DISABLE HEADER ROLL DISPLAY STATUS ONLY DISABLE FRAME Text Register (TXT1) 8-BIT FULL FIELD FIELD POLARITY POLARITY POLARITY Text Register (TXT2) BANK REQ3 REQ0 Text Register (TXT3) PRD4 PRD0 Text Register (TXT4) BANK ENABLE QUAD WIDTH ENABLE EAST/WEST DISABLE DOUBLE HEIGHT MESH ENABLE MESH ENABLE TRANS ENABLE SHADOW ENABLE 1999 alternate location available graphic attribute, additional locations (logic enable display quadruple width characters (logic eastern language selection character codes (logic disable normal decoding double height characters (logic enable meshing black background (logic enable meshing coloured background (logic display black background video (logic display shadow/fringe (default black) (logic page request data select acquisition Bank (logic page request start column page request disable acquisition extension packets (logic disable checking packets written into memory (logic disable writing data into Display memory (logic disable automatic processing X/26 data (logic acquire data line (logic VSYNC pulse second half line during even field (logic HSYNC reference edge negative going (logic VSYNC reference edge negative going (logic store packet extension packet memory (logic page memory (logic display from page memory (logic extension packet memory (logic FRAME output switched automatically video displayed (logic disable writing rolling headers time into memory (logic display only (logic FRAME output always (logic enable capture data (logic enable capture inventory page block (logic
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
Text Register (TXT5) BKGND BKGND TEXT TEXT PICTURE PICTURE Text Register (TXT6) BKGND BKGND TEXT TEXT PICTURE PICTURE Text Register (TXT7) STATUS CURSOR REVEAL BOTTOM/TOP DOUBLE HEIGHT Text Register (TXT8) FLICKER STOP DISABLE SPANISH RECEIVED(2) RECEIVED(2) disable `Flicker Stopper' circuitry (logic background colour displayed outside teletext boxes (logic background colour displayed inside teletext boxes (logic active outside teletext boxes (logic active inside teletext boxes (logic text displayed outside teletext boxes (logic text displayed inside teletext boxes (logic video displayed outside teletext boxes (logic video displayed inside teletext boxes (logic background colour displayed outside teletext boxes (logic background colour displayed inside teletext boxes (logic active outside teletext boxes (logic active inside teletext boxes (logic text displayed outside teletext boxes (logic text displayed inside teletext boxes (logic video displayed outside teletext boxes (logic video displayed inside teletext boxes (logic FUNCTION
SAA55xx
display memory information above teletext page display (logic display cursor position given TXT9 TXT10 (logic display characters area with conceal attribute (logic display memory rows when DOUBLE HEIGHT height (logic display each character twice normal height (logic enable display teletext boxes memory (logic enable display teletext boxes memory (logic enable display teletext boxes memory (logic
disable special treatment Spanish packet characters (logic packet data been processed (logic data been processed (logic enable acquisition data (logic select CVBS1 source device (logic
CVBS1/CVBS0
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
Text Register (TXT9) CURSOR FREEZE CLEAR MEMORY(1) R0(3) Text Register (TXT10) C0(4) Text Register (TXT11) Text Register (TXT12) 625/525 SYNC SPANISH VER3 VER0 VIDEO SIGNAL QUALITY Text Register (TXT13) RECEIVED PAGE CLEARING DISPLAY TEXT TEXT 8/30 FASTEXT Text Register (TXT14) PAGE3 PAGE0 Text Register (TXT15) BLOCK3 BLOCK0 Text Register (TXT17) FORCE ACQ1 FORCE ACQ0 FORCE ACQ<1:0>: automatic selection force timing, force teletext standard force timing, force teletext standard force timing, force teletext standard FORCE DISP1 FORCE DISP0 FORCE DISP<1:0>: automatic selection force display mode lines row) force display mode lines row) valid (default mode) current micro block accessed TXT9, TXT10 TXT11 current display page data (logic software power-on page clear progress (logic 525-line synchronisation display (logic 525-line being received (logic 625-line being received (logic packet 8/30/x(625) packet 4/30/x(525) data detected (logic packet x/27 data detected (logic 525-line CVBS signal being received (logic Spanish character present (logic mask programmable identification character acquisition synchronized CVBS (logic current memory column value lock cursor current position (logic clear memory block pointed TXT15 (logic access extension packet memory (logic current memory value FUNCTION
SAA55xx
data value written read from memory location defined TXT9, TXT10 TXT15
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
FUNCTION
SAA55xx
SCREEN COL2 SCREEN COL0 Defines colour displayed instead picture black background; these bits equivalent components. SCREEN COL<2:0>: transparent CLUT entry CLUT entry CLUT entry CLUT entry CLUT entry CLUT entry CLUT entry Text Register (TXT18) NOT3 NOT0 Text Register (TXT19) Text Register (TXT20) LANG ENABLE LAN2 LAN0 Text Register (TXT21) PORT PORT Text Register (TXT22) GPF7 GPF6 GPF5 GPF4 GPF3 GPF2 GPF1 GPF0 Watchdog Timer (WDT) WDV7 WDV0 Watchdog Timer period reserved standard device (logic pages available (logic PWM0, PWM1, PWM2 PWM3 outputs routed Port Port respectively (logic reserved text acquisition available (logic reserved enable I2C-bus Port selection (P1.5/SDA1 P1.4/SCL1) (logic enable I2C-bus Port selection (P1.7/SDA0 P1.6/SCL0) (logic enable LAN<2:0> define language option display, instead C12, alternative C12, bits with menus enable twist character (logic language control bits (C12, C14) that twisted character twist character selection national option table selection, maximum when used with EAST/WEST basic character selection
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
Watchdog Timer (WDTKEY) WKEY7 WKEY0(5) Wide Screen Signalling (WSS1) WSS<3:0> ERROR WSS3 WSS0 Wide Screen Signalling (WSS2) WSS<7:4> ERROR WSS7 WSS4 Wide Screen Signalling (WSS3) WSS<13:11> ERROR WSS13 WSS11 WSS<10:8> ERROR WSS10 WSS8 XRAMP XRAMP7 XRAMP0 Notes This flag software reset hardware. This flag hardware must reset software. Valid range mode Valid range mode Must disable Watchdog Timer when active. internal access upper byte address error WSS<13:11> (logic signalling bits define reserved elements (group error WSS<10:8> (logic signalling bits define subtitles (group error WSS<7:4> (logic signalling bits define enhanced services (group error WSS<3:0> (logic signalling bits define aspect ratio (group Watchdog Timer FUNCTION
SAA55xx
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
Character feature bits
SAA55xx
Features available SAA55xx devices reflected specific area character ROM. These sections character mapped Special Function Registers: TXT22 TXT12. Character address 09FEH mapped TXT22 shown Table Character address 09FFH mapped TXT12 shown Table Table Character TXT22 mapping used; reserved MAPPED ITEMS Character address 09FEH Mapped TXT22 Table
Description Character address 09FEH bits FUNCTION reserved; normally logic Text Acquisition available Text Acquisition available reserved PWM0, PWM1, PWM2 PWM3 output routed Port Port respectively PWM0, PWM1, PWM2 PWM3 output routed Port Port respectively page available page available standard device reserved; normally logic
NUMBER
Table Character TXT12 mapping used; reserved MAPPED ITEMS Character address 09FFH Mapped TXT12 Table
Description Character address 09FFH bits FUNCTION Spanish character present Spanish character present reserved; normally logic
NUMBER
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
External (auxiliary) memory 8.6.1 AUXILIARY PAGE SELECTION
SAA55xx
normal 80C51 external memory area been mapped internally device, this means that MOVX instruction accesses memory internal device.
Auxiliary page pointer used select pages within Auxiliary RAM, pages allocated, refer Fig.10 further detail. page consists consecutive bytes.
handbook, halfpage 7FFFH
FFFFH
4800H 47FFH DISPLAY TEXT PAGES 2000H 1FFFH 500H 4FFH DATA 0000H 8700H
GSA031
8C00H 87FFH DISPLAY REGISTERS 87F0H
871FH CLUT
lower kbytes Amount Data depends device. Amount Display depends device.
upper kbytes
Fig.9 Auxiliary allocation.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
SAA55xx
handbook, full pagewidth
MOVX Ri,A MOVX XRAMP
MBK958
FFFFH XRAMP FF00H FEFFH XRAMP FE00H MOVX DPTR,A MOVX DPTR 01FFH XRAMP 0100H 00FFH 0000H
Fig.10 Indirect addressing Auxiliary RAM.
POWER-ON RESET
automatic reset obtained when turned connecting RESET VDDP through capacitor, providing rise time does exceed oscillator start-up time does exceed ensure correct initialisation, RESET must held high long enough oscillator settle following power-up, usually Once oscillator stable, further clocks required generate reset (two machine cycles microcontroller). Once above reset condition been detected internal reset signal triggered which remains active 2048 clock cycles.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
REDUCED POWER MODES There power saving modes, Idle Power-down, incorporated into page devices. There additional Standby mode incorporated into page devices. When utilizing mode, power device (VDDP, VDDC VDDA) should maintained, since power saving achieved clock gating section section basis. 10.1 Idle mode
SAA55xx
third method terminating Idle mode with external hardware reset. Since oscillator running, hardware reset need only active machine cycles clocks MHz) complete reset operation. Reset defines SFRs Display memory initialized state, maintains other values. Code execution commences with Program Counter `0000'. 10.2 Power-down mode
During Idle mode, Acquisition, Display Central Processing Unit (CPU) sections device disabled. following functions remain active: Memory interface I2C-bus interface Timer/Counters Watchdog Timer Pulse Width Modulators. enter Idle mode PCON register must set. Watchdog Timer must disabled prior entering Idle mode prevent device being reset. Once Idle mode, crystal oscillator continues run, internal clock CPU, Acquisition Display gated out. However, clocks Memory interface, I2C-bus interface, Timer/Counters, Watchdog Timer Pulse Width Modulators maintained. state frozen along with status SFRs, internal contents maintained, device output values. Since output values Green Blue (RGB) Video Data Switch (VDS) maintained display output must disabled before entering this mode. There three methods recover from Idle mode: Assertion enabled interrupt will cause cleared hardware, thus terminating Idle mode. interrupt serviced, following instruction RETI, next instruction executed will after instruction that device into Idle mode. second method exiting Idle mode interrupt generated Compare circuit. When device configured this mode, detection analog threshold input used trigger wake-up device i.e. Front Panel Key-press. above, interrupt serviced, following instruction RETI, next instruction executed will following instruction that device into Idle mode.
Power-down mode crystal oscillator stopped. contents SFRs Data memory maintained, However, contents Auxiliary/Display memory lost. port pins maintain values defined their associated SFRs. Since output values maintained display output must made inactive before entering Power-down mode. Power-down mode activated setting PCON register. advised disable Watchdog Timer prior entering power-down. There three methods exiting power-down: external interrupt provides first mechanism waking from power-down. Since clock stopped, external interrupts needs level sensitive prior entering power-down. interrupt serviced, following instruction RETI, next instruction executed will after instruction that device into Power-down mode. second method exiting power-down interrupt generated Compare circuit. When device configured this mode, detection certain analog threshold input used trigger wake-up device i.e. Front Panel Key-press. above, interrupt serviced, following instruction RETI, next instruction executed will following instruction that device into power-down. third method terminating Power-down mode with external hardware reset. Reset defines SFRs Display memory, maintains other values. Code execution commences with Program Counter `0000'.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
10.3 Standby mode 11.2.1 OPEN-DRAIN
SAA55xx
This mode only available page devices. When Standby mode entered both Acquisition Display sections disabled. following functions remain active: 80C51 core Memory interface I2C-bus interface Timer/Counters Watchdog Timer Software Pulse Width Modulators. enter Standby mode, STANDBY control ROMBK (bit must set. used conjunction with either Idle Power-down modes switch between power saving modes. This mode enables 80C51 core decode either remote commands receive I2C-bus commands without device being fully powered. Standby state maintained upon exit from either Idle mode Power-down mode. wake-up from Standby necessary 80C51 core remains operational. Since output values maintained display output must disabled before entering this mode. FACILITY 11.1 ports
open-drain configuration used bidirectional operation port. requires external pull-up resistor, pull-up voltage maximum value allow connection device into environment. I2C-bus ports (P1.4,P1.5, P1.6 P1.7) only configured open-drain. 11.2.2 QUASI-BIDIRECTIONAL
quasi-bidirectional configuration combination open-drain push-pull. requires external pull-up resistor VDDP (nominally When signal transition from LOW-to-HIGH output from device, into push-pull configuration clock cycle (166 after which goes into open-drain configuration. This configuration used speed edges signal transitions. This default mode operation pads after reset. 11.2.3 HIGH-IMPEDANCE
high-impedance configuration used input only operation port. When using this configuration output transistors turned off. 11.2.4 PUSH-PULL
push-pull configuration used output only. this mode signal driven either VDDP, which nominally 11.3 Port alternate functions
SAA55xx devices have lines, each individually addressable, form three parallel 8-bit addressable ports which Port Port Port Port 5-bit parallel only. 11.2 Port type
Ports shared with alternative functions enable control external devices circuitry. alternative functions enabled setting appropriate also writing logic port that function occupies. 11.4 support
individual ports programmed function four configurations: open-drain, quasi-bidirectional, high-impedance push-pull. configuration selected using associated Port Configuration Registers: PnCFGA PnCFGB (where port number Table
Port pins P0.5 P0.6 have current sinking capability enable LEDs series with current limiting resistors driven directly, without need additional buffering circuitry.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
INTERRUPT SYSTEM device interrupt sources, each which enabled disabled. When enabled each interrupt assigned priority levels. There four interrupts that common 80C51, these external interrupts (EX0 EX1) other timer interrupts (ET0 ET1). addition conventional 80C51 interrupts, application specific interrupt incorporated internal device which following functionality: Display Busy interrupt (EBUSY). interrupt generated when display enters either Horizontal Vertical Blanking Period. i.e. Indicates when microcontroller update Display without causing undesired effects screen. This interrupt configured modes using Memory Mapped Register (MMR) Configuration (address 87FFH, TXT/V): Text Display Busy. interrupt generated each active horizontal display line when Horizontal Blanking Period entered Vertical Display Busy. interrupt generated each vertical display field when Vertical Blanking Period entered. 12.1 Interrupt enable structure
SAA55xx
requests same priority level received simultaneously, internal polling sequence determines which request serviced. Thus, within each priority level there second priority structure determined polling sequence defined Table Table Interrupt priority (within same level) PRIORITY WITHIN LEVEL highest lowest INTERRUPT VECTOR 0003H 000BH 0013H 001BH 002BH 0033H
SOURCE EBUSY 12.3
Interrupt vector address
processor acknowledges interrupt request executing hardware generated LCALL appropriate servicing routine. interrupt vector addresses each source shown Table 12.4 Level/edge interrupt
Each individual interrupts enabled disabled setting clearing relevant Interrupt Enable Register (IE). interrupt sources also globally disabled clearing (IE.7). 12.2 Interrupt enable priority
external interrupt programmed either level-activated transition-activated setting clearing IT0/IT1 bits Timer Control (TCON). Table External interrupt activation LEVEL active INT0 negative edge INTI positive negative edge external interrupt INT1 differs from standard 80C51 interrupt that activated both edges when edge sensitive mode. This allow software pulse width measurement handling remote control inputs. EDGE
Each interrupt source assigned priority levels. interrupt priorities defined Interrupt Priority Register (IP). priority interrupt interrupted high priority interrupt, another priority interrupt. high priority interrupt interrupted other interrupt source. requests different priority levels received simultaneously, request with highest priority level serviced.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
SAA55xx
handbook, full pagewidth
source enable IE<0:6> global enable IE.7 priority control IP<0:6>
highest priority level highest priority level
EBUSY
lowest priority level lowest priority level
GSA033
interrupt source
Fig.11 Interrupt structure.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
TIMER/COUNTER 16-bit timers/counters incorporated Timer Timer Both configured operate either timers event counters. Timer mode, register incremented every machine cycle. therefore counting machine cycles. Since machine cycle consists twelve oscillator periods, count rate 1/12fosc MHz. Counter mode, register incremented response negative transition corresponding external Since pins sampled once machine cycle, takes machine cycles recognise transition, this gives maximum count rate MHz. There Special Function Registers used control timers/counters. These are: TCON, TMOD, TL0, TH0, TH1. timer/counter function selected control bits Timer Mode (TMOD). These Timer/Counters have four operating modes, which selected bit-pairs TMOD. Detail modes operation given "Handbook IC20, 80C51-Based 8-bit Microcontrollers". actual Timer/Counter registers Timer byte high byte. actual Timer/Counter registers Timer byte high byte. WATCHDOG TIMER Watchdog Timer counter that once overflow state forces microcontroller into reset condition. purpose Watchdog Timer reset microcontroller enters erroneous processor state (possibly caused electrical noise RFI) within reasonable period time. When enabled, Watchdog circuitry will generate system reset user program fails reload Watchdog Timer within specified length time known Watchdog Interval (WI). Watchdog Timer consists 8-bit counter with 11-bit prescaler. prescaler with signal whose frequency 1/12fosc oscillator).
SAA55xx
8-bit timer incremented every seconds where: 2048 2048 2.048 14.1 Watchdog Timer operation
Watchdog operation activated when Power Control (PCON) set. Watchdog disabled software loading value into Watchdog (WDTKEY). This must performed before entering Idle Power-down mode prevent exiting mode prematurely. Once activated Watchdog Timer (WDT) must reloaded before timer overflows. must enable loading SFR, once loaded reset hardware, this prevent erroneous software from loading SFR. value loaded into defines Watchdog Interval (WI). 2.048 range intervals from which gives which gives 2.048 PULSE WIDTH MODULATORS device eight 6-bit Pulse Width Modulated (PWM) outputs analog control e.g. volume, balance, bass, treble, brightness, contrast, saturation. outputs generate pulse patterns with repetition rate 21.33 with high time equal value multiplied 0.33 analog value determined ratio high time repetition time, voltage proportional setting obtained means external integration network (low-pass filter). 15.1 control
relevant enabled setting enable PWxE PWMx Control Register (where high time defined value PWxV<5:0>.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
15.2 Tuning Pulse Width Modulator (TPWM)
SAA55xx
resolution voltage with nominal value 3.3/ external analog voltage lower value equivalent VSSA upper value equivalent VDDP Vtn, where threshold voltage type Metal Oxide Semiconductor transistor. reason this that input pins analog signals (P3.0 P3.3) tolerant normal port operations, i.e. when used analog input. protect analog multiplexer comparator circuitry from series transistor used limit voltage. This limiting introduces voltage drop equivalent (0.6 input voltage. Therefore, input voltage range VDDP VDDP returns same comparison value. 15.3.3 COMPARATOR MODE
device single 14-bit that used Voltage Synthesis Tuning. method operation similar normal except repetition period 42.66 15.2.1 TPWM CONTROL
SFRs used control TPWM, they TDACL TDACH. TPWM enabled setting TPWE TDACH SFR. most significant bits TD<13:7> alter high period between 42.33 least significant bits TD<6:0> extend certain pulses further 0.33 e.g. TD<6:0> then periods will extended 0.33 TD<6:0> then periods will extended. TPWM will start output value until TDACH been written Therefore, value changed, TDACL should written before TDACH. 15.3 Software (SAD)
Four successive approximation Analog-to-Digital Converters implemented software making on-board 8-bit Digital-to-Analog Converter Analog Comparator. 15.3.1 CONTROL
module incorporates Comparator mode which selected using DC_COMP control SADB SFR. This mode enables microcontroller detect threshold crossing input selected analog input (P3.0/ADC0, P3.1/ADC1, P3.2/ADC2 P3.3/ADC3) Software ADC. level sensitive interrupt generated when analog input voltage level falls below analog output level DAC. This mode intended provide device with wake-up mechanism from Power-down Idle mode when key-press front panel detected. following software sequence should used when utilizing this mode Power-down Idle: Disable INT1 using SFR. INT1 level sensitive using TCON SFR. digital input level desired threshold level using SAD/SADB SFRs select required input (P3.0/ADC0, P3.1/ADC1, P3.2/ADC2 P3.3/ADC3) using CH<1:0> SFR. Enter Compare mode setting DC_COMP enable SADB SFR. Enable INT1 using SFR. Enter Power-down Idle mode. Upon wake-up should restored conventional operating mode disabling DC_COMP control bit.
control required analog input done using channel select bits CH<1:0> SFR, this selects required analog input passed inputs comparator. second comparator input generated whose value bits SAD<7:0> SADB SFRs. comparison between inputs made when start compare set, this must least instruction cycle after SAD<7:0> value been set. result comparison given instruction cycle after setting 15.3.2 INPUT VOLTAGE
external analog voltage that used comparison with internally generated voltage does have same voltage range. lower reference level VSSA upper reference level VSSP.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
SAA55xx
handbook, halfpage
VDDP
ADC0 ADC1 ADC2 ADC3 CH<1:0>
SAD<3:0> 8-BIT SADB<3:0>
MBK960
Fig.12 block diagram.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
I2C-BUS SERIAL I2C-bus consists serial data (SDA) line serial clock (SCL) line. definition I2C-bus protocol found document "The I2C-bus (including specification)". This document ordered using code 9398 40011. device operates four modes: Master transmitter Master receiver Slave transmitter Slave receiver. microcontroller peripheral controlled Serial Control (S1CON) status indicated Status (S1STA). Information transmitted/received to/from I2C-bus using Data (S1DAT) Slave Address (S1ADR) used configure slave address peripheral. byte level I2C-bus serial port identical I2C-bus serial port P8xCE558, except clock rate selection bits CR<2:0> S1CON. operation subsystem described detail "P8xCE558 data sheet". 16.1 I2C-bus port selection 17.1 Memory structure
SAA55xx
memory partitioned into distinct areas, dedicated Auxiliary area, Display area. Display area when being used Data Capture display, used extension auxiliary area. 17.1.1 AUXILIARY
Auxiliary initialised power-up. contents Auxiliary maintained during Idle mode, lost Power-down mode entered. 17.1.2 DISPLAY
Display initialised power-up value throughout. contents Display maintained when entering Idle mode. Idle mode exited using interrupt then contents unchanged, Idle mode exited using reset then contents initialised 20H. 17.2 Memory mapping
dedicated Auxiliary area occupies maximum kbytes, with address range from 0000H 1FFFH. Display occupies maximum kbytes with address range from 2000H 47FFH mode (see Fig.13). 17.3 Addressing memory
I2C-bus ports available SCL0/SDA0 SCL1/SDA1. selection port done using TXT21.I2C PORT TXT21.I2C PORT When port enabled, information transmitted from device goes onto enabled port. information transmitted device only acted port enabled. both ports enabled then data transmitted from device seen both ports, however data transmitted device port seen other port. MEMORY INTERFACE memory interface controls access embedded Dynamic Random Access Memory (DRAM), refreshing DRAM page clearing. DRAM shared between Data Capture, display microcontroller sections. Data Capture section uses DRAM store acquired information that been requested. display reads from DRAM information converts into values. microcontroller uses DRAM embedded auxiliary RAM.
memory addressed microcontroller ways, either directly using MOVX command, Special Function Registers depending what address required. Display memory range 2000H 47FFH either directly accessed using MOVX, Special Function Registers. 17.3.1 DISPLAY MEMORY ACCESS
Display memory when mode (see Fig.14) configured columns wide rows occupies bits memory. There maximum display pages. Using TXT15.BLOCK<3:0>, required display page selected written column within that block selected using TXT9.R<4:0> TXT10.C<5:0>. data selected position read written using TXT11.D<7:0>.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
Whenever read write performed TXT11, values stored TXT9 column value stored TXT10 automatically incremented. rows column value incremented maximum which point resets increments counter value. When column reached values column both reset zero. Writing values outside valid range TXT9 TXT10 will cause undetermined operation auto-incrementing function accesses TXT11. 17.3.2 DISPLAY MEMORY MOVX ACCESS
SAA55xx
When this occurs, space code (20H) written into every location rows basic page memory, appropriate packet extension packet memory where teletext packet written. This last either basic page memory, TXT0.X24 POSN set, extension packet memory, set. Page clearing takes place before line which header arrived which initiated page clear. This means that field between page header rest page which necessary many teletext decoders required. 17.4.2 SOFTWARE PAGE CLEAR
important generation displays, that this mode access, understand mapping MOVX address onto display column value. This mapping column onto address shown Table values shown added onto base address required memory block (see Fig.13) give 16-bit address. 17.4 Page clearing
software also initiate page clear, setting TXT9.CLEAR MEMORY bit. When does every location memory block pointed TXT15.BLOCK<3:0> cleared space code (20H). CLEAR MEMORY latched software does have reset after been set. Only page cleared line software requests page clear will carried next line which Data Capture hardware does force page cleared. flag, TXT13.PAGE CLEARING, provided indicate that software requested page clear being carried out. flag when logic written into TXT9.CLEAR MEMORY reset when page clear been completed. TXT0.INV page clear initiated Block locations cleared 00H.
Page clearing performed request from either Data Capture block, microcontroller under control embedded software. power-on reset whole page memory cleared. TXT13.PAGE CLEARING will while this takes place. 17.4.1 DATA CAPTURE PAGE CLEAR
When page header acquired first time after page request page header acquired with erase (C4) page memory `cleared' spaces before rest page arrives.
Table Column MOVX address (lower bits address) COL. 000H 020H 2E0H 300H 320H COL. 017H 037H 3F7H 317H 337H COL. COL. 01FH 03FH 2FFH 31FH 3F8H 3F0H 340H 338H COL. 3FFH 3F7H 347H 33FH
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
SAA55xx
lower kbytes
handbook, halfpage
7FFFH
BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK
4400H 4000H 3C00H 3800H 3400H 3000H 2C00H 2800H 2400H 2000H
AUXILIARY 0000H
GSA034
Fig.13 DRAM memory mapping.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
SAA55xx
handbook, full pagewidth
control data
Column
non-displayable data (byte reserved)
active position TXT9.R<4:0> 01H, TXT10.C<5:0> 0AH, TXT11
MBK962
Fig.14 memory map.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
DATA CAPTURE Data Capture section takes analog Composite Video Blanking Signal (CVBS), from this extracts required data, which then decoded stored memory. extraction data performed digital domain. first stage convert analog CVBS signal into digital form. This done using sampling MHz. data clock recovery then performed Multi-Rate Video Input Processor (MulVIP). From recovered data clock following data types extracted: Teletext (625/525), WSS. extracted data stored either memory (DRAM) Memory interface locations. 18.1 Data Capture features
SAA55xx
Data Capture Wide Screen Signalling (WSS) decoding Automatic selection between WST/625 Automatic selection between WST/VPS line Vertical Blanking Interval (VBI) Real-time capture decoding Teletext hardware, enable optimized microprocessor throughput pages stored on-chip Inventory transmitted Teletext pages stored Transmitted Page Table (TPT) Subtitle Page Table (SPT) Automatic detection FASTEXT transmission Real-time packet engine hardware processing accented, characters Signal quality detector WST/VPS data types Comprehensive Teletext language coverage Full Field Vertical Blanking Interval (VBI) data capture data.
CVBS inputs Video Signal Quality detector Data Capture 625-line Data Capture 525-line Data Capture data (Programme Delivery Control (PDC) system
handbook, full pagewidth
CVBS0
CVBS1
CVBS SWITCH
CVBS data<7:0> DATA SLICER CLOCK RECOVERY SYNC SEPARATOR ACQUISITION TIMING SYNC_FILTER
ACQUISITION WST/VPS/WSS output data memory interface SFRs
GSA032
Fig.15 Data capture block diagram.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
18.1.1 CVBS SWITCH
SAA55xx
18.1.6.1 Making page request
CVBS switch used select required analog input depending value TXT8.CVBS1/CVBS0. 18.1.2 ANALOG-TO-DIGITAL CONVERTER
output CVBS switch passed differential-to-single-ended converter, although this device used single-ended configuration with reference. analog output differential amplifier converted into digital representation full flash with sampling rate MHz. 18.1.3 MULTI-RATE VIDEO INPUT PROCESSOR
page requested writing series bytes into TXT3.PRD<4:0> which corresponds number page required. bytes written into TXT3 stored with auto-incrementing address. start address using TXT2.SC<2:0> define which part page request being written, TXT2.REQ<3:0> used define which page requests being modified. TXT2.REQ<3:0> greater than 09H, then data being written TXT3 ignored. Table shows contents page request RAM. pages teletext acquired page device, when TXT1.EXT logic pages acquired when this logic page device page acquisition channels banked, bank being selected using TXT2.ACQ BANK. CARE' part page number logic then that part page number ignored when teletext decoder deciding whether page being received should stored not. example, CARE' bits four subcode digits logic then every subcode version page will captured. Table contents Page request START COLUMN PRD4 CARE Magazine CARE Page Tens PRD3 PRD2 PRD1 PRD0 HOLD MAG2 MAG1 MAG0
multi-rate video input processor Digital Signal Processor designed extract data recover clock from digitised CVBS signal. 18.1.4 DATA STANDARDS
data clock standards that recovered shown Table Table Data slicing standards DATA STANDARD 18.1.5 DATA CAPTURE TIMING CLOCK RATE (MHz) 6.9375 5.7272
Data Capture timing section uses synchronisation information extracted from CVBS signal generate required horizontal vertical reference timings. timing section automatically recognises selects appropriate timings either synchronisation synchronisation. flag TXT12.VIDEO SIGNAL QUALITY when timing section locked correctly incoming CVBS signal. When TXT12.VIDEO SIGNAL QUALITY another flag TXT12.525/625 SYNC used identify standard. 18.1.6 ACQUISITION
CARE Page Units CARE Hour Tens CARE Hours Units CARE Minutes Tens CARE Minutes Units
acquisition sections extracts relevant information from serial stream data from MulVIP stores memory.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
When HOLD logic teletext decoder will recognise page having correct page number pages will captured. addition providing user requested hold function this should used prevent inadvertent capture unwanted page when page request being made. example, previous page request page this being changed page 234, would possible capture page this arrived after only requested magazine number been changed. bits control error checking which should carried packets when page being requested captured. This described more detail Section 18.1.6.3. multi-page device, each packet only written into place teletext page matches more than page requests data written into area memory corresponding lowest numbered matching page request. power-up each page request defaults page, hold error check Mode
SAA55xx
When requested page header acquired first time, rows relevant memory block cleared space, i.e. have written into every column, before rest page arrives. also cleared TXT0.X24 POSN set. TXT1.EXT extension packets corresponding page also cleared. last characters page header used provide time display always extracted from every valid page header arrives written into display block. TXT0.DISABLE HEADER ROLL prevents data being written into page memory except when page acquired i.e. rolling headers time written into memory. TXT1.ACQ prevents data being written into memory teletext acquisition section. When parallel magazine mode transmission being received only headers magazine page requested considered valid purposes rolling headers time. Only magazine used even don't care magazine requested. When serial magazine mode transmission being received page headers considered valid.
18.1.6.2
Rolling headers time
When page been requested conventional decoder turn header display green display each page header arrives until correct page been found. When page request changed (i.e. when TXT3 written flag (PBLF) written into column corresponding block page memory. state flag each block updated every line, current display block, acquisition section writes valid page headers which arrive into display block automatically writes alphanumeric green character into column display block every line.
18.1.6.3
Error checking
Before teletext packets written into page memory they error checked. error checking carried depends packet number, byte number, error check mode bits page request data TXT1.8-BIT bit. uncorrectable error occurs Hamming checked addressing control bytes page header Hamming checked bytes packet 8/30, byte written into memory set, error flag software. uncorrectable errors detected other Hamming checked data byte written into memory.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
SAA55xx
Packet handbook, full pagewidth '8-bit' '8-bit' Packet X/1-23 '8-bit' error check mode '8-bit' error check mode '8-bit' error check mode '8-bit' error check mode '8-bit' Packet X/24 '8-bit' '8-bit' Packet X/27/0 Packet 8/30/0,1 Packet 8/30/2,3,4-15
MGK465
8-bit data
parity checked
Hamming checked
Fig.16 Error checking.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
SAA55xx
handbook, full pagewidth
Basic Page Blocks 8/9) Control Data 10(3) Packet Packet Packet Packet Packet Packet Packet Packet Packet Packet Packet X/10 Packet X/11 Packet X/12 Packet X/13 Packet X/14 Packet X/15 Packet X/16 Packet X/17 Packet X/18 Packet X/19 Packet X/20 Packet X/21 Packet X/22 Packet X/23 Packet X/24(1) Data(2)
GSA003
only
`X24 POSN' data block unused blocks Byte reserved.
Fig.17 Packet storage locations.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
18.1.6.4 Teletext memory organisation
SAA55xx
Packet page header, split into parts when written into text memory. first bytes header contain control addressing information. They Hamming decoded written into columns also contains magazine number acquired page PLBF flag last bytes unused used software, necessary.
teletext memory divided into banks blocks. Normally, when TXT1.EXT logic each blocks contains teletext page arranged same basic page memory page device block contains extension packets. When TXT1.EXT logic extension packets captured block memory used store another page. number memory block into which page written corresponds page request number which resulted capture page.
Extension Packet Block
handbook, full pagewidth
Packet X/24 page block 0(1) Packet X/27/0 page block Packet 8/30/0.1 Packet 8/30/2.3 Packet X/24 page block 1(1) Packet X/27/0 page block Packet X/24 page block 2(1) Packet X/27/0 page block Packet X/24 page block 3(1) Packet X/27/0 page block Packet X/24 page block 4(1) Packet X/27/0 page block Packet X/24 page block 5(1) Packet X/27/0 page block Packet X/24 page block 6(1) Packet X/27/0 page block Packet X/24 page block 7(1) Packet X/27/0 page block Packet X/24 page block 8(1) Packet X/27/0 page block Packet 8/30/4-15
Data 10(2)
GSA002
`X24 POSN' Byte reserved.
Fig.18 Extension packet storage locations.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
18.1.6.5 data contents
SAA55xx
magazine serial (C11) indicates whether transmission serial parallel magazine transmission. This affects acquisition section operates dealt with automatically. newsflash (C5), subtitle (C6), suppress header (C7), inhibit display (C10) language control (C12 bits dealt with automatically display section. update (C8) effect hardware. remaining bytes page header parity checked written into columns Bytes which pass parity check have logic written into page memory. Bytes with parity errors written into memory.
Hamming error flags on-board Hamming checker detects that there been uncorrectable (2-bit) error associated byte. possible page still acquired some page address information contains uncorrectable errors that part page request `don't care'. There error flag magazine number uncorrectable error this information prevents page being acquired. interrupt sequence (C9) automatically dealt with acquisition section that rolling headers contain discontinuity page number sequence.
Table data basic page memory PBLF Hamming error Hamming error Hamming error Hamming error Hamming error Hamming error Hamming error Hamming error FOUND unused MAG2 MAG1 MAG0
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
18.1.6.6 Inventory page
SAA55xx
particular page when page header received that page. when page header page received which `subtitle' page header control (C6) set. particular page when page header received that page. when page header page received which `subtitle' page header control (C6) set.
TXT0.INV logic memory block used inventory page.The inventory page consists tables: Transmitted Page Table (TPT) Subtitle Page Table (SPT). each table, every possible combination page tens units digit, FFH, represented byte. Each these bytes corresponds magazine number each page number, from 100H 8FFH, represented table.
Bytes table
handbook, full pagewidth
column
bits each byte
xfef
MGD160
Fig.19 Transmitted/subtitle page organisation.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
SAA55xx
handbook, full pagewidth
Transmitted Pages Table
Subtitle Pages Table
Unused Unused Unused Unused Unused Unused Unused Unused Unused
MGD165
Fig.20 Inventory page organisation.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
18.1.6.7 Packet processing
18.3 acquisition
SAA55xx
uses packet transmit characters which basic teletext character set. family automatically decodes packet data and, character corresponding that being transmitted available character set, automatically writes appropriate character code into correct location teletext memory. This full implementation packet specification allowed level teletext, often referred level 1.5. convention, packets page transmitted before normal packets. prevent default character data overwriting packet data device incorporates mechanism which prevents packet data from being overwritten. mechanism disabled when Spanish national option detected Spanish transmission system sends even parity (i.e. incorrect) characters basic page locations corresponding characters sent packet these will overwrite packet characters anyway. special treatment Spanish national option prevented TXT12.ROM VER3 logic TXT8.DISABLE SPANISH set. Packet data processed regardless TXT1.EXT bit, setting theTXT1.X26 disables packet processing. TXT8.PKT26 RECEIVED hardware whenever character written into page memory packet decoding hardware. flag reset writing logic into bit. 18.1.7 ACQUISITION
When TXT0.VPS set, data present line field CVBS signal input teletext decoder error checked stored block basic page memory. device automatically detects whether teletext being transmitted this line decodes data appropriately. Each byte memory consists biphase decoded data bits (bits biphase error flag (bit three logic (bits TXT13.VPS RECEIVED hardware whenever data acquired. Full details system found "Specification Domestic Video Programme Delivery Control System (PDC); Tech. 3262-E". 18.4 acquisition
Wide Screen Signalling data transmitted line gives information aspect ratio display position transmitted picture, position subtitles camera/film mode. Some additional bits reserved future use. total data bits transmitted. available data bits transmitted Wide Screen Signalling signal captured stored SFRs WSS1, WSS2 WSS3. bits stored groups related bits, error flag provided each group indicate when transmission error been detected more bits group. Wide screen signalling data only acquired when TXT8.WSS set. TXT8.WSS RECEIVED hardware whenever wide screen signalling data acquired. flag reset writing logic into bit.
family capable acquiring Level 625-line 525-line World System Teletext. 18.2 Broadcast service data detection
When packet 8/30 detected, packet 4/30 when device receiving line transmission, TXT13. 8/30 flag set. flag reset writing into bit.
handbook, full pagewidth
column
teletext page header data
byte
byte
byte
byte
byte
byte
byte
MBK964
Fig.21 data storage.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
DISPLAY display section based requirements Level Teletext. There some enhancements with locally generated OSDs. display section reads contents Display memory interprets control/character codes. From this information other global settings, display produces required signals Video/Data (Fast Blanking) signal signal processing device. display synchronised signal processing device horizontal vertical sync signals provided external circuits (Slave Sync mode). From these signals display timings derived. 19.1 Display features Level features
SAA55xx
Single/Double/Quadruple Width Height characters Variable flash rate controlled software Fixed character matrix Soft colours using Colour Look Table (CLUT) with 4096 colour palette Fringing (Shadow) selectable from N-S-E-W direction Fringe colour selectable Meshing defined area Contrast reduction defined area Cursor Character (G0/G2) single device (e.g. Latin Cyrillic Greek Arabic) Mosaic graphics, Limited Line drawing characters.
Teletext Enhanced On-Screen Display (OSD) modes
handbook, full pagewidth
VSYNC HSYNC
DISPLAY TIMING address MICROPROCESSOR INTERFACE data FUNCTION REGISTERS address memory interface from memory interface address data data DISPLAY DATA ADDRESSING ATTRIBUTE HANDLING
address data control
PARALLEL/SERIAL CONVERTER FRINGING
DATA BUFFER CHARACTER DRCs data CHARACTER FONT ADDRESSING
CLUT
address
MBK965
Fig.22 Display block diagram.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
19.2 Display mode
SAA55xx
consecutive combination `double width' `double size' (0EH/BEH/0FH/BFH) activates quadruple width characters, provided quadruple width characters enabled TXT4.QUAD WIDTH ENABLE. Three vertical sizes available normal double quadruple control characters `normal size' (0CH/BCH) enable normal size, `double height' `double size' (0DH/BDH/0FH/BFH) enable double height characters. Quadruple height characters achieved using double height characters setting global attributes TXT7.DOUBLE HEIGHT (expand) TXT7.BOTTOM/TOP. double height characters used Teletext mode, single height characters lower double height character automatically disabled. 19.3.4 COLOURS
display configured with additional serial global attributes. display configured fixed rows with characters row. 19.3 19.3.1 Display feature descriptions FLASH
Flashing causes foreground colour pixel displayed background pixels.The flash frequency controlled software setting resetting Status (see Table appropriate interval. This attribute control character `flash' (08H) (see Fig.26) remains valid until until reset control character `steady' (09H). 19.3.2 BOXES
types boxes exist, Teletext box. Teletext activated `start box' control character (0BH), start characters required begin Teletext box, with starting between characters. ends line after `end box' control character. boxes started using size implying control characters (BCH, BDH, BFH). starts after control character (`set after') ends either next size implying character (`set at'). attributes flash, Teletext box, conceal, separate graphics, twist hold graphics reset start box, they start row. boxes only valid mode which defined TXT5 TXT6 03H. 19.3.3 SIZE
19.3.4.1
Colour Look Table (CLUT)
CLUT with colour entries provided. colours programmable palette 4096 bits CLUT defined writing data that resides MOVX address space 80C51. Table CLUT colour values RED<3:0> (B11 0000 0000 1111 1111 GRN<3:0> 0000 0000 1111 1111 BLUE<3:0> 0000 1111 0000 1111 COLOUR ENTRY
size characters modified both horizontal vertical directions. Three horizontal sizes available normal double quadruple control characters `normal size' (0CH/BCH) enables normal size, `double width' `double size' (0EH/BEH/0FH/BFH) enables double width characters.
19.3.5
FOREGROUND COLOUR
foreground colour selected control character (see Fig.26). colour control characters take effect start next character (set-after) remain valid until row, until modified control character. Only foreground colours available. TEXT foreground control characters CLUT entries shown Table
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
Table Foreground CLUT mapping CONTROL CODE 19.3.6 DEFINED COLOUR black green yellow blue magenta cyan white CLUT ENTRY 19.3.7 FRINGING
SAA55xx
display fringing controlled TXT4.SHADOW bit. When alphanumeric characters being displayed shadowed, graphics characters shadowed. 19.3.8 MESHING
attribute effects background colour being displayed. Alternate pixels displayed background colour video. structure offset pixel from scan line scan line, thus achieving checker board display background colour video. TXT: There meshing attributes that only affects black background colours TXT4.B MESH ENABLE second that only affects backgrounds other than black TXT4.C MESH ENABLE. black background defined CLUT entry non-black background defined CLUT entry 19.3.9 CURSOR
BACKGROUND COLOUR
control character background (1DH) used change background colour current foreground colour. selection immediate (set remains valid until until otherwise modified. TEXT background control characters CLUT entries shown Table Table Background CLUT mapping CONTROL CODE DEFINED COLOUR black green yellow blue magenta cyan white CLUT ENTRY
cursor operates reversing background foreground colours character position pointed active cursor position. cursor enabled using TXT7.CURSOR When active, cursor appears defined TXT9.R<4:0> column defined TXT10.C<5:0>. position cursor fixed using TXT9.CURSOR FREEZE. valid range positioning valid range column
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
SAA55xx
handbook, full pagewidth
MBK972
Fig.23 South south-west fringing.
handbook, full pagewidth
MBK973
Fig.24 Meshing meshing/fringing (south west).
handbook, full pagewidth
MBK971
Fig.25 Cursor display.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
19.4 Character attribute coding
SAA55xx
character coding serial format, with only attribute being changed single location. serial attributes take effect either position attribute (set at), following location (set after). attribute remains effective until either modified serial attributes until row. default settings start Foreground colour white (CLUT address Background colour black (CLUT address Horizontal size vertical size (normal size) Alphanumeric Contiguous Mosaic Graphics Release Mosaics Flash Conceal Twist off. attributes have individual codes which defined basic character table (see Fig.26).
1999
This text here white force landscape pages rotated correctly when browsing through Acrobat reader.This text here _white force landscape pages rotated correctly when browsing through Acrobat reader.This text here inThis text here white force landscape pages rotated correctly when browsing through Acrobat reader. white force landscape pages 1999 Philips Semiconductors
Standard microcontrollers with On-Screen Display (OSD)
column graphics black graphics graphics green background black back ground background green background yellow background blue background magenta background cyan background white
alpha black alpha
alpha green alpha yellow
graphics yellow
alpha blue alpha magenta
graphics blue graphics magenta
alpha cyan alpha white
graphics cyan graphics white conceal display
flash
steady
contiguous graphics separated graphics
start
twist
normal size double height double width double size
normal height double height
black back ground back ground hold graphics release graphics
double width double size
Preliminary specification
handbook, full pagewidth
SAA55xx
MBK974
character dependent language page, refer National Option characters customer definable On-Screen Display character
Fig.26 basic character (Pan-European).
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
19.5 Screen global controls
SAA55xx
teletext boxes messages been superseded this device concept, these bits remain allow teletext boxes used, required. 19.6 Screen colour
number attributes available that affect whole display region, cannot applied selectively regions display. 19.5.1 DISPLAY MODES
display mode controlled bits TXT5 TXT6. There three control functions: Text Background Picture Separate sets bits used inside outside teletext boxes that different display modes invoked. TXT6 used newsflash (C5) subtitle (C6) bits basic page memory set, otherwise TXT5 used. This allows software type display required newsflash subtitle pages (e.g. text inside boxes, picture outside) this will invoked without further software intervention when such page acquired. When teletext control characters present display page memory, appropriate control must set, TXT7.BOX TXT7.BOX TXT7.BOX This allows display mode different inside Teletext compared outside. These bits present allow boxes certain areas screen disabled. Table display control bits PICTURE TEXT
Screen colour displayed from 10.5 62.5 after active edge HSYNC input lines inclusive, 625-line display, lines inclusive 525-line display. register bits TXT17.SCREEN COL<2:0> used define colour displayed place picture black background colour. bits zero, screen colour defined `transparent' picture background colour displayed normal. Otherwise bits define CLUT entries 19.7 Text display control
display organised fixed size rows columns 39), This standard size teletext transmissions. control data displayed used configure display page correctly.
BACKGROUND
EFFECT Text mode, black screen Text mode, background always black Text mode Video mode Mixed text mode Text mode, picture outside text area
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
SAA55xx
handbook, full pagewidth
control data
non-displayable data byte reserved
MBK968
Fig.27 text area.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
19.8 Display positioning
SAA55xx
screen colour extends over large vertical horizontal range that offset needed. text area offset both directions relative vertical horizontal sync pulses.
display consists screen colour covering whole screen text area that placed within visible screen area.
handbook, full pagewidth
horizontal sync screen colour offset lines offset text vertical offset SCREEN COLOUR AREA horizontal sync delay TEXT AREA
vertical sync
0.25 character offset
text area start text area
MGL150
Fig.28 Display area positioning.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
19.8.1 SCREEN COLOUR DISPLAY AREA
SAA55xx
Note that Text Position Vertical Register should Display Busy interrupt generated these circumstances. 19.9 Character
This area covered screen colour. screen colour display area starts with fixed offset from leading edge horizontal sync pulse horizontal direction. vertical offset necessary. Table Screen colour display area VECTOR Horizontal Vertical DESCRIPTION Start after leading edge horizontal sync Line field (321, field leading edge vertical sync (line numbering using standard). TEXT DISPLAY AREA
consist alphanumeric characters required Teletext customer definable characters. character sets displayed once. These basic alternate (Twist Set). basic selected using TXT18.BS<1:0>. alternate/twist character defined TXT19.TS<1:0>. Since alternate character option enabled disabled using TXT19.TEN, language code that defined alternate defined TXT19.TC<2:0>. 19.10 Display synchronization horizontal vertical synchronizing signals from deflection used inputs. Both signals inverted before being delivered Phase Selector section. SFRs bits TXT1.HPOLARITY TXT1.VPOLARITY control polarity. line locked clock derived from free running oscillator Phase Selector. This line locked clock used clock whole Display block. horizontal vertical sync signals synchronized with clock before being used Display section. 19.11 Video/data switch (fast blanking) polarity polarity Video/data (fast blanking) signal inverted. polarity with VDSPOL Brightness. Table Fast blanking signal polarity VDSPOL CONDITION display Video display display Video display
19.8.2
text area defined start with offset both horizontal vertical direction. Table Text display area VECTOR Horizontal DESCRIPTION full sized characters row. Start position setting from characters from leading edge horizontal sync. Fine adjustment quarter characters. lines (nominal 297). Start position setting from leading edge vertical sync, legal values lines. (line numbering using standard).
Vertical
horizontal offset Text Area Start. offset done full width characters using TAS<5:0> quarter characters using HOP<1:0> fine setting. values TAS<5:0> will result corrupted display. width text area defined Text Area setting character value TAE<5:0>. This number determines where background colour text area will extend row. will also terminate character fetch process thus eliminating necessity attribute. This entails however writing positions. vertical offset Text Position Vertical Register. offset value VOL<5:0> done number scan lines.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
19.12 Video/data switch adjustment take into account delay between values signal external buffering, signal moved relation signals. signal either clock cycle before after signal, coincident with signal. This done using VDEL<2:0> Configuration. 19.13 brightness control brightness control provided allow upper output voltage level modified. nominal value into resistor, varied between brightness Brightness Register. Table brightness BRI3 BRI0 0000 1111 highest value BRIGHTNESS lowest value
SAA55xx
MEMORY MAPPED REGISTERS (MMR) memory mapped registers used control display. registers mapped into microcontroller MOVX address space, starting address 87F0H extending 87FFH. Table address summary REGISTER MEMORY ADDRESS 87F1H 87F2H 87F3H 87F4H 87F7H 87F8H 87FCH 87FDH 87FFH FUNCTION Text Position Vertical Text Area Start Fringing Control Text Area Brightness Status HSYNC Delay VSYNC Delay Configuration
19.14 Contrast reduction bits SFRs TXT5 TXT6 control when output device activated (i.e. pulled LOW). This output intended display circuits reduce contrast video when active. result contrast reduction improve readability text mixed teletext video display. bits TXT5 TXT6 SFRs allow display that, example, areas inside teletext boxes will contrast reduced when subtitle being displayed that rest screen will displayed normal video.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
Table 87F1 87F2 87F3 87F4 87F7 87F8 NAME HOP1 FRC3 VDSPOL BUSY HOP0 FRC2 FIELD HSD6 VSD6 VDEL2 VOL5 TAS5 FRC1 TAE5 HSD5 VSD5 VDEL1 VOL4 TAS4 FRC0 TAE4 HSD4 VSD4 VDEL0 VOL3 TAS3 FRDN TAE3 BRI3 HSD3 VSD3 TXT/V VOL2 TAS2 FRDE TAE2 BRI2 HSD3 VSD2 VOL1 TAS1 FRDS TAE1 BRI1 HSD1 VSD1
SAA55xx
VOL0 TAS0 FRDW TAE0 BRI0 HSD0 VSD0
RESET
Text Position Vertical Text Area Start Fringing Control Text Area Brightness Status
87FC HSYNC Delay 87FD VSYNC Delay 87FF Configuration Table definition REGISTER Text Position Vertical VOL5 VOL0 Text Area Start HOP1 HOP0 TAS5 TAS0 Fringing Control FRC3 FRC0 FRDN FRDE FRDS FRDW Text Area TAE5 TAE0 Brightness VDSPOL
FUNCTION
display start vertical offset from VSYNC (lines)
fine horizontal offset quarter characters text area start
fringing colour, value address CLUT fringe north direction (logic fringe east direction (logic fringe south direction (logic fringe west direction (logic
text area end, full characters
polarity (1), Video (0), Video
BRI3 BRI0
brightness control
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
REGISTER Status read BUSY FIELD Status write HSYNC Delay HSD6 HSD0 VSYNC Delay VSD6 VSD0 Configuration VDEL2 VDEL0 pixel delay between output switched video, active active pixel earlier then synchronous active pixel after TXT/V BUSY signal switch; horizontal (logic VSYNC delay number 8-bit clock cycles HSYNC delay, full size characters active flash region background colour only displayed (logic access display memory could cause display problems (logic even field (logic active flash region background only displayed (logic FUNCTION
SAA55xx
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
LIMITING VALUES accordance with Absolute Maximum Rating System (IEC 134). SYMBOL VDDX IIOK Tamb Tstg Note PARAMETER supply voltage (all supplies) input voltage (any input) output voltage (any output) output current (each output) input output diode current operating ambient temperature storage temperature note note CONDITIONS MIN. -0.5 -0.5 -0.5 +4.0 MAX.
SAA55xx
UNIT
+125
This maximum value refers tolerant I/Os maximum only when present. CHARACTERISTICS 10%; Tamb unless otherwise specified. SYMBOL Supplies VDDX IDDP IDDC IDDC(id) IDDC(pd) IDDC(stb) IDDA IDDA(id) IDDA(pd) IDDA(stb) Digital inputs RESET Vhys LOW-level input voltage HIGH-level input voltage hysteresis voltage Schmitt trigger input input leakage current equivalent pull-down resistance 1.49 0.44 55.73 70.71 1.34 0.58 0.17 92.45 supply voltage (VDD VSS) periphery supply current core supply current Idle mode core supply current Power-down mode core supply current Standby mode core supply current analog supply current Idle mode analog supply current Power-down mode analog supply current Standby mode analog supply current note 0.76 5.11 0.87 0.45 0.95 6.50 1.20 PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
SYMBOL HSYNC, VSYNC Vhys Digital outputs FRAME, LOW-level output voltage HIGH-level output voltage output rise time output fall time 90%; 90%; push-pull 2.84 7.50 6.70 8.85 7.97 LOW-level input voltage HIGH-level input voltage hysteresis voltage Schmitt trigger input input leakage current 1.44 0.40 PARAMETER CONDITIONS MIN. TYP.
SAA55xx
MAX.
UNIT
1.31 0.56 0.00
0.13 10.90 10.00
(OPEN-DRAIN OUTPUT) LOW-level output voltage HIGH-level pull-up output voltage LOW-level input voltage HIGH-level input voltage input leakage current output rise time output fall time 90%; 90%; 2.84 0.00 7.20 4.90 8.64 7.34 0.14 0.00 5.50 0.12 11.10 9.40
Digital input/outputs P0.0 P0.4, P0.7, P1.0 P1.1, P2.1 P2.7, P3.0 P3.7 Vhys LOW-level input voltage HIGH-level input voltage hysteresis voltage Schmitt trigger input input leakage current LOW-level output voltage HIGH-level output voltage output rise time push-pull 90%; push-pull 90%; 1.43 0.41 2.81 6.50 8.47 1.28 5.50 0.55 0.01 0.18 5.50 10.70
output fall time
5.70
7.56
10.00
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
SYMBOL P1.2, P1.3 P2.0 Vhys LOW-level input voltage HIGH-level input voltage hysteresis voltage Schmitt trigger input input leakage current LOW-level output voltage HIGH-level output voltage output rise time push-pull 90%; push-pull 90%; 1.45 0.42 2.81 7.00 8.47 PARAMETER CONDITIONS MIN. TYP.
SAA55xx
MAX.
UNIT
1.29 5.50 0.56 0.02 0.17 5.50 10.50
P0.5 P0.6 Vhys
output fall time
5.40
7.36
9.30
LOW-level input voltage HIGH-level input voltage input leakage current hysteresis voltage Schmitt trigger input LOW-level output voltage HIGH-level output voltage output rise time push-pull 90%; push-pull 90%;
1.43 0.42 2.76 7.40
8.22
1.28 5.50 0.11 0.58 0.20 5.50 8.80
output fall time
4.20
4.57
5.20
P1.4 P1.7 (OPEN-DRAIN) Vhys LOW-level input voltage HIGH-level input voltage hysteresis voltage Schmitt trigger input input leakage current LOW-level output voltage output fall time 90%; 1.62 0.49 69.70 83.67 1.45 5.50 0.60 0.13 0.35 103.30
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
SYMBOL Analog inputs CVBS0 CVBS1 Vsync Vvid(p-p) Zsource IREF Rgnd ADC0 ADC3 Analog outputs output current (black Level) output current (maximum Intensity) output current (70% full Intensity) Rload load resistor VSSA load capacitance VDDA VDDA Intensity level code VDDA Intensity level code resistor tolerance 6.67 HIGH-level input voltage HIGH-level input voltage input capacitance resistor ground resistor tolerance sync voltage amplitude video input voltage amplitude (peak-to-peak value) source impedance HIGH-level input voltage input capacitance PARAMETER CONDITIONS MIN. TYP.
SAA55xx
MAX.
UNIT
VDDA
VDDA
Analog input/output SYNC_FILTER Csync Vsync Crystal oscillator XTALIN LOW-level input voltage HIGH-level input voltage input capacitance VSSA VDDA storage capacitor ground sync filter level voltage nominal sync amplitude 0.35 0.55 0.75
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
SYMBOL XTALOUT fxtal Cosc Txtal Notes Peripheral current dependent external components voltage levels I/Os. Crystal order number 4322 05561. output capacitance fundamental mode Tamb Tamb Tamb Tamb note PARAMETER CONDITIONS MIN. TYP.
SAA55xx
MAX.
UNIT
Crystal specification; notes nominal frequency crystal load capacitance crystal motional capacitance resonance resistance crystal holder capacitance temperature range adjustment tolerance drift
capacitors XTALIN, XTALOUT Tamb
note 10-6 ±100 10-6
4322 05561 crystal used, then formulae crystal specification should used. Where mean capacitances chip XTALIN XTALOUT. Cext value mean stray capacitances external circuit XTALIN XTALOUT. maximum value crystal holder capacitance ensure start-up, Cosc need reduced from initially selected value. Cosc(typ) Cext C0(max) 1/2(Cosc Cext)
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
22.1 I2C-bus characteristics
SAA55xx
Table I2C-bus characteristics FAST-MODE I2C-bus SYMBOL fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO Notes device must internally provide hold time least signal (referred VIL(min) signal) order bridge undefined region falling edge SCL. maximum fHD;DAT only device does stretch period tLOW signal. fast-mode I2C-bus device used standard mode I2C-bus system requirement tSU;DAT must then met. This will automatically case device does stretch period signal. such device does stretch period signal, must output next data line tr(max) tSU;DAT 1000 +1250 (according standard mode I2C-bus specification) before line released. clock frequency free time between STOP START condition hold time (repeated) START condition. After this period, first clock pulse generated. period clock HIGH period clock set-up time repeated START condition data hold time; notes data set-up time, note rise time both signals fall time both signals set-up time STOP condition capacitive load each line PARAMETER MIN. MAX. UNIT
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
QUALITY RELIABILITY
SAA55xx
This device will meet Philips Semiconductors General Quality Specification Business group "Consumer Integrated Circuits SNW-FQ-611-Part principal requirements shown Tables 23.1 Group
Table Acceptance tests TEST Mechanical Electrical Note fraction defective devices, parts million. 23.2 Group cumulative target: cumulative target: <100 REQUIREMENTS(1)
Table Processability tests package family) TEST Solderability Mechanical Solder heat resistance 23.3 Group 0/16 lots 0/15 lots 0/15 lots REQUIREMENTS
Table Reliability tests process family) TEST Operational life Humidity life CONDITIONS REQUIREMENTS(1) hours <1000 temperature, humidity, bias 1000 hours, <2000 equivalent test) Temperature cycling performance Tstg(min) Tstg(max) <2000
Note fraction devices failing test condition, Failures Million. Table Reliability tests device type) TEST latch-up CONDITIONS REQUIREMENTS
Human body model 2000 Machine model latch-up (absolute maximum)
1999
This text here white force landscape pages rotated correctly when browsing through Acrobat reader.This text here _white force landscape pages rotated correctly when browsing through Acrobat reader.This text here inThis text here white force landscape pages rotated correctly when browsing through Acrobat reader. white force landscape pages 1999
Vtune brightness contrast saturation volume volume Vafc status
APPLICATION INFORMATION
Philips Semiconductors
handbook, full pagewidth
Standard microcontrollers with On-Screen Display (OSD)
PH2369 P2.0/TPWM P2.1/PWM0 P2.2/PWM1 P2.3/PWM2 P2.4/PWM3 P2.5/PWM4 P2.6/PWM5 P2.7/PWM6 P3.0/ADC0 P3.1/ADC1 P3.2/ADC2 P3.3/ADC3
EEPROM PCF8582E
P1.5/SDA1 P1.4/SCL1 P1.7/SDA0 P1.6/SCL0 P1.3/T1 P1.2/INT0 P1.1/T0 P1.0/INT1 VDDP RESET XTALOUT XTALIN OSCGND VDDC VSSP VSYNC HSYNC VDDA P3.4/PWM7 FRAME
MBK980
control signals
RECEIVER
program+ program- VHF-L VHF-H menu control signals minus(-) plus(+) CVBS (IF) CVBS (SCART)
field flyback line flyback
VSSD P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 VSSA CVBS0 CVBS1 SYNC_FILTER IREF
SAA55xx
TV's display circuits
Preliminary specification
SAA55xx
Fig.29 Application diagram.
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
ELECTROMAGNETIC COMPATIBILITY (EMC) GUIDELINES Optimization circuit return paths minimisation common mode emission will assisted using double sided Printed-Circuit Board (PCB) with inductance ground plane. single sided printed-circuit board local ground plane under whole Integrated Circuit (IC) should present shown Fig.30. This should connected widest possible connection back printed-circuit board ground connection, bulk electrolytic decoupling capacitor. should preferably connect other grounds way, wire links should present this connect. wire links increases ground bounce introducing inductance into ground. supply pins decoupled ground plane under This easily accomplished using surface mount capacitors, which more effective than leaded components high frequency.
SAA55xx
Using device socket will unfortunately area inductance external bypass loop. ferrite bead inductor with resistive characteristics high frequencies utilised supply line close decoupling capacitor provide high impedance. prevent pollution conduction onto signal lines (which then radiate) signals connected supply pull-up resistor should connected side this ferrite component. OSCGND should connected only crystal load capacitors local circuit ground. Physical connection distances associated active devices should short. Output traces should routed with close proximity mutually coupled ground return paths.
handbook, full pagewidth
+3.3
electrolytic decoupling capacitor
other connections VDDC VDDP VDDA VSSP
ferrite beads
decoupling capacitors
under-IC plane connection note: wire links
under-IC plane
VSSC
VSSA
MBK979
Fig.30 Power supply connections EMC.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
PACKAGE OUTLINES SDIP52: plastic shrink dual in-line package; leads (600 mil)
SAA55xx
SOT247-1
seating plane
index
scale
DIMENSIONS original dimensions) UNIT Note Plastic metal protrusions 0.25 maximum side included. OUTLINE VERSION SOT247-1 REFERENCES JEDEC EIAJ EUROPEAN PROJECTION max. 5.08 min. 0.51 max. 0.53 0.40 0.32 0.23 47.9 47.1 14.0 13.7 1.778 15.24 15.80 15.24 17.15 15.90 0.18 max. 1.73
ISSUE DATE 90-01-22 95-03-11
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
SAA55xx
LQFP100: plastic profile quad flat package; leads; body
SOT407-1
index detail
scale
DIMENSIONS original dimensions) UNIT max. 0.20 0.05 0.25 0.28 0.16 0.18 0.12 14.1 13.9 14.1 13.9 0.75 0.45 0.12 1.15 0.85 1.15 0.85
16.25 16.25 15.75 15.75
Note Plastic metal protrusions 0.25 maximum side included. OUTLINE VERSION SOT407-1 REFERENCES JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-12-19 97-08-04
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
SOLDERING 27.1 Introduction soldering through-hole mount packages
SAA55xx
total contact time successive solder waves must exceed seconds. device mounted seating plane, temperature plastic body must exceed specified maximum storage temperature (Tstg(max)). printed-circuit board been pre-heated, forced cooling necessary immediately after soldering keep temperature within permissible limit. 27.3 Manual soldering
This text gives brief insight wave, manual soldering. more in-depth account soldering found "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 90011). Wave soldering preferred method mounting through-hole mount packages printed-circuit board. 27.2 Soldering dipping solder wave
maximum permissible temperature solder solder this temperature must contact with joints more than seconds. 27.4
Apply soldering iron less) lead(s) package, either below seating plane more than above temperature soldering iron less than remain contact seconds. temperature between contact seconds.
Suitability through-hole mount packages dipping wave soldering methods SOLDERING METHOD PACKAGE DIPPING WAVE suitable(1)
DBS, DIP, HDIP, SDIP, Note
suitable
SDIP packages, longitudinal axis must parallel transport direction printed-circuit board.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA55xx
This data sheet contains target goal specifications product development. This data sheet contains preliminary data; supplementary data published later. This data sheet contains final product specifications.
Limiting values given accordance with Absolute Maximum Rating System (IEC 134). Stress above more limiting values cause permanent damage device. These stress ratings only operation device these other conditions above those given Characteristics sections specification implied. Exposure limiting values extended periods affect device reliability. Application information Where application information given, advisory does form part specification. LIFE SUPPORT APPLICATIONS These products designed life support appliances, devices, systems where malfunction these products reasonably expected result personal injury. Philips customers using selling these products such applications their risk agree fully indemnify Philips damages resulting from such improper sale. PURCHASE PHILIPS COMPONENTS
Purchase Philips components conveys license under Philips' patent components system provided system conforms specification defined Philips. This specification ordered using code 9398 40011.
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
NOTES
SAA55xx
1999
Philips Semiconductors
Preliminary specification
Standard microcontrollers with On-Screen Display (OSD)
NOTES
SAA55xx
1999
Philips Semiconductors worldwide company
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