FEATURES Complete Monolithic 12-Bit with: Track/Hold Amplifier Convert

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FEATURES Complete Monolithic 12-Bit with: Track/Hold Amplifier Convert

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LC2MOS Complete, 12-Bit, Sampling AD7870A
FEATURES Complete Monolithic 12-Bit with: Track/Hold Amplifier Converter On-Chip Reference Laser-Trimmed Clock Parallel, Byte Serial Digital Interface Input Frequency Data Access Time Power-60 APPLICATIONS Digital Signal Processing Speech Recognition Synthesis Spectrum Analysis High Speed Modems Servo Control
GENERAL DESCRIPTION
AD7870A fast, complete, 12-bit converter. consists track/hold amplifier, successive approximation ADC, buried Zener reference versatile interface logic. features self-contained internal clock that laser trimmed guarantee accurate control conversion time. external clock timing components required; on-chip clock overridden external clock required. AD7870A offers choice three data output formats: single, parallel, 12-bit word, 8-bit bytes serial data. Fast access times standard control inputs ensure easy interfacing modern microprocessors digital signal processors. AD7870A operates from power supplies, accepts bipolar input signals convert full power signals kHz. addition traditional accuracy specifications such linearity, full-scale offset errors, AD7870A also fully specified dynamic performance parameters including harmonic distortion signal-to-noise ratio. AD7870A fabricated Analog Devices' linear compatible CMOS (LC2MOS) process, mixed technology process that combines precision bipolar circuits with power CMOS logic. part available 24-pin, 0.3-inch wide, plastic dual inline package (DIP).
PRODUCT HIGHLIGHTS
Complete 12-bit chip. AD7870A most complete monolithic available combines 12-bit with internal clock, track/ hold amplifier reference single chip. Dynamic specifications users. AD7870A fully specified tested parameters, including signal-to-noise ratio, harmonic distortion intermodulation distortion. digital timing parameters also tested guaranteed over full operating temperature range. Fast microprocessor interface. Data access times make AD7870A compatible with modern 16-bit microprocessors digital signal processors.
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Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Site: http://www.analog.com Fax: 617/326-8703 Analog Devices, Inc., 1997
AD7870A-SPECIFICATIONS otherwise noted. specifications
Parameter DYNAMIC PERFORMANCE Signal-to-Noise Ratio3 (SNR) +25°C TMIN TMAX Total Harmonic Distortion (THD) Peak Harmonic Spurious Noise Intermodulation Distortion (IMD) Second Order Terms Third Order Terms Track/Hold Acquisition Time ACCURACY Resolution Minimum Resolution Which Missing Codes Guaranteed Integral Nonlinearity Bipolar Zero Error Positive Full-Scale Error4 Negative Full-Scale Error4 ANALOG INPUT Input Voltage Range Input Current REFERENCE OUTPUT +25°C Tempco Reference Load Sensitivity (REF OUT/I) LOGIC INPUTS Input High Voltage, VINH Input Voltage, VINL Input Current, Input Current (12/8 Input Only) Input Capacitance, CIN5 LOGIC OUTPUTS Output High Voltage, Output Voltage, DB11-DB0 Floating State Leakage Current Floating-State Output Capacitance5 CONVERSION TIME External Clock (fCLK MHz) Internal Clock POWER REQUIREMENTS Power Dissipation
(VDD
AGND DGND fCLK internal, unless TMAX unless otherwise noted.)
Units
Test Conditions/Comments
Sine Wave, SAMPLE Typically 71.5 Sine Wave, fSAMPLE Typically kHz, fSAMPLE Typically kHz, kHz, fSAMPLE kHz, kHz, fSAMPLE
Bits Bits
Volts 2.99 3.01 ppm/°C
Reference Load Current Change µA-500 Reference Load Should Change During Conversion
7.6/8 8/10
min/µs min/µs
ISOURCE ISINK
Specified Performance Specified Performance Typically Typically Typically
NOTES Temperature range follow: Version: +70°C. (pk-pk) calculation includes distortion noise components. Measured with respect internal reference includes bipolar offset error. Sample tested +25°C ensure compliance. Specifications subject change without notice.
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AD7870A TIMING CHARACTERISTICS1,
Parameter t115 t126
AGND DGND Figures 10.)
Limit TMIN, TMAX Version)
Units
Conditions/Comments CONVST Pulse Width Setup Time (Mode Pulse Width Hold Time (Mode Delay Data Access Time after Relinquish Time after HBEN Setup Time HBEN Hold Time SSTRB SCLK Falling Edge Setup Time SCLK Cycle Time SCLK Valid Data Delay. SCLK Rising Edge SSTRB Relinquish Time after SCLK
NOTES Timing specifications bold print 100% production tested. other times sample tested ensure compliance. input signals specified with (10% timed from voltage level Serial timing measured with pull-up resistor SDATA SSTRB pull-up SCLK. capacitance three outputs measured with load circuits Figure defined time required output cross defined time required data lines change when loaded with circuits Figure SCLK mark/space ratio (measured from voltage level 40/60 60/40. SDATA will drive higher capacitive loads this will since increases external time constant (4.7 hence time reach Specifications subject change without notice.
High-Z
High-Z
High-Z
High-Z
Figure Load Circuits Access Time
Figure Load Circuits Output Float Delay
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AD7870A
ABSOLUTE MAXIMUM RATINGS*
AGND -0.3 AGND +0.3 AGND DGND -0.3 +0.3 AGND AGND Digital Inputs DGND -0.3 +0.3 Digital Outputs DGND -0.3 +0.3 Operating Temperature Range Commercial Version) +70°C
Storage Temperature Range -65°C +150°C Lead Temperature (Soldering, sec) +300°C Power Dissipation (Any Package) +75°C Derates above +75°C mW/°C
*Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only; functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD7870A features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality. ORDERING GUIDE Temperature Range +70°C (dBs) Relative Accuracy (LSB) Package Option* N-24
WARNING!
SENSITIVE DEVICE
CONFIGURATION
Model AD7870AJN
Plastic DIP.
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AD7870A
DESCRIPTION
Mnemonic DB11/HBEN
Function Read. Active logic input. This input used conjunction with enable data outputs. Interrupt, Active logic output indicating converter status. timing diagrams. Clock input. external TTL-compatible clock applied this input pin. Alternatively, tying this enables internal laser-trimmed clock oscillator. Data (MSB)/High Byte Enable. function this dependent state 12/8/CLK input (see below). When 12-bit parallel data selected, this provides DB11 output. When byte data selected, this becomes HBEN logic input. HBEN used 8-bit interfacing. When HBEN low, DB7/LOW DB0/DB8 become DB0. With HBEN high, DB7/LOW DB0/DB8 used upper byte data (see Table Data 10/Serial Strobe. When 12-bit parallel data selected, this provides DB10 output. SSTRB active open-drain output that provides strobe framing pulse serial data. external pull-up resistor required SSTRB. Data 9/Serial Clock. When 12-bit parallel data selected, this provides output. SCLK gated serial clock output derived from internal external clock. 12/8/CLK input then SCLK runs continuously. 12/8/CLK then SCLK gated after serial transmission complete. SCLK open-drain output requires external pull-up resistor. Data 8/Serial Data. When 12-bit parallel data selected, this provides output. SDATA open-drain serial data output which used with SCLK SSTRB serial data transfer. Serial data valid falling edge SCLK while SSTRB low. external pull-up resistor required SDATA. Three-state data outputs controlled Their function depends 12/8/CLK HBEN inputs. With 12/8/CLK high, they always DB7-DB4. With 12/8/CLK their function controlled HBEN (see Table Digital Ground. Ground reference digital circuitry. Three-state data outputs which controlled Their function depends 12/8/CLK HBEN inputs. With/12/8/CLK high, they always DB3-DB0. With 12/8/CLK their function controlled HBEN (see Table Positive Supply, Analog Ground. Ground reference track/hold, reference DAC. Voltage Reference Output. internal reference provided this pin. external load capability Analog Input. analog input range Negative Supply, Three Function Input. Defines data format serial clock format. With this output data format 12-bit parallel only. With this either byte serial data available SCLK continuous. With this either byte serial data again available SCLK continuous. Convert Start. high transition this input puts track/hold into hold mode starts conversion. This input asynchronous independent Chip Select. Active logic input. device selected when this input active.
Table Output Data Byte Interfacing
DB10/SSTRB
DB9/SCLK
DB8/SDATA
8-11
DB7/LOW- DB4/LOW
DGND 13-16 DB3/DB11- DB0/DB8 AGND 12/8/CLK
CONVST
HBEN HIGH
DB7/LOW
DB6/LOW
DB5/LOW
DB4/LOW
DB3/DB11
DB2/DB10
DB1/DB9
DB0/DB8 (LSB)
DB11 (MSB) DB10
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AD7870A
CONVERTER DETAILS
AD7870A complete 12-bit converter, requiring external components apart from power supply decoupling capacitors. comprised 12-bit successive approximation based fast settling voltage-output DAC, high speed comparator SAR, track/hold amplifier, buried Zener reference, clock oscillator control logic.
INTERNAL REFERENCE
AD7870A on-chip temperature compensated buried Zener reference that factory trimmed Internally provides both reference bias required bipolar operation. reference output available (REF OUT) capable providing external load. maximum recommended capacitance normal operation reference required external AD7870A, should decoupled with resistor series with parallel combination tantalum capacitor ceramic capacitor. These decoupling components required remove voltage spikes caused AD7870A's internal operation.
Figure Analog Input
ANALOG INPUT
Figure shows AD7870A analog input. analog input range into input resistance typically designed code transitions occur midway between successive integer values (i.e., LSB, LSBs, LSBs LSBs). output code twos complement binary with FS/4096 V/4096 1.46 ideal input/output transfer function shown Figure
Figure Reference Circuit
TRACK-AND-HOLD AMPLIFIER
Figure Bipolar Input/Output Transfer Function
BIPOLAR OFFSET FULL SCALE ADJUSTMENT
track-and-hold amplifier analog input AD7870A allows accurately convert input sine wave peak-peak amplitude 12-bit accuracy. input bandwidth track/hold amplifier much greater than Nyquist rate even when operated maximum throughput rate. cutoff frequency occurs typically kHz. track/hold amplifier acquires input signal 12-bit accuracy less than overall throughput rate equal conversion time plus track/hold amplifier acquisition time. input clock throughput rate max. operation track/hold essentially transparent user. track/hold amplifier goes from tracking mode hold mode start conversion. track-to-hold transition occurs falling edge CONVST.
most digital signal processing (DSP) applications, offset full-scale errors have little effect system performance. Offset error always eliminated analog domain coupling. Full-scale error effect linear does cause problems long input signal within full dynamic range ADC. Some applications will require that input signal span full analog input dynamic range. such applications, offset full-scale error will have adjusted zero. Where adjustment required, offset error must adjusted before full-scale error. This achieved trimming offset driving analog input AD7870A while input voltage below ground. trim procedure follows: apply voltage 0.73 (-1/2 LSB) Figure adjust offset voltage until output code flickers between 1111 1111 1111 0000 0000 0000. Gain error adjusted either first code transition (ADC negative full scale) last code transition (ADC positive full scale). trim procedures both cases follows (see Figure
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AD7870A
ideal input/output transfer function shown Figure output converted natural binary inverting MSB.
Figure Full-Scale Adjust Circuit
Positive Full-Scale Adjust
Apply voltage 2.9978 (FS/2 LSBs) Adjust until output code flickers between 0111 1111 1110 0111 1111 1111.
Negative Full-Scale Adjust
Figure Unipolar Transfer Function
UNIPOLAR OFFSET FULL-SCALE ADJUSTMENT
Apply voltage -2.9993 (-FS/2 LSB) adjust until output code flickers between 1000 0000 0000 1000 0000 0001.
UNIPOLAR OPERATION
typical unipolar circuit shown Figure AD7870A used offset analog input analog input range determined ratio minimum range with which circuit will work O/C). resistor values given Figure input ranges included offset full-scale adjust only should omitted adjustment required.
When absolute accuracy required, offset full-scale error adjusted zero. Offset must adjusted before full scale. This achieved applying input voltage (1/2 LSB) adjust until output code flickers between 1000 0000 0000 1000 0000 0001. full-scale adjustment, apply input voltage (FS-3/2 LSBs) adjust until output code flickers between 0111 1111 1110 0111 11111111.
TIMING CONTROL
AD7870A capable basic interfacing mode. this mode (Mode CONVST line used start conversion drive track/hold into hold mode. conversion track/hold returns tracking mode. principally intended digital signal processing other applications where precise sampling time required. these applications, important that signal sampling occurs exactly equal intervals minimize errors sampling uncertainty jitter. these cases, CONVST line driven timer some precise clock source.
DATA OUTPUT FORMATS
Figure Unipolar Circuit
AD7870A offers choice three data output formats, serial parallel. parallel data formats single, 12-bit parallel word 16-bit data buses two-byte format 8-bit data buses. data format controlled 12/8/CLK input. logic high this selects 12-bit parallel output format only. logic applied this allows user access either serial byte formatted data. Three pins previously assigned four MSBs parallel form used serial communications while fourth becomes control input byte-formatted data.
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AD7870A
Parallel Output Format
parallel formats available AD7870A 12-bit wide data word two-byte data word. first, bits data available same time DB11 (MSB) through (LSB). second, reads required access data. When this data format selected, DB11/HBEN assumes HBEN function. HBEN selects which byte data read from AD7870A. When HBEN low, lower eight bits data placed data during read operation; with HBEN high, upper four bits 12-bit word placed data bus. These four bits right justified thereby occupy lower nibble data while upper nibble contains four zeros.
Serial Output Format
during serial transmission only. these cases, shut down conversion allow multiple ADCs share common serial bus. However, some serial systems (e.g., TMS32020) require serial clock that runs continuously. Both options available AD7870A using 12/8/CLK input. With this input serial clock (SCLK) runs continuously; when 12/8/CLK SCLK turned transmission.
MODE INTERFACE
Serial data available AD7870A when 12/8/CLK input this case DB10/SSTRB, DB9/SCLK DB8/SDATA pins assume their serial functions. Serial data available during conversion with word length bits; four leading zeros, followed 12-bit conversion result starting with MSB. data synchronized serial clock output (SCLK) framed serial strobe (SSTRB). Data clocked high transition serial clock valid falling edge this clock while SSTRB output low. SSTRB goes within three clock cycles after CONVST, first serial data (the first leading zero) valid first falling edge SCLK after SSTRB goes low. three serial lines open-drain outputs require external pull-up resistors. serial clock derived from clock source, which internal external. Normally, SCLK required
Conversion initiated going pulse CONVST input. falling edge this CONVST pulse starts conversion drives track/hold amplifier into hold mode. normally high goes conversion. This line used interrupt microprocessor. read operation AD7870A accesses data line reset high falling edge Trying exercise during conversion cause errors conversion progress. applications where precise sampling critical, CONVST pulse generated from microprocessor line OR-gated with decoded address. Figure shows timing diagram 12-bit parallel data output format (12/8/CLK read AD7870A conversion accesses bits data same time. control output three-state drivers. high, databus three-state. hardwired low, data from previous conversion will remain databus. This data will updated approximately tCONVERT after falling edge CONVST. With hardwired low, line will remain low. Serial data available this data output format.
Figure Mode Timing Diagram, 12-Bit Parallel Read
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AD7870A
Figure Mode Timing Diagram, Byte Serial Read
timing diagram byte serial data shown Figure goes conversion reset high first falling edge This first read conversion either access byte high byte data depending status HBEN (Figure shows byte only example). diagram shows both noncontinuously continuously running clock (dashed line).
AD7870A DYNAMIC SPECIFICATIONS
output spectrum from evaluated applying sine-wave signal very distortion input which sampled sampling rate. Fast Fourier Transform (FFT) plot generated from which data obtained. Figure shows typical 2048 point plot AD7870AJN with input signal sampling frequency kHz. obtained from this graph 72.6 should noted that harmonics taken into account when calculating SNR.
AD7870A specified 100% tested dynamic performance specifications. These specifications required signal processing applications such speech recognition, spectrum analysis high speed modems. These applications require information ADC's effect spectral content input signal. Hence, parameters which AD7870A specified include SNR, harmonic distortion, intermodulation distortion peak harmonics. These terms discussed more detail following sections.
Signal-to-Noise Ratio (SNR)
measured signal-to-noise ratio output ADC. signal magnitude fundamental. Noise nonfundamental signals half sampling frequency (FS/2) excluding dependent upon number quantization levels used digitization process; more levels, smaller quantization noise. theoretical signal-to-noise ratio sine wave input given =(6.02N 1.76) where number bits. Thus ideal 12-bit converter,
Figure Plot
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AD7870A
Effective Number Bits
formula given relates number bits. Rewriting formula, (2), possible obtain measure performance expressed effective number bits (N).
1.76 6.02
ratio individual distortion products amplitude fundamental expressed dBs. this case, input consists two, equal amplitude, distortion sine waves. Figure shows typical plot AD7870A.
effective number bits device calculated directly from measured SNR. Figure shows typical plot effective number bits versus frequency AD7870AJN, with sampling frequency kHz. effective number bits typically falls between 11.7 11.85 corresponding figures 72.2 73.1
Figure Effective Number Bits Frequency
Harmonic Distortion
Harmonic distortion ratio harmonics fundamental. AD7870A, total harmonic distortion (THD) defined
Figure Plot
Peak Harmonic Spurious Noise
where amplitude fundamental amplitudes second through sixth harmonic. also derived from plot output spectrum.
Intermodulation Distortion
Peak harmonic spurious noise defined ratio value next largest component output spectrum FS/2 excluding value fundamental. Normally, value this specification will determined largest harmonic spectrum, parts where harmonics buried noise floor peak will noise peak.
Linearity Plot
With inputs consisting sine waves frequencies, active device with nonlinearities will create distortion products difference frequencies where etc. Intermodulation terms those which neither equal zero. example, second order terms include fb), while third order terms include (2fa fb), (2fa fb), 2fb) 2fb). Using CCIF standard, where input frequencies near input bandwidth used, second third order terms different significance. second order terms usually distanced frequency from original sine waves while third order terms usually frequency close input frequencies. result, second third order terms specified separately. calculation intermodulation distortion specification where
When sine wave specified frequency applied input AD7870A, several million samples taken, histogram showing frequency occurrence each 4096 codes generated. From this histogram data possible generate integral linearity plot shown Figure This shows very good integral linearity performance from AD7870A input frequency kHz. absence large spikes plot shows good differential linearity. Simplified versions formulae used outlined below.
INL(i 4096 fs)-V
where INL(i) integral linearity code V(fs) V(o) estimated full-scale offset transitions V(i) estimated transition code.
-10-
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AD7870A
V(i) estimated code transition point derived follows:
cum(i
noisy code transitions. Other causes concern ground loops digital feedthrough from microprocessors. These factors that influence ADC, proper layout that minimizes these effects essential best performance.
LAYOUT HINTS
where peak signal amplitude, number histogram samples cum(i) V(n) occurrences
Ensure that layout printed circuit board digital analog signal lines separated much possible. Take care digital track alongside analog signal track. Guard (screen) analog input with AGND. Establish single point analog ground (star ground) separate from logic system ground AD7870A AGND close possible AD7870A. Connect other grounds AD7870A DGND this single analog ground point. connect other digital grounds this analog ground point. impedance analog digital power supply common returns essential noise operation ADC, make foil width these tracks wide possible. ground planes minimizes impedance paths also guards analog circuitry from digital noise.
NOISE
Figure Plot
APPLICATION HINTS
Good printed circuit board (PCB) layout important overall circuit design itself achieving high speed performance. AD7870A required make decisions size 1.465 Thus, designer conscious noise both itself preceding analog circuitry. Switching mode power supplies recommended switching spikes will feed through comparator causing
Keep input signal leads signal return leads from AGND short possible minimize input noise coupling. applications where this possible, shielded cable between source ADC. Reduce ground circuit impedance much possible since potential difference grounds between signal source appears error voltage series with input signal.
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
24-Pin Plastic (N-24)
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-11-
-12-
C1628-7.5-2/92
PRINTED U.S.A.

FEATURES Complete Monolithic 12-Bit with: Track/Hold Amplifier Convert

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