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Am29F010B
There change this datasheet result offering device Spansion product. changes that have been made result normal datasheet improvement noted document revision summary, where supported. Future routine revisions will occur when appropriate, changes will noted revision summary.
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Publication Number 22336 Revision
Amendment Issue Date August 2005
THIS PAGE INTENTIONALLY LEFT BLANK
Am29F010B
Megabit (128 8-bit) CMOS Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
Single power supply operation read, erase, program operations Simplifies system-level power requirements Manufactured 0.32 process technology Compatible with Am29F010 Am29F010A device High performance maximum access time power consumption typical active read current typical program/erase current typical standby current Flexible sector architecture Eight Kbyte sectors combination sectors erased Supports full chip erase Sector protection Hardware-based feature that disables/reenables program erase operations combination sectors Sector protection/unprotection implemented using standard PROM programming equipment Embedded Algorithms Embedded Erase algorithm automatically pre-programs erases chip combination designated sector Embedded Program algorithm automatically programs verifies data specified address Erase Suspend/Resume Supports reading data from sector being erased Minimum million erase cycles guaranteed sector 20-year data retention 125°C Reliable operation life system Package options 32-pin PLCC 32-pin TSOP 32-pin PDIP Compatible with JEDEC standards Pinout software compatible with single-power-supply flash Superior inadvertent write protection Data# Polling Toggle Bits Provides software method detecting program erase cycle completion
This Data Sheet states AMD's current technical specifications regarding Products described herein. This Data Sheet revised subsequent versions modifications changes technical specifications.
Publication# 22336 Rev: Amendment/+4 Issue Date: August 2005
GENERAL DESCRIPTION
Am29F010B Mbit, Volt-only Flash memory organized 131,072 bytes. Am29F010B offered 32-pin PDIP, PLCC TSOP packages. byte-wide data appears DQ0-DQ7. device designed programmed in-system with standard system Volt supply. 12.0 volt required program erase operations. device also programmed erased standard EPROM programmers. This device manufactured using AMD's 0.32 process technology, offers features benefits Am29F010 Am29F010A. standard device offers access times allowing high-speed microprocessors operate without wait states. eliminate contention device separate chip enable (CE#), write enable (WE#) output enable (OE#) controls. device requires only single volt power supply both read write functions. Internally generated regulated voltages provided program erase operations. device entirely command compatible with JEDEC single-power-supply Flash standard. Commands written command register using standard microprocessor write timings. Register contents serve input internal state machine that controls erase programming circuitry. Write cycles also internally latch addresses data needed programming erase operations. Reading data device similar reading from other Flash EPROM devices. Device programming occurs executing program command sequence. This invokes Embedded Program algorithm-an internal algorithm that automatically times program pulse widths verifies proper cell margin. Device erasure occurs executing erase command sequence. This invokes Embedded Erase algorithm-an internal algorithm that automatically preprograms array already programmed) before executing erase operation. During erase, device automatically times erase pulse widths verifies proper cell margin. host system detect whether program erase operation complete reading (Data# Polling) (toggle) status bits. After program erase cycle been completed, device ready read array data accept another command. sector erase architecture allows memory sectors erased reprogrammed without affecting data contents other sectors. device erased when shipped from factory. hardware data protection measures include detector automatically inhibits write operations during power transitions. hardware sector protection feature disables both program erase operations combination sectors memory, implemented using standard EPROM programmers. system place device into standby mode. Power consumption greatly reduced this mode. AMD's Flash technology combines years Flash memory manufacturing experience produce highest levels quality, reliability, cost effectiveness. device electrically erases bits within sector simultaneously Fowler-Nordheim tunneling. bytes programmed byte time using EPROM programming mechanism electron injection.
Am29F010B
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TABLE CONTENTS
Product Selector Guide Block Diagram Connection Diagrams Configuration Logic Symbol Ordering Information Device Operations
Table Am29F010B Device Operations
DQ5: Exceeded Timing Limits DQ3: Sector Erase Timer
Table Write Operation Status
Absolute Maximum Ratings
Figure Maximum Negative Overshoot Waveform Figure Maximum Positive Overshoot Waveform
Requirements Reading Array Data Writing Commands/Command Sequences Program Erase Operation Status Standby Mode Output Disable Mode
Table Am29F010B Sector Addresses Table
Operating Ranges Characteristics Test Conditions
Figure Test Setup Table Test Specifications
Switching Waveforms Characteristics
Figure Read Operations Timings
Autoselect Mode
Table Am29F010B Autoselect Codes (High Voltage Method)
Erase Program Operations
Figure Program Operation Timings Figure Chip/Sector Erase Operation Timings Figure Data# Polling Timings (During Embedded Algorithms) Figure Toggle Timings (During Embedded Algorithms)
Sector Protection/Unprotection Hardware Data Protection
Write Inhibit Write Pulse "Glitch" Protection Logical Inhibit Power-Up Write Inhibit
Erase Program Operations
Alternate Controlled Writes Figure Alternate Controlled Write Operation Timings
Command Definitions Reading Array Data Reset Command Autoselect Command Sequence Byte Program Command Sequence
Figure Program Operation
Chip Erase Command Sequence Sector Erase Command Sequence Erase Suspend/Erase Resume Commands
Figure Erase Operation Table Am29F010B Command Definitions
Write Operation Status DQ7: Data# Polling
Figure Data# Polling Algorithm
DQ6: Toggle Reading Toggle
Figure Toggle Algorithm
Erase Programming Performance Latchup Characteristic TSOP Capacitance PLCC PDIP Capacitance Data Retention Physical Dimensions 032-32-Pin Plastic 032-32-Pin Plastic Leaded Chip Carrier 032-32-Pin Standard Thin Small Outline Package 032-32-Pin Standard Thin Small Outline Package Revision Summary
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Am29F010B
PRODUCT SELECTOR GUIDE
Family Part Number Speed Option -120 Am29F010B
Access Time (ns) Access (ns) Access (ns)
Note: Characteristics section full specifications.
BLOCK DIAGRAM
DQ0-DQ7
Erase Voltage Generator
Input/Output Buffers
State Control Command Register
Voltage Generator Chip Enable Output Enable Logic Data Latch
Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0-A16
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CONNECTION DIAGRAMS
PDIP
PLCC
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Am29F010B
CONNECTION DIAGRAMS
Standard TSOP
Reverse TSOP
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CONFIGURATION
A0-A16 Addresses DQ0-DQ7 Data Inputs/Outputs
LOGIC SYMBOL
Chip Enable Output Enable Write Enable +5.0 Volt Single Power Supply (See Product Selector Guide speed options voltage supply tolerances) Device Ground Connected Internally
A0-A16 DQ0-DQ7
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Am29F010B
ORDERING INFORMATION Standard Products
standard products available several packages operating ranges. order number (Valid Combination) formed combination elements below. Am29F010B
TEMPERATURE RANGE Commercial (0°C +70°C) Industrial (-40°C +85°C) Extended (-55°C +125°C) Commerical (0°C +70°C) with Pb-free Package Industrial (-40°C +85°C) with Pb-free Package Extended (-55°C +125°C) with Pb-free Package PACKAGE TYPE 32-Pin Plastic PDIP 032) 32-Pin Rectangular Plastic Leaded Chip Carrier 032) 32-Pin Thin Small Outline Package (TSOP) Standard Pinout 032) 32-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR032) SPEED OPTION Product Selector Guide Valid Combinations DEVICE NUMBER/DESCRIPTION Am29F010B Megabit (128 8-Bit) CMOS Flash Memory Volt-only Read, Program, Erase
Valid Combinations Am29F010B-45 Am29F010B-55
Voltage
Valid Combinations Valid Combinations list configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
Am29F010B-70
Am29F010B-90 Am29F010B-120
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DEVICE OPERATIONS
This section describes requirements device operations, which initiated through internal command register. command register itself does occupy addressable memor location. register composed latches that store commands, along with address data information needed execute command. contents register serve inputs internal state machine. state machine outputs dictate function device. appropriate device operations table lists inputs control levels required, resulting output. following subsections describe each these operations further detail.
Table
Operation Read Write Standby Output Disable Hardware Reset
Am29F010B Device Operations
Addresses (Note DQ0-DQ7 DOUT High-Z High-Z High-Z
Legend: Logic VIL, Logic High VIH, 12.0 Don't Care, Addresses Data DOUT Data Notes: Addresses A16:A0. sector protect sector unprotect functions must implemented programming equipment. "Sector Protection/Unprotection" section.
Requirements Reading Array Data
read array data from outputs, system must drive pins VIL. power control selects device. output control gates array data output pins. should remain VIH. internal state machine reading array data upon device power-up, after hardware reset. This ensures that spurious alteration memory content occurs during power transition. command necessary this mode obtain array data. Standard microprocessor read cycles that assert valid addresses device address inputs produce valid data device data outputs. device remains enabled read access until command register contents altered. "Reading Array Data" more information. Refer Read Operations table timing specifications Read Operations Timings diagram timing waveforms. ICC1 Characteristics table represents active current specification reading array data.
Writing Commands/Command Sequences
write command command sequence (which includes programming data device erasing sectors memory), system must drive VIL, VIH. erase operation erase sector, multiple sectors, entire device. Sector Address Tables indicate address space that each sector occupies. "sector address" consists address bits required uniquely select sector. "Command Definitions" section details erasing sector entire chip. After system writes autoselect command sequence, device enters autoselect mode. system then read autoselect codes from internal register (which separate from memory array) DQ7-DQ0. Standard read cycle timings apply this mode. Refer "Autoselect Mode" "Autoselect Command Sequence" sections more information. ICC2 Characteristics table represents active current specification write mode. Characteristics" section contains timing specification tables timing diagrams write operations.
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Am29F010B
Program Erase Operation Status
During erase program operation, system check status operation reading status bits DQ7-DQ0. Standard read cycle timings read specifications apply. Refer "Write Operation Status" more information, each Characteristics section appropriate data sheet timing diagrams.
device enters CMOS standby mode when held (Note that this more restricted voltage range than VIH.) device enters standby mode when held VIH. device requires standard access time (tCE) before ready read data. device deselected during erasure programming, device draws active current until operation completed. ICC3 Characteristics tables represents standby current specification.
Standby Mode
When system reading writing device, place device standby mode. this mode, current consumption greatly reduced, outputs placed high impedance state, independent input.
Output Disable Mode
When input VIH, output from device disabled. output pins placed high impedance state.
Table
Sector
Am29F010B Sector Addresses Table
Address Range 00000h-03FFFh 04000h-07FFFh 08000h-0BFFFh 0C000h-0FFFFh 10000h-13FFFh 14000h-17FFFh 18000h-1BFFFh 1C000h-1FFFFh
Note: sectors Kbytes size.
Autoselect Mode
autoselect mode provides manufacturer device identification, sector protection verification, through identifier codes output DQ7-DQ0. This mode primarily intended programming equipment automatically match device programmed with corresponding programming algorithm. However, autoselect codes also accessed in-system through command register. When using programming equipment, autoselect mode requires address Address pins must shown Autoselect Codes (High Voltage Method) table. addition, when verifying
sector protection, sector address must appear appropriate highest order address bits. Refer corresponding Sector Address Tables. Command Definitions table shows remaining address bits that don't care. When necessary bits have been required, programming equipment then read corresponding identifier code DQ7-DQ0. access autoselect codes in-system, host system issue autoselect command command register, shown Command Definitions table. This method does require VID. "Command Definitions" details using autoselect mode.
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Table
Am29F010B Autoselect Codes (High Voltage Method)
(protected)
Description Manufacturer Device Am29F010B
Sector Protection Verification
(unprotected)
Logic VIL, Logic High VIH, Sector Address, Don't care.
Sector Protection/Unprotection
hardware sector protection feature disables both program erase operations sector. hardware sector unprotection feature re-enables both program erase operations previously protected sectors. Sector protection/unprotection must implemented using programming equipment. procedure requires high voltage (VID) address control pins. Details this method provided supplement, publication number 22337. Contact representative obtain copy appropriate document. device shipped with sectors unprotected. offers option programming protecting sectors factory prior shipping device through AMD's ExpressFlashService. Contact representative details. possible determine whether sector protected unprotected. "Autoselect Mode" details.
gramming, which might otherwise caused spurious system level signals during power-up power-down transitions, from system noise. Write Inhibit When less than VLKO, device does accept write cycles. This protects data during power-up power-down. command register internal program/erase circuits disabled, device resets. Subsequent writes ignored until greater than VLKO. system must provide proper signals control pins prevent unintentional writes when greater than VLKO. Write Pulse "Glitch" Protection Noise pulses less than (typical) OE#, initiate write cycle. Logical Inhibit Write cycles inhibited holding VIL, VIH. initiate write cycle, must logical zero while logical one. Power-Up Write Inhibit during power device does accept commands rising edge WE#. internal state machine automatically reset reading array data power-up.
Hardware Data Protection
command sequence requirement unlock cycles programming erasing provides data protection against inadvertent writes (refer Command Definitions table). addition, following hardware data protection measures prevent accidental erasure pro-
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Am29F010B
COMMAND DEFINITIONS
Writing specific address data commands sequences into command register initiates device operations. Command Definitions table defines valid register command sequences. Writing incorrect address data values writing them improper sequence resets device reading array data. addresses latched falling edge CE#, whichever happens later. data latched rising edge CE#, whichever happens first. Refer appropriate timing diagrams Characteristics" section.
Autoselect Command Sequence
autoselect command sequence allows host system access manufacturer devices codes, determine whether sector protected. Command Definitions table shows address data requirements. This method alternative that shown Autoselect Codes (High Voltage Method) table, which intended PROM programmers requires address autoselect command sequence initiated writing unlock cycles, followed autoselect command. device then enters autoselect mode, system read address number times, without initiating another command sequence. read cycle address XX00h retrieves manufacturer code. read cycle address XX01h returns device code. read cycle containing sector address (SA) address returns that sector protected, unprotected. Refer Sector Address tables valid sector addresses. system must write reset command exit autoselect mode return reading array data.
Reading Array Data
device automatically reading array data after device power-up. commands required retrieve data. device also ready read array data after completing Embedded Program Embedded Erase algorithm. system must issue reset command re-enable device reading array data goes high, while autoselect mode. "Reset Command" section, next. also "Requirements Reading Array Data" "Device Operations" section more information. Read Operations table provides read parameters, Read Operation Timings diagram shows timing diagram.
Byte Program Command Sequence
Programming four-bus-cycle operation. program command sequence initiated writing unlock write cycles, followed program set-up command. program address data written next, which turn initiate Embedded Program algorithm. system required provide further controls timings. device automatically provides internally generated program pulses verify programmed cell margin. Command Definitions take shows address data requirements byte program command sequence. When Embedded Program algorithm complete, device then returns reading array data addresses longer latched. system determine status program operation using DQ7or DQ6. "Write Operation Status" information these status bits. commands written device during Embedded Program Algorithm ignored. Programming allowed sequence across sector boundaries. cannot programmed from back "1". Attempting halt operation "1", cause Data# Polling algorithm indicate operation successful. However, succeeding read will show that data still "0". Only erase operations convert "1". August 2005
Reset Command
Writing reset command device resets device reading array data. Address bits don't care this command. reset command written between sequence cycles erase command sequence before erasing begins. This resets device reading array data. Once erasure begins, however, device ignores reset commands until operation complete. reset command written between sequence cycles program command sequence before programming begins. This resets device reading array data. Once programming begins, however, device ignores reset commands until operation complete. reset command written between sequence cycles autoselect command sequence. Once autoselect mode, reset command must written return reading array data. goes high during program erase operation, writing reset command returns device reading array data.
Am29F010B
START
Embedded Erase algorithm complete, device returns reading array data addresses longer latched. Figure illustrates algorithm erase operation. Erase/Program Operations tables Characteristics" parameters, Chip/Sector Erase Operation Timings timing waveforms.
Write Program Command Sequence
Sector Erase Command Sequence
Embedded Program algorithm progress Data Poll from System
Verify Data?
Sector erase cycle operation. sector erase command sequence initiated writing unlock cycles, followed set-up command. additional unlock write cycles then followed address sector erased, sector erase command. Command Definitions table shows address data requirements sector erase command sequence. device does require system preprogram memory prior erase. Embedded Erase algorithm automatically programs verifies sector zero data pattern prior electrical erase. system required provide controls timings during these operations. After command sequence written, sector erase time-out begins. During time-out period, additional sector addresses sector erase commands written. Loading sector erase buffer done sequence, number sectors from sector sectors. time between these additional cycles must less than otherwise last address command might accepted, erasure begin. recommended that processor interrupts disabled during this time ensure commands accepted. interrupts re-enabled after last Sector Erase command written. time between additional sector erase commands assumed less than system need monitor DQ3. command during time-out period resets device reading array data. system must rewrite command sequence additional sector addresses commands. system monitor determine sector erase timer timed out. (See "DQ3: Sector Erase Timer" section.) time-out begins from rising edge final pulse command sequence. Once sector erase operation begun, other commands ignored. When Embedded Erase algorithm complete, device returns reading array data addresses longer latched. system determine status erase operation using DQ6. Refer "Write Operation Status" information these status bits.
Increment Address
Last Address?
Programming Completed
Note: appropriate Command Definitions table program command sequence.
Figure
Program Operation
Chip Erase Command Sequence
Chip erase six-bus-cycle operation. chip erase command sequence initiated writing unlock cycles, followed set-up command. additional unlock write cycles then followed chip erase command, which turn invokes Embedded Erase algorithm. device does require system preprogram prior erase. Embedded Erase algorithm automatically preprograms verifies entire memory zero data pattern prior electrical erase. system required provide controls timings during these operations. Command Definitions table shows address data requirements chip erase command sequence. commands written chip during Embedded Erase algorithm ignored. system determine status erase operation using DQ6. "Write Operation Status" information these status bits. When August 2005
Am29F010B
Figure illustrates algorithm erase operation. Refer Erase/Program Operations tables Characteristics" section parameters, Sector Erase Operations Timing diagram timing waveforms.
Erase Suspend/Erase Resume Commands
Erase Suspend command allows system interrupt sector erase operation then read data from, program data sector selected erasure. This command valid only during sector erase operation, including time-out period during sector erase command sequence. Erase Suspend command ignored written during chip erase operation Embedded Program algorithm. Writing Erase Suspend command during Sector Erase time-out immediately terminates time-out period suspends erase operation. Addresses "don't-cares" when writing Erase Suspend command. When Erase Suspend command written during sector erase operation, device requires maximum suspend erase operation. However, when Erase Suspend command written during sector erase time-out, device immediately terminates time-out period suspends erase operation. After erase operation been suspended, system read array data from sector selected erasure. (The device "erase suspends" sectors selected erasure.) Normal read write timings command definitions apply. Reading address within erase-suspended sectors produces status data DQ7-DQ0. system determine sector actively erasing erase-suspended. "Write Operation Status" information these status bits. After erase-suspended program operation complete, system once again read array data within non-suspended sectors. system determine status program operation using status bits, just standard program operation. Operation Status" more information. system also write autoselect command sequence when device Erase Suspend
mode. device allows reading autoselect codes even addresses within erasing sectors, since codes stored memory array. When device exits autoselect mode, device reverts Erase Suspend mode, ready another valid operation. "Autoselect Command Sequence" more information. system must write Erase Resume command (address bits "don't care") exit erase suspend mode continue sector erase operation. Further writes Resume command ignored. Another Erase Suspend command written after device resumed erasing.
START
Write Erase Command Sequence
Data Poll from System
Embedded Erase algorithm progress
Data FFh?
Erasure Completed
Notes: appropriate Command Definitions table erase command sequence. "DQ3: Sector Erase Timer" more information.
Figure
Erase Operation
Am29F010B
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Command Definitions
Table
Command Sequence (Note Read (Note Reset (Note Reset (Note Manufacturer Autoselect (Note Device Sector Protect Verify (Note
Am29F010B Command Definitions
Cycles (Notes 2-3)
Cycles
First Addr XXXX Data
Second Addr Data
Third Addr
Fourth Data
Fifth Addr Data
Sixth Addr Data
Data Addr
(SA)
Program Chip Erase Sector Erase Erase Suspend (Note Erase Resume (Note Legend: Don't care
Address memory location read. Data read from location during read operation. Address memory location programmed. Addresses latch falling edge pulse, whichever happens later.
Data programmed location Data latches rising edge pulse, whichever happens first. Address sector verified autoselect mode) erased. Address bits A16-A14 uniquely select sector.
Notes: Table description operations. values hexadecimal. Except when reading array autoselect data, command cycles write operations. unlock command cycles required when reading array data. Reset command required return reading array data when device autoselect mode, goes high (while device providing status data). device accepts three-cycle reset command sequence backward compatibility.
fourth cycle autoselect command sequence read operation. data unprotected sector protected sector. "Autoselect Command Sequence" more information. system read non-erasing sectors, enter autoselect mode, when Erase Suspend mode. Erase Suspend command valid only during sector erase operation. Erase Resume command valid only during Erase Suspend mode.
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Am29F010B
WRITE OPERATION STATUS
device provides several bits determine status write operation: DQ3, DQ5, DQ6, DQ7. Table following subsections describe functions these bits. each offer method determining whether program erase operation complete progress. These three bits discussed first.
START
DQ7: Data# Polling
Data# Polling bit, DQ7, indicates host system whether Embedded Algorithm progress completed. Data# Polling valid after rising edge final pulse program erase command sequence. During Embedded Program algorithm, device outputs complement datum programmed DQ7. When Embedded Program algorithm complete, device outputs datum programmed DQ7. system must provide program address read valid status information DQ7. program address falls within protected sector, Data# Polling active approximately then device returns reading array data. During Embedded Erase algorithm, Data# Polling produces DQ7. When Embedded Erase algorithm complete, Data# Polling produces DQ7. This analogous complement/true datum output described Embedded Program algorithm: erase function changes bits sector "1"; prior this, device outputs "complement," "0." system must provide address within sectors selected erasure read valid status information DQ7. After erase command sequence written, sectors selected erasing protected, Data# Polling active approximately then device returns reading array data. selected sectors protected, Embedded Erase algorithm erases unprotected sectors, ignores selected sectors that protected. When system detects changed from complement true data, read valid data DQ7- following read cycles. This because change asynchronously with DQ0-DQ6 while Output Enable (OE#) asserted low. Data# Polling Timings (During Embedded Algorithms) figure Characteristics" section illustrates this. Table shows outputs Data# Polling DQ7. Figure shows Data# Polling algorithm.
Read DQ7-DQ0 Addr
Data?
Read DQ7-DQ0 Addr
Data?
FAIL PASS
Notes: Valid address programming. During sector erase operation, valid address address within sector selected erasure. During chip erase, valid address non-protected sector address. should rechecked even because change simultaneously with DQ5.
Figure
Data# Polling Algorithm
DQ6: Toggle
Toggle indicates whether Embedded Program Erase algorithm progress complete. Toggle read address, valid after rising edge final pulse com-
Am29F010B
August 2005
mand sequence (prior program erase operation), during sector erase time-out. During Embedded Program Erase algorithm operation, successive read cycles address cause toggle. (The system either control read cycles.) When operation complete, stops toggling. After erase command sequence written, sectors selected erasing protected, toggles approximately then returns reading array data. selected sectors protected, Embedded Erase algorithm erases unprotected sectors, ignores selected sectors that protected. program address falls within protected sector, toggles approximately after program command sequence written, then returns reading array data. Write Operation Status table shows outputs Toggle DQ6. Refer Figure toggle algorithm, Toggle Timings figure Characteristics" section timing diagram.
START
Read DQ7-DQ0
Read DQ7-DQ0
(Note
Toggle Toggle?
Reading Toggle
Refer Figure following discussion. Whenever system initially begins reading toggle status, must read DQ7-DQ0 least twice determine whether toggle toggling. Typically, system would note store value toggle after first read. After second read, system would compare value toggle with first. toggle toggling, device completed program erase operation. system read array data DQ7-DQ0 following read cycle. However, after initial read cycles, system determines that toggle still toggling, system also should note whether value high (see section DQ5). system should then determine again whether toggle toggling, since toggle have stopped toggling just went high. toggle longer toggling, device successfully completed program erase operation. still toggling, device complete operation successfully, system must write reset command return reading array data. remaining scenario that system initially determines that toggle toggling gone high. system continue monitor toggle through successive read cycles, determining status described previous paragraph. Alternatively, choose perform other system tasks. this case, system must start August 2005
Read DQ7-DQ0 Twice
(Notes
Toggle Toggle?
Program/Erase Operation Complete, Write Reset Command Program/Erase Operation Complete
Notes: Read toggle twice determine whether toggling. text. Recheck toggle because stop toggling changes "1". text.
Figure
Toggle Algorithm
beginning algorithm when returns determine status operation (top Figure
DQ5: Exceeded Timing Limits
indicates whether program erase time exceeded specified internal pulse count limit. Under these conditions produces "1." This failure condition that indicates program erase cycle successfully completed.
Am29F010B
failure condition appear system tries program location that previously programmed "0." Only erase operation change back "1." Under this condition, device halts operation, when operation exceeded timing limits, produces "1." Under both these conditions, system must issue reset command return device reading array data.
guarantee that time between additional sector erase commands will always less than also "Sector Erase Command Sequence" section. After sector erase command sequence written, system should read status (Data# Polling) (Toggle ensure device accepted command sequence, then read DQ3. "1", internally controlled erase cycle begun; further commands ignored until erase operation complete. "0", device will accept additional sector erase commands. ensure command been accepted, system software should check status prior following each subsequent sector erase command. high second status check, last command might have been accepted. Table shows outputs DQ3.
DQ3: Sector Erase Timer
After writing sector erase command sequence, system read determine whether erase operation begun. (The sector erase timer does apply chip erase command.) additional sectors selected erasure, entire timeout also applies after each additional sector erase command. When time-out complete, switches from "1." system ignore sys-
Table
Operation Standard Mode Erase Suspend Mode Embedded Program Algorithm Embedded Erase Algorithm Reading within Erase Suspended Sector
Write Operation Status
(Note DQ7# Data Toggle Toggle toggle Data (Note Data Data
Reading within Non-Erase Suspended Sector
Notes: requires valid address when reading status information. Refer appropriate subsection further details. switches when Embedded Program Embedded Erase operation exceeded maximum timing limits. "DQ5: Exceeded Timing Limits" more information.
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ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages -65°C +125°C Ambient Temperature with Power Applied. -55°C +125°C Voltage with Respect Ground (Note -2.0 +7.0 (Note -2.0 +13.0 other pins (Note -2.0 +7.0 Output Short Circuit Current (Note
Notes: Minimum voltage input -0.5 During voltage transitions, inputs overshoot -2.0 periods Figure Maximum voltage input pins During voltage transitions, input pins overshoot periods Figure Minimum input voltage -0.5V. During voltage transitions, pins overshoot -2.0 periods Figure Maximum input voltage +12.5 which overshoot 14.0 periods more than output shorted time. Duration short circuit should greater than second. Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational sections this specification implied. Exposure device absolute maximum rating conditions extended periods affect device reliability. +2.0 +0.5 +0.8 -0.5 -2.0
Figure Maximum Negative Overshoot Waveform
Figure Maximum Positive Overshoot Waveform
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) +70°C Industrial Devices Ambient Temperature (TA) -40°C +85°C Extended Devices Ambient Temperature (TA) -55°C +125°C Supply Voltages devices .+4.75 +5.25 ±10% devices .+4.50 +5.50
Operating ranges define those limits between which functionality device guaranteed.
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Am29F010B
CHARACTERISTICS TTL/NMOS Compatible
Parameter Symbol ILIT ICC1 ICC2 ICC3 VLKO Parameter Description Input Load Current Input Load Current Output Leakage Current Active Read Current (Notes Active Write Current (Notes Standby Current Input Voltage Input High Voltage Voltage Autoselect Sector Protect Output Voltage Output High Voltage Lock-out Voltage -2.5 Test Description VCC, Max, 12.5 VOUT VCC, VIL, VIL, -0.5 10.5 ±1.0 ±1.0 12.5 0.45 Unit
Notes: current listed typically less than mA/MHz, with VIH. Maximum specifications tested with VCC=VCCmax. active while Embedded Program Embedded Erase Algorithm progress. 100% tested.
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CHARACTERISTICS (Continued) CMOS Compatible
Parameter Symbol ILIT ICC1 ICC2 ICC3 VOH1 VOH2 VLKO Lock-out Voltage Parameter Description Input Load Current Input Load Current Output Leakage Current Test Description VCC, Max, 12.5 VOUT VCC, -0.5 5.25 -2.5 -100 0.85 10.5 ±1.0 ±1.0 12.5 0.45 Unit
Active Current (Notes VIL, Active Current (Notes Standby Current (Note Input Voltage Input High Voltage Voltage Autoselect Sector Protect Output Voltage Output High Voltage VIL,
Notes: current listed typically less than mA/MHz, with VIH. Maximum specifications tested with VCC=VCCmax. active while Embedded Program Embedded Erase Algorithm progress. 100% tested. ICC3 extended temperatures +85°C).
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Am29F010B
TEST CONDITIONS
Table
Test Condition Device Under Test Output Load Output Load Capacitance, (including capacitance) Input Rise Fall Times Input Pulse Levels Input timing measurement reference levels Note: Diodes IN3064 equivalent Output timing measurement reference levels 0.0-3.0 others Unit gate 0.45-2.4
Test Specifications
Figure
Test Setup
SWITCHING WAVEFORMS
WAVEFORM INPUTS Steady Changing from Changing from Don't Care, Change Permitted Does Apply Changing, State Unknown Center Line High Impedance State (High OUTPUTS
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CHARACTERISTICS Read-only Operations Characteristics
Parameter Symbol JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tACC Parameter Description Read Cycle Time (Note Address Output Delay Chip Enable Output Delay Output Enable Output Delay Chip Enable Output High (Note Output Enable Output High (Note Read tOEH Output Enable Hold Time (Note Output Hold Time From Addresses OE#, Whichever Occurs First Toggle Data Polling Test Setup Speed Options -120 Unit
tAXQX
Notes: 100% tested. Figure Table test specifications.
Addresses tOEH HIGH Outputs Output Valid HIGH Addresses Stable tACC
Figure
Read Operations Timings
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Am29F010B
CHARACTERISTICS Erase Program Operations
Parameter Symbol JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX tOES tGHWL tELWL tWHEH tWLWH tWHWL tWHWH1 tWHWH2 tGHWL tWPH tWHWH1 tWHWH2 tVCS Notes: 100% tested. "Erase Programming Performance" section more informaiton. Parameter Description Write Cycle Time (Note Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Recover Time Before Write (OE# High Low) Setup Time Hold Time Write Pulse Width Write Pulse Width High Byte Programming Operation (Note Chip/Sector Erase Operation (Note Time (Note Speed Options -120 Unit
Am29F010B
August 2005
CHARACTERISTICS
Program Command Sequence (last cycles) Addresses 555h Data Status DOUT tWPH tWHWH1 Read Status Data (last cycles)
tVCS
Note: program address, program data, DOUT true data program address.
Figure
Program Operation Timings
Erase Command Sequence (last cycles) Addresses 2AAh
555h chip erase
Read Status Data
tWPH
tWHWH2
Data
Chip Erase Progress Complete
tVCS
Note: sector address (for Sector Erase), Valid Address reading status data (see "Write Operation Status").
Figure
Chip/Sector Erase Operation Timings
August 2005
Am29F010B
CHARACTERISTICS
Addresses tACC tOEH
High
Complement
Complement
True
Valid Data
High
DQ0-DQ6
Status Data
Status Data
True
Valid Data
Note: Valid address. Illustration shows first status cycle after command sequence, last status read cycle, array data read cycle.
Figure
Data# Polling Timings (During Embedded Algorithms)
Addresses tACC tOEH
High
Valid Status (first read)
Valid Status (second read)
Valid Status (stops toggling)
Valid Data
Note: Valid address; required DQ6. Illustration shows first status cycle after command sequence, last status read cycle, array data read cycle.
Figure
Toggle Timings (During Embedded Algorithms)
Am29F010B
August 2005
CHARACTERISTICS Erase Program Operations
Alternate Controlled Writes
Parameter Symbol JEDEC tAVAV tAVEL tELAX tDVEH tEHDX Standard tOES tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH2 tGHEL tCPH tWHWH1 tWHWH2 Parameter Description Write Cycle Time (Note Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time (Note Read Recover Time Before Write Setup Time Hold Time Pulse Width Pulse Width High Byte Programming Operation (Note Chip/Sector Erase Operation (Note Speed Options -120 Unit
Notes: 100% tested. "Erase Programming Performance" section more information.
August 2005
Am29F010B
CHARACTERISTICS
program erase program sector erase chip erase
Data# Polling
Addresses tGHEL tCPH Data
program erase program sector erase chip erase
tWHWH1
DQ7#
DOUT
Notes: Program Address, Program Data, Sector Address, DQ7# Complement Data Input, DOUT Array Data. Figure indicates last cycles command sequence.
Figure
Alternate Controlled Write Operation Timings
ERASE PROGRAMMING PERFORMANCE
Limits Parameter Chip/Sector Erase Time Byte Programming Time Chip Programming Time (Note (Note (Note 6.25 Unit Comments Excludes programming prior erasure (Note Excludes system-level overhead (Note
Notes: Typical program erase times assume following conditions: 25°C, VCC, million cycles. Additionally, programming typicals assume checkerboard pattern. Under worst case conditions 90°C, (4.75 -45), 100,000 cycles. typical chip programming time considerably less than maximum chip programming time listed, since most bytes program faster than maximum byte program time listed. maximum byte program time given exceeded, only then does device section further information. pre-programming step Embedded Erase algorithm, bytes programmed before erasure. System-level overhead time required execute four-bus-cycle command sequence programming. Table further information command definitions. device minimum guaranteed erase cycle endurance million cycles.
Am29F010B
August 2005
LATCHUP CHARACTERISTIC
Parameter Description Input Voltage with respect pins Current Note: Includes pins except VCC. Test conditions: Volt, time. -1.0 -100 +100
TSOP CAPACITANCE
Parameter Symbol COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Capacitance VOUT Test Conditions Unit
Notes: Sampled, 100% tested. Test conditions 25°C, MHz.
PLCC PDIP CAPACITANCE
Parameter Symbol COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Capacitance VOUT Test Conditions Unit
Notes: Sampled, 100% tested. Test conditions 25°C, MHz.
DATA RETENTION
Parameter Description Minimum Pattern Data Retention Time Test Conditions 150°C Unit Years Years
125°C
August 2005
Am29F010B
PHYSICAL DIMENSIONS 032-32-Pin Plastic
10/99
Am29F010B
August 2005
PHYSICAL DIMENSIONS* (continued) 032-32-Pin Plastic Leaded Chip Carrier
10/99
August 2005
Am29F010B
PHYSICAL DIMENSIONS* (continued) 032-32-Pin Standard Thin Small Outline Package
10/99
reference only. ANSI standard Basic Space Centering.
Am29F010B
August 2005
PHYSICAL DIMENSIONS* (continued) 032-32-Pin Standard Thin Small Outline Package
10/99
reference only. ANSI standard Basic Space Centering.
August 2005
Am29F010B
REVISION SUMMARY Revision (August 1999)
Initial release. Am29F010B replaces Am29F010A data sheet (22181B+1).
Revision (November 2000)
Global Added table contents. Removed Preliminary status from document. Ordering Information Deleted burn-in option.
Revision (September 1999)
Device Operations Sector Protection/Unprotection: Corrected publication number programming supplement.
Revision (November 2002)
Ordering Information Deleted (PDIP, Extended Temperature Range) combination from speed options. Operating Ranges Changed Case Temperature Ambient Temperature.
Revision (September 1999)
Erase Programming Performance table Notes corrected erase cycle endurance million cycles.
Revision (November 1999)
Characteristics-Figure Program Operations Timing Figure Chip/Sector Erase Operations Deleted tGHWL changed waveform start high. Physical Dimensions Replaced figures with more detailed illustrations.
Revision (September 2004)
Added PB-Free option Standard Ordering Matrix. Updated Valid Combinations
Revision (April 2005)
Added nomenclature Valid Combinations.
Revision (August 2005)
Added Pb-free option PLCC PDIP packages.
Colophon products described this document designed, developed manufactured contemplated general use, including without limitation, ordinary industrial use, general office use, personal use, household use, designed, developed manufactured contemplated that includes fatal risks dangers that, unless extremely high safety secured, could have serious effect public, could lead directly death, personal injury, severe physical damage other loss (i.e., nuclear reaction control nuclear facility, aircraft flight control, traffic control, mass transport control, medical life support system, missile launch control weapon system), where chance failure intolerable (i.e., submersible repeater artificial satellite). Please note that Spansion will liable and/or third party claims damages arising connection with above-mentioned uses products. semiconductor devices have inherent chance failure. must protect against injury, damage loss from such failures incorporating safety design measures into your facility equipment such redundancy, fire protection, prevention over-current levels other abnormal operating conditions. products described this document represent goods technologies subject certain restrictions export under Foreign Exchange Foreign Trade Japan, Export Administration Regulations applicable laws other country, prior authorization respective government entity will required export those products
Trademarks Copyright ©2002-2005 Advanced Micro Devices, Inc. rights reserved. AMD, logo, combinations thereof registered trademarks Advanced Micro Devices, Inc. ExpressFlash trademark Advanced Micro Devices, Inc. Product names used this publication identification purposes only trademarks their respective companies.
Am29F010B
August 2005
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