On-chip CS5516 CS5520 complete solutions digitizing level signals

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On-chip CS5516 CS5520 complete solutions digitizing level signals

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CS5516 CS5516 CS5520 CS5520 16-bit 20-bit Bridge Transducer Converter 16-Bit/20-Bit Bridge Transducer Converters
On-chip
CS5516 CS5520 complete solutions digitizing level signals from strain gauges, load cells, pressure transducers. family output transducers, including those requiring bridge excitation, interfaced directly CS5516 CS5520. devices offer on-chip software programmable instrumentation amplifier block, choice bridge excitation, software selectable reference signal demodulation. CS5516 uses delta-sigma modulation achieve 16-bit resolution output word rates Sps. CS5520 achieves 20-bit resolution output word rates Sps. CS5516 CS5520 sample rate user form either external CMOS clock crystal. On-chip digital filtering provides rejection frequencies above 4.096 clock. CS5516 CS5520 include system calibration null offset gain errors input channel. digital values associated with system calibration written read from, calibration locations time serial communications port. 4-bit offset converter, conjunction with digital correction, initially used zero input offset value. ORDERING INFORMATION page
Instrumentation Amplifier On-chip Programmable Gain Amplifier On-Chip 4-Bit Offset Removal Dynamic Excitation Options Linearity Error: ±0.0015%
20-bit, Missing Codes
CMRR
50/60 System Calibration Capability with calibration read/write option 5-wire Serial Communications Port Power Consumption:
Standby Mode Portable applications
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Cirrus Logic, Inc. Crystal Semiconductor Products Division http://www.cirrus.com P.O. 17847, Austin, Texas 78760 (512) 7222 FAX: (512) 7581 http://www.crystal.com
Copyright Cirrus Logic, Inc. 1997 Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) (All Rights Reserved)
DS74F1 DS74F2
CS5516
VA+, VD+, MDRV+ VA-, -5V; VREF= 2.5V(external differential voltage across VREF+ VREF-); fCLK 4.9152 MHz; Excitation Gain Bipolar Mode; Rsource with 4.7nF AGND (see Note unless otherwise specified.) Parameter* Specified Temperature Range (Note (Note (Note (Note 0.0015 ±0.25 ±0.005 0.003 ±0.5 Units ±%FS LSB16 ppm/°C LSB16 LSB16 µV/°C
ANALOG CHARACTERISTICS TMIN TMAX;
Accuracy
Linearity Error Differential Nonlinearity Unipolar Gain Error Bipolar Gain Error Unipolar/Bipolar Gain Drift Unipolar Offset Bipolar Offset Offset Drift Noise (Referred Input)
Gain nVrms Gain nVrms Gain nVrms Gain nVrms Notes: VREF pins present very high input resistance minor dynamic load which scales master clock frequency. Both source resistance shunt capacitance therefore critical determining source impedance requirements CS5516 CS5520 these pins. Applies after system calibration temperature interest.
0.76 1.52 3.04 6.08
LSB's 0.26 0.50 1.00 2.00 4.00
Unipolar Mode 0.0004 0.0008 0.0015 0.0030 0.0061 VREF 2.5V
LSB's 0.13 0.26 0.50 1.00 2.00
Bipolar Mode 0.0002 0.0004 0.0008 0.0015 0.0030 gain
CS5516; 16-Bit Unit Conversion Factors Refer Specification Definitions immediately following Description Section. Specifications subject change without notice. DS74F1 DS74F2
CS5520
ANALOG CHARACTERISTICS (continued)
Parameter* Specified Temperature Range Missing Codes) (Note (Note (Note (Note Gain Gain Gain Gain 0.0007 ±0.005 0.0015 Units ±%FS Bits ppm/°C LSB20 LSB20 µV/°C nVrms nVrms nVrms nVrms
Accuracy
Linearity Error Differential Nonlinearity Unipolar Gain Error Bipolar Gain Error Unipolar/Bipolar Gain Drift Unipolar Offset Bipolar Offset Offset Drift Noise (Referred Input)
0.025 0.047 0.095 0.190 0.380
LSB's 0.26 0.50 1.00 2.00 4.00
Unipolar Mode 0.0000238 0.0000477 0.0000954 0.0001907 0.0003814 VREF 2.5V
0.25 0.50
LSB's 0.13 0.26 0.50 1.00 2.00
Bipolar Mode 0.0000119 0.0000238 0.0000477 0.0000954 0.0001907 gain
0.125 0.25 0.50
CS5520; 20-Bit Unit Conversion Factors
Refer Specification Definitions immediately following Description Section. Specifications subject change without notice. DS74F1 DS74F2
CS5516, CS5520
ANALOG CHARACTERISTICS (continued)
Parameter Specified Temperature Range Unipolar Bipolar (Note 12.5, ±12.5, ±25, ±50, ±100 (Note (Note (Note (Note XIN/128 V/µsec nVrms Units
Analog Input
Analog Input Range Common Mode Rejection Input Capacitance Input Bias Current
Instrumentation Amplifier
Gain Bandwidth Unity Gain Bandwidth Output Slew Rate Noise Power Supply Rejection 50/60 Common Mode Range Chopping Frequency
Programmable Gain Amplifier
Gain Tracking
4-Bit Offset Trim
Accuracy
Voltage Reference Input
Range Common Mode Rejection: Input Capacitance
Input Bias Current (Note Notes: This includes on-chip digital filtering. maximum magnitude differential input voltage, Vdiff(in) determined following: Vdiff(in) |Vcm/12.5 should never exceed 300mV. common mode voltage which applied instrumentation amplifier inputs. above equation should used calculate allowable common mode voltage given differential voltage applied first gain stage inputs. This limit ensures that instrumentation amplifier does saturate. Gain tracking accuracy significantly improved uploading calibrated gain word gain register each gain selection. common mode voltage Voltage Reference Input, plus reference range, [(VREF+) (VREF-)]/2, must exceed volts.
DS74F1 DS74F2
CS5516, CS5520
ANALOG CHARACTERISTICS (continued)
Parameter (4.75V 5.25V) Source Current Sink Current IAID+ ID(Note Normal Operation Standby Mode Positive Supplies Negative Supplies (Note Unipolar Mode Bipolar Mode (Note Unipolar Mode Bipolar Mode (Notes Unipolar Mode Bipolar 3.75 ±100 -2.7 -0.6 37.5 -3.5 -0.8 Units ppm/°C mV/V µVp-p
Modulator Differential Voltage Reference
Nominal Output Voltage Initial Output Voltage Tolerance Temperature Coefficient Line Regulation Output Voltage Noise Output Current Drive:
Power Supplies
Power Supply Currents
Power Dissipation:
Power Supply Rejection:
System Calibration Specifications
Positive Full Scale Calibration Range 0.8T 0.8T Voffset (1.2T) Voffset (1.2T) 1.2T 1.2T
Maximum Ratiometric Offset Calibration Range
Differential Input Voltage Range
Notes: outputs unloaded. inputs CMOS levels. T=VREF/(Gx25), where full scale span, where VREF differential voltage across VREF+ VREF- volts, gain setting second gain block. This sets overall gain 100, 200. gain then fine tuned using calibration full scale point. When calibrated. Voffset offset corrected offset calibration routine. offset large
DS74F1 DS74F2
CS5516, CS5520
DYNAMIC CHARACTERISTICS
Parameter VREF Input Sampling Frequency Modulator Sampling Frequency Output Update Rate Filter Corner Frequency Settling Time ±0.0007% Step) Symbol fout f-3dB Ratio fclk/128 fclk/256 fclk/81,920 fclk/341,334 6/fout Units
DIGITAL CHARACTERISTICS TMIN TMAX; VA+, VA-, DGND measurements below performed under static conditions.
Parameter High-Level Input Voltage: Low-Level Input Voltage High-Level Output Voltage Low-Level Output Voltage Input Leakage Current 3-State Leakage Current Digital Output Capacitance Pins Except Pins Except (Note lout 1.6mA Symbol Cout (VD+)-1.0 Units
Notes: Iout -100 This guarantees ability drive load. (VOH 2.4V Iout µA).
DS74F1 DS74F2
CS5516, CS5520
RECOMMENDED OPERATING CONDITIONS (AGND, DGND Note 12.)
Parameter Power Supplies: Positive Digital Negative Digital Positive Analog Negative Analog Symbol VDVA+ VA(VREF+) (VREF-) -4.5 -4.5 -5.0 -5.0 -5.5 -5.5 Units
Differential Analog Reference Voltage Analog Input Voltage:
(Note Unipolar VAIN Bipolar VAIN Notes: voltages with respect ground. CS5516 CS5520 accept input voltages unipolar mode bipolar mode where T=VREF/(Gx25). gain setting second gain block. When inputs exceed these values, CS5516 CS5520 will output positive full scale input above negative full scale inputs below AGND unipolar bipolar mode. This applies when analog input does exceed overrange.
ABSOLUTE MAXIMUM RATINGS*
Parameter Power Supplies: Positive Digital Negative Digital Positive Analog Negative Analog VREF pins
(AGND, DGND voltages with respect ground.) Symbol (Note VDVA+ VAlin VINA VIND -0.3 -0.3 -0.3 +0.3 (VA-)-0.3 -0.3 (VA+)+0.3 -5.5 -5.5 (VA+)+0.3 (VD+)+0.3 Units
Input Current, Except Supplies Analog Input Voltage Digital Input Voltage Ambient Operating Temperature
(Notes
Storage Temperature Tstg Notes: should more positive than (VA+)+0.3V. must always less than (VA+)+0.3 V,and never exceed 6.0V. Applies pins including continuous overvoltage conditions analog input pins. Transient currents 100mA will cause latch-up. Maximum input current power supply WARNING: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes.
DS74F1 DS74F2
CS5516, CS5520
SCLK
Write Timing (Not Scale)
MSB-1
DRDY
SCLK
MSB-1
Read Timing (Not Scale)
DRDY
MSB-1
SCLK
Read Timing with (Not Scale)
SCLK
with Continuous SCLK (Not Scale)
DS74F2 DS74F1
CS5516, CS5520
SWITCHING CHARACTERISTICS
Parameter
TMIN TMAX; VA+, VA-, -5V±5%; Input Levels: Logic Logic VD+; Symbol trise tfall Digital Input Digital Output Digital Input Digital Output (Note (Note 1/XIN 4.096 Units
Master Clock Frequency: Internal Oscillator External Clock Master Clock Duty Cycle Rise Times Fall Times
Startup
Power-on Reset Period Oscillator Start-up Time Pulse Width XTAL 4.9152 MHz(Note tpor tost tres SCLK Pulse Width High Pulse Width
Serial Port Timing
Serial Clock Frequency Serial Clock
Write Timing
Enable Valid Latch Clock Data Set-up Time prior SCLK rising Data Hold Time After SCLK Rising SCLK Falling Prior Disable
Read Timing
Data Valid SCLK Falling Data SCLK Falling Hi-Z DRDY Falling Valid Data Rising Hi-Z Disable Hold Time Enable Set-up Time Enable Hold Time
Disable Set-up Time Notes: Specified using points waveform interest. Output loaded with Oscillator start-up time varies with crystal parameters. This specification does apply when using external clock source.
DS74F1 DS74F2
CS5516, CS5520 GENERAL DESCRIPTION CS5516 CS5520 monolithic CMOS converters which include instrumentation amplifier input, on-chip programmable gain amplifier, offset trimming. While devices optimized ratiometric measurement Wheatstone bridge applications, they used general purpose low-level signal measurement. Each devices includes two-channel differential delta-sigma modulator (the signal measurement input reference input digitized independently before digital output word computed), calibration microcontroller, two-channel digital filter, programmable instrumentation amplifier block, 4-bit
Analog Supply
coarse offset trimming, circuitry generation demodulation (actually switched bridge excitation, serial port. CS5516 outputs 16-bit words; CS5520 outputs 20-bit words. CS5516/20 devices measure either unipolar bipolar signals. Self-calibration utilized maximize performance measurement system. better understand capabilities CS5516/20, helpful examine some error sources bridge measurement systems.
MDRV1 MDRV+
XOUT Optional Clock Source
Bridge Excitation Supply
Excitation Supply Synch. Signals
CS5516 CS5520 SCLK
VREF+ VREFAIN+ AINAGND1 AGND2
SMODE DRDY DGND VD10
Serial Data Interface
Unused logic inputs must connected DGND Analog Supply
Control Logic
Figure System Connection Diagram: Excitation Mode Using External Excitation
DS74F1 DS74F2
CS5516, CS5520 THEORY OPERATION front page this data sheet illustrates block diagram CS5516 CS5520 converter. device includes instrumentation amplifier with fixed gain This chopper-stabilized instrumentation amplifier followed programmable gain stage with gain settings sensitivity input function programmable gain setting reference voltage connected between VREF+ VREF- pins device. full scale converter VREF/( unipolar, ±VREF/(G bipolar, where VREF reference voltage between VREF+ VREF- pins, gain setting programmable gain amplifier, gain instrumentation amplifier.
Analog Supply
After programmable gain block, output 4-bit combined with input signal. used subtract offset from analog input signal. Offsets large ±200 full scale trimmed from input signal. CS5516 CS5520 optimized perform ratiometric measurement bridge-type transducers. devices support bridge excitation modes (switched bridge excitation. switched-dc modes operation converter fully demodulates both reference voltage analog input signal from bridge.
MDRV1 MDRV+
XOUT Optional Clock Source
CS5516 CS5520 SCLK VREF+ VREFAIN+ AINAGND1 AGND2 VA0.1 VD21 SMODE DRDY DGND
Control Logic Serial Data Interface
Unused logic inputs must connected DGND Analog Supply
Figure System Connection Diagram: Excitation Mode (EXC
DS74F1 DS74F2
CS5516, CS5520
Command Register
RSB2 RSB1 RSB0
RSB2-0
NAME Register Select
VALUE
Read/Write
FUNCTION Must always logic Selects Register Read Written CONVERSION DATA (read only) CONFIGURATION GAIN RATIOMETRIC OFFSET NON-RATIOMETRIC OFFSET NON-RATIOMETRIC OFFSET VREF USED Write register selected RSB2-0 bits Read from register selected RSB2-0 bits Used Used Used
Table CS5516 CS5520 Commands
CS5516/20 includes microcontroller which manages operation chip. Included microcontroller eight different registers associated with operation device. 8-bit command register used interpret instructions received serial port. When power applied, device been reset, serial port initialized into command mode. this mode waiting receive 8-bit command serial port. first bits into serial port placed into command register. Table lists valid command words reading from writing internal registers converter. Once valid 8-bit command word been received decoded, serial port goes into data mode. data mode next serial clock pulses shift data either into serial port. When writing data port, data immediately follow command word. When reading data from port, user must pause after clocking 8-bit command word allow microcontroller time decode command word, access appropriate regis12
read, present 24-bit word port. microcontroller will signal when 24-bit read data available causing DRDY low. user must write read full 24-bit word except case reading conversion data. read data conversion mode, user read less than bits then made inactive going inactive releases user control over port allows data updates port. user instruct on-chip microcontroller perform certain operations configuration register. Whenever word written 24-bit configuration register, microcontroller then decodes word executes configuration register instructions. Table illustrates bits configuration register. bits configuration register will discussed various sections this data sheet.
DS74F1 DS74F2
CS5516, CS5520
Configuration Register
Register Reset
DAC3 DAC2 DAC1 DAC0 FUNCTION Offset Subtract Offset This read only2
Register Reset
DAC3 DAC2-0
NAME Sign Bits
Excitation:
Internal External
VALUE 0000 1000 0100 0010 0001
F1-F0
Select Frequency
G1-G0
Select Gain
Select Unipolar/Bipolar Mode Awake/Sleep Execute Calibration
CC3-CC0
Calibration Control Bits
Reset Filter
Offset Offset Offset 100% Offset These bits read only2 125% Offset 150% Offset 175% Offset outputs determined bits input which determines phase demodulation clock output Excitation BX1=0 BX2=+5 Excitation Frequency XIN/8192 Excitation Frequency XIN/16384 Excitation Frequency XIN/4096 Must always logic Gain (X25) Gain (X25) Gain (X25) Gain (X25) Bipolar Measurement Mode Unipolar Measurement Mode Must always logic Awake Mode Sleep Mode Calibration active Perform calibration selected CC3-CC0 bits. must written back after calibration completed Must always logic Must always logic calibration performed Calibrate non-ratiometric offset, VREF Calibrate non-ratiometric offset, Calibrate ratiometric offset, Calibrate gain, Must always logic Must always logic Must always logic Normal operation Reset Filter
Notes: 1.Reset State write these bits does change register values. These bits just mirror register contents.
Table Configuration Register DS74F1 DS74F2
CS5516, CS5520 System Initialization Whenever power applied CS5516/CS5520 converters, devices must reset known condition before proper operation occur. internal reset applied after power established lasts approximately also used establish reset condition. reset signal should remain least clock cycle ensure adequate reset time. recommended that used reset converter power supplies rise very slowly with poor startup characteristics. signal generated microcontroller output, circuit. reset function initializes configuration register five calibration registers; places microcontroller command mode ready accept command from serial port. Whenever device reset DRDY will logic on-chip registers initialized following states:
Configuration Calibration registers: Gain Ratiometric Offset Non-ratiometric Offset VREF Non-ratiometric Offset 000000(H) 000000(H) 800000(H) 000000(H) 000000(H) 000000(H)
CALIBRATION After CS5516/20 reset, device functional perform measurements without being calibrated. converter will utilize initialized values calibration registers calculate output words. converter uses outputs (AIN VREF) dual channel converter along with contents calibration registers compute conversion data word. following equation indicates computation.
[[DD
VREF
Where output data, DAIN DVREF digital output words from VREF digital filter channels, contents following calibration registers: non-ratiometric offset VREF non-ratiometric offset ratiometric offset Gain computed output word, two's complement number. Calibration minimizes errors converted output data. calibration been performed, measurements will include offset gain errors entire system. converter calibrated each time powered calibration words from previous calibration uploaded into appropriate calibration registers from some type E2PROM system microcontroller. converter uses five different registers store specific calibration information. Each calibration registers stores information pertinent correcting specific source error associated with either converter with input transducer wiring. method
DS74F1 DS74F2
CS5516, CS5520
Configuration Register
Type VREF Non-ratiometric Offset Non-ratiometric Offset Ratiometric Offset System Gain VREF Non-ratiometric Offset Calibration
Calibration Time 573,440/fclk 573,440/fclk 2,211,840/fclk 573,440/fclk 573,440/fclk
DRDY remains high through calibration sequence. modes, DRDY falls immediately upon completion calibration sequence.
Table CS5516/CS5520 Calibration Control
which calibration initiated common each calibration registers. configuration register controls execution calibration process. Bits CC3-CC0 configuration register determine which type calibration will performed which five calibration registers will affected. falling edge 24th SCLK, configuration word will latched into configuration register selected calibration will executed. time required perform calibration listed Table DRDY will remain logic during calibration, will when calibration step completed. serial port should accessed while calibration progress. configuration register remains logic until overwritten configuration word Consequently, left active, write (the falling edge 24th SCLK) register inside converter will cause re-execution calibration sequence. This occurs because internal microcontroller executes contents configuration register every time 24th SCLK falls after writing 24-bit word internal register. certain that calibrations will re-executed each time word written read serial port, configuration register must written back logic after final calibration step been completed. CC3-CC0 bits configuration register determine type calibration perDS74F1 DS74F2
formed. calibration steps should performed following sequence. user determines that non-ratiometric offset calibration important, non-ratiometric offset errors VREF input channels should calibrated first. Then ratiometric offset channel should calibrated. finally, channel gain should calibrated. Non-ratiometric Errors calibrate VREF non-ratiometric errors, input channels VREF path into converter path into converter must grounded (this occur pins bridge excitation shown Figure 3.). Then bits configuration register must logic converter will then perform non-ratiometric calibration place
CS5516 CS5520
VREF+
VREFAIN+
AIN*Note: bridge grounded with relay with jumpers perform non-ratiometric calibration.
Figure Non-ratiometric System Calibration using Internal Excitation
CS5516, CS5520 proper calibration words VREF non-ratiometric registers. Note that non-ratiometric offsets calibrated simultaneously independently, they must calibrated prior other calibration steps non-ratiometric offset calibration used. effects non-ratiometric errors significant enough affect user application, they left uncalibrated (after reset, non-ratiometric offset registers will contain 000000(H)). Ratiometric Offset Once non-ratiometric errors have been calibrated, ratiometric offset error channel should calibrated next. perform this calibration step, reference voltage must applied VREF+ VREF- pins. Then, place "zero" weight scale platform. This will result offset voltage into converter which will represent offset bridge, wiring, input converter itself. configuration word with bits logic then written into configuration register. During ratiometric offset calibration microcontroller first uses successive approximation algorithm compute correct values DAC3-DAC0 bits register. This accommodates large offsets input signal. Once four bits computed, this amount offset removed from input signal. microcontroller then computes appropriate number place ratiometric offset register calibrate remaining offset removed DAC. Gain After ratiometric offset been calibrated, next step perform gain calibration. Gain calibration performed with "full scale" weight scale platform. bits configuration register logic gain calibration channel final calibration step. After
DRDY falls signal completion this calibration step, configuration register must back logic terminate calibration mode. Limitations Calibration Range There five calibration registers converter. There non-ratiometric offset calibration registers, input VREF input; 4-bit offset trim DAC; ratiometric offset calibration register input; gain calibration register. After non-ratiometric offsets calibrated, either 24-bit non-ratiometric calibration registers represents 2-23 proportion internally-scaled MDRV (Modulator Differential Reference Voltage). MDRV+ MDRV- pins, MDRV nominal value 3.75 volts. This voltage internally scaled nominal volts (never less than volts) with non-ratiometric calibration. non-ratiometric calibration words stored complement form with count equal slightly less than input internal converter. channel this will scaled down gain instrumentation amplifier (X25) gain. gain count non-ratiometric register will represent slightly less than Non-ratiometric offset VREF input cannot exceed volts within calibration range converter. Nonratiometric offset calibrated channel cannot exceed volts divided channel gain. With gain maximum non-ratiometric offset which calibrated channel cannot exceed When ratiometric offset calibrated, 4bit coarsely trims offset from analog signal. ratiometric offset which remains finely trimmed after signal been converted; using contents ratiometric offset register digital correction.
DS74F1 DS74F2
CS5516, CS5520 bits manipulated user subtract offset percent nominal input signal. ratiometric offset register manipulated subtract offset equal maximum differential input signal into amplifier. ratiometric offset register represents 2-23 proportion voltage input across VREF+ VREFpins internal input channel converter. This will scaled down channel gain when calculated relative instrumentation amplifier input. example, with VREF gain count ratiometric offset register would represent about instrumentation amplifier input. proportion remains ratiometric even VREF voltage should change. 24-bit register content stored complement form. Manipulation ratiometric offset register allows user shift transfer function allow load cell creep load cell zero drift. gain calibration performed last. contents gain register spans from 2-23 shown Table After gain calibration been performed, numeric value gain register should exceed range 1.2. gain calibration range nominal value 1.0. nominal value input span dictated VREF voltage, gain, instrumentation gain. converter operate with gain slope factors from (decimal), when slope exceeds converter output code computation lack adequate resolution result missing codes transfer function. Internal circuitry saturate large signals which would calibrate gain factor less than 0.8. typical weigh scale application, CS5516/CS5520 will calibrated combination with load cell factory. Once calibrated, calibration words off-loaded from converter stored E2PROM. When powered-up field calibration words up-loaded into appropriate registers. This viable because VREF input converter "chopper-stabilized" maintain excellent stability when subjected changes temperature. Programmable Gain Amplifier programmable gain amplifier inside CS5516/20 offers gains This addition fixed gain input instrumentation amplifier. gain tracking about percent between ranges. user remove this error performing gain calibration factory with full scale signal each range. gain calibration word each gain range off-loaded into E2PROM uploaded into gain register whenever gain setting selected PGA. Gain stability over temperature converter itself approximately ppm/°C when device used ratiometrically. Serial Interface Modes CS5516/20 support either serial interfacing. SMODE sets operating mode serial interface. With SMODE device assumes user operating with either wire interface. five wire mode includes SOD, SID, SCLK, DRDY, four wire mode, connected DGND logic user would then interface SOD, SID, SCLK, DRDY pins.
DS74F1 DS74F2
CS5516, CS5520
VREF Non-Ratiometric Offset Registers
Register Reset
2-18 2-19 2-20 2-21 2-22 2-23
represents 2-23 proportion internal MDRV (2.5 Volts)
Register
Register Reset
DAC3 DAC2 DAC1 DAC0 FUNCTION Offset Subtract Offset Offset Offset Offset 100% Offset 125% Offset 150% Offset 175% Offset These bits mirror Configuration Register
Register Reset
DAC3 DAC2-0
NAME Sign Bits
Bits
VALUE
read only
Note: Reset State write these bits does change register values.
Ratiometric Offset Register
Register Reset
2-18 2-19 2-20 2-21 2-22 2-23
represents 2-23 proportion voltage [<(VREF+) (VREF-)>/GAIN] where GAIN Gain
GAIN Register
Register Reset
2-18 2-19 2-20 2-21 2-22 2-23
gain register span from (2-2-23). After Reset MSB=1, other bits
Table Calibration Registers DS74F1 DS74F2
CS5516, CS5520 Reading register converter requires command word written pin. example, read conversion data register, following command sequence should performed. First, command word 88(H) would issued port. wire interface mode, this would involve activating low, followed SCLKs (note that SCLK must always start transition from high latch transmit data, then back again) input 8-bit command word. must serial port recognize SCLKs during write read, actually first rising SCLK during command time that gives user control over port. After writing command word, user must pause wait until CS5520 presents selected register data serial port. DRDY signal will fall when data available. When reading conversion data register, take 112,000 clock cycles DRDY fall after 88(H) command word recognized. Figure illustration command data word timing. conversion data register actually accumulator post-processor which computes output data. each filter convolution cycle, internal microcontroller checks read conversion data register command been interpreted. transfers accumulator result serial port. Whenever registers other than conversion data register read, DRDY will fall within clock cycles (62.5 with 4.096 MHz) after command word recognized. When DRDY falls, SCLKs then issued port read 24-bit output data word. DRDY will return high after bits have been clocked out. will Hi-Z state whenever high, after output data bits have been clocked port. CS5516/20 designed such that output conversion data words continuously, without issuing command word prior each data read. Under following circumstances, continuous conversion data read from port after issuing only 88(H) command word. Once command read conversion data register issued, DRDY must allowed low, after which SCLKs issued read data. This will cause DRDY return high. converter will continue output conversion words update rate long different command word started prior DRDY falling again. user required read every output word remain continuous update mode. DRDY will toggle high, then each output word becomes available. command word issued immediately after data word read, converter will read conversion mode. Figure illustrates continuous data mode. user should perform data reads command writes within 51,000 clock cycles after DRDY falls avoid ambiguity controls serial port. SMODE (tied VD+), interface operates wire interface using only SOD, SID, SCLK. wire mode must tied DGND. DRDY operates normally used. Instead, DRDY signal modifies behavior signal, allowing signal user when data available. read data from converter requires command word written pin. output normally high (never Hi-Z). When output data available, signal will low. user would then issue SCLKs SCLK clear this data ready signal. falling edge SCLK will present first 24-bit output word. SCLKs then issued read data. Then will high. should remain whenever
DS74F1 DS74F2
CS5516, CS5520
SCLK
Command Time SCLKs
Data Time SCLKs Write
SCLK
Command Time SCLKs DRDY
Data Time SCLKs
Read Wire)
SCLK
Command Time SCLKs
81,920 Clock Cycles SCLKs Clear DRDY
Read Wire)
Data Time SCLKs
falls Command 88(H)
Figure Command Data Word Timing *See text time.
DS74F1 DS74F2
CS5516, CS5520 being written. When reading SOD, SCLK cannot continuous must burst clock cycle bit. continuous read conversion data mode also functional 3-wire interface mode. Issue 88(H) command word converter. Then wait low. Issue SCLKs clear data ready function. data will then appear pin. Issue SCLKs read conversion word. falling edge 24th SCLK will return high. will next DRDY falling time indicate conversion word. Eight SCLKs must again issued clear data ready function before clocking data conversion word. will continue toggle each time word available even conversion data read. terminate continuous conversion mode, input 8-bit comman word immediately after reading conversion word. user should perform data reads command writes within 51,000 clock cycles after falls avoid ambiguity controls serial port. Serial Port Initialization reason off-chip microcontroller fails know whether serial port CS5516/20 data mode command mode, following initialization procedure issued port force CS5516/20 into command mode. Write more pin. Then issue single pin. port will then initialized into command mode will waiting 8-bit command word. Bridge Excitation Options CS5516/CS5520 converters optimized Wheatstone bridge applications. converters support either (switched bridge excitation. Bridge Excitation CS5516/CS5520 configured bridge excitation either ways. configuration register either internal external excitation. internally-controlled mode (EXC bits must logic this condition, bridge excited from supply with resistor divider develop appropriate reference voltage VREF+ VREF- pins. Note that bridge excitation
Port Access Period Valid 51,000 Clock Cycles
SCLK SCLKs
Data Bits 81,920 Clock Cycles
SCLKs
SCLKs
DRDY
Data Bits Data Bits
Figure Continuous Read Conversion Data Mode Wire) DS74F1 DS74F2
CS5516, CS5520 plied prior CS5516/CS5520 being powered-up. With EXC, logic output will logic volts) output will logic volts). second method configuring converter excitation setting pulling (pin (pin through resistor. This sets converter with external excitation which uses input excitation frequency. With VD+, external excitation frequency zero, Bridge Excitation bridge excitation involves using clock signal generate square wave which repetitively reverses excitation polarity bridge. excite bridge dynamically requires some type bridge driver external CS5516/CS5520 converter. This driver driven square wave clock. source this clock depends upon whether converter internal excitation external excitation. Figure illustrates sample bridge drive circuit when operating internal excitation mode.
TP0610 MICREL MIC4428 MIC4425 EXC+
from pins converter form two-phase non-overlapping clock. converter capable demodulating this clocked excitation. only signals into AIN+ VREF+ pins converter phase with demodulation clock inside converter (see Figure non-overlapping clock signals from CMOS level outputs volts) capable driving load. buffer amplifier MUST used drive bridge.
(Out) (Out)
Demod Clock (Internal) Note: signals from bridge into AIN+ VREF+ converter must phase with demodulation clock. cycle clock.
Figure Internal Excitation Clock Phasing
Whenever internal mode used dynamic bridge excitation signals non-overlapping. non-overlapping time clock cycle. converter also configured provide dynamic bridge excitation when operating external-controlled bridge excitation mode. With configuration register logic becomes input which determines bridge excitation frequency phase. should near duty cycle. user select excitation frequency with following restrictions. excitation frequency must synchronous with frequency converter must chosen using following equation: Fexc XIN) 81,920 where integer lies range including 160. Fexc desired bridge excitation frequency. Other asynchronous freDS74F1 DS74F2
EXC-
Figure Sample Bridge Driver
Using internal excitation involves setting configuration register setting bits select excitation frequency bridge. this mode excitation frequency sub-multiple clock frequency. excitation clock output
CS5516, CS5520 quencies possible introduce jitter component output signals. desirable choose excitation frequency where interference components present, such their harmonics. frequency divided down using counter external converter. Fexc would input converter synchronize internal operations amplifiers synchronous detection circuitry generate clock output from pin. output then used drive bridge amplifier with signal proper phase detection converter. Figure indicates necessary phase signals ensure proper demodulation. verter VREF+/VREF- leads converter filtered, care should exercised choice components. With either excitation, should limit input filtering resistors below Values greater than this will degrade noise performance converter. excitation applications, filtering must broadband enough that switched excitation signal settle within µsecs. Failure meet this settling requirement will affect measurement accuracy. Figure illustrates acceptable filter components excitation. only differential filtering required, single capacitor placed between AIN+ AIN- (and VREF+ VREF-) place capacitors ground.
7.5k EXC+ VREF+
(In) (Out)
EXCAIN+
7.5k
Demod Clock (Internal) Note: signals from bridge into AIN+ VREF+ converter must phase with demodulation clock. 64/XIN
0.0047 0.0047
VREF- CS5516 AIN+ CS5520
AIN-
AIN-
Figure VREF Input Filter Components
Figure External Excitation Clock Phasing
Whenever dynamic excitation clock output from either pins (during internal excitation) from (during external excitation) changes states, converter waits cycles before sampling VREF signal inputs. delay allows some time signal settle from modulation event. Input Filtering Some load cells located distance from input converter. Under these conditions, separate twisted pair cabling recommended excitation drive bridge, excitation sense leads used), AIN±/- signal leads. AIN+/AIN- leads conDS74F1 DS74F2
Voltage Reference Considerations CS5516/20 include on-chip voltage reference which output MDRV- referenced from MDRV+ pin. converter designed operated ratiometric measurement device. 2-channel delta-sigma converter uses internal MDVR (Modulator Differential Voltage Reference) reference. Since MDVR used converting both VREF signals same time, absolute value MDVR tempco important when CS5516/20 used ratiometric measurement mode. voltage reference output, MDVR-, should decoupled using capacitor which connected MDRV+ supply line. Voltage reference decou23
CS5516, CS5520 pling shown system connection diagrams. absolute measurements made CS5516/20, then precision reference should input into VREF+ VREF- terminals. Clock Generator CS5516/20 includes gate which connected crystal oscillator provide master clock chip. Alternatively, external (CMOS compatible) clock input into pin. Figure illustrates simple model on-chip gate oscillator. onchip oscillator designed typically operate with crystal frequencies between without additional loading capacitors. other crystal frequencies, ceramic resonators used, additional loading capacitance necessary.
digital filter deep notch transfer function (XIN 4.096 MHz) (XIN 4.9152 MHz) other frequencies used. filter transfer function will scale proportionally. Figure shows transfer function filter when operated three different frequencies. With 3.579 XIN, filter offers greater than rejection both
Magnitude (dB) 3.579 4.096 4.915
-100 -120 -140 -160 21.8 43.7 87.3 131.0 Input Frequency (Hz) 174.7 218.5
Internal circuitry XOUT
Figure Filter Magnitude Response
4.096
2000 umhos
External XTAL
Phase (degrees)
Figure On-Chip Gate Oscillator Model
XOUT used drive CMOS gate system clock requirements. sure include gate's input capacitance stray capacitance part loading capacitance resonating element. Digital Filter CS5516/20 optimized operate with clock frequencies 4.096 4.9152 MHz. These result filter having bandwidth with output word rates Sps. rejection 50Hz minimum with 4.096 clock. Similar rejection obtained with 4.9152 clock.
-120 -150
-180
Input Frequency (Hz)
Figure Filter Phase Response.
output word rate converter scales with clock rate ratio XIN/81,920; 4.096 MHz. very narrow signal bandwidths, such desired, averaging output words recommended.
DS74F1 DS74F2
CS5516, CS5520 digital filter computes output data word every 81,920 clock cycles. input experiences large change amplitude, gain changed, calibration registers changed, take filter cycles (81,920 clock cycles) filter compute output word which fully settled input signal. Output Coding CS5516/20 converters output data binary format when operating unipolar mode two's complement when operating bipolar mode. Table illustrates output coding converters. Note that when reading conversion data from converter data word output sign first. Falling edges SCLK advance data word next lower bit. output conversion words from both CS5516 CS5520 bits long. CS5516 data bits followed flag bits (all identical). CS5520 data bits followed flag bits (all identical). read conversion data, including error flag information will require least SCLKs CS5516 least SCLKs CS5520.
Unipolar Input Offset Bipolar Input Two's Voltage Binary Voltage Complement >(VFS-1.5 LSB) FFFF >(VFS-1.5 LSB) 7FFF FFFF 7FFF VFS-1.5 VFS-1.5 -FFFF 7FFE 8000 0000 VFS/2-0.5 -0.5 -7FFF FFFF 0001 8001 +0.5 -VFS+0.5 -0000 8000 <(+0.5 LSB) 0000 <(-VFS+0.5 LSB) 8000
Under normal operating conditions, flag bits will zeroes. flag bits will ones whenever overrange condition exists. Under large overrange conditions where input signal exceeds nominal full scale input approximately times (for example: input when nominal full scale input set-up mV), converter unable compute proper output code. this condition flag bits will conversion data value other than full scale plus minus. After converter first powered-up, issued, device comes SLEEP mode, first conversion data read erroneously have error flag bits "1". Synchronizing Multiple Converters Multiple converters made output their conversion words same time they operated from same clock signal XIN. synchronize multiple converters requires that they have their configuration register written logic then back filters will allowed start convolutions after falling edge 24th SCLK used write configuration register.
Unipolar Input Offset Bipolar Input Two's Voltage Binary Voltage Complement >(VFS-1.5 LSB) FFFFF >(VFS-1.5 LSB) 7FFFF FFFFF 7FFFF VFS-1.5 VFS-1.5 -FFFFE 7FFFE 80000 00000 VFS/2-0.5 -0.5 -7FFFF FFFFF 00001 80001 +0.5 -VFS+0.5 -00000 80000 <(+0.5 LSB) 00000 <(-VFS+0.5 LSB) 80000
CS5516 Output Coding
CS5520 Output Coding
Note: table equals full scale voltage between +VREF/(G ground unipolar mode; between ±VREF/(G bipolar mode. signal input section converter been amplified instrumentation amplifier (x25) gain, text about error flags under overrange conditions.
Table Output Coding CS5516/20 Converters. DS74F1 DS74F2
CS5516, CS5520 filter will start convolution next rising edge clock after 24th SCLK falls. Sleep Mode CS5516/20 configuration register which allows users device sleep condition lower quiescent power. Upon reset device logic which places device 'awake' condition. Writing will shutdown most chip, including oscillator. desirable following sequence when coming sleep. Write logic configuration register. same configuration word write logic configuration register. Then wait until certain that oscillator started. After oscillator started clock present pin, back user should then wait least output word update periods before expecting valid output data word. Noise Performance Typical noise performance converter listed specification tables each gain. Figure illustrates noise histogram 1000 output conversions from CS5520. data histogram collected using CDB5520 evaluation board; with VREF volts, bipolar mode. data shows standard deviation data LSBs. equivalent [VREF 2(bipolar)]/ [Inst gain gain number codes] (2.5 2E20) 47.7 standard deviation equivalent data Normal Gaussian. noise presented plot which good agreement with typical noise specification gain Applications Application Notes section databook.
DS74F1 DS74F2
Figure CS5520 Noise Histogram.
Schematic Layout Review Service
Confirm Optimum Schematic Layout Before Building Your Board. Free Review Service Call Applications Engineering.
CS5516, CS5520 DESCRIPTIONS
Modulator Diff. Voltage Modulator Diff. Voltage Positive Analog Power Negative Analog Power Analog Ground Analog Analog Analog Ground Voltage Voltage Bridge Excite Bridge Excite
MDRV+ MDRVVA+ VAAGND1 AIN+ AINAGND2 VREF+ VREFBX2
SMODE XOUT VDVD+ DGND SCLK DRDY
Serial Interface Mode Crystal Crystal Negative Digital Power Positive Digital Power Digital Ground Serial Output Data Serial Input Data Serial Clock Input Data Ready Chip Select Reset
Power Supply Connections Positive Digital Power, Positive digital supply voltage. Nominally volts. Negative Digital Power, Negative digital supply voltage. Nominally volts. DGND Digital Ground, Digital ground. Positive Analog Power, Positive analog supply voltage. Nominally volts. Negative Analog Power, Negative analog supply voltage. Nominally volts. AGND1, AGND2 Analog Ground, PINS Analog ground. Clock Generator XIN; XOUT Crystal Crystal Out, Pins internal gate connected these pins enabling either crystal ceramic resonator provide master clock device. Alternatively, external (CMOS compatible) clock input master clock device.
DS74F1 DS74F2
CS5516, CS5520 Digital Inputs Reset, Reset initializes calibration registers known condition places serial port into command mode. Chip Select, input which enabled external device gain control over serial port. When this high, high impedance state SMODE SCLK Serial Data Clock, clock signal this determines output rate data from input data rate pin. Serial Input Data, This used inputting command configuration words inputting calibration words. Data input rate determined SCLK. don't care state when data being clocked SMODE Serial Interface Mode, Selects operating mode serial port. When serial port operates wire interface mode. When high chip will enter wire interface mode. Analog Inputs AIN+ AIN- Analog Inputs, PINS analog input signals from transducer. These true differential inputs. VREF+ VREF- Voltage Reference Inputs, PINS 9,10. These differential analog reference voltage inputs. MDRV+ Modulator Differential Voltage Reference, Positive terminal internal differential voltage reference which tied positive supply (VA+) ground (AGND). MDRV- Modulator Differential Voltage Reference, This -3.75V modulator differential voltage reference output used generate analog reference. Note this with reference MDRV+ pin.
DS74F1 DS74F2
CS5516, CS5520 Digital Outputs Bridge Excitation Signals, PINS These buffered drive transducer used synchronizing signals transducer drive circuit. signals. DRDY Data Ready, DRDY goes every 81,920 cycles (when read conversion data mode) indicate that data been placed output port. DRDY goes high when serial port data clocked out, when serial port being updated with data, when calibration progress, when device SLEEP. Serial Output Data, Data from serial port will output from this rate determined SCLK data will either conversion data, calibration values, dependent upon command word that been previously input pin. furnishes high impedance output state when transmitting data (SMODE
ORDERING INFORMATION
ORDERING GUIDE
Model
Package
Resolution
Liearity Error
Channels
Temperature
CS5516-AP Model Number CS5516-AP CS5516-AS CS5516-AS CS5516-ASZ (lead free) CS5520-BP CS5520-BS CS5520-BP CS5520-BS CS5520-BSZ (lead free)
24-pin Error Linearity Plastic(Max) 0.003% 0.003% 24-pin SOIC 0.0015% 0.0015% 24-pin Plastic 24-pin SOIC
Temperature Range -40°C0.0030% +85°C Bits -40°C +85°C -40°C +85°C -40°C +85°C Bits 0.0015%
Package 24-pin 0.3" Plastic 24-pin 0.3" SOIC 24-pin 0.3" Plastic 24-pin 0.3" SOIC
ENVIRONMENTAL, MANUFACTURING, HANDLING INFORMATION
Model Number Peak Reflow Temp Rating* Floor Life Limit Days Days Limit Days Days
CS5516-AP CS5516-AS CS5516-ASZ (lead free) CS5520-BP CS5520-BS CS5520-BSZ (lead free)
(Moisture Sensitivity Level) specified IPC/JEDEC J-STD-020.
DS74F1 DS74F2
CS5516, CS5520 SPECIFICATION DEFINITIONS Linearity Error deviation code from straight line which extends between fixed points converter transfer function. unipolar mode, straight line extends from point located below first code transition, count above zeros; second point located beyond code transition ones. bipolar mode, straight line extends from point located beyond code transition ones, passing through point below code 8000(H) (16-bit); 80000(H) (20-bit); extending beyond negative full scale. Units percent full-scale. Differential Nonlinearity deviation code's width from ideal width. Units LSBs. Full Scale Error deviation last code transition form ideal [{(VREF+)-(VREF-)}-3/2 LSB]. Units LSBs. Unipolar Offset deviation first code transition from ideal (1/2 above AGND) when unipolar mode (BP/UP low). Units LSBs. Bipolar Offset deviation mid-scale transition (011.111 100.000) from ideal (1/2 below AGND) when bipolar mode (BP/UP high). Units LSBs.
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product questions inquiries contact Cirrus Logic Sales Representative. find nearest www.cirrus.com
IMPORTANT NOTICE Cirrus Logic, Inc. subsidiaries ("Cirrus") believe that information contained this document accurate reliable. However, information subject change without notice provided without warranty kind (express implied). Customers advised obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgment, including those pertaining warranty, indemnification, limitation liability. responsibility assumed Cirrus this information, including this information basis manufacture sale items, infringement patents other rights third parties. This document property Cirrus furnishing this information, Cirrus grants license, express implied under patents, mask work rights, copyrights, trademarks, trade secrets other intellectual property rights. Cirrus owns copyrights associated with information contained herein gives consent copies made information only within your organization with respect Cirrus integrated circuits other products Cirrus. This consent does extend other copying such copying general distribution, advertising promotional purposes, creating work resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS DESIGNED, AUTHORIZED WARRANTED AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO BODY, AUTOMOTIVE SAFETY SECURITY DEVICES, LIFE SUPPORT PRODUCTS OTHER CRITICAL APPLICATIONS. INCLUSION CIRRUS PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK CIRRUS DISCLAIMS MAKES WARRANTY, EXPRESS, STATUTORY IMPLIED, INCLUDING IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE, WITH REGARD CIRRUS PRODUCT THAT USED SUCH MANNER. CUSTOMER CUSTOMER'S CUSTOMER USES PERMITS CIRRUS PRODUCTS CRITICAL APPLICATIONS, CUSTOMER AGREES, SUCH USE, FULLY INDEMNIFY CIRRUS, OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS OTHER AGENTS FROM LIABILITY, INCLUDING ATTORNEYS' FEES COSTS, THAT RESULT FROM ARISE CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, Cirrus Logic logo designs trademarks Cirrus Logic, Inc. other brand product names this document trademarks service marks their respective owners.
DS74F1 DS74F2
CDB5516 CDB5516 CDB5520 CDB5520 CS5516 CS5520 Evaluation Boards CS5516 CS5520 Evaluation Board
On-board
CDB5516 CDB5520 provide quick easy evaluation CS5516 CS5520 bridge transducer converters. Direct connection bridge evaluation board provided. board also contains microcontroller, with firmware which allows board controlled simple serial commands, using RS232 communications port ORDERING INFORMATION CDB5516 CDB5520 Evaluation Board Evaluation Board
microcontroller RS232 Serial Communicationswith host Supports either bridge drive On-board bridge driver Supports ratiometric absolute measurements Evaluation software included
Load Cell AIN+
Clock CS5516 CS5520 RS232 Driver/ Receiver SCLK
AINVREF+ VREFBridge Excitation
Microcontroller
RS232 Connector
Cirrus Logic, Inc. Crystal Semiconductor Products Division http://www.cirrus.com P.O. 17847, Austin, Texas 78760 (512) 7222 FAX: (512) 7581 http://www.crystal.com
Copyright Inc. 2005 Copyright Cirrus Logic,© Cirrus Logic, Inc. 1998 (All Rights Reserved) (All Rights Reserved)
DS74DB# DS74DB4
CDB5516/CDB5520 Introduction CDB5516/20 evaluation board provides means testing CS5516 CS5520 bridge transducer converters. board designed interfaced PC-compatible computer RS-232 port. Software supplied with board which provides control registers CS5516 CS5520. board configured operated from volt power supplies. bridge transducer bridge transducer simulator required board evaluated ratiometric operating mode. Evaluation Board Overview Figure illustrates schematic bridge driver converter portion circuit board. converter operates from crystal. This results converter outputting conversion words rate. board comes configured interfaced bridge transducer 6-pin transducer terminal block. sense lines transducer terminal block provide reference voltage converter. absolute measurements, user connect either external reference voltage volts) reference terminal block connect on-board volt LT1019 reference voltage reference converter.
+5VA
MICREL MIC4428
TP0610
+5VA
0.1µF 0.1µF
100k
MDRV+ MDRV-
CS5516/20
100k
0.1µF
4.000
SIG+
SIGSENSE+ SENSEEXC+ 7.5k
-5VA
4.7nF
AIN+
AGND1 AGND2 XOUT SMODE
OSCLK
SMODE
4.7nF
AINR11
470pF VREF+
SCLK DRDY
SCLK DRDY
EXC-
Figure
5.0k
7.5k
REF+
470pF
VREF-
DGND
VAVD-
4.7nF
REFR3 +5VA
0.1µF
-5VA
0.1µF
0.1µF DRDY SCLK
0.1µF
LT10192.5V
AGND
DGND
Figure Bridge Driver Converter
SMODE
DS74DB4 DS74DB3
CDB5516/CDB5520 bridge driver, composed Siliconix TP0610 transistor Micrel MIC4428 dual CMOS driver, provided which allows output from CS5516 CS5520 provide either excitation bridge. digital interface pins converter connect microcontroller, alternatively, these connections cut, on-board microcontroller removed, user's microcontroller interfaced header connector. Figure illustrates Motorola 68HC705C8 microcontroller which reads writes data into converter communicates with PC-compatible computer RS-232 interface. microcontroller derives clock from converter clock. microcontroller configured communicate over RS-232 link 4800 baud, parity, 8-bit data, stop bit. Motorola MC145407 RS-232 interface chip used send recieve data PC-compatible computer 25-pin SubD connector. Table lists commands sent microcontroller write read from registers converter. software other than that provided with evaluation board used, format data transmitted over RS232 line follow: Write commands com+5VD +5VD 47µF
0.1µF RESET
RESET
10µF
10µF
C2C2+
C1C1+
68HC705C8
10µF
+5VD
OSCLK SMODE From Figure SCLK
OSC2 OSC1
TCMP TCAP
DRDY
MC145407 10µF Sub-D
Figure Microcontroller RS-232 Interface DS74DB4 DS74DB3
CDB5516/CDB5520
Register Conversion Data Register Configuration Register Register Gain Register Ratiometric Offset Register Nonratiometric Offset Register VREF Nonratiometric Offset Register Read 50(H) 51(H) 53(H) 52(H) 54(H) 55(H) 56(H) D1(H) D3(H) D2(H) D4(H) D5(H) D6(H) Write
Table Microcontroller commands RS-232
posed byte command which transmitted with first. command followed three data bytes which make 24-bit word written selected register converter. three bytes transmitted lowest order byte first (bits with byte transmitted first. Figure illustrates power supply connections evaluation board. Voltages analog digital required. Using Evaluation Board Prior using board evaluate CS5516 CS5520 converter, good understanding full potential converter necessary. recommended that CS5516/CS5520 device data sheet thoroughly read prior attemp ting aluation board. CS5516 CS5520 bridge transducer converter actually contains converters.
AGND
converters used convert VREF voltage input, other used convert signal input. Both converters utilize on-chip voltage reference perform conversions their respective inputs. Since both converters same reference they track another. digital processing logic converter depends presence both signals properly compute digital output word. evaluation board configured bridge measurement, bridge (load cell simulator) connected bridge transducer terminal block, converter will output code zero because reference voltage present between VREF+ VREF- pins. span input signal determined combination instrumentation amplifier gain (X25), programmable gain amplifier (PGA) gain, magnitude voltage between VREF+ VREF- input pins, calibration words gain offset. ex+5
+5VA
+5VD
47µF
0.1µF
47µF
0.1µF
DGND
47µF
0.1µF
-5VA
Figure Power Supplies DS74DB4 DS74DB3
CDB5516/CDB5520 ample, board comes with precision resistors which divide excitation supply (nominally volts total) down volts between VREF+ VREF- input pins. This sets nominal full scale voltage into converter. input span instrumentation amplifier calculated knowing gain setting, that gain instrumentation amplifier X25. gain then input span instrumentation amplifier will volts (VREF+ VREF-) divided 2.5/(200) 12.5 millivolt nominal unipolar mode. device then calibrated with input voltage which less than nominal greater than nominal. Therefore, with this VREF+ VREF- voltage (2.5 volts) gain input span calibrated handle span from high modify input span user either change gain modify resistor divider bridge sense voltage yield appropriate value range volts. This makes converter quite flexible handling load cells with different output levels. Whenever configured bridge transducer device, CS5516 CS5520 converter operates ratiometric measurement mode. Figures illustrate connect 4-wire 6-wire bridge transducers board. Alternatively, CS5516 CS5520 configured absolute measurement precision reference voltage supplied between VREF+ VREF- pins converter. board modified accept reference into voltage reference terminal block; on-board LT1019-2.5 volt reference used reference voltage converter. either these inputs will require that jumper wires soldered either 1A-1B select external voltage reference input, 2A-2B select on-board LT1019-2.5. Figure illustrates connection external voltage reference evaluation board absolute voltage measurement applications. achieve accurate reference voltage resistor
SENSE SENSE
SENSE SENSE
Figure 4-Wire Bridge Connections
Figure 6-Wire Bridge Connections
DS74DB4 DS74DB3
CDB5516/CDB5520 must removed from between +VREF -VREF pins. desirable also remove C16, some applications. Calibrating Converter explained CS5516/CS5520 data sheet, order which calibration steps performed important. chooses non-ratiometric calibration capabilities converter, non-ratiometric errors VREF channels should calibrated first. non-ratiometric calibration steps performed same time. Before nonratiometric offset calibration initiated, bridge should grounded. This achieved evaluation board moving jumpers output MIC4428 driver position (see Figure converter then instructed configuration register bits perform non-ratiometric calibration steps. Once non-ratiometric calibrations completed, jumpers output MIC4428 driver should returned position. After non-ratiometric calibration steps performed, ratiometric offset then calibrated. With "zero weight" load cell, converter instructed configuration register perform ratiometric offset calibration step. Finally, with "full scale weight" load cell, converter instructed perform gain calibration step. converter then ready perform conversions. Software evaluation board comes with software RS-232 cable interface board RS-232 port PC-compatible computer. software diskette contains README.TXT file which explains operation.
AGND
+5VA
+5VD
47µF
0.1µF
47µF
0.1µF
DGND
47µF
0.1µF
-5VA
Figure Using Off-board Voltage Reference
DS74DB4 DS74DB3
CDB5516/CDB5520 Figure illustrates software supplied with CDB5516/CDB5520 evaluation board. software allows user manipulate registers converter perform calibrations conversions. decodes status configuration register indicates gain register scale factor. software enables user collect data file, average samples compute average standard deviation samples which have been collected.
Figure Screen CDB5516/CDB5520 Evaluation Board Software
DS74DB4 DS74DB3
CDB5516/CDB5520
Figure CDB5520 Silkscreen
DS74DB4 DS74DB3
CDB5516/CDB5520
Figure CDB5520 Ground Plane
DS74DB4 DS74DB3
CDB5516/CDB5520
Figure CDB5520 Solder Side Trace Layer
DS74DB4 DS74DB3
Contacting Cirrus Logic Support
product questions inquiries contact Cirrus Logic Sales Representative. find nearest www.cirrus.com
IMPORTANT NOTICE Cirrus Logic, Inc. subsidiaries ("Cirrus") believe that information contained this document accurate reliable. However, information subject change without notice provided without warranty kind (express implied). Customers advised obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgment, including those pertaining warranty, indemnification, limitation liability. responsibility assumed Cirrus this information, including this information basis manufacture sale items, infringement patents other rights third parties. This document property Cirrus furnishing this information, Cirrus grants license, express implied under patents, mask work rights, copyrights, trademarks, trade secrets other intellectual property rights. Cirrus owns copyrights associated with information contained herein gives consent copies made information only within your organization with respect Cirrus integrated circuits other products Cirrus. This consent does extend other copying such copying general distribution, advertising promotional purposes, creating work resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS DESIGNED, AUTHORIZED WARRANTED AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO BODY, AUTOMOTIVE SAFETY SECURITY DEVICES, LIFE SUPPORT PRODUCTS OTHER CRITICAL APPLICATIONS. INCLUSION CIRRUS PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK CIRRUS DISCLAIMS MAKES WARRANTY, EXPRESS, STATUTORY IMPLIED, INCLUDING IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE, WITH REGARD CIRRUS PRODUCT THAT USED SUCH MANNER. CUSTOMER CUSTOMER'S CUSTOMER USES PERMITS CIRRUS PRODUCTS CRITICAL APPLICATIONS, CUSTOMER AGREES, SUCH USE, FULLY INDEMNIFY CIRRUS, OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS OTHER AGENTS FROM LIABILITY, INCLUDING ATTORNEYS' FEES COSTS, THAT RESULT FROM ARISE CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, Cirrus Logic logo designs trademarks Cirrus Logic, Inc. other brand product names this document trademarks service marks their respective owners.
DS74DB4

On-chip CS5516 CS5520 complete solutions digitizing level signals

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