20-bit Converters Non-aliasing,20-Bit Converter Features Mon
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CS5501 CS5501 CS5503 CS5503
20-bit Converters Non-aliasing,20-Bit Converter
Features
Monolithic CMOS with Filtering
6-pole, Low-pass Gaussian Filter
Description
CS5501 CS5503 CMOS converters ideal measuring low-frequency signals representing physical, chemical, biological processes. They utilize charge-balance techniques achieve 16-bit (CS5501) 20-bit (CS5503) performance with kSps word rates. converters continuously sample rate user form either CMOS clock crystal. Onchip digital filtering processes data updates output register kSps rate. converters' lowpass, 6-pole Gaussian response filter designed allow corner frequency settings from CS5501 CS5503. Thus, each converter rejects line frequencies well noise spurious frequencies. CS5501 CS5503 include on-chip self-calibration circuitry which initiated time temperature insure offset full-scale errors typically less than CS5501 less than CS5503. devices also applied system calibration schemes null offset gain errors input channel. Each device's serial port offers general purpose modes operation direct interface shift registers synchronous serial ports industry-standard microcontrollers. addition, CS5501's serial port offers third, UART-compatible mode asynchronous communication. ORDERING INFORMATION page
Output Word Rates
Chip Self-calibration Circuitry Linearity Error: ±0.0003% Differential Nonlinearity: CS5501: 16-bit, Missing Codes (DNL ±1/8 LSB) CS5503: 20-bit, Missing Codes
System Calibration Capability Flexible Serial Communications Port
Microcontroller-compatible Formats 3-state Data Clock Outputs UART Format (CS5501 only)
Pin-selectable Unipolar/Bipolar Ranges Power Consumption:
Sleep Mode Portable Applications
BP/UP SLEEP
CS5503 Calibration Calibration Calibration Calibration SRAM Microcontroller Microcontroller SRAM Charge-balanced Converter VREF Charge-Balanced Converter VREF Analog 6-pole Gaussian Low-pass Digital Analog Modulator 6-Pole Gaussian Filter Modulator Low-Pass Digital Filter VDAGND AGND Clock Generator Serial Interface Logic20 SDATA SDATA Clock Generator Serial Interface Logic DGND DGND CLKIN CLKOUT CLKOUTCLKIN DRDYDRDYMODESCLK SCLK MODE
BP/UPSLEEP CS5501
Cirrus Logic, Inc. www.cirrus.com http://www.cirrus.com
Copyright Cirrus Logic, 2005 Copyright Cirrus Logic, Inc.Inc. 2003 (All(All Rights Reserved) Rights Reserved)
DS31F4 DS31F5
CS5501 CS5503
CS5501/CS5503
CS5501 ANALOG CHARACTERISTICS TMIN TMAX; VA+, VA-, -5V; VREF 2.5V; CLKIN 4.096MHz; Bipolar Mode; MODE +5V; Rsource with AGND (see Note Digital Inputs: Logic GND; Logic VD+; unless otherwise specified.)
CS5501-A, Parameter* Specified Temperature Range TMIN TMAX (Note (Note (Note (Note (Note (Note (Note (Note 0.0015 0.0007 0.0003 ±1/8 ±0.13 ±1.2 ±0.25 ±4.2 ±0.25 ±2.1 ±0.5 ±0.6 1/10 0.003 0.0015 0.0012 ±1/2 ±0.5 CS5501-S, +125 0.0007 ±1/8 ±0.13 ±2.3 ±0.25 +3.0 -25.0 ±0.25 +1.5 -12.5 ±0.5 ±1.2 1/10 0.003 0.0015 ±1/2 ±0.5 Units ±%FS ±%FS ±%FS LSB16 LSB16 LSB16 LSB16 LSB16 LSB16 LSB16 LSB16 LSB16 LSBrms
Accuracy
Linearity Error
Differential Nonlinearity Full Scale Error Full Scale Drift Unipolar Offset Unipolar Offset Drift Bipolar Offset Bipolar Offset Drift
Bipolar Negative Full Scale Error Bipolar Negative Full Scale Drift Noise (Referred Output)
Notes: presents very high input resistance minor dynamic load which scales master clock frequency. Both source resistance shunt capacitance therefore critical determining CS5501's source impedance requirements. more information refer text section Analog Input Impedance Considerations. Applies after calibration temperature interest. Total drift over specified temperature range since calibration power-up 25°C (see Figure 11). This guaranteed design characterization. Recalibration temperature will remove these errors.
Unipolar Mode Bipolar Mode LSB's LSB's 0.26 0.50 1.00 2.00 4.00 0.0004 0.0008 0.0015 0.0030 0.0061 0.13 0.26 0.50 1.00 2.00 0.0002 0.0004 0.0008 0.0015 0.0030
CS5501 Unit Conversion Factors, VREF 2.5V Refer Specification Definitions immediately following Description Section. DS31F5 DS31F4
CS5501 CS5503
CS5501/CS5503
VA+, VA-, -5V; VREF 2.5V; CLKIN 4.096MHz; Bipolar Mode; MODE +5V; Rsource 750. with AGND (see Note unless otherwise specified.) CS5503-A, Parameter* Specified Temperature Range Accuracy Linearity Error TMIN TMAX (Note (Note (Note (Note (Note (Note (Note (Note 0.0015 0.0007 0.0003 0.003 0.0015 0.0012 CS5503-S, +125 0.0007 -400 -200 0.003 Units
±%FS ±%FS ±%FS
CS5503 ANALOG CHARACTERISTICS TMIN TMAX;
Differential Nonlinearity (Not Missing Codes) Full Scale Error Full Scale Error Drift Unipolar Offset Unipolar Offset Drift Bipolar Offset Bipolar Offset Drift
Bits LSB20 LSB20 LSB20 LSB20 LSB20 LSB20 LSB20 LSB20 LSBrms (20)
Bipolar Negative Full Scale Error Bipolar Negative Full Scale Drift Noise (Referred Output)
Unipolar Mode Bipolar Mode LSB's LSB's 0.13 0.26 0.50 1.00 2.00 0.0000119 0.12 0.0000238 0.24 0.0000477 0.47 0.0000954 0.95 0.0001907 1.91
0.596 0.25 0.0000238 0.24 1.192 0.50 0.0000477 0.47 2.384 1.00 0.0000954 0.95 4.768 2.00 0.0001907 1.91 9.537 4.000 0.0003814 3.81
CS5503 Unit Conversion Factors, VREF 2.5V
Refer Specification Definitions immediately following Description Section.
DS31F5 DS31F4
CS5501 CS5503
CS5501/CS5503
ANALOG CHARACTERISTICS (Continued)
CS5501/3-A, Parameter* CS5501/3-S, Units
Power Supplies
Power Supply Currents IAID+ IDPower Dissipation SLEEP High SLEEP Power Supply Rejection Positive Supplies Negative Supplies 0.03 0.03
(Note
(Note
(Note
Analog Input
Analog Input Range Unipolar Bipolar Input Capacitance Bias Current (Note +2.5 ±2.5 VREF+0.1 VREF+0.1 -(VREF+0.1) +2.5 ±2.5 VREF+0.1 VREF+0.1 -(VREF+0.1)
System Calibration Specifications
Positive Full Scale Calibration Range Positive Full Scale Input Overrange Negative Full Scale Input Overrange Maximum Offset Calibration Range Unipolar Mode Bipolar Mode Input Span (Notes -(VREF +0.1) -40%VREF +40%VREF (Note VREF 2VREF +0.2 -(VREF +0.1) -40%VREF +40%VREF VREF 2VREF +0.2
Notes: outputs unloaded. 0.1Hz 10Hz. PSRR will exceed benefit digital filter. unipolar mode offset have negative value (-VREF) such that unipolar mode mimic bipolar mode operation. specifications Input Overrange Input Span apply additional constraints offset calibration range. Unipolar mode, Input Span difference between full scale zero scale. Bipolar mode, Input Span difference between positive negative full scale points. When using less than maximum input span, span range placed anywhere within range ±(VREF 0.1).
Specifications subject change without notice. DS31F5 DS31F4
CS5501/CS5503
CS5501 CS5503
DYNAMIC CHARACTERISTICS
Parameter Sampling Frequency Output Update Rate Filter Corner Frequency Settling Time +0.0007% Step)
Output Amplitude CLKIN CLKIN -100 CLKIN -120 -140 Frequency 1000
Symbol -3dB
Ratio CLKIN/ CLKIN /1024 CLKIN /409,600 506,880/CLKIN
Units
Frequency Response
S1,2 -1.4667 j1.8199 S3,4 -1.7559 j1.0008
S5,6 -1.8746 j0.32276
S-Domain Pole/Zero Plot (Continuous-Time Representation) H(x) 0.694x2 0.241x4 0.0557x6 0.009664x8 0.00134x10 0.000155x12]-1/2 where f/f-3dB, f-3dB CLKIN/409,600, frequency interest. Continuous-Time Representation 6-Pole Gaussian Filter
DS31F5 DS31F4
CS5501 CS5503
CS5501/CS5503
DIGITAL CHARACTERISTICS Tmin Tmax; VA+, 10%; VA-, 10%)
Parameter Calibration Memory Retention Power Supply Voltage (VD+ VA+) High-Level Input Voltage Except CLKIN High-Level Input Voltage CLKIN Low-Level Input Voltage Except CLKIN Low-Level Input Voltage CLKIN High-Level Output Voltage Low-Level Output Voltage Input Leakage Current 3-State Leakage Current Digital Output Capacitance Iout=1.6mA (Note Symbol Cout (VD+)-1.0V Units
Notes: Iout -100 This guarantees ability drive load. (VOH 2.4V Iout µA).
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supplies: Positive Digital Negative Digital Positive Analog Negative Analog Symbol VDVA+ VAIin VINA VIND Tstg -0.3 -0.3 (VA-)-0.3 -0.3 (VA+)+0.3 -6.0 -6.0 (VA+)+0.3 (VA+)+0.3 Units
Input Current, Except Supplies (Notes Analog Input Voltage (AIN VREF pins) Digital Input Voltage Ambient Operating Temperature Storage Temperature
Notes: Applies pins including continuous overvoltage conditions analog input (AIN) pin. Transient currents 100mA will cause latch-up. Maximum input current power supply
DS31F5 DS31F4
CS5501/CS5503
CS5501 CS5503
RECOMMENDED OPERATING CONDITIONS (AGND, DGND (Note
Parameter Power Supplies: Positive Digital Negative Digital Positive Analog Negative Analog (Note Unipolar Bipolar VAIN VAIN Symbol VDVA+ VAVREF -4.5 -4.5 AGND -VREF -5.0 -5.0 -5.5 -5.5 VREF VREF Units
Analog Reference Voltage Analog Input Voltage:
Notes: voltages with respect ground. CS5501 CS5503 accept input voltages analog supplies (VA+ VA-). They will accurately convert filter signals with noise excursions 100mV beyond |VREF|. After filtering, devices will output input above VREF input below AGND unipolar mode -VREF bipolar mode.
SWITCHING CHARACTERISTICS Tmin Tmax; CLKIN=4.096 MHz; VA+, 5V±10%;
VA-, 10%; Input Levels: Logic Logic VD+; unless otherwise specified.) Parameter Master Clock Frequency: Symbol Digital Input Digital Output Digital Input Digital Output (Note (Note trise trise tfall tfall tscs tsls tsch 4096 5000 5000 Units
Internal Gate Oscillator CLKIN (See Table Externally Supplied: (Note CLKIN Maximum Minimum (Note CLKIN
CLKIN Duty Cycle Rise Times: Fall Times: Times: Hold Time:
SC1, SLEEP High CLKIN High (Note SC1, hold after falls
Notes: CLKIN must supplied whenever CS5501 CS5503 SLEEP mode. clock present when SLEEP mode, device draw higher current than specified possibly become uncalibrated. CS5501/CS5503 production tested 4.096 MHz. guaranteed characterization operate kHz. Specified using points waveform interest. order synchronize several CS5501's CS5503's together using SLEEP pin, this specification must met.
DS31F5 DS31F4
CS5501 CS5503
CS5501/CS5503
SWITCHING CHARACTERISTICS (continued) Tmin Tmax; VA+, 10%; VA-, 10%; Input Levels: Logic Logic VD+;
Parameter Symbol tcsd1 tdd1 tcd1 tph1 tpl1 tfd2 tfd1 3/CLKIN 1/CLKIN 1/CLKIN 4/CLKIN +200 Units
Mode (Mode VD+)
Access Time SDATA Delay Time SCLK Delay Time 4.096 MHz) Serial Clock (Out) Output Float Delay Output Float Delay SDATA SCLK Falling SDATA SDATA SCLK Rising Pulse Width High 4.096 MHz) Pulse Width SCLK Rising Hi-Z High Output Hi-Z (Note
Mode (Mode DGND)
Serial Clock (In) Serial Clock (In) Access Time Maximum Data Delay Time Output Float Delay Pulse Width High Pulse Width Data Valid (Note (Note SCLK Falling SDATA High Output Hi-Z fsclk tph2 tpl2 tcsd2 tdd2 tfd3
Output Float Delay SCLK Falling Output Hi-Z tfd4 Notes: returned high before data bits output, SDATA SCLK outputs will complete current data then high impedance. activated asynchronously DRDY, will recognized occurs when DRDY high clock cycles. propagation delay time great CLKIN cycles plus guarantee proper clocking SDATA when using asychronous SCLK(i) should taken high sooner than CLKIN cycles plus 160ns after goes low. SDATA transitions falling edge SCLK(i).
CLKIN SLEEP VALID
tfd1 SDATA
SC1,
Calibration Control Timing
Sleep Mode Timing Synchronization
Output Float Delay Mode (Note
DS31F5 DS31F4
CS5501/CS5503
CS5501 CS5503
CLKIN csd1 SDATA Hi-Z SCLK Hi-Z MSB-1 MSB-2 Hi-Z Hi-Z
MODE Timing Relationships
DRDY
csd2
MSB-1 Hi-Z
SDATA SCLK
Hi-Z
csd2
SDATA SCLK
Hi-Z
MSB-1
Hi-Z
MODE Timing Relationships
DS31F5 DS31F4
CS5501 CS5503
CS5501/CS5503
SWITCHING CHARACTERISTICS (continued) Tmin Tmax; VA+, 10%; VA-, 10%; Input Levels: Logic Logic VD+;
Parameter Symbol fsclk Pulse Width High Pulse Width SCLK Falling High Output Hi-Z (Note tph3 tpl3 tcss tdd3 tfd5 Units
Mode (Mode VD-) CS5501 only
Serial Clock (In) Serial Clock (In) Set-up Time Output Float Delay
Maximum Data Delay Time SCLK Fall SDATA
Notes: returned high after 11-bit data packet started, SDATA output will continue output data until second stop bit. that time SDATA output will high impedance.
DRDY SCLK(i) SDATA Hi-Z START BIT8 High Byte BIT9 BIT6 BIT7 STOP1 STOP2 Hi-Z
Byte
MODE Timing Relationships (CS5501 only)
DS31F5 DS31F4
CS5501/CS5503 GENERAL DESCRIPTION CS5501/CS5503 monolithic CMOS converters designed specifically high resolution measurement low-frequency signals. Each device consists charge-balance converter (16Bit CS5501, 20-Bit CS5503), calibration microcontroller with on-chip SRAM, serial communications port. CS5501/CS5503 converters perform conversions continuously update their output ports after every conversion (unless serial port active). Conversions performed serial port updated independent external control. Both devices capable measuring either unipolar bipolar input signals, calibration cycles initiated time ensure measurement accuracy. CS5501/CS5503 perform conversions rate determined master clock signal. master clock external clock with crystal connected pins on-chip gate oscillator. master clock frequency determines: sample rate analog input signal. corner frequency on-chip digital filter. output update rate serial output port. CS5501/CS5503 design includes several selfcalibration modes several serial port interface modes offer users maximum system design flexiblity. Delta-Sigma Conversion Method CS5501/CS5503 converters chargebalance techniques achieve cost, high resolution measurements. charge-balance converter consists basic blocks: analog modulator digital filter. elementary example charge-balance converter conventional voltage-to-frequency converter counter. VFC's 1-bit output conveys inforDS31F5 DS31F4
CS5501 CS5503
mation form frequency duty cycle), which then filtered (averaged) counter higher resolution.
Filter
1-bit Digital Filter Comparator 16-bits
Figure Charge Balance (Delta-Sigma) Converter
analog modulator CS5501/CS5503 multi-order delta-sigma modulator. modulator consists 1-bit converter (that comparator) embedded analog feedback loop with high open loop gain (see Figure modulator samples converts input rate well above bandwidth interest. 1-bit output comparator sampled intervals based clock rate part this information (either conveyed digital filter. digital filter much more sophisticated than simple counter. filter chip 6-pole pass Gaussian response which rolls dB/decade dB/octave). corner frequency digital filter scales with master clock frequency. comparison, VFC's dual slope converters offer (sin x)/x filtering high frequency rejection (see Figure comparison characteristics these filter types). When operating from master clock digital filter CS5501/CS5503 offers better than rejection line frequencies does require type line synchronization achieve this rejection. should noted that CS5501/CS5503 will update output port almost 1000 times second when operating from clock. This much higher update rate (typically factor least times) than either VFCs dual-slope converters offer. more detailed discussion delta-sigma modulator Application note "Delta-Sigma
CS5501 CS5503
CS5501/CS5503
Magnitude (dB)
Magnitude (dB)
CLKIN CLKIN
CLKIN=1
-100
Frequency (Hz)
-100
Frequency (Hz)
Averaging (Integrating) Filter Response (tavg Figure Filter Responses
6-Pole Gaussian Filter Response
Conversion Technique Overview" application note section data book. application note discusses delta-sigma modulator some aspects digital filtering.
Clock Generator CS5501/CS5503 both include gates which connected crystal oscillator provide master clock signal chip. Alternatively, external (CMOS compatible) clock input CLKIN master clock device. Figure illustrates simple model on-chip gate oscillator. gate typical transconductance 1500 µmho. gate model includes capacitors input output pins. These capacitances include typical stray capacitance pins device. on-chip
CLKIN 10pF CLKOUT 10pF 1500 umho
OVERVIEW shown block diagram front page data sheet, CS5501/CS5503 segmented into five circuit functions. heart chip charge balance converter (16-bit CS5501, 20-bit CS5503). converter other circuit functions chip must driven clock signal from clock generator. serial interface logic outputs converted data. calibration microcontroller along with calibration SRAM (static RAM), supervises device calibration. Each segment chip control lines associated with function each pins described description section data sheet.
Table
Figure On-chip Gate Oscillator Model DS31F5 DS31F4
CS5501/CS5503 gate oscillator designed properly operate without additional loading capacitors when using 4.096 MHz) crystal. other crystal frequencies ceramic resonators used, loading capacitors necessary reliable operation oscillator. Table illustrates some typical capacitor values used with selected resonating elements.
Resonators Ceramic Crystals 2.000 3.579 4.096 30pF 20pF None 30pF 20pF None 330pF 100pF 50pF 20pF 470pF 100pF 50pF 20pF
CS5501 CS5503
(Asynchronous Communication) mode; CS5501 only MODE tied (-5V) CS5503 only operate first modes, SSC. Synchronous Self-Clocking Mode When operated mode (MODE tied VD+), CS5501/CS5503 furnish both serial output data (SDATA) internally-generated serial clock (SCLK). Internal timing mode illustrated Figure Figure shows detailed mode timing both CS5501/CS5503. filter cycle occurs every 1024 cycles CLKIN. During each filter cycle, status polled eight specific times during cycle. when polled, CS5501/CS5503 begin clocking data bits out, first, SCLK output rate CLKIN/4. Once transmission complete, DRDY rises both SDATA SCLK outputs into high impedance state. filter cycle begins each time DRDY falls. line active, DRDY will return high 1020 clock cycles after falls. Four clock cycles later DRDY will fall signal that serial port been updated with data that filter cycle begun. first polling during filter cycle occurs clock cycles after DRDY falls (the rising edge CLKIN which DRDY falls considered clock cycle number one). Subsequent pollings occur intervals clock cycles thereafter (76, 204, 332, etc.). signal polled beginning each eight data output windows which occur filter cycle. transmit data during eight output windows, must least three CLKIN cycles before polled. does meet this set-up time, data will transmitted during window time. Furthermore, latched internally therefore must held during entire data transmission obtain data bits.
Table Resonator Loading Capacitors
CLKOUT (pin used drive external CMOS gate system clock requirements. this case, external gate capacitance must taken into account when choosing value Caution: clock signal should always present whenever SLEEP inactive (SLEEP VD+). clock provided part when SLEEP, part draw excess current possibly even lose calibration data. This because device built using dynamic logic. Serial Interface Logic CS5501 serial data output operate following three different serial interface modes depending upon MODE selection: (Synchronous Self-Clocking) mode; MODE tied (+5V). (Synchronous External Clocking) mode; MODE tied DGND.
DS31F5 DS31F4
CS5501 CS5503
CS5501/CS5503
fout =1024/CLKIN 64/CLKIN Digital Time Polled Analog Time Digital Time1
64/CLKIN Internal Status DRDY CS5501 SCLK CS5501 SDATA CS5503 SCLK CS5503 SDATA Hi-Z Hi-Z Hi-Z Hi-Z
Note
Analog Time 76/CLKIN
Hi-Z (MSB) (LSB) Hi-Z Hi-Z (MSB) (LSB) Hi-Z
Note: There analog digital settling periods filter cycle shown). Data output mode only digital time periods each filter cycle. Figure Internal Timing
CLKIN CLKIN cycles DRDY SDATA SCLK CS5501 CS5503 Hi-Z Hi-Z (MSB) B15* B19** B14* B18** (LSB) Hi-Z Hi-Z
Figure Synchronous Self-Clocking (SSC) Mode Timing
eighth output window time overlaps time which serial output port updated. recognized being when polled eighth window time, data will output normal, serial port will updated with data until next serial port update time. Under these conditions, serial port will experience update rate only kSps
(CLKIN 4.096 MHz) instead normal kSps serial port update rate. Upon completion transmission data bits, SCLK SDATA outputs will high impedance state even with held low. event that taken high before data bits output, SDATA SCLK outputs will
DS31F5 DS31F4
CS5501/CS5503 complete current data output high impedance state when SCLK goes low. Synchronous External Clocking Mode When operated mode (MODE tied DGND), CS5501/CS5503 outputs data serial port rate determined external clock which input into SCLK pin. this mode output port will updated every 1024 CLKIN cycles. DRDY will when data loaded into output port. active, DRDY will return positive 1020 CLKIN cycles later remain four CLKIN cycles. taken will recognized immediately unless occurs while DRDY high four clock cycles. soon recognized, SDATA output will come high-impedance state present data bit. data will remain present until falling edge SCLK occurs advance output MSB-1 bit. external SCLK operated asynchronously CLKIN, errors result output data unless certain precautions taken. activated asynchronously, occur during four clock cycles when DRDY high therefore recognized immediately. certain that data misread errors will result occurs this time, SCLK input should transition high latch until four CLKIN cycles plus after taken low.
DRDY
CS5501 CS5503
This insures that will recognized will become stable before SCLK transitions positive latch data bit. When SCLK returns serial port will present MSB-1 data output. Subsequent cycles SCLK will advance data output. When data bits clocked out, DRDY will then high SDATA output will into high impedance state. input goes data bits clocked port, filter cycles will continue occur output serial port will updated with data (DRDY will remain low). taken high time, SDATA output will high impedance state. data bits serial port have been clocked out, they will remain available until DRDY returns high four clock cycles. After this DRDY will fall port will updated with 16-bit word CS5501 20-bit word CS5503. acceptable clock less than possible data bits returned high allow port updated. Figure illustrates serial port timing mode. Asynchronous Communication Mode (CS5501 Only) CS5501, mode activated when MODE tied When operating mode CS5501 designed
SCLK
(MSB) B15* B19**
(LSB) B14* B18**
Hi-Z
SDATA
Hi-Z CS5501 CS5503
Figure Synchronous External-Clocking (SEC) Mode Timing DS31F5 DS31F4
CS5501 CS5503
CS5501/CS5503 provide data output UART compatible format. baud rate SDATA output will determined rate SCLK input. data which output SDATA will formatted such that will contain data packets. Each packet includes start bit, eight data bits, stop bits. packet which carries most-significant-byte data will output first, with being first data output after start bit. this mode, DRDY will occur every 1024 clock cycles. serial port outputting data byte, DRDY will return high after 1020 clock cycles remain high clock cycles. DRDY will then indicate that update serial output port with word occurred. initiate transmission from port line must taken low. Then SCLK, which input this mode, must transition from high latch state internal CS5501. Once recognized latched low, port will begin output data. Figure details timing this output. returned high before 11-bit transmission transmission will continue until second stop first 11-bit packet output. SDATA output will into high impedance state after second stop output. obtain second 11-bit packet must again brought before DRDY goes high second 11-bit data packet will overwritten with serial port update. second 11-bit packet, need only need latched falling edge SCLK. Alternately, line taken held until both 11-bit data packets output. This preferred method control will prevent losing second 11-bit data packet port updated. Some serial data rates quite slow compared rate which CS5501 update output port. slow data rate will leave only short period time start second 11bit packet returned high momentarily. held continuously hard-wired DGND), serial port will updated only after bits have been clocked port. Upon completion transmission 11-bit data packets SDATA output will into high impedance state. time during transmission taken back high, current 11-bit data packet will continue output. second stop data packet, SDATA output will into high impedance state. Linearity Performance CS5501/CS5503 delta-sigma converters like conventional charge-balance converters that they have source nonmonotonicity. devices therefore have missing codes their transfer functions. Figure plot
SCLK
DRDY
Stop Stop Start Stop Stop
SDATA
Hi-Z
Start
Figure CS5501 Asynchronous (UART) Mode Timing DS31F5 DS31F4
CS5501/CS5503
CS5501 CS5503
+1/2
(LSB)
-1/2
32,768
65,535
Codes
Figure CS5501 Differential Nonlinearity Plot
excellent differential linearity achieved CS5501. CS5501/CS5503 also have excellent integral linearity, which accomplished with well-designed charge-balance architecture. Each device also achieves input drift through chopper-stabilized techniques input stage. assure that CS5501/CS5503 achieves excellent performance over time temperature, uses digital calibration techniques minimize offset gain errors typically within ±1/2 bits CS5501 bits CS5503. Calibration CS5501/CS5503 offer both self-calibration system level calibration capability. understand calibration features, basic comprehension internal workings converter helpful. mentioned previously this data sheet, converter consists sections. First analog modulator which delta-sigma type charge-balance converter. This followed digital filter. filter circuitry actually arithmetic logic unit (ALU) whose architecture instructions execute filter function. modulator (explained more detail applications note "Delta-Sigma Conversion Technique Overview") uses VREF voltage connected determine magnitude voltages used feedback DAC. modulator accepts analog signal input produces data stream output. This data stream value change
DS31F5 DS31F4
(from vice versa) every CLKIN cycles. input voltage increases ratio modulator increases proportionally. density data stream modulator therefore provides digital representation analog input signal where density defined ratio number number modulator given period time. density output modulator also function voltage VREF pin. voltage VREF increases value (say, temperature drift), analog input voltage into modulator remains constant, density output modulator will decrease (less will occur). analog input into modulator which necessary produce given binary output code from converter ratiometric voltage VREF pin. This means that VREF increases cent, analog signal must also increase cent maintain same binary output code from converter. complete calibration occur, calibration microcontroller inside device needs record data stream density modulator different input conditions. First, "zero scale" point must presented modulator. Then "full scale" point must presented modulator. unipolar self-cal mode zero scale point AGND full scale point voltage VREF pin. calibration microcontroller then remembers density modulator each these points calculates slope factor (LSB/µV). This slope factor
CS5501 CS5503
CS5501/CS5503 represents gain slope input output transfer function converter. unipolar mode calibration microcontroller determines slope factor dividing span between zero point full scale point total resolution converter (216 CS5501, resulting 65,536 segments CS5503, resulting 1,048,578 segments). bipolar mode calibration microcontroller divides span between zero point full scale point into 524,288 segments CS5503 32,768 segments CS5501. then extends measurement range 524,288 segments CS5503, 32,768 segments CS5501, below zero scale point achieve bipolar measurement capability. either unipolar bipolar modes calculated slope factor saved later used calculate binary output code when analog signal present during measurement conversions. System calibration allows converter compensate system gain offset errors (see
VREF Transducer Analog Signal Conditioning Circuitry SCLK CS5501 CS5503 SDATA
DATA
Figure System calibration performs same slope factor calculations self uses voltage values presented system zero scale point full scale point. Table depicts calibration modes available. system calibration modes listed. first mode offers system level calibration system offset system gain. This step calibration. zero scale point (system offset) must presented converter first. voltage that represents zero scale point must input converter before calibration step initiated must remain stable until step complete. DRDY output from converter will signal when step complete going low. After zero scale point calibrated, voltage representing full scale point input converter second calibration step initiated. Again voltage must remain stable throughout calibration step. This step calibration mode offers another calibration feature. After step calibration
Figure System Calibration
Type
Self-Cal System Offset System Gain System Offset
AGND
VREF VREF
Sequence
Step Step Step Step
Calibration Time
3,145,655/fclk 1,052,599/fclk 1,068,813/fclk 2,117,389/fclk
DRDY remains high throughout calibration sequence. Self-Cal mode (SC1 low) DRDY falls once CS5501 CS5503 settled analog input. other modes DRDY falls immediately after calibration term been determined. Table Calibration Control DS31F5 DS31F4
CS5501/CS5503 sequence (system offset system gain) been properly performed, additional offset calibrations performed themselves reposition gain slope (the slope factor changed) adjust zero reference point system zero reference value. second system calibration mode available which uses input voltage zero scale calibration point, uses VREF voltage full scale calibration point. Whenever system calibration mode used, there limits amount offset amount span which accommodated. range input span which accommodated either unipolar bipolar mode restricted less than voltage VREF more than 200% (VREF 0.1) amount offset which calibrated depends upon whether unipolar bipolar mode being used. unipolar mode system calibration modes handle offsets positive VREF (this restricted minimum span requirement VREF) negative -(VREF 0.1) This capability enables unipolar mode CS5501/CS5503 calibrated mimic bipolar mode operation. bipolar mode system offset calibration range restricted maximum ±40% VREF. should noted that span restrictions limit amount offset which calibrated. span range converter bipolar mode extends equidistance from voltage used zero scale point. When zero scale point calibrated must cause either endpoints bipolar transfer function exceed positive negative input overrange points (+(VREF 0.1) (VREF 0.1) span range minimum (80% VREF) offset voltage move ±40% VREF without causing points transfer function exceed overrange points. Alternatively, span range 200%
DS31F5 DS31F4
CS5501 CS5503
VREF, input offset cannot move more than +0.1 before endpoint transfer function exceeds input overrange limit. Initiating Calibration Table illustrates calibration modes available CS5501/CS5503. shown table function BP/UP which determines whether converter calibrated measure bipolar unipolar signals. calibration step initiated bringing (13) high least CLKIN cycles reset part then bringing low. states (pin (pin along with BP/UP (pin will determine type calibration performed. inputs latched when goes low. BP/UP input latched therefore must remain fixed state throughout calibration measurement cycles. time state BP/UP changed, calibration cycle must performed enable CS5501/CS5503 properly function mode. When calibration step initiated, DRDY signal will high remain high until step finished. Table illustrates number clock cycles each calibration requires. Once calibration step initiated must finish before calibration step executed. step system calibration mode, offset calibration step must initiated before initiating gain calibration step. When self-cal completed DRDY falls output port updated with data word that represents analog input signal pin. When system calibration step completed, DRDY will fall output port will updated with appropriate data value (zero scale point, full scale point). system calibration mode, digital filter must settle before output code will represent value analog input signal.
CS5501 CS5503
CS5501/CS5503
1LSB Unipolar CS5501 Self-Cal System AGND SOFF VREF SGAIN VREF 65,536 SGAIN-SOFF 65,536 CS5503 VREF 1,048,526 SGAIN-SOFF 1,048,526 CS5501 2VREF 65,536 2(SGAIN-SOFF) 65,536 Bipolar CS5503 2VREF 1,048,526 2(SGAIN-SOFF) 1,048,526
Mode
Zero Scale
Gain Factor
Table Output Code Size After Calibration
Input Voltage, Unipolar Mode System-Cal >(SGAIN LSB) SGAIN Self-Cal >(VREF LSB) VREF Output Codes (Hex) CS5501 FFFF FFFF CS5503 FFFFF FFFFF Input Voltage, Bipolar Mode Self-Cal >(VREF LSB) VREF AGND -VREF+ <(-VREF+0.5 LSB) System >(SGAIN LSB) SGAIN SOFF -0.5 -SGAIN 2SOFF <(-SGAIN+2SOFF+0.5 LSB)
FFFE
8000
FFFFE
80000
(SGAIN SOFF)/2 VREF/2 SOFF <(SOFF LSB) AGND <(AGND+0.5 LSB)
7FFF
0001
7FFFF
00001
0000
0000
00000
00000
Table Output Coding
Tables indicate output code size output coding CS5501/CS5503 various modes. calibration equations which represent CS5501/CS5503 transfer function shown Figure
Underrange Overrange Considerations input signal range CS5501/CS5503 will determined mode which part calibrated. Table indicates input signal range various modes operation. input signal exceeds full scale point converter will output ones. signal less than zero scale point unipolar) more negative magnitude than minus full scale point bipolar) will output zeroes. Note that modulator-filter combination chip CS5501/CS5503 designed accurately convert filter input signals with noise excursions which extend below analog value which produces zeros above analog value which produces ones out. Overrange noise excursions greater than increase output noise. pins CS5501/CS5503 include diodes which clamp input signals within positive negative supplies. signal (including AIN) exceeds supply voltage (either
DS31F5 DS31F4
DOUT Slope (AIN Unipolar Offset) Unipolar Calibration
CS5501 DOUT Slope (AIN Bipolar Offset) LSB16 CS5503 DOUT Slope(AIN Bipolar Offset) LSB20 Bipolar Calibration
Figure Calibration Equations
CS5501/CS5503 clamp diode will forward-biased. Under these fault conditions CS5501/CS5503 might damaged. Under normal operating conditions (with power supplies established), device will survive transient currents through clamp diodes continuous currents drive current into should limited safe value overvoltage condition likely occur. application note "Buffer Amplifiers CS501X Series Converters" further discussion clamp diode input structure current limiting circuits. System Synchronization more than CS5501/CS5503 included system which operating from common clock, devices synchronized sample output exactly same time. This accomplished either ways. First, single signal issued CS5501/CS5503's system. insure synchronization same clock signal signal should falling edge CLKIN. second, common SLEEP control signal issued. SLEEP signal goes positive with appropriate time CLKIN, parts will synchronized same clock cycle. Analog Input Impedance Considerations analog input CS5501/CS5503 modeled illustrated Figure capacitor used dynamically sample input signal. Every CLKIN cycles switch alternately connects capacitor output buffer then directly pin. Whenever sample capacitor switched from output buffer pin, small packet charge dynamic demand current) will required from input source settle voltage sample capacitor final value. voltage output buffer differ from actual input voltage
DS31F5 DS31F4
CS5501 CS5503
CS5501 CS5503
AGND
Figure Analog Input Model
offset voltage buffer. Timing allows cycles master clock (CLKIN) voltage sample capacitor settle final value. equation which defines settling time
Vmax
Where final settled value, Vmax maximum error voltage value input signal, value input source resistance, sample capacitor plus value stray additional capacitance input pin. value equal 64/CLKIN. Vmax occurs instance when sample capacitor switched from buffer output pin. Prior switch, error estimated being less than equal Vmax equal prior error (Ve) plus additional error from buffer offset. estimate Vmax
Vmax Ve+100mV
20pF (20pF+CEXT)
Where CEXT combination external stray capacitance. From equation which defines settling time, equation maximum acceptable source resistance derived
CS5501 CS5503
CS5501/CS5503 equation which defines settling time, equation maximum acceptable source resistance derived
Rsmax CLKIN(20pF+CEXT 20pF(100mv) 20pF+CEXT
This equation assumes that offset voltage buffer which worst case. value maximum error voltage which acceptable. maximum error voltage (Ve) CS5501 (1/4LSB 16-bits) CS5503 (1/4LSB 20-bits), above equation indicates that when operating from 4.096 CLKIN, source resistances CS5501 CS5503 acceptable absence external capacitance (CEXT higher input source resistances desired master clock rate reduced yield longer settling time cycle period.
CS5501 Bipolar Offset
drift. Charge injection analog switches leakage currents sampling node primary sources offset voltage drift converter. Figure indicates typical offset drift temperature changes experienced after calibration Drift relatively flat about Above leakage current becomes dominant source offset drift. Leakage currents approximately double with each temperature increase. Therefore offset drift leakage current increases temperature increases. value voltage sample capacitor updated rate determined master clock, therefore amount offset drift which occurs will proportional elapsed time between samples. conclusion, offset drift increases with temperature inversely proportional CLKIN rate. minimize offset drift with increased temperature, higher CLKIN rates desirable. temperatures above CLKIN rate above recommended. effects offset drift temperature changes eliminated recalibrating CS5501/CS5503 whenever temperature changed. Gain drift within converter depends predominately upon temperature tracking internal capacitors. Gain drift affected leakage currents, therefore gain drift significantly less than comparable offset errors temperature increases. typical gain drift over specified temperature range less than LSBs CS5501 less than LSBs CS5503 Measurement errors offset drift gain drift eliminated time recalibrating converter. Using system calibration mode also minimize offset gain errors signal conditioning circuitry. CS5501/CS5503 recalibrated temperature remove effects these errors. Linearity differential linearity significantly affected temperature changes.
DS31F5 DS31F4
-160 -240
-320
Temperature Deg.
Figure Typical Self-Cal Bipolar Offset Temperature After Calibration
Analog Input Drift Considerations CS5501/CS5503 analog input uses chopperstabilization techniques minimize input offset
CS5503 Bipolar Offset
CS5501/CS5503 Filtering system level, digital filter CS5501/CS5503 modeled exactly like analog filter with minor differences. Digital filtering resides behind conversion thus reject noise injected during conversion process (i.e. power supply ripple, voltage reference noise, noise itself). Analog filtering cannot. Also, since digital filtering resides behind converter, noise riding unfiltered near-full-scale input could potentially overrange ADC. contrast, analog filtering removes noise before ever reaches CS5501/CS5503 each contain analog modulator digital filter which reserve headroom such that device process signals with 100mV "excursions" above full-scale still output accurately converted filtered data. Filtered input signals above full-scale still result output ones. digital filter's corner frequency occurs CLKIN/409,600, where CLKIN master clock frequency. With 4.096MHz clock,
Vertical scale normalized input step size expanded view
CS5501 CS5503
filter corner 10Hz output register updated 4kHz rate. CLKIN frequency reduced with proportional reduction filter corner frequency update rate output register. plot filter response shown specification tables section this data sheet. Both CS5501/CS5503 employ internal digital filtering which creates 6-pole Gaussian relationship. With corner frequency CS5501/CS5503 offer approximately 55dB rejection 60Hz signals coming into either VREF pins. With cut-off, 60Hz rejection increases more than 90dB. digital filter (rather than analog modulator) dominates converters' settling step-function inputs. Figure illustrates settling characteristics filter. vertical axis normalized input step size. horizontal axis filter cycles. With full scale input step (2.5 unipolar mode) output will exhibit overshoot about 0.25 LSB16 CS5501 LSB20 CS5503.
1.0000125 1.0000100 1.0000075 Settling Accuracy 1.0000050 1.0000025 1.0000000 0.9999975 0.9999950 0.9999925 0.9999900 1.00000381 Vertical scale normalized input step size
Settling Accuracy
0.99999850 Settling response monotonically increasing from zero here, then exhibits overshoot undershoot shown.
0.9999875
Filter Cycles (1024 CLKIN cycles)
Filter Cycles (1024 CLKIN cycles)
Settling Time Input Step Change
Expanded Version
DS31F5 DS31F4
CS5501 CS5503
CS5501/CS5503 Anti-Alias Considerations digital filter CS5501/CS5503 does provide rejection around integer multiples oversampling rate [(N*CLKIN)/256, where 1,2,3,.]. That with 4.096 master clock noise analog input signal within narrow bands around kHz, kHz, kHz, etc., passes unfiltered digital output. Most broadband noise will very well filtered because CS5501/CS5503 very high oversampling ratio kHz: 2x10 Hz). Broadband noise reduced
eout 2f-3dB eout 0.035
Post Filtering Post filtering useful enhance noise performance CS5503. With constant input voltage output codes from CS5503 will exhibit some variation noise. CS5503 typically LSB20 noise output codes. Additional variation output codes arise noise from input signal source from voltage reference. Post filtering (digital averaging) will necessary achieve less than noise 20-bit level. CS5503 peak noise less than 18-bit level without additional filtering care exercised design voltage reference input signal condition circuitry. Noise bandwidth from both VREF inputs should minimized ensure maximum performance. amount noise will highly system dependent, specific recommendation post filtering applications cannot stated. following guidelines helpful. Realize that digital filter CS5503, like other pass filter, acts information storage unit. filter retains past information period time even after input signal changed. implication this that immediately sequential 20-bit updates serial port contain highly correlated information. most efficiently post filter CS5503 output data, uncorrelated samples should used. Samples which have sufficiently reduced correlation obtained CS5503 allowed execute filter cycles between each subsequent data word collected post filtering. character noise data will influence post filtering requirements. general rule, averaging uncorrelated data samples will reduce noise 1/N. While this rule assumes that noise white (which true CS5503 true real system signals between 10Hz), does offer starting point developing post filtering algorithm removing noise from data. algorithm
DS31F5 DS31F4
where eout noise terms referred input. Since f-3dB equals CLKIN/409,600 equals CLKIN/256, digital filter reduces white, broadband noise 96.5% independent CLKIN frequency. example, typical operational amplifier's 50µV noise would reduced 1.75µV (0.035 LSB's 16-bit level CS5501 LSB's 20-bit level CS5503). Simple high frequency analog filtering signal conditioning circuitry removing energy multiples sampling rate.
Bits Output Accuracy Filter Cycles CLKIN Cycles 348,160 364,544 398,336 445,440 470,016 486,400 497,664 506,880 512,000 516,096 518,144 519,168
Table Settling Time Pole Pass Filter CS5501 Accuracy with Full Scale Step Input
CS5501/CS5503 will have empirically tested meets system requirements. recommended that testing include input signals across entire input span converter signal level will affect amount noise from reference input which transferred output data. Voltage Reference Power Supplies Grounding voltage reference applied VREF input defines analog input range CS5501/CS5503. preferred reference 2.5V, device typically accept references from Input signals which exceed 2.6V cause some linearity degradation. Figure illustrates voltage reference connections CS5501/CS5503.
CS5501 CS5503
CS5501 CS5503
band-gap references available which supply with CS5501/CS5503. Many these devices specified noise, especially bandwidth. Some these devices exhibit noise characteristics which degrade performance CS5501/CS5503.
CS5501/CS5503 analog ground connection, AGND, measurement reference node. carries power supply current. AGND should used reference node both analog input signal reference voltage which input into VREF pin. analog digital supply inputs pinned separately minimize coupling between analog digital sections chip. achieve maximum performance, four supplies CS5501/CS5503 should decoupled their respective grounds using capacitors. This illustrated System Connection Diagram, Figure beginning this data sheet. CMOS devices, CS5501/CS5503 require that positive analog supply voltage always greater than equal positive digital supply voltage. voltage positive digital supply should ever become greater than voltage positive analog supply, diode junctions CMOS structure which normally reversebiased will become forward-biased. This cause part draw high currents experience permanent damage. connections shown Figure eliminate this possibility. ensure reliable operation, certain that power applied part before signals AIN, VREF, logic input pins present. current supplied into before chip poweredup, latch result. system, desirable power CS5501/CS5503, volt25
Example LT1019 -2.5
VREF AGND
Figure Voltage Reference Connections
circuitry inside VREF identical that seen pin. sample capacitor (see Figure requires packets charge from external reference just does. Therefore same settling time requirements apply. Most reference IC's handle this dynamic load requirement without inducing errors. They exhibit sufficiently output impedance wide enough bandwidth settle within necessary accuracy requisite CLKIN cycles. Noise from reference filtered digital filter, reference should chosen minimize noise below CS5501/CS5503 typically exhibit noise respectively. This specification assumes clean reference voltage. Many monolithic
DS31F5 DS31F4
CS5501 CS5503
CS5501/CS5503
Analog Supply Calibration Control CLKIN CLKOUT SLEEP CS5501 CS5503 MODE SCLK SDATA DRDY VREF AGND DGND Recommended reduce high frequency noise Optional Clock Source Sleep Mode Control Output Mode Select Serial Data Interface Control Logic
Analog Signal Source VREF ±VREF
Bipolar/ Unipolar Input Select
BP/UP
0.0047
Analog Supply Analog Supply
Voltage Reference
+2.5V
Unused Logic Inputs must connected DGND
Figure Typical Connection Diagram
reference, analog signal conditioning circuitry from same primary source. separate supplies used, recommended that CS5501/CS5503 powered first. common power source used analog signal conditioning circuitry well converter, this power source should applied before application power digital logic supply. CS5501/CS5503 exhibit good power supply rejection frequencies within passband Hz). small offset gain error caused long term drift power supplies
removed recalibration. Above digital filter will provide additional rejection. When benefits digital filter added regular power supply rejection effects line frequency variations power supplies will reduced greater than supply voltages CS5501/CS5503 generated with dc-dc converter operating frequency dc-dc converter should operate sampling frequency CS5501/CS5503 integer multiples thereof. these frequencies digital filter will power supply rejection. Anti-Alias Considerations section this data sheet.
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CS5501/CS5503 recommended system connection diagram CS5501/CS5503 illustrated Figure Note that digital logic inputs which unused should tied either DGND appropriate. They should left floating; should they tied some other logic supply voltage system. Power-up Initialization Upon power-up, calibration cycle must initiated insure consistent starting condition initially calibrate device. must strobed high minimum clock cycles. falling edge will initiate calibration cycle. simple power-on reset circuit built using resistor capacitor (see Figure 16). resistor capacitor values should allow clock oscillator startup time, voltage reference stabilization time.
CS5501 CS5503
reading will occur after rising edge SLEEP occurs. Battery Backed-up Calibrations CS5501/CS5503 SRAM store calibration information. contents SRAM will lost whenever power removed from chip. Figure shows battery back-up scheme that used retain calibration memory during system down time and/or protect against intermittent power loss. Note that upon loss power, SLEEP input goes low, reducing power consumption just Lithium cells available which average 1750 mAhours before they drop below typical memory-retention specification CS5501/CS5503.
1N4148
CS5501 CS5503 AGND DGND SLEEP
1N4148
CS5501
1N4148
(2V+Vd) 4.5V
Figure Power-On Reset Circuitry (Self-Calibration Only)
devices' power dissipation temperature drift, warm-up time required accommodate self-heating effects. Sleep Mode CS5501/CS5503 include sleep mode (SLEEP DGND) which shuts down internal analog digital circuitry reducing power consumption less than calibration coefficients retained memory such that time required after "awakening" recalibration. Still, CS5501/CS5503 will require time digital filter settle before accurate
DS31F5 DS31F4
Figure Example Calibration Memory Battery Back-Up Circuit
When SLEEP active (SLEEP DGND), both must remain powered less than retain calibration memory. VDand voltages reduced must allowed above ground potential. negative supply must exhibit source impedance powered-down state current into flows pin. (AGND only reference node. power supply current flows AGND.) Care should taken
CS5501 CS5503 CS5501 CS5503
ensure that logic inputs maintained either DGND potential when SLEEP low. Note that battery life could shortened supply drops slowly during power-down. supply drops below battery voltage below logic threshold SLEEP pin, battery will supplying CS5501/CS5503 full power (typically mA). Faster transitions SLEEP triggered using resistive divider simple resistor network generate SLEEP input from supply.
Output Loading Considerations
maximize performance CS5501/ CS5503, output drive currents from digital output lines should minimized.
Schematic Layout Review Service
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CS5501/CS5503 DESCRIPTIONS
SERIAL INTERFACE MODE SELECT CLOCK CLOCK SYSTEM CALIBRATION DIGITAL GROUND NEGATIVE DIGITAL POWER NEGATIVE ANALOG POWER ANALOG GROUND ANALOG VOLTAGE REFERENCE MODE CLKOUT CLKIN DGND VDVAAGND VREF
CS5501 CS5503
SDATA SCLK DRDY BP/UP SLEEP
SERIAL DATA OUTPUT SERIAL CLOCK INPUT/OUTPUT DATA READY SYSTEM CALIBRATION CHIP SELECT POSITIVE DIGITAL POWER POSITIVE ANALOG POWER CALIBRATE BIPOLAR/UNIPOLAR SELECT SLEEP
Pinout applies both SOIC packages
Clock Generator CLKIN; CLKOUT -Clock Clock Out, Pins gate inside CS5501/CS5503 connected these pins used with crystal ceramic resonator provide master clock device. Alternatively, external (CMOS compatible) clock input CLKIN master clock device. When SLEEP mode, master clock (CLKIN) should present times. Serial Output MODE -Serial Interface Mode Select, Selects operating mode serial port. tied (-5V), CS5501 will operate UART-compatible mode Asynchronous Communication. SCLK will operate input data rate, data will transmit formatted with start stop bits. MODE tied DGND, CS5501/CS5503 will operate (Synchronous External-Clocking) mode, with SCLK operating input output appearing MSB-first. MODE tied (+5V), CS5501/CS5503 will operate (Synchronous Self-Clocking) mode, with SCLK providing serial clock output CLKIN/4 (25% duty-cycle). DRDY -Data Ready, DRDY goes every 1024 cycles CLKIN indicate that data been placed output port. DRDY goes high when serial port data clocked out, when serial port being updated with data, when calibration progress, when SLEEP low. -Chip Select, input which enabled external device gain control over serial port CS5501/CS5503.
DS31F4 DS31F5
CS5501 CS5503
CS5501/CS5503 SDATA -Serial Data Output, Data from serial port will output from this rate determined SCLK format determined MODE pin. furnishes high impedance output state when transmitting data. SCLK -Serial Clock Input/Output, clock signal this determines output rate data from SDATA pin. MODE determines whether SCLK signal input output. SCLK provide high impedance output when data being output from SDATA pin. Calibration Control Inputs SC1; -System Calibration Pins Control inputs CS5501/CS5503's calibration microcontroller calibration. state determine which calibration modes selected operation (see Table BP/UP -Bipolar/Unipolar Select, Determines whether CS5501/CS5503 will calibrated measure bipolar (BP/UP VD+) unipolar (BP/UP DGND) input signals. Recalibration necessary whenever state BP/UP changed. -Calibrate, brought high clock cycles more, CS5501/CS5503 will reset upon returning full calibration cycle will begin. state SC1, SC2, BP/UP when brought determines type length calibration cycle initiated (see Table Also, single signal used strobe pins high several CS5501/CS5503's synchronize their operation. spurious glitch this inadvertently place chip Calibration mode. Other Control Input SLEEP -Sleep, When brought low, CS5501/CS5503 will enter low-power state. When brought high again, CS5501/CS5503 will resume operation without need recalibrate. After SLEEP goes high again, device's output will settle within +0.0007% analog input value within 1.3/f-3dB, where f-3dB passband frequency. SLEEP input also used synchronize sampling output updates several CS5501/CS5503's. Analog Inputs VREF -Voltage Reference, Analog reference voltage input. -Analog Input,
DS31F4 DS31F5
CS5501/CS5503 Power Supply Connections -Positive Digital Power, Positive digital supply voltage. Nominally volts. -Negative Digital Power, Negative digital supply voltage. Nominally volts. DGND -Digital Ground, Digital ground. -Positive Analog Power, Positive analog supply voltage. Nominally volts. -Negative Analog Power, Negative analog supply voltage. Nominally volts. AGND -Analog Ground, Analog ground.
CS5501 CS5503
DS31F4 DS31F5
CS5501 CS5503
CS5501/CS5503 SPECIFICATION DEFINITIONS Linearity Error deviation code from straight line which connects endpoints Converter transfer function. endpoint located below first code transition other endpoint located beyond code transition ones. Units percent full-scale. Differential Linearity deviation code's width from ideal width. Units LSB's. Full-Scale Error deviation last code transition from ideal (VREF-3/2 LSB's). Units LSBs. Unipolar Offset deviation first code transition from ideal (1/2 above AGND) when unipolar mode (BP/UP low). Units LSBs. Bipolar Offset deviation mid-scale transition (011.111 100.000) from ideal (1/2 below AGND) when bipolar mode (BP/UP high). Units LSBs. Bipolar Negative Full-Scale Error deviation first code transition from ideal when bipolar mode (BP/UP high). Ideal defined lying straight line which passes through final mid-scale code transitions. Units LSBs. Positive Full-Scale Input Overrange absolute maximum positive voltage allowed either accurate system calibration accurate conversions. Units volts. Negative Full-Scale Input Overrange absolute maximum negative voltage allowed either accurate system calibration accurate conversions. Units volts. Offset Calibration Range CS5501/CS5503 calibrate their offset voltage applied when system calibration mode. first code transition defines Unipolar Offset when BP/UP mid-scale transition defines Bipolar Offset when BP/UP high. Offset Calibration Range specification indicates range voltages applied that CS5501 CS5503 accept still calibrate offset accurately. Units volts. Input Span voltages applied system-calibration schemes define CS5501/CS5503 analog input range. Input Span specification indicates minimum maximum input spans from zero-scale full-scale unipolar, from positive full scale negative full scale bipolar, that CS5501/CS5503 accept still calibrate gain accurately. Units volts.
DS31F4 DS31F5
CS5501 CS5503
ORDERING INFORMATION
Model Package Resolution Throughput Linearity Temperature
CS5501-BP CS5501-BS CS5501-BSZ (lead free) CS5503-BP CS5503-BS CS5503-BSZ (lead free)
20-pin Plastic 20-pin SOIC 20-pin Plastic 20-pin SOIC Bits Bits kSps 0.0015
ENVIRONMENTAL, MANUFACTURING, HANDLING INFORMATION
Model Peak Relfow Temp Rating* Maximum Floor Life
CS5501-BP CS5501-BS CS5501-BSZ (lead free) CS5503-BP CS5503-BS CS5503-BSZ (lead free)
Limit Days Days Limit Days Days
(Moisture Sensitivity Level) specified IPC/JEDEC J-STD-020.
DS31F5
CS5501 CS5503
CS5501/CS5503 APPENDIX APPLICATIONS Parallel Interface Figures show serial-to-parallel conversion circuits interfacing CS5501 mode 8-bit systems respectively. Each circuit includes optional 74HCT74 flip-flop latch DRDY generate level-sensitive interrupt. Both circuits require that parallel read process synchronized CS5501's operation. That system must enable registers' parallel output while they accepting serial data from CS5501. CS5501's DRDY falls just prior serial data transmission
CS5501 CS5503 SDATA MODE DRDY SCLK 74HCT299
returns high last shifts out. Therefore, DRDY polled rising transition directly, latched levelsensitive interrupt. With input tied CS5501 will shift every available sample (4kHz word rate with 4MHz master clock). Lower output rates (and interrupt rates) generated dividing down DRDY output applying Totally asynchronous interfaces created using Shift Data control signal from system which enables CS5501's input and/or shift registers' inputs. DRDY output then used disable serial data transmission once output word been fully registered.
74HCT299 74HCT74
RESET
Only needed interrupt driven systems
DRDY (For polling)
Figure 16-bit Parallel Interface DS31F4 DS31F5
CS5501/CS5503 such asynchronous configurations CS5501 operated much like successive-approximation converter with Convert signal subsequent read cycle. required latch 16-bit data, then 74HC595 8-bit "shift register with latch" parts used instead 74HC299's. Serial Interfaces Figures offer both hardware software interfaces several industry-standard microcontrollers using CS5501's output modes. each instance system initialization routine provided which configures controller's ports accept CS5501's serial data clock outputs and/or generate
CS5501 CS5503
serial clock. routine also sets CS5501 into known state. each interface, second subroutine also provided which will collect complete 16-bit output word from CS5501. Figure illustrates detailed timing throughout subroutine particular interface COPS family interface Figure
CS5501 CS5503
SDATA MODE DRDY SCLK 74HCT299
74HCT74
74HCT299
RESET
Only needed interrupt driven systems
DRDY (For polling)
Figure 8-Bit Parallel Interface DS31F4 DS31F5
CS5501 CS5503
CS5501/CS5503 Initial Code:
SPINIT: PSHA LDAA STAA LDAA STAA LDAA STAA LDAA STAA LDAA LDAA PULA #%x1xxxxxx PORTA #$10 SPCR #%xx0110xx DDRD #$50 SPCR SPSR SPDR Store temporary copy others don't cares inactive; deselect CS5501 Disable serial port SS-input, SCK-output, MOSI-output, MISO-input Data direction register port Enable serial port, CMOS outputs, master, highest clock rate (int. clk/2) Bogus read port SPIF flag Restore
CS5501 CS5503 SCLK MODE SDATA
68HC11 MISO (68HC05)
Figure 68HC11/CS5501 Serial Interface
Notes:
CS5501 Synchronous External Clocking mode. Using 68HC11's port. (Can CS5501's Asynchronous mode.) Maximum rate 1.05 Mbps.
SP_IN:
Code word data:
LDAA STAA STAA WAIT1: LDAA LDAA STAA WAIT2: LDAB LDAB STAB LDAB #%x0xxxxxx PORTA SPDR SPSR WAIT1 SPDR SPDR SPSR WAIT2 #%x1xxxxxx PORTA SPDR active; select CS5501 data serial port start port status SPIF (MSB) data yet, wait most significant byte Start serial port second byte port status SPIF (MSB) data yet, wait inactive; deselect CS5501 least significant byte
Assumptions:
used 68HC11 single-chip mode. Receive data polling. Normal equates peripheral registers. Data returned register
CS5501 CS5503 MODE SCLK SDATA
COPS (All COPS)
Initial Code:
SPINIT: inactive; deselect CS5501 Reset carry, used next instruction turn
Code word data:
SP_IN: GETNIB: 0,12 Point start data storage location carry enables instruction active; select CS5501 Shift register mode, Start clocking serial port Wait (first) M.S. nibble nibble data from nibble memory, inc. pointer, overflow, jump around this inst. Reset carry disables instruction Bogus read stops inactive; deselect CS5501
Figure COPS/CS5501 Interface
Notes:
CS5501 Synchronous External Clocking mode. COPS baud 62.5 kbps. (Others kbps) timing diagram detailed timing.
GETNIB
Assumptions:
used Register (upper four nibbles) used store 16-bit word.
DS31F4 DS31F5
CS5501/CS5503
Instruction SYNC (COPS internal) (G0) Shift SCLK (SK) GDAT: GETLP:
CS5501 CS5503
DATA (SI)
HI-Z
(MSB)
Instruction SYNC (COPS internal) (G0)
GETLP: GETLP
GETLP: GETLP
GETLP: GETLP
SCLK (SK) DATA (SI)
skip Instruction SYNC (COPS internal) (G0) SCLK (SK) DATA (SI) GETLP
HI-Z
Figure Serial Timing Example COPS DS31F4 DS31F5
CS5501 CS5503
CS5501/CS5503 Initial Code:
SCLK DATA SPINIT: SETB SETB SETB SETB P1.1 P1.2 P1.3 DATA SCLK
CS5501 DRDY MODE SCLK SDATA
8051 INT1 P1.1 P1.2
P1.3
Disable INT1 INT1 falling edge triggered DATA input deselect CS5501 SCLK Enable INT1 interrupt
Figure MCS51 (8051) /CS5501 Serial Interface
Code word data:
0003H LJMP GETWD GETWD: PUSH PUSH PSW,#08 R6,#8 MSBYTE:SETB SCLK C,DATA SCLK DJNZ R6,MSBYTE R7,A R6,#8 LSBYTE: SETB SCLK C,DATA SCLK DJNZ R6,LSBYTE R6,A SETB RETI Interrupt vector Save temp. copy Save temp. copy register bank active number bits byte select CS5501 Toggle SCLK high data into carry Toggle SCLK low; next data Shift DATA into register Dec. another MSbyte into Reset number bits byte Toggle SCLK high data into carry Toggle SCLK low; next data Shift DATA into register Dec. another LSbyte into deselect CS5501 Restore original value Restore original value
Notes:
CS5501 Synchronous External Clocking mode. Interrupt driven 8051 (For polling, connect DRDY another port pin).
Assumptions:
INT1 external interrupt used. Register bank used store data word, MSbyte. enabled elsewhere.
CS5501 SCLK MODE SDATA P1.2
8051
(Assumptions cont.) Word received (ACC) registers, MSbyte. error checking done. Equates used peripheral names.
Initial Code:
SPINIT: SETB SMOD SMOD baud OSC/32 SETB P1.2 inactive SCON,#1001000B Enable serial port mode receiver enabled, transmitter disabled Disable serial port interrupts (polling)
Figure MCS51 (8051) /CS5501 UART Interface
Notes:
CS5501 Asynchronous (UART-like) mode. 8051 mode with MHz, baud kbps.
Code word data:
SP_IN: SETB P1.2 RI,$ A,SBUF RI,$ B,SBUF P1.2 active; select CS5501 Wait first byte most significant byte wait second byte least significant byte inactive; deselect CS5501
Assumptions:
P1.2 (port used Using serial port mode Baud rate OSC/32.
DS31F4 DS31F5
CS5501/CS5503
CS5501 MODE SCLK SDATA TMS70X2 SCLK (TMS70CX2)
CS5501 CS5503
Initial Code:
SPINIT: DINT MOVP MOVP MOVP MOVP MOVP MOVP MOVP MOVP %1,ADDR port output %1,APORT inactive) %0,P17 %>10,SCTLO Resets port errors %?x1x01101,SMODE port Isosync, %?00x1110x,SCTLO bits, parity %07,T3DATA baud rate %?01000000,SCTL1 multiprocessor; prescale MOVP %0,IOCNT1 Disable INT4 will poll port PUSH Store original MOVP RXBUF,A Bogus read receiver port flag Restore original EINT
Figure TMS70X2/CS5501 Serial Interface
Notes:
CS5501 Asynchronous (UART-like) mode. TMS70X2 Isosynchronous mode. TMS70X2 with master clock baud =1.0 Mbps.
Code word data:
SP_IN: WAIT1 MOVP BTJZP MOVP BTJZP MOVP MOVP %0,APORT active, select CS5501 %2,SSTAT,WAIT1 Wait receive first byte RXBUF,A most significant byte reg. %2,SSTAT,WAIT2 Wait receive second byte RXBUF,B least significant byte reg. %1,APORT inactive, deselect CS5501
Assumptions:
WAIT2 used Receive data polling. Word received upon return, byte. error checking done. Normal equates peripheral registers.
DS31F4 DS31F5
CS5501 CS5503
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IMPORTANT NOTICE Cirrus Logic, Inc. subsidiaries ("Cirrus") believe that information contained this document accurate reliable. However, information subject change without notice provided without warranty kind (express implied). Customers advised obtain latest version relevant infor mation verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgment, including those pertaining warranty, indemnification, limitation liability. responsibility assumed Cirrus this information, including this information basis manufacture sale items, infringement patents other rights third parties This document property Cirrus furnishing this information, Cirrus grants license, express implied under patents, mask work rights, copyrights trademarks, trade secrets other intellectual property rights. Cirrus owns copyrights associated with information contained herein gives consent copies made information only within your organization with respect Cirrus integrated circuits other products Cirrus. This consent does extend other copying such copying general distribution, advertising promotional purposes, creating work resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPER ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS DESIGNED, AUTHORIZED WARRANTED AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO BODY, AUTOMOTIVE SAFETY SECURITY DEVICES LIFE SUPPORT PRODUCTS OTHER CRITICAL APPLICATIONS. INCLUSION CIRRUS PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK CIRRUS DISCLAIMS MAKES WARRANTY, EXPRESS, STATUTORY IMPLIED, INCLUDING IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE, WITH REGARD CIRRUS PRODUCT THAT USED SUCH MANNER. CUSTOMER CUSTOMER'S CUSTOMER USES PERMITS CIRRUS PRODUCTS CRITICAL APPLICATIONS, CUSTOM AGREES, SUCH USE, FULLY INDEMNIFY CIRRUS, OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS OTHER AGENTS FROM LIABILITY, INCLUDING ATTORNEYS' FEES COSTS, THAT RESULT FROM ARISE CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, Cirrus Logic logo designs trademarks Cirrus Logic, Inc. other brand product names this document trademarks service marks their respective owners.
DS31F5
CDB5501 CDB5501 CDB5503 CDB5503 CS5501 CS5503 Evaluation Board CS5501/CS5503 Evaluation Boards
Features Description
CDB5501/CDB5503 evaluation board designed maximum flexibility when evaluating CS5501/CS5503 converters. board easily configured evaluate features CS5501/CS5503, including changes master clock rate, calibration modes, output decimation rates, interface modes. evaluation board interfaces with most microcontrollers allows full control features CS5501 CS5503. switch selectable control also available event microcontroller used. evaluation board also offers computer data interfaces including RS-232 parallel port outputs evaluating CS5501. calibration modes selectable including Self-Cal, System Offset Cal, System Offset System Gain Cal. calibration initiated time pressing pushbutton switch. ORDERING INFORMATION CDB5501 CDB5503
Operation with on-board clock generator, onboard crystal, off-board clock source. switch selectable micro port controllable:
On-board Decimation Counter Multiple Data Output Interface Options:
RS-232 (CS5501) Parallel Port (CS5501) Micro Port (CS5501 CS5503)
Unipolar/Bipolar input range Sleep Mode-All Modes
Evaluation Board Evaluation Board
CLKIN CS5501/ CS5503 Divider
Decimation Counter Micro Port
Parallel Port
VREF
RS-232 Port
Cirrus Logic, Inc. Crystal Semiconductor Products Division http://www.cirrus.com P.O. 17847, Austin, Texas 78760 (512) 7222 FAX: (512) 7581 http://www.crystal.com
Copyright Cirrus Copyright Cirrus Logic, Inc. 2005Logic, Inc. 1998 (All Rights Reserved) (All Rights Reserved)
DS31DB4 DS31DB3
Header
Header
CDB5501 CDB5503
CDB5501/CDB5503 INTRODUCTION CDB5501/CDB5503 evaluation board provides maximum flexibility controlling interfacing CS5501/CS5503 converters. CS5501 CS5503 require minimal amount external circuitry. devices operate with crystal ceramic resonator) voltage reference. evaluation board includes several clock source options, volt trimmable reference, circuitry support several data interface schemes. board operates from volt power supplies. Evaluation Board Overview CDB5501/CDB5503 evaluation board includes extensive support circuitry evaluation CS5501/CS5503. support circuitry includes following sections: clock generator which on-board oscillator counter divider volt trimmable voltage reference. Decimation Counter. parallel output port (for CS5501 only). RS-232 interface (for CS5501 only). micro port (for CS5501 CS5503). switch pushbutton. Clock Generator CS5501/CS5503 operate on-chip oscillator off-chip clock source. evaluation board includes 4.9152 gate oscillator counter-divider chain primary clock source CS5501/CS5503. counter-divider outputs offer several jumper-selectable frequencies clock inputs CS5501/CS5503. 4.9152 crystal frequency chosen allow counter-divider chain also provide common serial data rates
(1200, 2400, 4800, etc.) when CDB5501 evaluation board configured provide RS-232 data output. different operating frequency CS5501/CS5503 desired, three options exist. First, input provided allow external CMOS (+5V) compatible clock used. Second, crystal (Y1) on-board gate oscillator changed. third, onchip oscillator CS5501/CS5503 used with crystal connected position. Volt Reference volt (LT1019CN8-2.5) reference provided board. Potentiometer allows initial value reference accurately trimmed. Decimation Counter CS5501/CS5503 updates internal output register with 16-bit word every 1024 clock cycles master clock. Each time output register updated DRDY line goes low. Although output data updated high rate desirable certain applications activate read data much lower rate. decimation counter provided board this purpose. counter reduces rate which line CS5501 activated only allowing occur sub-multiple DRDY rate. Parallel Output Port (for CS5501 only) output data from CS5501/CS5503 serial form. Some applications require data read parallel format. Therefore evaluation board includes 8-bit shift registers with three-state outputs. Data from CS5501 shifted into registers then read parallel fashion. parallel port comes 16-bit parallel output reconfigured provide 8-bit reads. parallel port supports CS5501 only, since CS5503 outputs 20-bit words.
DS31DB3 DS31DB4
CDB5501 CDB5503
CDB5501/CDB5503 RS-232 Port (for CS5501 only) CS5501 data output mode which formats data UART compatible; each serial output byte preceded start terminated with stop bits. Serial data this format commonly transferred using RS-232 data interface. Therefore evaluation board includes RS-232 driver output connector. CS5503 does provide this output mode. Micro Port CS5501/CS5503 designed compatible with many micro-controllers. Therefore evaluation board provides access data output pins control pins CS5501/CS5503 header connectors. Switch Pushbutton Although control lines CS5501/CS5503 available header connectors edge board, preferable require software control these pins. Therefore switch control provided some these control lines. input CS5501/CS5503 made available header remote control, pushbutton control also provided. Jumper Selections evaluation board many jumper selectable options. This table describes jumper selections available. Selects between on-board 4.9152 oscillator (INT) external (EXT) clock source input clock generator/ divider chain. Allows counter/divider output clock rates selected input clock CS5501/CS5503. Allows selection baud rate clocks when CS5501 UART compatible mode. When using on-board 4.9152 standard baud rates between 1200 19,200 available. Selects divide ratio Decimation Counter. Selects three available output data modes CS5501 available output data modes CS5503. Enables output Decimation Counter control line CS5501/CS5503. Connects baud clock from on-board clock divider input SCLK CS5501/CS5503.
4.9152 74HC00 INTCLK EXTCLK
74HC4040
CLKIN Master Clock Baud Clock
BRCLK (fig. CLKIN (fig.
Figure Clock Generator DS31DB3 DS31DB4
CDB5501 CDB5503
CDB5501/CDB5503 Clock Options Several clock source options available. These include: external clock CMOS-Compatible); on-board 4.9152 crystal oscillator with divider .7); 4.096 crystal. Connector allows jumper selection either external clock on-board 4.9152 crystal oscillator (See Figure schematic) clock source CLKIN signal CS5501/CS5503 (shown Figure position selected, CMOS-compatible clock signal volt supply) should input connector labeled CLKIN. position selected 4.9152 oscillator output input counter/divider either
74HC4040
V+10 74HC74 V+13
Decimation Counter
74HC126
(fig.
DRDY DRDY (fig.
CLKIN (fig.
CLKOUT CLKIN
TP10 SDATA (fig.
SDATA CS5501/ CS5503
74HCT04 SCLK (fig.
SCLK
MODE
11U7 BRCLK (fig.
MODE: Mode available only CS5501
Figure Decimation Counter Microport DS31DB3 DS31DB4
CDB5501 CDB5503
CDB5501/CDB5503 Data Output from CS5501/CS5503
CLKIN Source CS5501/CS5503 On-Board 4.9152 CMOS CLKIN
CLKIN Rate Selection (CLK/2n) with selected. 4.9152
CLKIN Rate 4.9152 2.4576 1.2288 614.4 307.2 153.6 kHz+ 76.8 kHz+ 38.4 kHz*
CS5501 three available data output modes (The CS5503 available data output modes). operating mode part determined input voltage level MODE (pin device. Once mode selected, four other pins device involved data output. first these DRDY (pin 18). output from chip which signals whenever data word available internal output register CS5501/CS5503. Data then read from register, only when (pin low. When low, data bits output serial form SDATA (pin 20). Synchronous Self-Clocking mode CS5501/CS5503, chip provides output data clock from SCLK (pin 19). This output clock synchronous with output data used clock data into external register. Synchronous External-Clocking Asynchronous Communications modes CS5501, SCLK input external clock which determines rate which data bits appear SDATA output pin. CS5503, only synchronous external-clocking mode available. signals necessary reading data from CS5501/CS5503 available connector shown Figure
Exceeds CLKIN Specifications CS5501. Exceeds CLKIN specifications CS5503.
Table Clock Generator
case, counter divides input clock where binary sub-multiples counter input clock input CS5501/CS5503 jumper selection connector CS5501/CS5503 contains on-chip oscillator which needs only external crystal function. Ceramic resonators used well although ceramic resonators frequency crystals will require loading capacitors proper operation. test oscillator CS5501/CS5503 with crystal (Y2) jumper wire near crystal must opened another jumper wire soldered into appropriate holes provided connect crystal chip. Additional holes provided board loading capacitors.
Data Output Mode Synchronous Self-Clocking Synchronous External-Clocking Asynchronous Communications
Available CS5501 only.
Table Data Output Mode
DS31DB3 DS31DB4
CDB5501 CDB5503
CDB5501/CDB5503 CS5501/CS5503 Data Output Mode Selection Connector (see Figure allows jumper selection three data output modes. These modes are: (Synchronous Self-Clocking); (Synchronous External Clocking); (Asynchronous Communication). mode available only CS5501) (Synchronous Self-Clocking) Mode mode designed interface those microcontrollers which allow external clocking their serial inputs. mode also allows easy connection serial-to-parallel conversion circuitry. mode serial data serial clock output from CS5501/CS5503 whenever line activated. illustrated Figure signals available connector P10. signal controlled remotely jumper should placed Connection) position. This removes Decimation Counter output from controlling line. Data Output Interface: Parallel Port (for CS5501 evaluation only). Whenever CS5501 operated mode 16-bit output data clocked into 8-bit shift registers. registers have three-state parallel outputs which available (see Figure flip-flop (U8A) used signal remote reading device whenever registers updated. (Parallel Data Ready) signal from flip-flop available Q-bar output from flip-flop locks further updates registers until their data read DACK (Data ACKnowledge) signal received from remote device. Activation line determines rate which CS5501 will attempt update output shift registers. Data will shifted into
registers only DACK signal occurred since last update. line controlled remotely output Decimation Counter. controlled remotely, Decimation divide jumper should placed position. This insures that signal will occur same rate activated. positive going edge toggles flip-flop which signals update parallel port. parallel registers read 16bit parallel fashion configured read separately 8-bit bytes 8-bit bus. configure board byte-wide reads, byte-wide jumpers must soldered place. addition, proper "one byte time" address selection, connection circuit board needs opened jumper wire soldered proper place determine which register read when vice versa. Figure schematic details. evaluation board component layout diagram, Figure indicates location byte-wide jumpers address selection jumpers. After data read from registers DACK (Data Acknowledge) signal required from off-board controller reset flip-flop U8A. This enables registers accept data input once again. signals connector should used monitor control CS5501 output serial parallel conversion registers. aware that arbitrarily timed DACK signal cause output data registers enabled middle output word signal CS5501 properly sequenced. This will result incorrect data output registers. Decimation Counter used control output CS5501 (Jumper position), signal moniDS31DB3 DS31DB4
CDB5501 CDB5503
CDB5501/CDB5503
TP18 TP17 Header
SCLK (fig.
74HCT299
74HCT299
Byte Wide Jumpers
DACK
SDATA (fig.
(fig.
RN1.4 TP19
74HC74
74HCT04
Figure 16-Bit Parallel Port DS31DB3 DS31DB4
CDB5501 CDB5503
CDB5501/CDB5503 tored signal when data into output registers complete (DCS returns high). DACK signal needed this mode lockout signal inputs registers disabled removing connection circuit board. place provided board this purpose. pull-up resistor provided inputs registers connection opened. (Synchronous External Clocking) Mode mode enables CS5501/CS5503 directly interfaced microcontrollers which output clock signal synchronously input serial data input port. CS5501/CS5503 will output serial data rate determined clock from microcontroller. Connector allows microcontroller access CS5501/CS5503 signal lines which necessary operate mode. (chip select signal allows microcontroller control when CS5501/CS5503 output data. (data ready bar) signal indicates microcontroller when data from CS5501/CS5503 available. Clock from microcontroller input into (serial clock input) data output from CS5501/CS5503 presented (serial data) connector. Note that jumpers connectors must connection) position allow microcontroller full control over signals P10. (Asynchronous Communication) Mode (for CS5501 evaluation only) mode enables CS5501 output data UART-compatible format. Data output characters consisting start bit, eight data bits, stop bits each. output data rate clock input input connector (see Figure jumper must position. Alternatively output data rate selected sub-multiple external CLKIN signal board sub-multiple onboard 4.9152 oscillator. Counter divides input where .12. these outputs jumper selected connector (see Figure example, 4.9152 oscillator selected input then 1200 baud rate clock selected with jumper Table indicates baud rates available connector when 4.9152 oscillator used. on-board baud clock used, jumper connector should (Baud Clock) position. Data Output Interface: RS-232 (for CS5501 evaluation only).
On-Board Baud Rate Clock Input CS5501/CS5503 SCLK Input.
Baud Rate Clock Divider (CLK/2n) with selected. 4.9152
Baud Rate Divider 19.2
P-11
SCLK Input CS5501/CS5503 Connection Baud Clock
Table On-Board Baud Rate Generator
RS232 port depicted Figure Sub-D connector along with interface provides necessary circuitry connect CS5501 RS-232 input computer. proper operation (Asynchronous Communication) data output mode must selected.
DS31DB3 DS31DB4
CDB5501 CDB5503
CDB5501/CDB5503
DATA
Decimation Counter Accumulates 2n+1 DRDY Pulses Before Enabled.
MC145406 SDATA (fig. DRDY (fig. U11A
DECIMATION COUNTER Each time data word available output from CS5501/CS5503, DRDY line goes low, provided output port previously emptied. DRDY line directly tied input CS5501/CS5503, converter will output data every time data word presented output pin. some applications desirable reduce output word rate. rate
U11B
U11C
U11D U11E
U11F
V0.1
Sub-D
Figure RS-232 Port
addition, appropriate baud clock needs input CS5501. (Asynchronous Communication) mode mentioned earlier explanation baud rate clock generator data format output data mode. DRDY output from CS5501 signals (Clear Send) line RS-232 interface when data available. Decimation Counter used determine frequently output data transmitted. RS-232 interface evaluation card functionally adequate compliant with RS-232 standard. When MC145406 RS-232 receiver/driver chip operated volt supplies rather than volts (see MC145406 data sheet details) driver output swing reduced below specified limits. practical applications this signal swing limitation only reduces length cable circuit capable driving.
DS31DB3 DS31DB4
2n+1 1024 2048 4096
Output Connection Decimation Counter Table Decimation Counter Control
reduced lowering rate which line chip enabled. CDB5501/CDB5503 evaluation board uses counter, this purpose. known decimation counter (see Figure outputs counter available connector counter accumulates 2n+1 counts .11) which time selected output enables input CS5501/CS5503 jumper Decimation Counter, position).
CDB5501 CDB5503
CDB5501/CDB5503
Switch SW1-1 SW1-2 SW1-3 SW1-4
SLEEP
AWAKE
Type Self-Cal
AGND VREF VREF
Sequence Step Step Step Step
UNIPOLAR BIPOLAR
System Offset System Gain System Offset
Table Switch Selections
Table Calibration Mode Table
input flip-flop enabled same time goes low. When DRDY returns high flip-flop toggled resets counter back zero which terminates enable. counter then accumulates counts until selected output activates once again. Switch Selections/Calibration Initiation Several control pins CS5501/CS5503 level activated switch selection, microcontroller shown Figure switch selections depicted Tables pushbutton used initiate calibration cycle accordance with switch positions pushbutton should
activated time power first applied board time conversion mode (BP/UP) changed switch. Remote control signal available connector Connector also allows access switch functions microcomputer/microcontroller. switches should placed position off-board control signals connector implemented. Voltage Reference evaluation board includes volt reference. Potentiometer used trim reference output precise value. Analog Input Range: Unipolar Mode
CS5501/ CS5503 BP/UP SLEEP
value reference voltage sets analog input signal range. unipolar mode analog input range extends from AGND VREF. analog input goes above VREF converter will output "1's". input goes below AGND, CS5501/CS5503 will output "0's". Analog Input Range: Bipolar Mode analog signal input range bipolar mode reference from +VREF VREF. input signal goes above +VREF, CS5501/CS5503 will output "1's". Input signals below -VREF cause output data "0's".
WARNING: Some evaluation boards were produced with labels reversed silkscreen
Figure Switch Header Control Selection DS31DB3 DS31DB4
CDB5501 CDB5503
CDB5501/CDB5503 Analog Input: Overrange Precautions normal operation value reference voltage determines range analog input signal. Under abnormal conditions analog signal extend equal VAsupply voltages. event signal exceeds these supply voltages input current should limited analog input chip internally diode clamped both supplies. Excess current into damage device. evaluation board, resistor (see Figure does provide some current limiting event overrange signal which exceeds supply voltage.
DGND CS5501/ CS5503
TP11
TP14 VOUT TP15 AGND VREF
TP13
LT1019-2.5 TRIM
TP12 0.0047
VAVD-
VC17
TP16
Figure Voltage Reference Analog Input
DS31DB3 DS31DB4
CDB5501 CDB5503
CDB5501/CDB5503 Oscilloscope Monitoring SDATA output data from either CS5501 CS5503 observed dual trace oscilloscope with following hook-up. evaluation board operate mode. Connect scope probes (SCLK) TP10 (SDATA). third probe connected (DRDY) provide external trigger input scope (use falling edge DRDY trigger). With proper horizontal sweep, SDATA output bits from converter observed. Note that input voltage CS5501 adjusted mid-code value, converter will remain stable same output code. This illustrates noise level CS5501. CS5503 will exhibit LSB's noise observed output agreement with noise specifications. Evaluation Board Component Layout Design Considerations Figure reproduction silkscreen component placement board. evaluation board includes design features insure proper performance from converter chip. Separate analog digital ground planes have been used board insure good noise immunity digital system noise. Decoupling networks (R6, Figure have been used eliminate possibility noise power supplies digital section from affecting analog part converter chip. network (R10, C19) output LT1019-2.5 reference needed applications. been included insure best noise performance from reference
DS31DB3 DS31DB4
CDB5501 CDB5503
CDB5501/CDB5503
Figure CDB5501/CDB5503 Component Layout
DS31DB3 DS31DB4
CDB5501 CDB5503
Contacting Cirrus Logic Support
product questions inquiries contact Cirrus Logic Sales Representative. find nearest www.cirrus.com
IMPORTANT NOTICE Cirrus Logic, Inc. subsidiaries ("Cirrus") believe that information contained this document accurate reliable. However, information subject change without notice provided without warranty kind (express implied). Customers advised obtain latest version relevant infor mation verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgment, including those pertaining warranty, indemnification, limitation liability. responsibility assumed Cirrus this information, including this information basis manufacture sale items, infringement patents other rights third parties This document property Cirrus furnishing this information, Cirrus grants license, express implied under patents, mask work rights, copyrights trademarks, trade secrets other intellectual property rights. Cirrus owns copyrights associated with information contained herein gives consent copies made information only within your organization with respect Cirrus integrated circuits other products Cirrus. This consent does extend other copying such copying general distribution, advertising promotional purposes, creating work resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPER ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS DESIGNED, AUTHORIZED WARRANTED AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO BODY, AUTOMOTIVE SAFETY SECURITY DEVICES LIFE SUPPORT PRODUCTS OTHER CRITICAL APPLICATIONS. INCLUSION CIRRUS PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK CIRRUS DISCLAIMS MAKES WARRANTY, EXPRESS, STATUTORY IMPLIED, INCLUDING IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE, WITH REGARD CIRRUS PRODUCT THAT USED SUCH MANNER. CUSTOMER CUSTOMER'S CUSTOMER USES PERMITS CIRRUS PRODUCTS CRITICAL APPLICATIONS, CUSTOM AGREES, SUCH USE, FULLY INDEMNIFY CIRRUS, OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS OTHER AGENTS FROM LIABILITY, INCLUDING ATTORNEYS' FEES COSTS, THAT RESULT FROM ARISE CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, Cirrus Logic logo designs trademarks Cirrus Logic, Inc. other brand product names this document trademarks service marks their respective owners.
DS31DB4
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